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MTC MEMORY AND COMMAND
INTERPRETATION
The MTC9101 has a 128-word Read/Write
memory that is divided into 32 registers (16 bits per
register) for each of the four MTC channels (or
ports). The address of each of the various registers
in the MTC is a combination of two bits of the chan-
nel number and the five high-order bits of the func-
tion code used
to
write into or read from a particular
register.
The CP can read or write any register as long as
the specific channel is not busy. To write into a
register, an 110 output command is used; reading is
done with an 110 input command. Addressing of the
various registers relates to the 110 command as
follows:
8
14 151617 18
22 23
MTC Identifier
' : =--r---' L r-' ]
J
These 2 Bits identify which
--l
Tape Unit is &eing !lddressed
Direction Bit
0 =
Read (Input)
I = Write (Output)
These 5 Bits
identify the
Byte Pair in
MTCMemory
o
Data Bus
7 8
I = Write MTC
Memory
0= Read MTC
MemolY
''------~v
These 16 Bits will contain the
Byte Pair in MTC Memory
IS
The format shown is for a Write cycle on the bus.
For a Read cycle, the memory data will be returned
from the MTC on a second bus transfer.
To perform a specific operation, software first
loads the address, range, and configuration
registers. The task register is loaded last and
specifies the operation to be performed. The MTC
begins command execution when it receives the
task word.
CHANNEL NUMBER
Units attached to the MTC9101 are software-
addressable via channel numbers. Each tape unit
has two such channel numbers assigned, differing
only
in
their low-order bit position called the direction
bit.
PROGRAMMING
2-1
Section 2
Programming
The channel number for the MTC is separated
into three fields:
• MTC Identifier (bits 8-14) - switch-selectable
and assigned at system installation time.
• MTC Port (bits 15-16) - identifies which of
the four tape units is being addressed.
• Direction Bit (bit 17) - specifies in the IOLD
command whether it is an input or output data
transfer. For all other commands, the direc-
tion bit is ignored by the hardware.
SIMULTANEITY
The MTC9101 provides a single level of
simultaneity (only one data transfer can be active in
the subsystem). However, the MTC will accept a
data transfer command to unit B while unit A is
performing a data transfer, but will not start the
data transfer on B until A's data transfer is
completed.
INTERRUPTS
An interrupt will be attempted whenever a chan-
nel interrupt level is not zero, and an operation
initiated by an Output Task Word or Output Con-
trol Word instruction is completed or the Attention
bit is set in Status Word 1. If a negative response is
received during an interrupt cycle, the MTC will
store the interrupt until it can be retried. In the
meantime, the MTC can receive commands and/or
conduct data transfers on any ofthe other channels.
The channel with the pending interrupt will remain
busy and the MTC will not accept any commands
issued
to
that channel except an Output Control
Word.
If an interrupt level of a channel is zero (either via
initialization or loaded to zero) no interrupts will be
attempted for that channel. If a condition or event
occurs that would normally cause an interrupt, the
appropriate bits in the Status Words will be set, but
no interrupt will be attempted or accepted.
If the interrupt level is set to zero when an inter-
rupt is pending via an Output Control Word
(Initialize) or a Master Clear, the pending interrupt
will be discarded.
MEDIA INTERCHANGEABILITY
Tapes generated by these units are compatible
with tapes generated by other units if the other tape
units comply with American National Standards
Institute recording standards.
CFI0
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