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SINTRO Selftest Interrupt
The SINTRO interrupt request is activated by the ROM-based selftest firmware
when the self test sequence completes or whenever an idle self test failure is
detected. The host software reads the STR channel register to determine the
type of error detected. A more detailed description of the self test is contained
in Chapter 4.
SINTR1 LANIC Interrupt
This interrupt is activated by either the ROM-based kernel firmware or by the
downloaded operational firmware to signal the host software that some event in
the LANIC has occurred. Host software reads the SR channel register to
determine what type of event has occurred. The types of events fall into two
groups:- those related to a command issued to LANIC by the host software, and
those resulting from internal LANIC operations.
Interactive Command Completion
This response is given when the LANIC completes the execution of an
interactive command. The command-specific bits of the response code contain
status and error codes whose meanings depend on the associated command as
shown below.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
Completion status
Command code
,
,
I
I
I
,
, ,
I
I
I
02 -
03
04 -
08 -
09 -
OA -
08 -
Command code
Completion status
=
Command code originally given
=
See below and paragraph "Self test"
00 - command executed correctly
01
sync between driver and LANIC established
(e.g., an all-ones word written into CR)
illegal length command
command not found
command doesn't match length
host buffer crosses bank boundary
non-word address on download or dump
checksum didn't check (DOWNLOAD command)
illegal start address (START CODE command)
Principles of Operation
3-9
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