Fujitsu MB15F74UV Datasheet page 13

PHASE COMPARATOR OUTPUT WAVEFORM
fr
IF RF
fp
IF RF
LD
(FC bit "1")
o
D
IF RF
Z
FC bit "0"
( )
o
D
IF RF
Z
• LD Output Logic
IF-PLL section
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
Unlocking state
Notes : Phase error detection range
Pulses on Do
IF/RF
LD output becomes low when phase error is t
LD output becomes high when phase error is t
t and t depend on OSC
WU WL
t 2/fosc : e.g. t
WU
t 4/fosc : e.g. t
WU
t
WU
H
L
Locking state/Power saving state
Unlocking state
Locking state/Power saving state
Unlocking state
2 to 2
signals during locking state are output to prevent dead zone.
input frequency as follows.
IN
156.3 ns when fosc
WU
312.5 ns when fosc
WL
t
WL
L
H
RF-PLL section
or more.
WU
or less and continues to be so for three cycles or more.
WL
12.8 MHz
12.8 MHz
MB15F74UV
LD output
H
L
L
L
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