Block Diagram - Fujitsu MB15F74UV Datasheet

MB15F74UV

BLOCK DIAGRAM

Intermittent
PS (7)
IF
mode control
(IF-PLL)
(2)
fin
IF Prescaler
(IF-PLL)
(32/33, 64/65)
(3)
Xfin
IF
(18)
OSC
IN
OR
Prescaler
fin (14)
RF
(RF-PLL)
Xfin ( )
13
RF
(64/65, 128/129)
Intermittent
mode control
PS (9)
RF
(RF-PLL)
Schmitt
LE
(15)
trigger
circuit
Schmitt
trigger
Data (16)
circuit
Schmitt
Clock
(17)
trigger
circuit
4
3 bit latch
7 bit latch
Binary 7-bit
swallow counter
(IF-PLL)
2 bit latch 14 bit latch
Binary 14-bit pro-
grammable ref.
T1 T2
counter(IF-PLL)
Binary 14-bit pro-
T1 T2
grammable ref.
counter (RF-PLL))
2 bit latch 14 bit latch
Binary 7-bit
swallow counter
(RF-PLL)
3 bit latch 7 bit latch
Latch selector
C C
N N
23-bit shift register
1 2
V GND
CCIF
(5)
11 bit latch
Binary 11-bit
Phase
programmable
comp.
counter (IF-PLL) (IF-PLL)
fp
IF
1 bit latch
C/P setting
counter
fr
IF
fr
RF
C/P setting
counter
1 bit latch
fp
RF
Phase
Binary 11-bit
comp.
programmable
(RF-PLL)
counter (RF-PLL)
fp
RF
11 bit latch
(1) (11)
GND V GND
CCRF
IF
(4)
Fast Charge
Current
(6)
lock pump
Switch
Tuning (IF-PLL)
Lock Det.
(IF-PLL)
LD
IF
Fast
lock
Tuning
Selector
AND
LD
fr
IF
(8)
fr
RF
fp
IF
fp
RF
LD
RF
Lock Det.
(RF-PLL)
Charge
Current (10)
pump
Switch
(RF-PLL)
(12)
RF
Do
IF
LD
fout
Do
RF