Sharp ER-A750 Service Manual page 59

9. Interrupt control
There are roughly two types of interrupts:
•
Internal interrupts: Controlled inside the CPU
•
External interrupts: Input into the CPU from outside
9-1. Internal interrupts
Device interrupts built in the CPU are used for the following applica-
tions:
Event factor
SC11 Interrupt source as IR channel
SC12 Not used (SC1 is used for CKDC interface.)
FRT1 (ICI) INTMCR
(OCRA)
(OCRB)
(OVF)
FRT2 (ICI) Standard SHEN event (for CKDC)
(OCRA) Simple IRC timer event
(OCRB) RS232 timer event
(OVF) System timer (53 ms)
TMR (CMA)
(CMB)
(OVF)
WDT (OVF) Drawer open timer
A/D Not used
NMI SSP request
9-2. External interrupts
The following types of external interrupts are available:
•
NMI (SSP)
•
IRQ0 (Standard I/O interrupt)
•
IRQ1 (RS232 interrupt)
•
IRQ2 (Used as SCk terminal)
•
IRQ3 (Used as SCK terminal)
9-2-1. IRQ0 layout
The interrupt factors for a total of 16 standard I/Os are ORed inside
the MPCA7 and input into the CPU as IRQ0. Each interrupt factor
can be read by the internal register of the MPCA7.
Table 8
Application
MCR interrupt (to FT11 terminal)
<IRQ0 component bits – 1>
Address BIT7 BIT6
00FF80h POFF EXINT3
(S17) (S16)
BIT7: POFF (SI7)
Power failure detection signal input and software inter-
rupt 7 OR input
BIT6: EXINT3 (SI6)
Optional external interrupt signal and software interrupt 6
OR input
BIT5: EXINT2 (SI5)
Optional external interrupt signal and software interrupt 5
OR input
BIT4 1: SI4 SI1
Software interrupt
BIT0: EXINT0 (S10)
<IRQ0 component bits – 2>
Address BIT7 BIT6
00FF81h — EXINT0 KRQ1 SHEN1
BIT7: Not used
BIT6: EXINT0
Optional external interrupt signal
BIT5-3: KRQ1, SHEN1
Event request signal for CKDC interface channel 1
9-2-2. IRQ1 layout
The IRQ1 is an external interrupt terminal for an external optional
RS232, and input into the CPU through an optional slot bus.
9-2-3. IRQ2 layout
The IRQ2 terminal is used as the shift lock terminal (SCK1) for IR
interface.
10. WAIT control
The weight control function built in the MPCA7 is used to provide an
interface with low-speed devices.
7 – 29
Table 9
BIT5 BIT4 BIT3 BIT2
EXINT2 SI4 SI3 SI2
(S15)
Table 10
BIT5 BIT4 BIT3 BIT2
SHEN1 —
*
*: Edge interrupt
BIT1 BIT0
SI1 EXINT1
(S10)
BIT1 BIT0
— —