Block Diagram - Main Section - Sony SCD-XA5400ES Service Manual

6-3.

BLOCK DIAGRAM - MAIN Section -

PDT, BDTR, PBCK,
PLRCK, SBCK
PDT
(Page 17)
A
BDTR
SWITCHING
PBCK
PLRCK
SBCK INVERTER
27M
(Page 18) B
X151
22.5792MHz
CLOCK
BUFFER
IC152
R-ch is omitted due to same as L-ch.
• SIGNAL PATH
: SA-CD
SCD-XA5400ES
5 PDATA
1 DSDL
IC206
R-CH 2 DSDR
4 PBCK
PLRCK
6
D/A CONVERTER
IC292
D-FLIP FLOP
IC202
IC155
7 SCK
COUNTER
IC156
3 AB CK
CLOCK GENERATOR
IC151
10 MS
2 REF CLKP 15 11 MDI
12 MDO
14 RST
1 2
78 77 87 88 30 28 85
IOUTR+ 17 BUFFER LOW-PASS FILTER
IC253
IOUTR- 18 IC255
IOUTL+ 25 BUFFER LOW-PASS FILTER
IC203
IOUTL- 26 IC205
BUFFER
IC204
RELAY
CONTROL
Q151, 293
6 19
SYSTEM CONTROLLER
IC501 (3/4)
19 19
1 4 2
J252
R
3
RELAY DRIVE
Q252, 253
RY252
1 4 2
J202
3
L
ANALOG OUT
UNBALANCED
RELAY DRIVE
Q202, 203
RY202 J251
R
J201
L
RELAY DRIVE
RV801
Q201, 204
PHONE LEVEL
RY201
J801
-1 PHONES
LINE AMP
IC291
-2
AC_DET
C
SCD-XA5400ES
(Page 20)