Page 1 Preliminary User's Manual µPD72256, µPD72257 Graphics Controllers Hardware Document No. S19203EE1V3UM00 Date published July 07, 2009 © NEC Electronics 2008 Printed in Germany...
Page 2 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products.
Page 3 The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.
Page 4 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives anddistributors. They will verify: •...
Page 5 Preface Readers This manual is intended for users who want to understand the functions of this graphics controller. Purpose This manual presents the hardware manual for this graphics controller. Organization This system specification describes the following sections: • Pin function •...
Page 6 • HSYNC: horizontal synchronization signal, that marks the beginning of a new line • VSYNC: vertical synchronization signal, that marks the beginning of a new frame or field • CSYNC: composite synchronization signal, which presents a composition of the horizontal and vertical synchronization signals HSYNC and VSYNC •...
Page 7: Table Of Contents
Table of Contents Chapter 1 Introduction ............11 Block diagrams .
Page 8 5.2.1 LBus-I/F signals ............123 5.2.2 LBus-I/F addressing modes .
Page 9 7.2.2 Display data output formats ..........192 Timing Signals .
Page 10 8.9.5 Texture registers details ........... .272 8.9.6 Miscellaneous registers details .
Page 11: Chapter 1 Introduction
Chapter 1 Introduction Ravin-L (µPD72256) and Ravin-M (µPD72257) are new members of NEC’s low- cost graphics controller series, used to interface coloured TFT displays in embedded applications like automotive dashboard- or audio applications. Both products are focusing on cost optimization and flexibility. They are designed featuring a high compatibility between each other and are future save as they can be integrated into new SOC designs without changes.
Page 12: Block Diagrams
Chapter 1 Introduction 1.1 Block diagrams The block diagrams below show the functional modules of Ravin-M and Ravin-L, the bus systems and the external signals. Ravin-M HLBD[7:0] APB master HLBWR HLBRD HLBCS AHB master HLBDRQ Drawing HCLK HCLK Host-I/F HINT Engine SYSRESET SYSRESET...
Page 13 Introduction Chapter 1 Ravin-L AHB master Drawing HCLK Engine SYSRESET HLBD[7:0] APB master HLBWR APB slave Slave HLBRD HCLK HLBCS HLBDRQ SYSRESET Host-I/F MD[15:0] HINT MA[24:0] AHB master MCS0 MCS1 MDBA[1:0] HCLK HCLK MDDQM[1:0] MDRAS SYSRESET 160 KB MDCAS MDWE AHB slave MDCKE MDCLK...
Page 14 Chapter 1 Introduction Clocks The clock generation circuitry is part of the System Controller. It generates the main system clock HCLK, that is supplied to most modules. It is also used to set up and generate the pixel clocks VO0CLK and VO1CLK for the Video Output modules.
Page 15: Chapter 2 Pin Functions
Chapter 2 Pin Functions This chapter describes the pin functions of Ravin-L and Ravin-M. Ravin-M Ravin-M presents a variety of selectable pin functions to match different needs. The various Ravin-M pinout configurations trade between • Host-I/F width • SDRAM and/or SRAM Memory Interface width •...
Page 16: Ravin-L Pin List
Chapter 2 Pin Functions 2.1.1 Ravin-L pin list Table 2-1 Ravin-L pin list Input/ Internal pull-up Pin name number Output group VO0G4_MODE10 – VO0G5_MODE11 – VO0B0 – VO0B1 – DVDD33 n.a. DGND33 n.a. VO0B2 – VO0B3 – VO0B4 – VO0B5 –...
Page 17 Pin Functions Chapter 2 Input/ Internal pull-up Pin name number Output group DGND33 n.a. MDDQM0 – DVDD33 n.a. DGND33 n.a. MD15 MD14 MD13 MD12 MD11 MD10 DGND15 n.a. DVDD15 n.a. MDDQM1 – DVDD33 n.a. DGND33 n.a. MDCLK – MDFBCLK MDCKE –...
Page 18 Chapter 2 Pin Functions Input/ Internal pull-up Pin name number Output group n.c. n.c. n.c. DGND33 n.a. DVDD33 n.a. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. DVDD33 n.a. DGND33 n.a. n.c. n.c. DVDD33 n.c. MCS1 – MSWR –...
Page 19 Pin Functions Chapter 2 Input/ Internal pull-up Pin name number Output group n.c. n.c. n.c. VO0EN HINT DGND33 – DGND33 n.a. DVDD33 n.a. MA15 MA14 MA13 MA12 – MA10 – MA19 MA20 MA21 MA18 MA17 DGND33 n.a. DVDD33 n.a. HLBD7 HLBD6 HLBD5 HLBD4...
Page 20 Chapter 2 Pin Functions Input/ Internal pull-up Pin name number Output group VO0R1_MODE1 – VO0R2_MODE2 – VO0R3_MODE3 – VO0R4_MODE4 – DVDD33 n.a. DGND33 n.a. VO0R5_MODE5 – VO0G0_MODE6 – VO0G1_MODE7 – VO0G2_MODE8 – VO0G3_MODE9 – • n.c.: do not connect this pin, leave it open •...
Page 21: Ravin-M Pin List
Pin Functions Chapter 2 2.1.2 Ravin-M pin list Table 2-2 Ravin-M pin list Input/ Internal pull-up Pin name number Output group VO0G4_MODE10 – VO0G5_MODE11 – VO0B0 – VO0B1 – DVDD33 n.a. DGND33 n.a. VO0B2 – VO0B3 – VO0B4 – VO0B5 –...
Page 22 Chapter 2 Pin Functions Input/ Internal pull-up Pin name number Output group DGND33 n.a. MDDQM0 – DVDD33 n.a. DGND33 n.a. MD15 MD14 MD13 MD12 MD11 MD10 DGND15 n.a. DVDD15 n.a. MDDQM1 – DVDD33 n.a. DGND33 n.a. MDCLK – MDFBCLK MDCKE –...
Page 23 Pin Functions Chapter 2 Input/ Internal pull-up Pin name number Output group MD28_VO1VSYNC_MA20 MD27_VO1HSYNC_MA19 MD26_VO1G5_MA18 DGND33 n.a. DVDD33 n.a. MD25_VO1G4_MA17 MD24_VO1G3_MA16 VI0G3_VO1R4 VI0G2_VO1R3_VO0EN VI0G1ITU7_MA20_VO1G0 VI0G0ITU6_MA19_VO1R1 VI0R5ITU5_MA18_VO1R0 VI0R4ITU4_MA17_VO1B1 VI0R3ITU3_MA16_VO1B0 VI0R2ITU2_MA15 DVDD33 n.a. DGND33 n.a. VI0R1ITU1_MA14 VI0R0ITU0_MA13 VI0CLK HADA20_VO1G4 HADA19_VO1R4_MCS1 – HADA18_VO1R3_MSWR –...
Page 24 Chapter 2 Pin Functions Input/ Internal pull-up Pin name number Output group HADA2_VI0B1_VI0R2ITU2 HADA1_VI0B0_VI0R1ITU1 HADA0_VI0G5_VI0R0ITU0 HADBEN1_MA24_VO0EN HINT DGND33 – DGND33 n.a. DVDD33 n.a. HADD15_MA15_VO1VSYNC HADD14_MA14_VO1HSYNC HADD13_MA13_VO1CLK MA12 – MA10 – HADD12_MA19_VO1B5 HADD11_MA20_VO1B4 HADD10_MA21_VO1B3 HADD9_MA18_VO1B2 HADD8_MA17_VO1G5 DGND33 n.a. DVDD33 n.a. HADD7_HLBD7 HADD6_HLBD6 HADD5_HLBD5 HADD4_HLBD4...
Page 25 Pin Functions Chapter 2 Input/ Internal pull-up Pin name number Output group VO0R1_MODE1 – VO0R2_MODE2 – VO0R3_MODE3 – VO0R4_MODE4 – DVDD33 n.a. DGND33 n.a. VO0R5_MODE5 – VO0G0_MODE6 – VO0G1_MODE7 – VO0G2_MODE8 – VO0G3_MODE9 – • n.c.: do not connect this pin, leave it open •...
Page 26: Pull-Up Resistor Pin Groups
Chapter 2 Pin Functions 2.2 Pull-up resistor pin groups The pins, equipped with optional internal pull-up resistors, are grouped as follows: Table 2-3 Ravin-M pull-up resistor groups Pin group Control bit Pin number Pin name HADA8_VO1R5_VI0SYNC2 HADA7_VI0SYNC1_VI0G1ITU7 HADA6_VI0B5_VI0G0ITU6 HADA5_VI0B4_VI0R5ITU5 SYSPINMUX. HADA4_VI0B3_VI0R4ITU4 BUFPUEN0 HADA3_VI0B2_VI0R3ITU3...
Page 27 Pin Functions Chapter 2 Pin group Control bit Pin number Pin name MD15 MD14 MD13 MD12 MD11 MD10 MD23_VO1G2_MA15 MD22_VO1G1_MA14 MD21_VO1G0_MA13 MD20_VO1B5_VOB1_MCS1 MD19_VO1B4_MSWR MD18_VO1B3_MSOE MD17_VO1B2_MSBEN1 MD16_VO1B1_MSBEN0 SYSPINMUX. BUFPUEN5 MD31_VO1R2_MA23 MD30_VO1R1_MA22 MD29_VO1CLK_MA21 MD28_VO1VSYNC_MA20 MD27_VO1HSYNC_MA19 MD26_VO1G5_MA18 MD25_VO1G4_MA17 MD24_VO1G3_MA16 VI0G1ITU7_MA20_VO1G0 VI0G0ITU6_MA19_VO1R1 VI0R5ITU5_MA18_VO1R0 VI0R4ITU4_MA17_VO1B1 SYSPINMUX.
Page 28 Chapter 2 Pin Functions Pin group Control bit Pin number Pin name n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. HLBD7 HLBD6 HLBD5 BUFPUEN1 HLBD4 HLBD3 HLBD2 HLBD1 HLBD0 VO0EN MA15 MA14 MA13 BUFPUEN2 MA19 MA20 MA21 MA18 MA17 n.c. BUFPUEN3 n.c.
Page 29 Pin Functions Chapter 2 Pin group Control bit Pin number Pin name n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. BUFPUEN5 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. BUFPUEN6 n.c. n.c. n.c. n.c. MDFBCLK DVDD33 BUFPUEN7 HINT HLBDRQ...
Page 30: Ravin-L Pin Functions
Chapter 2 Pin Functions 2.3 Ravin-L Pin Functions For Ravin-L only a single pinout is available. It is set up by the following register setting: If SYSBOOTMODE.BOOTMODE9 = 0 (IRAM disabled): SYSPINMUX = 00ED 0003 PINMUX[3:0] = 0011 pinout option 3 (fixed) all SMUXm = 0 no SMUX selection (fixed) internal pull-up resistors enabled for...
Page 31: Ravin-L Pin To Signals Reference
Pin Functions Chapter 2 Xtal, Reset Xtal, Reset, Test 3.3V, 1.5V 3.3V, 1.5V System Control System Control Power Supply Power Supply Internal RAM Internal RAM Mem I/F 16-bit SDRAM/SRAM Mem I/F 16bit SD/SR 16-bit SDRAM 16-bit SRAM/Flash 16bit SD 16bit SR/Flash Figure 2-1 Ravin-L pinout 2.3.1 Ravin-L pin to signals reference...
Page 32 Chapter 2 Pin Functions Pin number Signal DGND33 n.c. n.c. n.c. n.c. n.c. DVDD15 DGND15 n.c. n.c. DVDD33 DGND33 MDA10PC MDBA1 MDBA0 MCS0 MDRAS MDCAS MDWE DVDD33 DGND33 MDDQM0 DVDD33 DGND33 MD15 MD14 MD13 MD12 MD11 MD10 DGND15 DVDD15 Preliminary User's Manual S19203EE1V3UM00...
Page 33 Pin Functions Chapter 2 Pin number Signal MDDQM1 DVDD33 DGND33 MDCLK MDFBCLK MDCKE MA11 DGND33 DVDD33 n.c. n.c. n.c. n.c. n.c. n.c. n.c. DGND33 DVDD33 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. DVDD33 DGND33 n.c. n.c. DVDD33 n.c.
Page 34 Chapter 2 Pin Functions Pin number Signal MCS1 MSWR MSOE n.c. n.c. DVDD15 DGND15 MSBEN1 MSBEN0 DGND33 DVDD33 MA16 MA24 MA23 MA22 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. VO0EN HINT DGND33 DGND33 DVDD33 MA15 MA14 MA13 MA12 MA10 MA19 MA20...
Page 35 Pin Functions Chapter 2 Pin number Signal HLBD5 HLBD4 HLBD3 HLBD2 HLBD1 HLBD0 HLBRD HLBWR HLBDRQ HLBCS n.c. DVDD15 DGND15 AVDD15 AGND RESET DGND33 VO0R0 VO0R1 VO0R2 VO0R3 VO0R4 DVDD33 DGND33 VO0R5 VO0G0 VO0G1 VO0G2 VO0G3 n.c.: do not connect, leave pin open Preliminary User's Manual S19203EE1V3UM00...
Page 36: Ravin-M Pin Functions
Chapter 2 Pin Functions 2.4 Ravin-M Pin Functions 2.4.1 Ravin-M pin multiplexing control The pins of Ravin-M are gathered in three different groups: • Non-mux I/O signals These signals are connected directly to external pins. Such pins carry always the same signal, independent of any pinout configuration. Non-SMUX I/O signals •...
Page 37 Pin Functions Chapter 2 of the MODE[3:0] pins at release of RESET. By this SYSPINMUX.PINMUX[3:0] are predefined at system start-up. SYSPINMUX.PINMUX[3:0] select one out of six pinout options according to following table: Table 2-6 Ravin-M pinout options SYSPINMUX.PINMUX[3:0] Option number 0001 0010 0011...
Page 38: Ravin-M Pinout Options
Chapter 2 Pin Functions 2.4.2 Ravin-M pinout options The Ravin-M pin layout offers 11 pinout options, which are controlled by settings in the SYSPINMUX register. Below table gives an overview, which signals are available at external pins, if a certain pinout option is chosen. Table 2-8 Ravin-M pinout options 1 Video Output I/F...
Page 39 Pin Functions Chapter 2 Preliminary User's Manual S19203EE1V3UM00...
Page 40 Chapter 2 Pin Functions 2.4.2.1 Ravin-M pinout option 1 Setup Ravin-M pinout option 1 is set up by the following register setting: SYSPINMUX = 00C0 0001 PINMUX[3:0] = 0001 pinout option 1 all SMUXm = 0 no SMUX selection internal pull-up resistors enabled for group 7: HINT, HADWAIT, HADCS, MDFBCLK, BUFPUEN[7:0] = C0 VI0CLK...
Page 41 Pin Functions Chapter 2 2.4.2.2 Ravin-M pinout option 2 Setup Ravin-M pinout option 2 is set up by the following register setting: SYSPINMUX = 00C0 0002 PINMUX[3:0] = 0010 pinout option 2 all SMUXm = 0 no SMUX selection internal pull-up resistors enabled for group 7: HINT, HADWAIT, HADCS, MDFBCLK, BUFPUEN[7:0] = C0 VI0CLK...
Page 42 Chapter 2 Pin Functions 2.4.2.3 Ravin-M pinout option 3 Setup Ravin-M pinout option 3 is set up by the following register setting: SYSPINMUX = 00CD 0003 PINMUX[3:0] = 0011 pinout option 3 all SMUXm = 0 no SMUX selection internal pull-up resistors enabled for group 7: HINT, HADWAIT, HADCS, MDFBCLK, VI0CLK BUFPUEN[7:0] = CD...
Page 43 Pin Functions Chapter 2 2.4.2.4 Ravin-M pinout option 6a Setup Ravin-M pinout option 6a is set up by the following register setting: SYSPINMUX = 00C0 0006 PINMUX[3:0] = 0110 pinout option 6 all SMUXm = 0 no SMUX selection internal pull-up resistors enabled for group 7: HINT, HADWAIT, HADCS, MDFBCLK, BUFPUEN[7:0] = C0 VI0CLK...
Page 44 Chapter 2 Pin Functions Preliminary User's Manual S19203EE1V3UM00...
Page 45 Pin Functions Chapter 2 2.4.2.5 Ravin-M pinout option 6b Setup Ravin-M pinout option 6b is set up by the following register setting: SYSPINMUX = 00C0 0506 PINMUX[3:0] = 0110 pinout option 6 SMUX93 = 1 VO1R0 output at pin 93 SMUX95 = 1 VO1B0 output at pin 95 all other SMUXm = 0...
Page 46 Chapter 2 Pin Functions Preliminary User's Manual S19203EE1V3UM00...
Page 47 Pin Functions Chapter 2 2.4.2.6 Ravin-M pinout option 7a Setup Ravin-M pinout option 7a is set up by the following register setting: SYSPINMUX = 0080 0007 PINMUX[3:0] = 0111 pinout option 7 all SMUXm = 0 no SMUX selection internal pull-up resistors enabled for BUFPUEN[7:0] = 80 group 7: HINT, HADWAIT, HADCS, MDFBCLK, VI0CLK...
Page 48 Chapter 2 Pin Functions 2.4.2.7 Ravin-M pinout option 7b Setup Ravin-M pinout option 7b is set up by the following register setting: SYSPINMUX = 0080 0087 PINMUX[3:0] = 0111 pinout option 7 SMUX12 = 1 VO0EN output at pin 12 all other SMUXm = 0 no SMUX selection internal pull-up resistors enabled for...
Page 49 Pin Functions Chapter 2 Preliminary User's Manual S19203EE1V3UM00...
Page 50 Chapter 2 Pin Functions 2.4.2.8 Ravin-M pinout option 7c Setup Ravin-M pinout option 7c is set up by the following register setting: SYSPINMUX = 0080 1F17 PINMUX[3:0] = 0111 pinout option 7 SMUX[95:91] = 1 VO1B[1:0], VO1R[1:0], VO1G0 output at pins 91 to 95 SMUX127 = 1 VO0EN output at pin 127 all other SMUXm = 0...
Page 51 Pin Functions Chapter 2 2.4.2.9 Ravin-M pinout option 7d Setup Ravin-M pinout option 7d is set up by the following register setting: SYSPINMUX = 0080 0017 PINMUX[3:0] = 0111 pinout option 7 SMUX127 = 1 VO0EN output at pin 127 all other SMUXm = 0 no SMUX selection internal pull-up resistors enabled for...
Page 52 Chapter 2 Pin Functions Preliminary User's Manual S19203EE1V3UM00...
Page 53 Pin Functions Chapter 2 2.4.2.10 Ravin-M pinout option 7e Setup Ravin-M pinout option 7e is set up by the following register setting: SYSPINMUX = 0080 0067 PINMUX[3:0] = 0111 pinout option 7 SMUX78 = 1 VO1R1 output at pin 78 SMUX26 = 1 VO1B1 output at pin 26 all other SMUXm = 0...
Page 54 Chapter 2 Pin Functions Preliminary User's Manual S19203EE1V3UM00...
Page 55 Pin Functions Chapter 2 2.4.2.11 Ravin-M pinout option 9 Setup Ravin-M pinout option 9 is set up by the following register setting: SYSPINMUX = 00C8 0009 PINMUX[3:0] = 1001 pinout option 9 all SMUXm = 0 no SMUX selection internal pull-up resistors enabled for group 7: HINT, HADWAIT, HADCS, MDFBCLK, BUFPUEN[7:0] = C8 VI0CLK...
Page 56: Ravin-M Pin To Signals Reference
Chapter 2 Pin Functions 2.4.3 Ravin-M pin to signals reference The following tables list the signals available at all pins for all Ravin-M pinout options. Table 2-9 Ravin-M pin to signal reference for options 1, 2, 3, 6a-b Host-I/F ADBus ADBus LBus ADBus...
Page 57 Pin Functions Chapter 2 Host-I/F ADBus ADBus LBus ADBus ADBus External data bus width 32 bit 16 bit 32 bit 16 bit 32 bit External SRAM size – 64 MB 128 MB – – Video Outputs 1 Video Input ITU RGB/ITU Pin number Option 1...
Page 58 Chapter 2 Pin Functions Host-I/F ADBus ADBus LBus ADBus ADBus External data bus width 32 bit 16 bit 32 bit 16 bit 32 bit External SRAM size – 64 MB 128 MB – – Video Outputs 1 Video Input ITU RGB/ITU Pin number Option 1...
Page 59 Pin Functions Chapter 2 Host-I/F ADBus ADBus LBus ADBus ADBus External data bus width 32 bit 16 bit 32 bit 16 bit 32 bit External SRAM size – 64 MB 128 MB – – Video Outputs 1 Video Input ITU RGB/ITU Pin number Option 1...
Page 60 Chapter 2 Pin Functions Host-I/F ADBus ADBus LBus ADBus ADBus External data bus width 32 bit 16 bit 32 bit 16 bit 32 bit External SRAM size – 64 MB 128 MB – – Video Outputs 1 Video Input ITU RGB/ITU Pin number Option 1...
Page 61 Pin Functions Chapter 2 Host-I/F ADBus ADBus LBus ADBus ADBus External data bus width 32 bit 16 bit 32 bit 16 bit 32 bit External SRAM size – 64 MB 128 MB – – Video Outputs 1 Video Input ITU RGB/ITU Pin number Option 1...
Page 62 Chapter 2 Pin Functions Host-I/F LBus LBus LBus LBus LBus ADBus External data bus width 32 External SRAM size 64 MB 64 MB 128 KB 32 MB 64 MB – Video Outputs 1 Video Input ITU RGB/ITU RGB/ITU Pin number Option 7a Option 7b Option 7c Option 7d Option 7e...
Page 63 Pin Functions Chapter 2 Host-I/F LBus LBus LBus LBus LBus ADBus External data bus width 32 External SRAM size 64 MB 64 MB 128 KB 32 MB 64 MB – Video Outputs 1 Video Input ITU RGB/ITU RGB/ITU Pin number Option 7a Option 7b Option 7c Option 7d Option 7e...
Page 64 Chapter 2 Pin Functions Host-I/F LBus LBus LBus LBus LBus ADBus External data bus width 32 External SRAM size 64 MB 64 MB 128 KB 32 MB 64 MB – Video Outputs 1 Video Input ITU RGB/ITU RGB/ITU Pin number Option 7a Option 7b Option 7c Option 7d Option 7e...
Page 65 Pin Functions Chapter 2 Host-I/F LBus LBus LBus LBus LBus ADBus External data bus width 32 External SRAM size 64 MB 64 MB 128 KB 32 MB 64 MB – Video Outputs 1 Video Input ITU RGB/ITU RGB/ITU Pin number Option 7a Option 7b Option 7c Option 7d Option 7e...
Page 66 Chapter 2 Pin Functions Host-I/F LBus LBus LBus LBus LBus ADBus External data bus width 32 External SRAM size 64 MB 64 MB 128 KB 32 MB 64 MB – Video Outputs 1 Video Input ITU RGB/ITU RGB/ITU Pin number Option 7a Option 7b Option 7c Option 7d Option 7e...
Page 67: Recommended Connection Of Unused Pins
Pin Functions Chapter 2 2.5 Recommended Connection of unused Pins In this section recommendations are given how to treat pins, which are not used in an application. The tables give recommended connnections of unused pin for all Ravin-M pinout options as well as for Ravin-L in the last table. "Signal"...
Page 68 Chapter 2 Pin Functions Ravin-M Option 1 Option 2 Option 3 Option 6a Signal Unused Signal Unused Signal Unused Signal Unused VO0CLK open VO0CLK open VO0CLK open VO0CLK open MD23 open MA15 open MD23 open VO1G2 open MD22 open MA14 open MD22 open...
Page 69 Pin Functions Chapter 2 Ravin-M Option 1 Option 2 Option 3 Option 6a Signal Unused Signal Unused Signal Unused Signal Unused MD14 open MD14 open MD14 open MD14 open MD13 open MD13 open MD13 open MD13 open MD12 open MD12 open MD12 open...
Page 70 Chapter 2 Pin Functions Ravin-M Option 1 Option 2 Option 3 Option 6a Signal Unused Signal Unused Signal Unused Signal Unused VIR5_ITU5 VIR5_ITU5 VIR5_ITU5 VIR5_ITU5 VIR4_ITU4 VIR4_ITU4 VIR4_ITU4 VIR4_ITU4 VIR3_ITU3 VIR3_ITU3 VIR3_ITU3 VIR3_ITU3 VIR2_ITU2 VIR2_ITU2 VIR2_ITU2 VIR2_ITU2 DVDD33 DVDD33 DVDD33 DVDD33 DGND33 DGND33...
Page 71 Pin Functions Chapter 2 Ravin-M Option 1 Option 2 Option 3 Option 6a Signal Unused Signal Unused Signal Unused Signal Unused HADD14 open HADD14 open MA14 open HADD14 open HADD13 open HADD13 open MA13 open HADD13 open MA12 open MA12 open MA12 open...
Page 72 Chapter 2 Pin Functions Ravin-M Option 1 Option 2 Option 3 Option 6a Signal Unused Signal Unused Signal Unused Signal Unused VO0G0 open VO0G0 open VO0G0 open VO0G0 open VO0G1 open VO0G1 open VO0G1 open VO0G1 open VO0G2 open VO0G2 open VO0G2 open...
Page 73 Pin Functions Chapter 2 Ravin-M Option 6b Option 7a Option 7b Option 7c Signal Unused Signal Unused Signal Unused Signal Unused open open open open MDA10PC open MDA10PC open MDA10PC open MDA10PC open MDBA1 open MDBA1 open MDBA1 open MDBA1 open MDBA0 open...
Page 74 Chapter 2 Pin Functions Ravin-M Option 6b Option 7a Option 7b Option 7c Signal Unused Signal Unused Signal Unused Signal Unused open open open open open open open open open open open open DGND33 DGND33 DGND33 DGND33 DVDD33 DVDD33 DVDD33 DVDD33 open open...
Page 75 Pin Functions Chapter 2 Ravin-M Option 6b Option 7a Option 7b Option 7c Signal Unused Signal Unused Signal Unused Signal Unused HADA13 open MSBEN0 open MSBEN0 open MSBEN0 open DGND33 DGND33 DGND33 DGND33 DVDD33 DVDD33 DVDD33 DVDD33 HADA12 open MA21 open MA21 open...
Page 76 Chapter 2 Pin Functions Ravin-M Option 6b Option 7a Option 7b Option 7c Signal Unused Signal Unused Signal Unused Signal Unused HADD0 open HLBD0 open HLBD0 open HLBD0 open HADRD open HLBRD open HLBRD open HLBRD open HADWR open HLBWR open HLBWR open...
Page 77 Pin Functions Chapter 2 Ravin-M Ravin-L Option 7d Option 7e Option 9 Signal Unused Signal Unused Signal Unused Signal Unused VO0B4 open VO0B4 open VO0B4 open VO0B4 open VO0B5 open VO0B5 open VO0B5 open VO0B5 open VO0HSYNC open VO0HSYNC open VO0HSYNC open VO0HSYNC open VO0VSYNC open...
Page 78 Chapter 2 Pin Functions Ravin-M Ravin-L Option 7d Option 7e Option 9 Signal Unused Signal Unused Signal Unused Signal Unused open open open open open open DVDD33 DVDD33 DVDD33 DVDD33 DGND33 DGND33 DGND33 DGND33 MD15 open MD15 open MD15 open MD15 MD14 open...
Page 79 Pin Functions Chapter 2 Ravin-M Ravin-L Option 7d Option 7e Option 9 Signal Unused Signal Unused Signal Unused Signal Unused MD25 open MD25 open MD25 open unused MD24 open MD24 open MD24 open unused VO1R4 open VO1R4 open VI0G3 unused VO1R3 open VO1R3...
Page 80 Chapter 2 Pin Functions Ravin-M Ravin-L Option 7d Option 7e Option 9 Signal Unused Signal Unused Signal Unused Signal Unused VO0EN open MA24 open VO0EN open VO0EN HINT HINT HINT HINT DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 DVDD33 DVDD33 DVDD33 DVDD33...
Page 81 Pin Functions Chapter 2 Ravin-M Ravin-L Option 7d Option 7e Option 9 Signal Unused Signal Unused Signal Unused Signal Unused VO0R2 open VO0R2 open VO0R2 open VO0R2 open VO0R3 open VO0R3 open VO0R3 open VO0R3 open VO0R4 open VO0R4 open VO0R4 open VO0R4...
Page 82: Pin States With Respect To Reset
Chapter 2 Pin Functions 2.6 Pin States with Respect to Reset Any reset (external RESET, internal S/W reset SWRESET, Watchdog reset WDRESET) re-initializes the pin functions to those chosen by the boot mode function pin option MODE[3:0]. Note that groups of internal pull-up resistors are activated, depending on the pinout option MODE[3:0].
Page 83: Chapter 3 Memory And Register Map
Chapter 3 Memory and Register Map This chapter describes the address ranges of the various Ravin-L and Ravin-M modules. From the external Host CPUs' perspective all modules appear in a single 4 GByte address map, though internally either the APB or AHB is used for accessing the respective module.
Page 84 Chapter 3 Memory and Register Map Address range Target 0000 0900 to 0000 1CFF Reserved 0000 1D00 to 0000 1DFF Drawing Engine registers 0000 1E00 to 0000 1FFF Reserved 0000 2000 to 0000 2FFF Video Output 0 0000 3000 to 0000 3FFF Memory Controller registers 0000 4000 to 0000 4FFF...
Page 85: Ravin-M Memory And Register Map
Memory and Register Map Chapter 3 3.2 Ravin-M Memory and Register Map The memory and register map and the AHB masters priorities of Ravin-M are shown in tables below. Table 3-4 Ravin-M memory and register map Address range Target Host-I/F module 0000 0000 to 0000 002F Host-I/F registers...
Page 86: Chapter 4 System Controller
Chapter 4 System Controller Register base All System Controller register addresses are given as address offsets to the base addresses address <SysC_Base>. The <SysC_Base> address of the System Controller is given in the following table: System Controller <SysC_Base> address 0000 0800 SysC Preliminary User's Manual S19203EE1V3UM00...
Page 87: Functional Overview
System Controller Chapter 4 4.1 Functional Overview The System Controller incorporates several functional blocks to generate reset and clock signals. It further evaluates the settings of the external mode signals MODE[11:0] and configures the start up configurations of the clock generator and the pin multiplexers accordingly.
Page 88: Clock Generator
Chapter 4 System Controller 4.2 Clock Generator By use of the external resonator, connected to the XT1/XT2 pins, the oscillator generates the clock CLKIN, that is input to the spread spectrum PLL. The PLL output clock PLLCLKOUT is the source of various clocks, provided to other modules: •...
Page 89: Pll Configuration
System Controller Chapter 4 4.2.1 PLL configuration The PLL is configured by a set of parameters, derived from the SYSPLLCTRL register. The frequency of PLLCLKOUT is calculated as follows: x (n/m) x 1/2 PLLCLKOUT CLKIN The values n, m, p are derived from SYSPLLCTRL register bits: •...
Page 90: Main System Clock
Chapter 4 System Controller 4.2.2 Main system clock The main system clock HCLK is formed by dividing the PLL output clock PLLCLKOUT by the HCLK divider. The divisor of the HCLK divider is defined by SYSCLKCTRL.BUSDIV[1:0]. The frequency of HCLK is calculated as follows: / (BUSDIV[1:0]+1) HCLK PLLCLKOUT...
Page 91: Resets
System Controller Chapter 4 4.3 Resets The graphics controller provides the following four reset sources: • external RESET • user reset via the control bit SYSRESET.PLLRESET • user reset via the control bit SYSRESET.SWRESET • system watchdog reset WDRESET The different resets act on different targets: System reset A system reset is applied to all modules except the clock generator circuitry.
Page 92: Pll Restart
Chapter 4 System Controller PLL reset Reset System SYSCLKCTRL Purpose SYSPLLCTRL source reset reset reset restart SYSRESET. reset of all system functions with SWRESET continuing clock operation WDRESET Synchronization After any reset has been applied the graphics controller is not operable for a certain time, which depends on the reset source.
Page 93: Software And Watchdog Reset
System Controller Chapter 4 At the end of T the reset interrupt RESINT is asserted, which has to be PLLSTART cleared by the Host CPU. 4.3.2 Software and Watchdog reset The user's software reset SWREST is asserted by setting SYSRESET.SWRESET = 1, while the Watchdog reset WDRESET is triggered by the System Watchdog.
Page 94: System Watchdog
Chapter 4 System Controller 4.4 System Watchdog In case the ADBus Host-I/F is used, a continuous assertion of the ADWAIT signal would block the Host CPU. The System Watchdog detects such situation and recovers from a possible stalled system. For this reason the external ADWAIT signal is monitored and in case it is asserted for more than 325 HCLK clocks the System Watchdog reset WDRESET is asserted.
Page 95: Video Input Control
System Controller Chapter 4 4.5.3 Video Input control The Video Input module control register SYSVIEN provides control bits to en- and disable the Video Input module and to active on-chip loop-back functions. 4.5.3.1 Video Input enable Prior using the Video Input module it has to be enabled. This is done by •...
Page 96 Chapter 4 System Controller SYSVIEN.VISEL[1:0] Video Output (Ravin-M only) Video Output Video Input Low level signals external Video Input I/F Figure 4-7 Loop-back circuit block diagram Loop-back options Since the Video Input as well as the Video Output modules provide several configuration options with respect to the video data format, synchronization signals and data clock phases, the settings of both modules must match in order to capture safely the Video Output data.
Page 97: Video Output Control
System Controller Chapter 4 Option Video Input settings Video Output settings • VOnLCDTIMING2.IHS = 0 VOnLCDTIMING2.IVS = 0 VInCONTROL.SYNCSEL[1:0] = 10 high active (CSYNC) VInCONTROL.SYNCINV = 0 • VOnLCDTIMING2.IHS = 1 VOnLCDTIMING2.IVS = 1 • VOnLCDTIMING2.IHS = 0 VOnLCDTIMING2.IVS = 1 VInCONTROL.SYNCSEL[1:0] = 10 low active (CSYNC)
Page 98: Boot Mode Function
Chapter 4 System Controller Video Output bus locking can be en- or disabled by: • SYSVOCTRL.VOnLOCKEN = 0: bus locking disabled • SYSVOCTRL.VOnLOCKEN = 1: bus locking enabled After release of RESET SYSVOCTRL.VOnLOCKEN is set to "0", thus bus locking is disabled.
Page 99 System Controller Chapter 4 Refer also to the description of the SYSBOOTMODE, SYSPLLCTRL and SYSCLKCTRL registers. MODE7 SDRAM enable MODE7 is used to enable the external SDRAM interface after RESET release. MODE7 is stored in SYSBOOTMODE.BOOTMODE7 and is used to set the reset value of the SYSCLKCTRL.SDREN bit.
Page 100: System Controller Registers
Chapter 4 System Controller 4.7 System Controller Registers 4.7.1 System Controller registers overview The System Controller is controlled and operated by means of the following registers: Table 4-4 System Controller registers overview Register function Name Address <SysC_Base> + 00 PLL control register SYSPLLCTRL <SysC_Base>...
Page 101: System Controller Registers Details
System Controller Chapter 4 4.7.3 System Controller registers details 4.7.3.1 SYSPLLCTRL - PLL control register This register controls the parameters of the PLL. The reset value depends on the boot mode, selected by MODE[5:4] after release of RESET. By this four different PLL default configurations can be chosen by setting of the external pins, refer to Table 4-7 .
Page 102 Chapter 4 System Controller Table 4-5 PLL output clock configuration PLLCLKOUT NDIV[6:0] n = NDIV + 1 MDIV[6:0] m = MDIV + 1 PDIV[1:0] p = PDIV [MHz} 0000000 0000000 invalid invalid 100 - 160 1011011 1011100 0000001 50 - 100 1011101 0000010 25 - 50...
Page 103 System Controller Chapter 4 Assumed f Resulting f MODE[5:4] SYSPLLCTRL reset value CLKIN PLLCKOUT 160 MHz B510 5F0B (dithering on: 20 MHz (NDIV=95, MDIV=11, PDIV=0, PC=1, modulation frequency 45 - 65 KHz, ADJ=5, MDL=3, S=2) dither range ca. 5%) Preliminary User's Manual S19203EE1V3UM00...
Page 104 Chapter 4 System Controller 4.7.3.2 SYSCLKCTRL - Clock control register This register defines the division factors for the main system clock HCLK and Video Output clocks VO0CLK/VO1CLK. It further allows to en-/disable the clock of the external SDRAM and, in case of Ravin-L, the internal SRAM.
Page 105 System Controller Chapter 4 Bit name Function Divider for the main system clock HCLK HCLK PLLCLKOUT 9 to 8 BUSDIV[1:0] HCLK PLLCLKOUT HCLK PLLCLKOUT HCLK PLLCLKOUT Divider for Video Output clock VO0CLK VO0CLK PLLCLKOUT 5 to 0 VO0DIV[5:0] VO0CLK PLLCLKOUT / 63 VO0CLK PLLCLKOUT...
Page 106 Chapter 4 System Controller IRAMCLKEN default The IRAMCLKEN default value is subject to the boot mode function and takes on (Ravin-L only) the level of MODE9 at RESET release: • MODE9 = 0 IRAMCLKEN = 0: internal SRAM disabled after RESET •...
Page 107 System Controller Chapter 4 4.7.3.3 SYSRESET - Reset control register This register allows to reset the graphics controller. If a "1" is written to either the PLLRESET or SWRESET bit the reset is performed and consequently the graphics controller will not be accessible until returning from reset state.
Page 108 Chapter 4 System Controller 4.7.3.4 SYSBOOTMODE - Boot mode register This register stores the levels of the pins MODE[11:0] upon release of the external reset RESET. Access This register can be read in 32-bit units. Address <SysC_Base> + 0C Initial Value 0000 0MMM with MMM = level of MODE[11:0] pins at reset release BOOT...
Page 109 System Controller Chapter 4 4.7.3.5 SYSREV - System Controller revision register This register shows the revision of the System Controller. Access This register can be read in 32-bit units. Address <SysC_Base> + 10 Initial Value 0000 0001 . This register is never modified. MAJOR MINOR Bit name...
Page 110 Chapter 4 System Controller 4.7.3.6 SYSPINMUX - Pin multiplex control register This register controls the pin multiplexer pinout options and the internal pull-up resistors of pin groups 0 to 7. It further provides control of the SMUXm multiplexers for some pins. For a detailed description of pinout options refer to the chapter "Pin Functions".
Page 111 System Controller Chapter 4 Bit name Function Internal pull-up resistor control of pin group 2: pins 127, 132 - 134, 137 - 141 BUFPUEN2 0 internal pull-up disabled 1 internal pull-up enabled Internal pull-up resistor control of pin group 1: pins 102, 144 -151 BUFPUEN1 0 internal pull-up disabled 1 internal pull-up enabled...
Page 112 Chapter 4 System Controller Bit name Function PINMUX[3:0] Pin multiplex option 0001 0010 0011 0110 0111 1001 all other settings prohibited Caution When changing PINMUX[3:0] or any SMUX bit make sure that the related interfaces are not active at the time of change and 50 ns after the change. When changing PINMUX[3:0] it is recommended to issue a software reset by SYSRESET.SWRESET = 1 afterwards.
Page 113 System Controller Chapter 4 Table 4-13 Ravin-L SYSPINMUX reset values SYSPINMUX.BUFPUEN SYSBOOTMODE. SYSPINMUX BOOTMODE9 reset value 00ED 0000 00FD 0000 Preliminary User's Manual S19203EE1V3UM00...
Page 114 Chapter 4 System Controller 4.7.3.7 SYSVIEN - Video Input enable control register This register specifies the source of the Video Input data and enables Video Input. Access This register can be read/written in 32-bit units. Address <SysC_Base> + 20 Initial Value 0000 0000 .
Page 115 System Controller Chapter 4 4.7.3.8 SYSVOCTRL - Video Output control register This register • controls the function of the VOnVSYNC pin to output VOnVSYNC or VOnEN • controls the function of the VOnHSYNC pin to output VOnHSYNC or VOnCSYN • enables/disables the AHB HLOCK function •...
Page 116 Chapter 4 System Controller Bit name Function 1 HLOCK generation enabled Enables the RAM palette in Video Output 0 VO0RAMEN 0 RAM palette disabled 1 RAM palette enabled Controls generation of composite (VO0CSYNC) or separate (VO0HSYNC/VO0VSYNC) synchronization signals of Video Output 0 CSYNCSEL0 0 VO0HSYNC/VO0VSYNC 1 VO0CSYNC via VO0HSYNC...
Page 117 System Controller Chapter 4 4.7.3.9 SYSWDCTRL - System Watchdog control register This register controls the operation of the System Watchdog. Access This register can be read/written in 32-bit units. Address <SysC_Base> + 28 Initial Value 0000 0000 . This register is initialized by any reset. WAIT Writing to the read-only bits is ignored, reading returns undefined values.
Page 118 Chapter 4 System Controller 4.7.3.10 SYSPROTECT - System control write protection register This register disables the System Controller registers write protection for a single write access, hence protecting the System Controller registers against unintentional write accesses. Before writing to any System Controller register SYSPROTECT must be written with 0000 00A5 .
Page 119: Chapter 5 Host Cpu Interface
Chapter 5 Host CPU Interface Ravin-M pin The availability of Host CPU I/F at external pins depend on the selected Ravin-M functions pinout option. Table 5-1 Host CPU I/F Ravin-M pinout options Ravin-M pinout option Signal 1, 2, 6 3, 7, 9 ADBus LBus HADA[20:0]...
Page 120 Chapter 5 Host CPU Interface Interrupt HOSTINTFLAG.INTINn Group Number Name Cause not used — INTIN11 not used — INTIN12 not used — INTIN13 not used — INTIN14 not used — INTIN15 VO0FUFINT Video Output 0 FIFO underflow INTIN16 VO0NBAINT Video Output 0 next base address INTIN17 VO0VCPINT Video Output 0 vertical compare...
Page 121 Host CPU Interface Chapter 5 Interrupt HOSTINTFLAG.INTINn Group Number Name Cause VO0FUFINT Video Output 0 FIFO underflow INTIN16 VO0NBAINT Video Output 0 next base address INTIN17 VO0VCPINT Video Output 0 vertical compare INTIN18 not used — INTIN19 not used — INTIN20 DRWINT Drawing Engine common interrupt...
Page 122: Functional Overview
Chapter 5 Host CPU Interface 5.1 Functional Overview External busses The Host-I/F offers the choice between two asynchronous external interfaces: • LBus-I/F: 8-bit interface without address signals The communication via the LBus-I/F uses a kind of protocol to transfer address information and data in a sequentiell manner. •...
Page 123: Lbus Interface
Host CPU Interface Chapter 5 HADA[20:0] HLBD[7:0] HLBWR HLBDRQ HADD[15:0] HADWR HADWAIT HINT HADCS HADRD HADBEN[1:0] HLBCS HLBRD LBus-I/F ADBus-I/F Interrupt controller iDATA[31:0] iADDR[27:0] Host-I/F interrutps Address decoder Host-I/F registers HIFSEL HCLK Group A Group B interrutps interrutps Figure 5-1 Host-I/F block diagram 5.2 LBus Interface The LBus-I/F achieves minimum signal count to the Host CPU by using only an...
Page 124: Lbus-I/F Addressing Modes
Chapter 5 Host CPU Interface The principle timing of the LBus-I/F is shown in the following diagram. LBCS LBWR LBRD LBD[7:0] Read data LBD[7:0] Write data Figure 5-2 LBus-I/F principle timing Note For information concerning the exact timing requirements refer to the Preliminary Data Sheet.
Page 125: Lbus-I/F Protocol
Host CPU Interface Chapter 5 This mode features an auto-increment function of the address during the data transfers. The 6-byte command eeBstCfg defines the 28-bit start address and the burst length (1 to 2 transfers). The length of a single data unit is fixed to word. Hence a maximum of 256 KB can be transferred in burst addressing mode.
Page 126: Mode
Chapter 5 Host CPU Interface 5.2.3.1 eeShortOffs command This command sets the upper 12 address bits of the address in short addressing mode. SHADDOFF[11:0] are used as ADD[23:12] during a eeShort access. Byte 2nd byte 1st byte Content SHADDOFF[11:4] SHADDOFF[3:0] Parameters •...
Page 127 Host CPU Interface Chapter 5 5.2.3.2 eeShort command This command initiates a data access in short (24-bit) addressing mode. The address ADD[27:0] that is accessed with eeShort is calculated as follows: ADD[27:0] = 0x0FF FFFF & ( (SHADDOFF[11:0] << 12) or LADD[11:0] ) Byte 2nd byte 1st byte...
Page 128 Chapter 5 Host CPU Interface 5.2.3.3 eeLong command This command initiates data access in long (28-bit) addressing mode and defines the access address ADD[27:0]. Byte 2nd byte 1st byte Content ADD[11:4] ADD[3:0] L[1:0] Byte 4th byte 3rd byte Content ADD[27:20] ADD[19:12] Parameters •...
Page 129 Host CPU Interface Chapter 5 5.2.3.4 eeBstCfg command This command prepares and starts a burst access. The burst length can be defined in the range of 1 to 2 The number of data bytes per burst transfer is fixed to 4, i.e. burst transfers always perform word accesses.
Page 130 Chapter 5 Host CPU Interface 5.2.3.5 eeNOP command This command performs no operation. Byte 1st byte Content command eeNOP transfer Figure 5-7 eeNOP command flow This command can be used to stuff bytes in case of any unaligned number of bytes when using DMA transfers.
Page 131 Host CPU Interface Chapter 5 5.2.3.6 Illegal interruption of the command-data flow The Host CPU has strictly to follow the above defined command-data flow schemes. In case the Host CPU applies erroneous read-write sequences, the LBus-I/F reacts as follows: The Host CPU issues a read access while the LBus-I/F expects a write The LBus-I/F returns the contents of the HOSTSTATUS register to the Host CPU and resets its internal command-data flow mechanism.
Page 132: Lbus-I/F Dma Request
Chapter 5 Host CPU Interface 5.2.4 LBus-I/F DMA request The LBus-I/F generates the signal HLBDRQ to request the next data transfer. HLBDRQ can be used as a DMA trigger signal on the Host CPU side in order to handle data transfers with minimum Host CPU load. Caution The DMA request generation operates only for word transfers.
Page 133: Adbus Interface
Host CPU Interface Chapter 5 remainders of the interrupted DMA transfer have to be transferred by a new DMA process. 5.3 ADBus Interface The ADBus-I/F delivers high data bandwidth by using the separate 16-bit data bus HADD[15:0] and 21-bit address bus HADA[20:0]. The address range is extended to 28 bit by offset addressing via four base address registers, thus giving immediate access to four 512 KB pages.
Page 134: Adbus-I/F Data Access
Chapter 5 Host CPU Interface - if HADA[20:19] = 0 and HADA[18:13] = 0: iADDR[27:0] = (0<<19) or HADA[18:0] (Host-I/F registers or APB) - if HADA[20:19] = 0 and HADA[18:13] ≠ 0: iADDR[27:0] = (BASEADDR0<<19) or HADA[18:0] (AHB) - if HADA[20:19] ≠ 0: iADDR[27:0] = (BASEADDRn<<19) or HADA[18:0] (AHB, n = 1 to 3) The table below summarizes the behaviour of the offset addressing function.
Page 135 Host CPU Interface Chapter 5 • first half-word accesses on word aligned address, i.e. HADBEN [1:0] = 00 , HADA[1:0] = 00 • second half-word on next halfword address, i.e. HADBEN[1:0] = , HADA[1:0] = 10 Combined write access If a ADBus write is performed with HADBEN[1:0] = 00 and HADA[1:0] = 00 , it is assumed to be the first half-word of a word write.
Page 136: Adbus-I/F Principle Timing
Chapter 5 Host CPU Interface 5.3.4 ADBus-I/F principle timing Generation of HADWAIT The wait signal HADWAIT requests the Host CPU to extend the bus timing in case the ADBus-I/F is still busy transferring the data internally. The Host CPU should sample the HADWAIT signal and stretch the access cycle upon demand, until the ADBus-I/F indicates ready status by de-assertion of HADWAIT.
Page 137 Host CPU Interface Chapter 5 ADBus principle read-write timing HADA[20:0] Address1 Address2 HADCS HADRD HADD[15:0] Read Data HADWR HADD[15:0] Write Data HADWAIT Figure 5-9 ADBus principle read-write timing HADWAIT falling edge because of HADCS falling edge HADWAIT rising edge after HADRD/HADWR falling edge HADWAIT falling edge after HADRD/HADWR rising edge HADWAIT rising edge because of HADCS rising edge Preliminary User's Manual S19203EE1V3UM00...
Page 138 Chapter 5 Host CPU Interface ADBus principle write timing with wait HADA[20:0] Address1 Address2 HADCS HADWR HADD[15:0] Write Data Write Data HADWAIT Figure 5-10 ADBus principle write timing with wait HADWAIT falling edge because of HADCS falling edge HADWAIT rising edge after HADWR falling edge HADWAIT falling edge after HADWR rising edge delayed HADWAIT rising edge after HADWR falling edge and wait time...
Page 139: Address Alignment
Host CPU Interface Chapter 5 ADBus principle read timing with wait HADA[20:0] Address1 Address2 HADCS HADRD HADD[15:0] Read Data Read Data HADWAIT Figure 5-11 ADBus principle read timing with wait HADWAIT falling edge because of HADCS falling edge HADWAIT rising edge after HADRD falling edge HADWAIT falling edge after HADRD rising edge delayed HADWAIT rising edge after HADRD falling edge and wait time...
Page 140: Interrupt Controller
Chapter 5 Host CPU Interface 5.5 Interrupt Controller The Host-I/F interrupt controller handles a total number of 32 interrupt signals, three of which are generated by the Host-I/F itself and the other 29 interrupts are generated by other functional blocks. The interrupt controller is operated by means of three registers: •...
Page 141 Host CPU Interface Chapter 5 HOSTINTENAB The HOSTINTENAB register applies an enable/mask bit HOSTINTENAB.INTENn to each interrupt signal. An interrupt event signal INTINn is only activated if its associated enable bit HOSTINTENAB.INTENn is 1. HOSTINTSTAT The HOSTINTSTAT.INTSTAT[31:0] bits reflect the status of all active and enabled - i.e.
Page 142: Ahb Master Status And Interrupts
Chapter 5 Host CPU Interface 5.6 AHB Master Status and Interrupts The Host-I/F accesses the AHB as a bus master. Since the AHB is a multi-master bus an arbiter grants access to the bus only to one master at a time. In order to make the status of the AHB transparent to the Host CPU, some information are provided in form of status information and interrupts.
Page 143: Host-I/F Registers
Host CPU Interface Chapter 5 5.7 Host-I/F Registers 5.7.1 Host-I/F registers overview The Host CPU I/F is controlled and operated by means of the following registers: Table 5-6 System Controller registers overview Register function Name Address 0000 0000 Host-I/F status register HOSTSTATUS HOSTVERSION 0000 000C Host-I/F version register...
Page 144: Host-I/F Registers Details
Chapter 5 Host CPU Interface 5.7.2 Host-I/F registers details 5.7.2.1 HOSTSTATUS - Host-I/F status register This register holds various status information. Access This register can be read in 8-bit, 16-bit and 32-bit units. If this register is read in 16-bit or 32-bit units the upper bits 15 to 8, respectively 31 to 8, return undefined values.
Page 145 Host CPU Interface Chapter 5 5.7.2.2 HOSTVERSION - Host-I/F version register This register returns the revision number of the Host CPU I/F. Access This register can be read in 8-bit, 16-bit and 32-bit units. If this register is read 16-bit or 32-bit units the upper bits 15 to 8, respectively 31 to 8, return undefined values.
Page 146 Chapter 5 Host CPU Interface 5.7.2.3 HOSTINTSTAT - Interrupt status register This register shows the status of the interrupt n. Interrupt n The available interrupt of this device are defined in the first section of this chapter under the key word "Interrupts". Access This register can be read in 32-bit units.
Page 147 Host CPU Interface Chapter 5 5.7.2.4 HOSTINTENAB - Interrupt enable register The interrupt enable register enables or masks the interrupt n. Interrupt n The available interrupt of this device are defined in the first section of this chapter under the key word "Interrupts". Access This register can be read/written in 32-bit units.
Page 148 Chapter 5 Host CPU Interface 5.7.2.5 HOSTINTFLAG - Interrupt input register The interrupt enable register enables or masks the interrupt n. Interrupt n The available interrupt of this device are defined in the first section of this chapter under the key word "Interrupts". The interrupt status bits of the two interrupt groups are treated differenctly: •...
Page 149 Host CPU Interface Chapter 5 5.7.2.6 HOSTCONTROL - Host-I/F DMA control register This register controls the function of the DMA request control. Access This register can be read/written in 8-bit, 16-bit and 32-bit units. If this register is read in 16-bit or 32-bit units the upper bits 15 to 8, respectively 31 to 8, return undefined values.
Page 150 Chapter 5 Host CPU Interface 5.7.2.7 HOSTADBASEn - ADBus base registers These registers set the base address for accesses through the ADBus interface and controls the word combining function. Access These registers can be read/written in 16-bit and 32-bit units. If these registers are read in 32-bit units the upper bits 31 to 8 return undefined values.
Page 151: Chapter 6 Video Input (Ravin-M Only)
Chapter 6 Video Input (Ravin-M only) Instances The Ravin-M has one instance of the Video Input I/F. Video Output Ravin-M Instance Name Instances index n Throughout this chapter, the instance of a Video Input I/F is identified by the index "n"...
Page 152: Functional Overview
Chapter 6 Video Input (Ravin-M only) 6.1 Functional Overview The Video Input module provides following features: • support of different video data formats: RGB(565) RGB(666) YUV(4:2:2) in Y1:U:Y2:V or U:Y1:V:Y2 order progressive scan supported interlaced scan supported (both fields stored in separate framebuffers) •...
Page 153 Video Input (Ravin-M only) Chapter 6 YUV(4:2:2) VInR[5:0]ITUn[5:0] YUV(4:2:2) YUV(4:4:4) VInG[1:0]ITUn[7:6] adjustment VInG[5:2] Data control YUV(4:4:4) VInB[5:0] Sync extraction VInSYNC1 RGB(666) YUV(4:4:4) VInSYNC2 VInCLK RGB(666) YUV(4:4:4) RGB(888) RGB(888) RGB(888) Scale 32 bit 32 bit Dithering FIFO RGB(888) RGB(565) crop VI0FFOINT VI0AHEINT VI0SCLINT Figure 6-1...
Page 154: Data Format And Synchronization
Chapter 6 Video Input (Ravin-M only) FIFO The RGB(565) data is intermediately stored in an 32-bit x 32-bit FIFO, thus holding the data of 64 pixels, which are transfered to the framebuffer via the AHB as a single burst. Interrupts The Video Input module generates three interrupts: VI0FFOINT (FIFO overflow), VI0AHEINT (AHB error) and VI0SCLINT (scanline).
Page 155: Rgb Data Input
Video Input (Ravin-M only) Chapter 6 The ITU-R656 conform Video Input decodes the embedded synchronization signal information in the data stream. According to this specification the input scans for the sequence FF , 00 , 00 and the fourth byte is then the timing reference code, which is either SAV (Start of Active Video) or an EAV (End of Active Video).
Page 156: Synchronization Status Information
Chapter 6 Video Input (Ravin-M only) The values VInSYNCDECODE.14SCN[9:0] and VInSYNCDECODE.34SCN[9:0] are described in pixel clocks. By use of these signals a internal "middle of scanline" signal is generated and HSYNC, VSYNC and the field information are derived. Caution Even if separate horizontal and vertical synchronization signals are supplied externally (VInCONTROL.SYNCSEL[1:0] = 10 ), the synchronization separator timing in VInSYNCDECODE has to be set correctly.
Page 157: Start And Stop Of Video Capturing
Video Input (Ravin-M only) Chapter 6 Further no scanline interrupt VInSCLINT, caused by any first field interrupt, will be generated. Interlaced video In case an interlaced scanned video is detected, the video data is stored in two separate framebuffers, depending on the field: •...
Page 158: Scaling, Cropping And Storing
Chapter 6 Video Input (Ravin-M only) 6.4 Scaling, Cropping and Storing The scale and crop unit allows to define a rectangle area of an incoming frame to be captured. Afterwards the captured area can be resized in x- and y-direction independently. Finally the video data is stored via a FIFO in the framebuffer.
Page 159: Cropping
Video Input (Ravin-M only) Chapter 6 6.4.1 Cropping Two counters are used to identify the pixel in each line and the line in each field: • The pixel counter PXCNT counts the pixels of each scanline. The counter is reset to 0 at the beginning of each new scanline, i.e. with each HSYNC.
Page 160: Scaling
Chapter 6 Video Input (Ravin-M only) 6.4.2 Scaling The captured image content is passed on to a scaler unit, that features independent scaling of the data in x- and y-direction. The geometry of the scaler output image is defined by the registers •...
Page 161 Video Input (Ravin-M only) Chapter 6 new frame reset y-scaler y = 0 frame end? frame end? y = y +1 xin = 0 y = y +1 line output? line end? reset x-scaler calculate intermediate luminance xin = xin +1 line end? calculate final pixel Pyout[xin]...
Page 162 Chapter 6 Video Input (Ravin-M only) For filtering of the lines to generate the output lines only the luminance values Y of the pixel is regarded. Thus Y is calculated for each pixel and stored in the line buffer Ylinebuf[1023:0]. For the Y calculation the colour components contribute in the relation R:G:B = 1:2:1.
Page 163 Video Input (Ravin-M only) Chapter 6 6.4.2.2 X-scaler The x-scaler allows up- and downscaling of a scanline. The x scaling factor is determined by VInSCALING.MX[6:0] and is calculated as x_scale = VInSCALING.MX[6:0] / 64 MX[6:0] > 64 performs an upscaling, MX < 64 a downscaling. If MX = 0, the x- scaler is disabled.
Page 164: Storing
Chapter 6 Video Input (Ravin-M only) 6.4.3 Storing The scaled 16-bit pixel data in RGB(565) colour format are collected in a FIFO before they are written to the framebuffer. The FIFO is 32-bit wide, thus two RGB (565) values are combined to a single 32-bit word. The framebuffer target addresses are defined in the registers VInSTARTADDR1 and VInSTARTADDR2.
Page 165: Yuv(4:2:2) To Yuv(4:4:4) Conversion
Video Input (Ravin-M only) Chapter 6 Figure 6-7 RGB(565) to RGB(666) conversion RGB(666) to RGB RGB(666) is converted to RGB(888) by appending the MSBs R [5:4], G [5:4], (888) [5:4] as the low order bits: • [7:0] = (R [5:0] << 2) + (R [5:4] >>...
Page 166: Yuv(4:4:4) To Rgb(888) Conversion
Chapter 6 Video Input (Ravin-M only) 6.5.3 YUV(4:4:4) to RGB(888) conversion The YUV(4:4:4) to RGB(888) conversion is done with following formulas: • R = 1.164 • (Y-16) + 1.596 • (V-128) • G = 1.164 • (Y-16) – 0.813 • (V-128) – 0.391 • (U-128) •...
Page 167: Dithering
Video Input (Ravin-M only) Chapter 6 6.7 Dithering The dither units adds random noise to a number of low order bits of each colour value of each RGB(888) pixel colour. The random noise is generated by a pseudo random number generator RNG. The noise is evenly distributed.
Page 168: Framebuffer Addressing
Chapter 6 Video Input (Ravin-M only) Table 6-4 RGB(565) data arrangement FIFO entry bit 31 to 16 bit 15 to 0 pixel 1 pixel 0 pixel 3 pixel 2 pixel 63 pixel 62 Above table reflects also the ordering of the captured Video Input data in the framebuffer.
Page 169: Interrupts
Video Input (Ravin-M only) Chapter 6 base addresses are effectively in use prior rewriting VInSTARTADDR1/ VInSTARTADDR2. For that purpose two status bits are provided to indicate, that the current base addresses have been copied to buffer address registers and the base address registers can be rewritten: •...
Page 170: Interrupt Control
Chapter 6 Video Input (Ravin-M only) When capturing interlaced video the interrupt can be en-/disabled for each field separately (first field, second field or both). In this case the currently captured field number, reflected in VInACTSCANLINE.AFDL, must match the field interrupt enable additionally to the scanline number in order to assert the VOnSCLINT interrupt.
Page 171: Video Input Registers
Video Input (Ravin-M only) Chapter 6 6.10 Video Input Registers 6.10.1 Video Input registers overview The Video Input is controlled and operated by means of the following registers: Table 6-5 Video Input registers overview Register function Name Address <VIn_Base> + 00 First field framebuffer start address register VInSTARTADDR1 Second field framebuffer start address...
Page 172: Video Input Registers Details
Chapter 6 Video Input (Ravin-M only) 6.10.2 Video Input registers details 6.10.2.1 VInCONTROL - Video Input control register This register holds all control bits to operate the Video Input. Access This register can be read/written in 32-bit units. Address <VIn_Base> + 18 Initial Value 0000 0000 .
Page 173 Video Input (Ravin-M only) Chapter 6 Bit name Function Video Input data is taken with rising clock edge of VInCLK Video Input data is taken with falling clock edge of VInCLK Selects Video Input data format RGBEN YUV format RGB format Enable Video Input data capture video capture disabled CAPEN...
Page 174 Chapter 6 Video Input (Ravin-M only) 6.10.2.2 VInSTARTADDR1 - First field framebuffer start address register This register defines the framebuffer address of the first pixel of the first field of each frame. The value becomes effective at the next start of the first field (this can be checked in the VInSTATUS register).
Page 175 Video Input (Ravin-M only) Chapter 6 6.10.2.3 VInSTARTADDR2 - Second field framebuffer start address register This register defines the framebuffer address of the first pixel of the second field of each frame. The value becomes effective at the next start of the first field (this can be checked in the VInSTATUS register).
Page 176 Chapter 6 Video Input (Ravin-M only) 6.10.2.4 VInSCALING - Scaling factors register This register defines the scaling factors of the x- and y-scaler. x-scaler The x-scaler factor calculates to MX[6:0]/64 with MX[6:0] < 64 for downscaling and MX[6:0] > 64 for upscaling. If MX[6:0] = 0 the x-scaler is disabled.
Page 177 Video Input (Ravin-M only) Chapter 6 6.10.2.5 VInSCALEDWIDTH - Scaled pixels/line register This register holds the number of scaled pixels per line to capture in framebuffer. The width must be a multiple of four pixels. Access This register can be read/written in 32-bit units. Address <VIn_Base>...
Page 178 Chapter 6 Video Input (Ravin-M only) 6.10.2.6 VInSCALEDHEIGHT - Scaled lines/field register This register holds the number of scaled lines per field to capture in framebuffer. Access This register can be read/written in 32-bit units. Address <VIn_Base> + 14 Initial Value 0000 0000 .
Page 179 Video Input (Ravin-M only) Chapter 6 6.10.2.7 VInSTARTX - First pixel register This register defines the first valid pixel to process. An internal pixel counter counts all incoming pixels. If this pixel counter equals VInSTARTX, all following pixels of the same scanline are passed on for further processing.
Page 180 Chapter 6 Video Input (Ravin-M only) 6.10.2.8 VInSTARTY - First line register This register defines the first valid scanline of the first and second field to process. An internal line counter counts all incoming lines and is reset with every VSYNC. If this line counter equals STARTY[9:0], all following lines of the same field are passed on for further processing.
Page 181 Video Input (Ravin-M only) Chapter 6 6.10.2.9 VInSTRIDEX - Scanlines offset register This register defines the address offset in byte of the first pixels of two consecutive captured Video Input scanlines. Access This register can be read/written in 32-bit units. Address <VIn_Base>...
Page 182 Chapter 6 Video Input (Ravin-M only) 6.10.2.10 VInADJUSTLEVEL - YUV adjustment control register This register defines the mode of the YUV adjustment unit and the coefficients for the input level adjustment in case YUV input data format is selected. Access This register can be read/written in 32-bit units.
Page 183 Video Input (Ravin-M only) Chapter 6 6.10.2.11 VInSYNCDECODE - CSYNC separator control register This register controls the composite synchronization signal CSYNC separator. Generation of the strobe signals at 1/4 and 3/4 of a scanline can be defined in multiples of 64 pixels. Access This register can be read/written in 32-bit units.
Page 184 Chapter 6 Video Input (Ravin-M only) 6.10.2.12 VInSTATUS - Video Input status register This register summarizes all status information for the Video Input. Access This register can be read in 32-bit units. Address <VIn_Base> + 20 Initial Value 0000 0000 0000 0000 00XX XXXX XXXX 00XX .
Page 185 Video Input (Ravin-M only) Chapter 6 6.10.2.13 VInSCANLINE - Active scanline register This register holds the current unscaled scanline number. It is reset with every VSYNC. Access This register can be read in 32-bit units. Address <VIn_Base> + 24 Initial Value 0000 0000 .
Page 186 Chapter 6 Video Input (Ravin-M only) 6.10.2.14 VInSCANLINEINT - Scanline interrupt control register This register holds the unscaled scanline number at which a Video Input scanline interrupt VInSCLINT is generated. It can be selected for which field the interrupt is asserted (first field, second field or both).
Page 187 Video Input (Ravin-M only) Chapter 6 6.10.2.15 VInREVISION - Video Input revision register This register shows the revision of the Video Input. Access This register can be read in 32-bit units. Address <VIn_Base> + 50 Initial Value 0000 0100 . This register is never modified. MAJOR MINOR Bit name...
Page 188: Chapter 7 Video Output
Chapter 7 Video Output Instances The Ravin-L has one, the Ravin-M two instances of the Video Output I/F. Video Output Ravin-L Ravin-M Instances Name VO0 to VO1 Instances index n Throughout this chapter, the instance of a Video Output I/F is identified by the index "n"...
Page 189 Video Output Chapter 7 Ravin-M pin The availability of Video Output signals at external pins depend on the selected functions Ravin-M pinout option. Table 7-1 Video Output Ravin-M pinout options Ravin-M pinout option Interface Signal 1, 2, 3 6a, 9 6b, 7c VO0R[5:0] √...
Page 190: Functional Overview
Chapter 7 Video Output 7.1 Functional Overview The Video Output module provides following features: • digital interface to TFT displays with up to 18 bpp resolution in RGB (666) format • support of different synchronization signals: composite sync CSYNC separate sync HSYNC and VSYNC selectable polarity of sync signals programmable timing of HSYNC and VSYNC valid VOnCLK data input clock edge selectable...
Page 191: Colour Formats
Video Output Chapter 7 True colour True colour pixel data in 16 bpp RGB(565) or 24 bpp RGB(888) colour format is fetched from the framebuffer, the CLUT is bypassed and the RGB data is immediately output to the external interface. CLUT palette In case of 8 bpp colour data CLUT(8) the 8 bit from the framebuffer addresses one of 256 entries in the CLUT.
Page 192: Display Data Output Formats
Chapter 7 Video Output Due to the 128 x 32 bit organization of the CLUT RAM, two output values are combined to a single RAM word, as shown below. Table 7-2 CLUT palette RAM organization Word 0 colour 1 colour 0 Word 1 colour 3 colour 2...
Page 193: Timing Signals
Video Output Chapter 7 Table 7-4 Display data output formats True colour modes CLUT mode Signal RGB(666) RGB(565) iRGB(1555) LCDBPP[2:0] = 101 LCDBPP[2:0] = 110 LCDBPP[2:0] = 011 VOnB5 VOnB4 VOnB3 VOnB2 VOnB1 VOnB0 undefined VOnG5 VOnG4 VOnG3 VOnG2 VOnG1 VOnG0 VOnR5 VOnR4...
Page 194: Synchronization Signals
Chapter 7 Video Output VOnCLK Video data IPC = 0 Video data IPC = 1 Figure 7-2 VOnCLK timing setting 7.3.2 Synchronization signals The Video Output module generates following synchronization signals: • VOnVSYNC: vertical (frame) synchronization signal VOnVSYNC can generate a video data enable signal VOnEN optionally, controlled by settings in the Video Output control register in the System Controller: SYSVOCTRL.VOnVSSELn = 0: VOnVSYNC output...
Page 195 Video Output Chapter 7 VOnHSYNC The diagram below illustrates the line synchronization timing settings. The video data enable signal VOnEN is derived from the other timing values: VOnEN width in pixels = pixels/line - horizontal (front porch + back porch + sync pulse width) The active level of the VOnHSYNC and VOnEN signals can be defined as follows: •...
Page 196: Dma Fifo And Framebuffer Addressing
Chapter 7 Video Output VOnVSYNC IVS = 0 VOnVSYNC IVS = 1 Active lines LCDVCOMP[1:0] = 10 VOnVCPINT LCDVCOMP[1:0] = 01 LCDVCOMP[1:0] = 00 LCDVCOMP[1:0] = 11 Figure 7-4 VOnVSYNC timing setting VOnCSYNC If the composite synchronization signal VOnCSYNC is selected to be output via VOnHSYNC (SYSVOCTRL.CSYNCSELn = 1), the active level of the horizontal and vertical synchronization signals must be set as follows: •...
Page 197: Fifo Watermark
Video Output Chapter 7 7.4.1 FIFO watermark A watermark level is set such that the FIFO requests data via its DMA function from the framebuffer when at least four locations in the FIFO become available. The watermark level can be configured: •...
Page 198: Interrupt Sources
Chapter 7 Video Output 7.5.1 Interrupt sources The Video Output module generates five interrupts. In the following all interrupts are described. It is assumed that the interrupts are unmasked, hence the raw interrupt generates its corresponding system interrupt. VOnMBEINT Bus error interrupt If the Video Output module attempts to access an undefined address range via the framebuffer base address register VOnLCDUPBASE, the bus error interrupt VOnMBEINT is generated.
Page 199: Interrupt Controller
Video Output Chapter 7 7.5.2 Interrupt controller The diagram below gives an overview about the interrupt controller. Each register of the interrupt controller provides one dedicated bit for each raw interrupt source. The raw interrupts are generated inside the Video Output module. Depending on the interrupt controller configuration a raw interrupt can generate a system interrupt to outside the Video Output module.
Page 200: Start And Stop Of Video Output
Chapter 7 Video Output 7.6 Start and Stop of Video Output For activating the Video Output module signals the bits VOnLCDCONTROL.LCDEN = 1 VOnLCDCONTROL.LCDPWR = 1 have to be set. Start of Video Output The sequence below describes of how to start up the output of display data. Before initialization all Video Output module signals are inactive and output low level.
Page 201: Video Output Registers
Video Output Chapter 7 7.7 Video Output Registers 7.7.1 Video Output registers overview The Video Output is controlled and operated by means of the following registers: Table 7-6 Video Output registers overview Register function Name Address <VOn_Base> + 000 Horizontal axis panel control register VOnLCDTIMING0 <VOn_Base>...
Page 202: Video Output Registers Details
Chapter 7 Video Output 7.7.2 Video Output registers details 7.7.2.1 VOnLCDTIMING0 - Horizontal axis panel control register This register specifies the synchronization and data timining of a line by the following: • horizontal synchronization pulse width in pixels • horizontal front porch width in pixels •...
Page 203 Video Output Chapter 7 7.7.2.2 VOnLCDTIMING1 - Vertical axis panel control register This register specifies the synchronization and data timining of a frame by the following: • vertical synchronization pulse width in lines • vertical front forch width in lines •...
Page 204 Chapter 7 Video Output 7.7.2.3 VOnLCDTIMING2 - Clock and signal polarity control register This register defines various properties of the control signals: • polarity of synchronization and data enable signals • valid edge VOnCLK pixel clock • number of pixel clocks/line Access This register can be read/written in 32-bit units.
Page 205 Video Output Chapter 7 Caution If the composite synchronization signal VOnCSYNC is selected to be output via VOnHSYNC (SYSVOCTRL.CSYNCSELn = 1), the active level of the horizontal and vertical synchronization signals must be set as follows: • VOnCSYNC active at high level if VOnLCDTIMING2.IVS = VOnLCDTIMING2.IVS.IHS, thus VOnLCDTIMING2.IHS = VOnLCDTIMING2.IVS = 0 VOnLCDTIMING2.IHS = VOnLCDTIMING2.IVS = 1...
Page 206 Chapter 7 Video Output 7.7.2.4 VOnLCDCONTROL - Control register This register controls the Video Output operating mode and the pixel parameters. Access This register can be read/written in 32-bit units. Address <VOn_Base> + 018 Initial Value 0000 0000 . This register is initialized by any reset. WATE MARK LCDVCOMP...
Page 207 Video Output Chapter 7 Bit name Function Blue-Red swapped output By setting BGR the display output signals of the blue VOnB[5:0] adn red VOnR[5:0] channels are swapped. RGB output BGR output (VOnB[5:0] and VOnR[5:0] swapped) The default value "0" of this bit must be changed to "1" after reset and must not be altered bit 5 afterwards.
Page 208 Chapter 7 Video Output 7.7.2.5 VOnLCDUPBASE - Framebuffer base address register This register defines the framebuffer base address of the frame to be output. VOnLCDUPBASE holds a byte address, thus the lower two bits must be 00 to 32-bit alignment in the framebuffer. Upon output start of a new display data frame, VOnLCDUPBASE is copied to the current framebuffer address register VOnLCDUPCURR, which is effectively used for addressing the framebuffer during frame output.
Page 209 Video Output Chapter 7 7.7.2.6 VOnLCDUPCURR - Current address register This register contains an approximate value of the currently used pixel data address. This register is loaded with the framebuffer start address, i.e. from VOnLCDUPBASE, with the beginning of each frame output and incremented when the DMA function transfers new data from the framebuffer to the FIFO.
Page 210 Chapter 7 Video Output 7.7.2.7 VOnLCDRIS - Raw interrupt status register This register monitors the status of all raw interrupts. To enable a raw interrupt to generate its corresponding system interrupt it must be unmasked by setting its mask bit in the VOnLCDIMSC register to 1. Access This register can be read in 32-bit units.
Page 211 Video Output Chapter 7 7.7.2.8 VOnLCDIMSC - Interrupt mask register This register contains the mask bits for all raw interrupts. The raw interrupt is enabled (unmasked) to generate the respective system interrupt, when its corresponding mask bit is set to 1. Access This register can be read/written in 32-bit units.
Page 212 Chapter 7 Video Output These registers contain 256 palette entries organized as 128 locations of two entries per word. Each word location contains two palette entries. This means that 128 word locations are used for the palette. Access These registers can be read/written in 32-bit units. Address <VOn_Base>...
Page 213 Video Output Chapter 7 7.7.2.9 VOnLCDICR - Interrupt clear register This register allows to clear a pending system interrupt. The pending system interrupts are monitored in the VOnLCDMIS register. Writing "1" to the respective bit in this register clears its system interrupt and consequently clears also its corresponding bit in VOnLCDMIS.
Page 214 Chapter 7 Video Output 7.7.2.10 VOnLCDMIS - Masked interrupt status register This register monitors the status of all system interrupts. The system interrupts are unmasked (enabled) raw interrupts. The raw interrupts status is shown in the raw interrupt status register VOnLCDRIS. The interrupt status can be changed from pending to inactive by writing a 1 to the corresponding bit in the interrupt clear register VOnLCDICR.
Page 215: Chapter 8 Drawing Engine
Chapter 8 Drawing Engine Indices Throughout this chapter following indices are used: • n = 1 to 6: denotes the limiter number and their dedicated registers • m = 1 to 2: denotes the band limiter number Register base All Drawing Engine register addresses are given as address offsets to the base addresses address <DrwE_Base>.
Page 216: Functional Overview
Chapter 8 Drawing Engine 8.1 Functional Overview The block diagram of the Drawing Engine below shows all components of the module and its interfaces. Registers Performance counters Display list FIFO Display list reader 32 x 32 bit Pixel selection Pixel selection FIFO 128 x 107 bit Texture cache Texture unit...
Page 217: Introduction
Drawing Engine Chapter 8 8.2 Introduction The Drawing Engine built into Ravin is very flexible. It is not bound to support just certain geometries like lines, triangles or circles. Ravin-M supports almost any object geometry. The edges of every object can be blurred or antialiased. This can be set for every edge independently.
Page 218 Chapter 8 Drawing Engine Coordinate transformation Edge setup Texture setup Ravin Antialiased rasterisation Texturing Colorization (rasterop) Blending Memory read Memory write Figure 8-3 Simplified rendering pipeline setup The Drawing Engine also supports the usage of display lists, which makes it possible to decouple CPU and graphics controller efficiently and do rendering in parallel to other CPU activities.
Page 219: Drawing Features
Drawing Engine Chapter 8 8.3 Drawing Features 8.3.1 Drawing features summary 8.3.1.1 Colour formats Supported colour formats are Framebuffer formats • a(8), aCLUT(8) • RGB(565) • RGB(888) • aRGB(4444) Texture formats • a(8), aCLUT(8) • RGB(565) • RGB(888) • aRGB(4444) •...
Page 220: Vector Drawing
Chapter 8 Drawing Engine 8.3.2 Vector drawing For a detailed explanation of the algorithms see the dedicated chapter about the rendering pipeline. Lines • arbitrary width • round endpoints • truncated endpoints • alpha gradients • soft edges (blurring) • render attribute: colour, pattern or texture Polygons •...
Page 221: Bitblt
Drawing Engine Chapter 8 8.3.3 BitBLT There is no need for a dedicated BitBlt unit in the Drawing Engine. The rendering pipeline described for vector drawing is used as BitBLT unit and already provides a 1pixel/cycle throughput. For a more detailed understanding please refer to the dedicated chapter about the rendering pipeline.
Page 222: Bilinear Filtering
Chapter 8 Drawing Engine 8.3.3.6 Bilinear filtering The texture unit can be used to scale, rotate or shear images. The texturing result can be filtered in x- and y-direction independently. When selecting both filters, the result is a bilinear filtered texture. Using the unit two times with two independent textures would generate trilinear filtered bitmaps, improving the visual impression for high dynamic scale ratios.
Page 223: Input And Output Data Formats
Drawing Engine Chapter 8 8.4 Input and Output Data Formats 8.4.1 Source and destination data There are two possible inputs and one possible output. One input is the framebuffer and one input is the texture input or the pattern input. The output is always the framebuffer.
Page 224 Chapter 8 Drawing Engine • 16 bpp RGB(565): The colour format uses 2 byte per pixel with 5 bit for red, 5 bit for blue and 6 bit for green. The blue colour is taken as the alpha channel during colour conversion. This alpha can be substituted with any alpha during the colourization step in the Drawing Engine.
Page 225: Rendering Pipeline
Drawing Engine Chapter 8 8.5 Rendering Pipeline 8.5.1 Coordinate transformation Coordinate transformation as rotation, translation, projection and scaling must be done on the application side. This is not part is the Drawing Engine hardware or driver. As all coordinates fed into the Drawing Engine are in fixed point format these calculations can be done in fixed point format and don’t need a floating point unit.
Page 226 Chapter 8 Drawing Engine The final output is then used as an alpha value. Edge antialiasing can be done with no additional effort with this hardware. To calculate the decision value for the each possible pixel with a limiter the bounding box of the object has to be calculated.
Page 227: Edge Setup Linear Case
Drawing Engine Chapter 8 8.5.3 Edge setup linear case 8.5.3.1 Mathematical background To setup a linear edge you can look at the line equation in the classical form: If you rewrite this you can write it as: ⋅ − ⋅ ⋅...
Page 228 Chapter 8 Drawing Engine   If n is normalized that means if the length of n is 1 then the dot product of       − and n is the projection of − to n and this is the distance d of the point P to the line.
Page 229 Drawing Engine Chapter 8 8.5.3.2 Limiter operation The Drawing Engine contains six limiters. Each limiter contains four registers: • DRWLnSTART • DRWLnXADD • DRWLnYADD The value register is not visible to the user and is just an internal register which is then output.
Page 230 Chapter 8 Drawing Engine 8.5.3.3 Example If a straight line is given by the points P and P then the values are calculated as the following: −   ∆          ∆ −...
Page 231: Edge Setup Quadratic Case
Drawing Engine Chapter 8 8.5.4 Edge setup quadratic case 8.5.4.1 Mathematical background It is also possible to setup the limiters to incrementally calculate the following equation: At the origin the value is like this: The step in x direction is like this: −...
Page 232 Chapter 8 Drawing Engine 8.5.4.2 Limiter operation In the quadratic case two linear limiters are combined to operate as one quadratic limiter, called limiter 1 and limiter 2. The registers are • DRW1START, DRW1XADD, DRW1YADD • DRW2START, DRW2XADD, DRW2YADD See below figure for details about this. The grey box is an addition that does different operation as in the linear setup.
Page 233 Drawing Engine Chapter 8 8.5.4.3 Example    Remember the equation for a circle width the center at     and radius r:   − − − If the braces are dissolved it looks like this: −...
Page 234: Band Filter
Chapter 8 Drawing Engine 8.5.5 Band filter The output of limiter 1 and 2 can be modified to use a bandfilter. The bandfilter has a single filter parameter w. Input value value>w value=(w+1)-value output value Figure 8-14 Bandfilter Input Figure 8-15 Bandfilter output after clamp with w = 5 Preliminary User's Manual S19203EE1V3UM00...
Page 235: Clamping Unit
Drawing Engine Chapter 8 8.5.6 Clamping unit The clamping unit cuts the limiter output to the interval [0:1]. Input value value<0 value=0 value>1 value=1 output value Figure 8-16 Clamping unit Preliminary User's Manual S19203EE1V3UM00...
Page 236: Combiner Unit
Chapter 8 Drawing Engine 8.5.7 Combiner unit The combiner unit can be operated in minimum mode and in maximum mode. In minimum mode the smaller value is output and in maximum mode the larger value is output. The minimum mode represents the intersection and the maximum mode the union of the two regions.
Page 237: Rasterization Optimization
Drawing Engine Chapter 8 8.5.8 Rasterization optimization During rasterization it is necessary to step through the whole bounding box one pixel after the other. This can lead to an unnecessary amount of steps through pixels that will not be drawn anyway. A contiguous horizontal line is called a span. For all convex primitives it is known beforehand that they can have only one span per line.
Page 238 Chapter 8 Drawing Engine Consider the last case: In this case the triangle has to be splitted and rendered as two parts for the spanstore optimization to work. It is also possible to delay spanstore activation for a number of lines. This is used by the driver with circles: In this case the spanstore would not be activated in the top left corner but in the bottom left corner.
Page 239 Drawing Engine Chapter 8 8.5.8.3 Optimization efficiency The efficiency of the optimizations with typical case can be seen in below figure. In this case the triangle is always rendered as single piece and is not separated into multiple triangles for higher optimizations. In this case the spanstore delay is used.
Page 240: Colourization
Chapter 8 Drawing Engine 8.5.9 Colourization After a pixel has been found to be part of the geometry, its colour is calculated. The Ravin Drawing Engine supports a very general colour calculation scheme. This makes it possible to support several colour modes. It is an interpolation between two colour registers DRWCOLOR1 and DRWCOLOR2.
Page 241: Texturing
Drawing Engine Chapter 8 8.5.10 Texturing The texture unit can cover any primitive with a picture. The picture can be stretched, shared, rotated and translated with the texture unit in one step. To avoid aliasing the result can be filtered bilinear in u and v directions. 8.5.10.1 Mathematical background The arbitrary mapping problem is completely determined by a mapping from 3...
Page 242 Chapter 8 Drawing Engine     O ′  Figure 8-26 Texture mapping, object space, transformation from coordinate system O to O’ to simplify calculations Figure 8-27 Texture mapping, texture space, texture with width w and height h Preliminary User's Manual S19203EE1V3UM00...
Page 243 Drawing Engine Chapter 8 In O’ the mapping is like this:         ′     ⇒                ...
Page 244 Chapter 8 Drawing Engine 8.5.10.2 Limiter operation The texture limiters operate exactly the same as the spatial limiters shown in the flowchart Figure 8-6 on page 229 . The register layout for the u limiter is the same: • DRWLUSTART = us •...
Page 245: Src_One
Drawing Engine Chapter 8 8.5.11 Blending The last step before the pixel will be written to the framebuffer is to blend the pixel with the data that has already been written to the framebuffer. If blending is activated the framebuffer, which is here referred to as DST, must be read. SRC is the output from the colourization unit.
Page 246 Chapter 8 Drawing Engine All possible blend modes are listed here: Mode BSF BSI BDF BDI Blend equation SRC_ONE DST_ONE SRC + DST SRC_ONE SRC_ONEDST_ALPHA SRC + DST*ALPHA SRC_ONE DST_ONE_MINUS_ALPHA SRC + DST * ( 1 – ALPHA ) SRC_ZERO DST_ONE SRC_ZERO DST_ZERO SRC_ZERO DST_ALPHA DST * ALPHA...
Page 247: Rendering Modes
Drawing Engine Chapter 8 8.6 Rendering Modes The redering process can be performed in two different modes: Register based mode In the register based operation mode the Host CPU configures and initiates each render process separately. To start a new render process the Host CPU has to wait until the previous one is completed.
Page 248 Chapter 8 Drawing Engine The register index is derived from the address offset of the register's address and can be calculated by dividing the address offset by 4. The index of each register is given in the register descriptions chapter. As the Drawing Engine registers are always 32 bit wide, each data, named data word, to be written to a register is of the same size.
Page 249 Drawing Engine Chapter 8 Caution Gap indices 80 must not be placed between other indices, like for instance "index1 - 80 - index3 - index4". Thus always fill all indices after 80 also with the gap index. If any of the special indices 80 and FF are used, no register index may follow after them in the same address word.
Page 250: Interrupts
Chapter 8 Drawing Engine 8.7 Interrupts The Drawing Engine generates three interrupts. 8.7.1 Interrupt sources DRWBUSIRQ Drawing Engine bus error interrupt If the Drawing Engine attempts to access an undefined address range via the • framebuffer base address register DRWORIGIN, •...
Page 251 Drawing Engine Chapter 8 DRWIRQCTL DRWSTATUS DRWBUSIRQ BUSIRQ BUSIRQEM BUSIRQCLR DRWDLISTIRQ DRWINT DLISTIRQ DLISTIRQEM DLISTIRQCLR DRWENUMIRQ ENUMIRQ ENUMIRQEM ENUMIRQCLR Figure 8-30 Interrupt controller Preliminary User's Manual S19203EE1V3UM00...
Page 252: Performance Counters
Chapter 8 Drawing Engine 8.8 Performance Counters The Drawing Engine features two independent 32-bit performance counter register DRWPERFCOUNTk (k = 1, 2) to count the number of occurrences of a certain event. The events to count can be set up independently for each performance counter register via the performance counter control register DRWPERFTRIGGER.PERFTRIGGER2 for DRWPERFCOUNT2 respectively DRWPERFTRIGGER.PERFTRIGGER1 for DRWPERFCOUNT1.
Page 253: Drawing Engine Registers
Drawing Engine Chapter 8 8.9 Drawing Engine Registers 8.9.1 Drawing Engine registers overview The Drawing Engine is controlled and operated by means of the registers in the table below. Index In addition to the address offset also the index is given, that is used to address the register in display list mode.
Page 254 Chapter 8 Drawing Engine Register function Name Address Index <DrwE_Base> + 50 Limiter 5 y-axis increment DRWL5YADD <DrwE_Base> + 54 Limiter 6 y-axis increment DRWL6YADD Limiter 1 band width <DrwE_Base> + 58 DRWL1BAND parameter Limiter 2 band width <DrwE_Base> + 5C DRWL2BAND parameter Texture registers:...
Page 255: Control Registers Details
Drawing Engine Chapter 8 8.9.2 Control registers details 8.9.2.1 DRWCONTROL - Geometry control register This register controls the pixel enumeration and selection units, deciding which pixels are part of the geometry. Access This register can be written in 32-bit units. Address <DrwE_Base>...
Page 256 Chapter 8 Drawing Engine Bit name Function 1 enabled Combine limter 5 & 6 as union (output is called D) UNION56 0 disabled 1 enabled Combine limter 3 & 4 as union (output is called B) UNION34 0 disabled 1 enabled Combine limter 1 &...
Page 257 Drawing Engine Chapter 8 Bit name Function 1 enabled Enable limiter 6 LIM6ENABLE 0 disabled 1 enabled Enable limiter 5 LIM5ENABLE 0 disabled 1 enabled Enable limiter 4 LIM4ENABLE 0 disabled 1 enabled Enable limiter 3 LIM3ENABLE 0 disabled 1 enabled Enable limiter 2 LIM2ENABLE 0 disabled...
Page 258 Chapter 8 Drawing Engine 8.9.2.2 DRWCONTROL2 - Surface control register This register controls the colourization and blending units, deciding what colour a pixel should have. Access This register can be written in 32-bit units. Address <DrwE_Base> + 04 Index Initial Value 0000 0000 .
Page 259 Drawing Engine Chapter 8 Bit name Function 16 bpp RGB(565) 32 bpp RGB(8888) 16 bpp aRGB(4444) 16 bpp aRGB(1555) Linear filtering on texture V axis TEXTURE no filtering on texture V axis FILTERY linear filtering on texture V axis Linear filtering on texture U axis TEXTURE no filtering on texture U axis FILTERX...
Page 260 Chapter 8 Drawing Engine 8.9.2.3 DRWIRQCTL - Interrupt control register This register enables interrupts and clears the interrupt status. Access This register can be written in 32-bit units. Address <DrwE_Base> + C0 Index Initial Value 0000 0000 . This register is initialized by any reset. BUSIRQC BUSIRQE DLISTIRQ...
Page 261 Drawing Engine Chapter 8 Bit name Function DLISTIRQ interrupt mask enable DLISTIRQEN 0 disable (mask) DLISTIRQ 1 enable (unmask) DLISTIRQ ENUMIRQ interrupt mask enable ENUMIRQEN 0 disable (mask) ENUMIRQ 1 enable (unmask) ENUMIRQ Preliminary User's Manual S19203EE1V3UM00...
Page 262 Chapter 8 Drawing Engine 8.9.2.4 DRWCACHECTL - Cache control register Internal caches can be enabled /disabled and flushed using this register. Note that caches will be disabled if a value without its enable bits set is written to DRWCACHECTL. Access This register can be written in 32-bit units.
Page 263 Drawing Engine Chapter 8 8.9.2.5 DRWSTATUS - Status control register The current Drawing Engine status can be polled by reading this register. Access This register can be read in 32-bit units. Address <DrwE_Base> + 00 Index no index because of read only access Initial Value 0000 0000 .
Page 264 Chapter 8 Drawing Engine 8.9.2.6 DRWHWREVISION - Hardware version and feature set ID Read this (constant) register to identify the present hardware revision and feature set. Access This register can be read in 32-bit units. Address <DrwE_Base> + 04 Index no index because of read only access Initial Value D/AVE 2D-TL: 000E 10020...
Page 265: Colour Registers Details
Drawing Engine Chapter 8 8.9.3 Colour registers details 8.9.3.1 DRWCOLOR1 - Base colour register This register defines the 32-bit ARGB value for the base colour, i.e. constant colour 1 Access This register can be written in 32-bit units. Address <DrwE_Base> + 64 Index Initial Value 0000 0000...
Page 266 Chapter 8 Drawing Engine 8.9.3.2 DRWCOLOR2 - Secondary colour register This register defines the 32-bit ARGB value for the secondary colour, i.e. constant colour 2. Secondary colour is relevant only when rendering patterns, textures or using a BC2 blendmode (see DRWCONTROL2). Access This register can be written in 32-bit units.
Page 267 Drawing Engine Chapter 8 8.9.3.3 DRWPATTERN - Pattern register Each bit in the pattern register is interpreted as a reference to one of the two colour registers ('0' = DRWCOLOR1; '1' = DRWCOLOR2). Access This register can be written in 32-bit units. Address <DrwE_Base>...
Page 268: Limiter Registers Details
Chapter 8 Drawing Engine 8.9.4 Limiter registers details 8.9.4.1 DRWLnSTART - Limiter n start value The start value is a 16:16 fixed point number valid at the first pixel of the bounding box. Note n = 1 to 6 Access This register can be written in 32-bit units.
Page 269 Drawing Engine Chapter 8 8.9.4.2 DRWLnXADD - Limiter n x-axis increment The LnXADD value is the 16:16 fixed point difference between two samples with a distance of one pixel along the x-axis. Note n = 1 to 6 Access This register can be written in 32-bit units. Address DRWL1XADD: <DrwE_Base>...
Page 270 Chapter 8 Drawing Engine 8.9.4.3 DRWLnYADD - Limiter n y-axis increment The LnYADD value is the 16:16 fixed point difference between two samples with a distance of one pixel along the y-axis. Note n = 1 to 6 Access This register can be written in 32-bit units. Address DRWL1YADD: <DrwE_Base>...
Page 271 Drawing Engine Chapter 8 8.9.4.4 DRWLmBAND - Limiter m band width parameter Postfilter First two limiter outputs can be routed through an additional unit before clamping in order to mirror their gradient and form a 'band' instead of the usual 'halfplane'. When band output filtering is enabled for limiter 1 (see DRWCONTROL.BAND1ENABLE) this register stores the 16:16 fixed point inner width of band region.
Page 272: Texture Registers Details
Chapter 8 Drawing Engine 8.9.5 Texture registers details 8.9.5.1 DRWTEXORIGIN - Texture base address register Address of the upper left corner texel. Addresses inside the framebuffer can be used as valid texture origin as well. Access This register can be written in 32-bit units. Address <DrwE_Base>...
Page 273 Drawing Engine Chapter 8 8.9.5.2 DRWTEXPITCH - Texels per texture line Pitch is equal or bigger than texture width. Access This register can be written in 32-bit units. Address <DrwE_Base> + B4 Index Initial Value 0000 0000 . This register is initialized by any reset. TEXPITCH[31:16] TEXPITCH[15:0] Bit name...
Page 274 Chapter 8 Drawing Engine 8.9.5.3 DRWTEXMASK - Texture size or texture address mask Depending on the clamping mode this register encodes the clamp limit or wrap mask. Access This register can be written in 32-bit units. Address <DrwE_Base> + B8 Index Initial Value 0000 0000...
Page 275 Drawing Engine Chapter 8 8.9.5.4 DRWLUSTART - U limiter start value The start value is a 16:16 fixed point number valid at the first pixel of the bounding box. Access This register can be written in 32-bit units. Address <DrwE_Base> + 90 Index Initial Value 0000 0000...
Page 276 Chapter 8 Drawing Engine 8.9.5.5 DRWLUXADD - U limiter x-axis increment The LUXADD value is the 16:16 fixed point difference between two samples with a distance of one pixel along the x-axis. Access This register can be written in 32-bit units. Address <DrwE_Base>...
Page 277 Drawing Engine Chapter 8 8.9.5.6 DRWLUYADD - U limiter y-axis increment The LUYADD value is the 16:16 fixedpoint difference between two samples with a distance of one pixel along the y-axis. Access This register can be written in 32-bit units. Address <DrwE_Base>...
Page 278 Chapter 8 Drawing Engine 8.9.5.7 DRWLVSTARTI - V limiter start value integer part The start value of the V limiter is a 32:16 fixed point number valid at the first pixel of the bounding box. Access This register can be written in 32-bit units. Address <DrwE_Base>...
Page 279 Drawing Engine Chapter 8 8.9.5.8 DRWLVSTARTF - V limiter start value fractional part The start value of the V limiter is a 32:16 fixed point number valid at the first pixel of the bounding box. Access This register can be written in 32-bit units. Address <DrwE_Base>...
Page 280 Chapter 8 Drawing Engine 8.9.5.9 DRWLVXADDI - V limiter x-axis increment integer part The LVXADDI value is the 32:16 fixed point difference between two samples with a distance of one pixel along the x-axis. Access This register can be written in 32-bit units. Address <DrwE_Base>...
Page 281 Drawing Engine Chapter 8 8.9.5.10 DRWLVYADDI - V limiter y-axis increment integer part The LVYADDI value is the 32:16 fixed point difference between two samples with a distance of one pixel along the y-axis. Access This register can be written in 32-bit units. Address <DrwE_Base>...
Page 282 Chapter 8 Drawing Engine 8.9.5.11 DRWLVYXADDF - V limiter increment fractional parts Both fractional parts (for DRWLVXADDI and DRWLVYADDI) are stored in this register. Access This register can be written in 32-bit units. Address <DrwE_Base> + AC Index Initial Value 0000 0000 .
Page 283 Drawing Engine Chapter 8 8.9.5.12 DRWTEXCLUT - Colour lookup table for the indexed texture format Triggers a write into the CLUT. Access This register can be written in 32-bit units. Address <DrwE_Base> + D8 Index no index because can not be written via display list commands Initial Value 0000 0000 .
Page 284: Miscellaneous Registers Details
Chapter 8 Drawing Engine 8.9.6 Miscellaneous registers details 8.9.6.1 DRWSIZE - Bounding box dimension This register stores the height and width (in pixels) of the primitives bounding box. Access This register can be written in 32-bit units. Address <DrwE_Base> + 78 Index Initial Value 0000 0000...
Page 285 Drawing Engine Chapter 8 8.9.6.2 DRWPITCH - Framebuffer pitch and spanstore delay Access This register can be written in 32-bit units. Address <DrwE_Base> + 7C Index Initial Value 0000 0000 . This register is initialized by any reset. PITCH Bit name Function 31 to 16 Spanstore delay...
Page 286 Chapter 8 Drawing Engine 8.9.6.3 DRWORIGIN - Framebuffer base address register Writing to DRWORIGIN will trigger the Drawing Engine to start rendering. Access This register can be written in 32-bit units. Address <DrwE_Base> + 80 Index Initial Value 0000 0000 .
Page 287 Drawing Engine Chapter 8 8.9.6.4 DRWDLISTSTART - Display list start address register Setting a new display list base address triggers execution of the new display list. Execution will stop only when a new list is set or the list terminates. Access This register can be written in 32-bit units.
Page 288 Chapter 8 Drawing Engine 8.9.6.5 DRWPERFTRIGGER - Performance counters control register The Drawing Engine will increment the performance counters DRWPERFCOUNT1 and DRWPERFCOUNT1 on every event selected by DRWPERFTRIGGER. Access This register can be written in 32-bit units. Address <DrwE_Base> + D4 Index Initial Value 0000 0000...
Page 289 Drawing Engine Chapter 8 8.9.6.6 DRWPERFCOUNTk - Performance counter k The Drawing Engine will increment the counters on every event selected by DRWPERFTRIGGER. Note k = 1 to 2 Access This register can be read and written in 32-bit units. Address DRWPERFCOUNT1: <DrwE_Base>...
Page 290: Chapter 9 External Memory Interface Controller
Chapter 9 External Memory Interface Controller Indices Throughout this chapter following indices are used: • n = 0 to 1: numbers the chip select signals MCS0 and MCS1 and their dedicated registers • k = 0 to 3: numbers the three different static memory timing parameter sets Register base All Memory Controller register addresses are given as address offsets to the base...
Page 291 External Memory Interface Controller Chapter 9 Ravin-M option Signal 1, 9 2, 7e 7a, 7b MSBEN0 – √ √ – √ √ √ MSBEN1 – √ √ – √ √ √ MSBEN2 – – √ – – – – MSBEN3 –...
Page 292 Chapter 9 External Memory Interface Controller • MCS1: 64 MB flash memory, 32-bit data bus width, base and alias address 0400 0000 , no page mode timing parameters defined by MEMSMTMGR2: 13 clocks read cycles, 4 clocks bus idle time, 4 clocks Caution As the Ravin-L supports only a 16-bit external memory data bus, the data bus width has to be changed by setting...
Page 293: Functional Overview
External Memory Interface Controller Chapter 9 9.1 Functional Overview Features The basic features of the Memory Controller are: • SDRAM and static memory controller (static RAM of NOR flash memory with shared address/data bus) • 25-bit address bus width MA[24:0] •...
Page 294: Sdram Interface
Chapter 9 External Memory Interface Controller MA[24:0] MD[31:0] Address decoder MCS0 MCS1 MDBA[1:0] MDDQM[3:0] SDR-SDRAM controller MDRAS Address MDCAS and data MDWE FIFO MDCKE Static memory controller MDCLK MDFBCLK MDA10PC MSOE Registers MSWR MSBEN[3:0] HCLK SDRAMEN Figure 9-1 Memory Controller block diagram 9.2 SDRAM Interface SDRAM chip selects SDRAM can be assigned to the chip select area MCS0.
Page 295: Sdram Initialization
External Memory Interface Controller Chapter 9 9.2.1 SDRAM Initialization The Memory Controller follows the JEDEC-recommended SDR-SDRAM power- on initialization sequence as follows: Upon power appliance and clock start, NOP condition is maintained for a minimum of MEMSTMG1R.TINIT clock cycles. Precharge commands for all banks are issued. Auto-refresh commands are issued, depending on the value MEMSTMG1R.INITREF.
Page 296 Chapter 9 External Memory Interface Controller Apply power and start clock MEMSTMG1R. TINIT Precharge all banks MEMSTMG0R. Auto-refresh MEMSTMG1R. INITREF MEMSTMG0R. TRCAR Set SDRAM mode register Ready for data transfer Figure 9-2 SDRAM power-on command sequence SDRAM mode The Memory Controller automatically sets the SDRAM devices' mode registers initialization during the power-up initialization.
Page 297: Sdram Refresh Control
External Memory Interface Controller Chapter 9 • burst length = 010 : length 4 The burst length is fixed and can not be changed. • burst type = 0: sequential bursts The burst type is fixed and can not be changed. •...
Page 298 Chapter 9 External Memory Interface Controller If the SDRAM needs to be refreshed while a burst is active, the Memory Controller will issue the refresh command after the ongoing burst completes. Thus the maximum time to complete a worst-case burst has to be taken into account. row_refresh_period = SDRAM_refresh_period / num_of_rows >...
Page 299 External Memory Interface Controller Chapter 9 Auto-refresh MEMSTMG0R. TRCAR Ready for new command Figure 9-4 SDRAM auto-refresh command sequence Preliminary User's Manual S19203EE1V3UM00...
Page 300 Chapter 9 External Memory Interface Controller 9.2.2.2 Self-refresh mode You can put the SDRAM into self-refresh mode, at which point the SDRAM retains data without external clocking and auto-refresh. Below figure illustrates the command sequence issued by the SDRAM controller to initiate, maintain, and exit the self-refresh mode.
Page 301 External Memory Interface Controller Chapter 9 Setting MEMSCTRL.FSREFB = 0 forces the Memory Controller to refresh only one row before putting the SDRAM into self-refresh mode. MEMSCTRL.FSREFA does the same, except that it controls the refresh pattern just after coming out of self-refresh mode. Since it takes time between setting MEMSCTRL.SREF = 1 and entering self- refresh mode, the Memory Controller provides the self-refresh status bit MEMSCTRL.SREFSTAT to indicate that the SDRAM is already in self-refresh...
Page 302: Static Memory Interface
Chapter 9 External Memory Interface Controller 9.3 Static Memory Interface Static memory chip Static memory can be assigned to the chip select areas MCS0 and MCS1. selects This section describes the functional details of the Memory Controller as a static memory controller.
Page 303 External Memory Interface Controller Chapter 9 9.3.1.1 Static RAM and Flash read timing Below diagram illustrates the read timing from static RAM or flash memory. The read cycle time parameter MEMSMTMGRk.TRC defines the number of system clocks of an entire read cycle. Caution Set the read cycle time parameter MEMSMTMGRk.TRC[5:0] one clock higher than required by the connected memory.
Page 304 Chapter 9 External Memory Interface Controller 9.3.1.2 Flash page read timing Below diagram illustrates the page read timing from flash memory. The read cycle time parameter MEMSMTMGRk.TRC defines the number of system clocks of the first read cycle. The page mode read cycle parameter MEMSMTMGRk.TPRC defines the number of system clocks of all following read cycles.
Page 305 External Memory Interface Controller Chapter 9 9.3.1.3 Static RAM and Flash write timing The diagram below illustrates the write timing to static RAM or flash memory. The write address setup time parameter MEMSMTMGRk.TAS defines the number of system clocks between assertion of MCSn and MSWR. The write pulse width parameter MEMSMTMGRk.TWP defines the number of system clocks of the MSWR active time.
Page 306 Chapter 9 External Memory Interface Controller 9.3.1.4 Data bus turnaround timing Below diagram illustrates the timing for consecutive accesses, whereas the data source, i.e. the device driving the data bus MD[31:0], changes. This is of concern in case of consecutive •...
Page 307: Address Decoder
External Memory Interface Controller Chapter 9 9.4 Address Decoder The Memory Controller is linked to the other internal modules via its AHB slave interface. The internal address IMEMADD[31:0] of the external memory to be accessed are transfered via the 32-bit AHB address bus. IMEMADD[31:0] always represents a byte address.
Page 308 Chapter 9 External Memory Interface Controller • memory size: MEMSMSKRn.MEMSIZE[4:0] = 1 to 17: memory size = MEMSIZE[4:0]-1 • 64 KB Addressing The Memory Controller supports a variety of memory sizes between minimum 64 KB up to 4 GB. The size of the memory within the chip select area n has to be defined by setting MEMSMSKRn.MEMSIZE[4:0].
Page 309 External Memory Interface Controller Chapter 9 Therefore an alias address has to be defined in the chip select alias register MEMCSALIASn. MEMCSALIASn has to be set up in the same way as the chip select base address register MEMSCSLRn, i.e. its upper bits MEMCSALIASn.CSAADDR[31:i] are compared with the internal memory address IMEMADD[31:i].
Page 310 Chapter 9 External Memory Interface Controller Example Following an example how to set up the various addressing registers. Externally 32 MB SDRAM shall be assigned to MCS0 and 16 MB flash memory to MCS1: • MEMSMSKR0 = 0000 000A : 32 MB SDRAM, thus address bits [31:25] are relevant for MCS0 •...
Page 311: Address Adjustment
External Memory Interface Controller Chapter 9 9.4.2 Address adjustment External addresses Depending on the selected bus width of the external memory the internal address, which always describe byte addresses, may be shifted before they are output to the external memory address bus. This way useless address bits are eliminated and the addressable range of the external memory is increased, if memory with a data bus larger than 8 bit is connected.
Page 312: Memory Controller Power-Down
Chapter 9 External Memory Interface Controller 9.5 Memory Controller Power-Down The SDRAM can be put into power-down mode to save power. This is executed by setting MEMSCTRL.PWDM = 1. The figure below illustrates the command sequence issued by the SDRAM controller to initiate, maintain, and exit power-down mode.
Page 313 External Memory Interface Controller Chapter 9 The Memory Controller keeps the SDRAM in this periodical power-down/refresh/ power-down sequence until it is commanded to exit power-down mode by MEMSCTRL.PWDM = 0. When a read/write request to the SDRAM occurs while the SDRAM is in power- down mode, the Memory Controller brings the SDRAM out of power-down mode and issues the read/write access to the SDRAM.
Page 314: Memory Controller Registers
Chapter 9 External Memory Interface Controller 9.6 Memory Controller Registers 9.6.1 Memory Controller registers overview The Memory Controller is controlled and operated by means of the following registers: Table 9-4 Memory Controller registers overview Register function Name Address <MemC_Base> + 00 SDRAM configuration register MEMSCONR <MemC_Base>...
Page 315: Memory Controller Registers Details
External Memory Interface Controller Chapter 9 9.6.2 Memory Controller registers details 9.6.2.1 MEMSCONR - SDRAM configuration register This register sets the SDRAM data and address bus properties. Access This register can be read/written in 32-bit units. Address <MemC_Base> + 00 Initial Value 0014 2F48 .
Page 316 Chapter 9 External Memory Interface Controller Bit name Function all other prohibited Number of address bits for row address 0111 8 bit 1000 9 bit 1001 10 bit ROWADDRW 8 to 5 [3:0] 1010 11 bit (default) 1011 12 bit 1100 13 bit all other...
Page 317 External Memory Interface Controller Chapter 9 9.6.2.2 MEMSTMG0R - SDRAM timing register 0 This register defines various timing parameters of the SDRAM interface. All values are given in system clock periods 1/f HCLK Access This register can be read/written in 32-bit units. Address <MemC_Base>...
Page 318 Chapter 9 External Memory Interface Controller Bit name Function 16 clocks TWR[1:0] defines the delay from last data in to next precharge command for writes. 1 clock (default) 2 clocks 13 to 12 TWR[1:0] 3 clocks 4 clocks TRP[2:0] defines the precharge period. 1 clock 2 clocks 11 to 9...
Page 319 External Memory Interface Controller Chapter 9 9.6.2.3 MEMSTMG1R - SDRAM timing register 1 This register defines various timing parameters of the SDRAM initialization phase after system start-up. All values are given in system clock periods 1/f HCLK Access This register can be read/written in 32-bit units. Address <MemC_Base>...
Page 320 Chapter 9 External Memory Interface Controller 9.6.2.4 MEMSCTLR - SDRAM control register This register controls various functions of the SDRAM controller. Access This register can be read/written in 32-bit units. Address <MemC_Base> + 0C Initial Value 0000 1088 . This register is initialized by any reset. NBK4 SREF FSRE...
Page 321 External Memory Interface Controller Chapter 9 Bit name Function refresh all rows PRCHALG determines when a row is precharged PRCHALG immediate precharge: row precharged at end of read/write operation delayed precharge: row kept open after read/write operations PWDM control the power-down mode of the Memory Controller PWDM leave power-down mode force power-down mode...
Page 322 Chapter 9 External Memory Interface Controller 9.6.2.5 MEMSREFR - SDRAM refresh register This register defines the refresh period in auto-refresh mode. The refresh period is the time between two refresh operations, the Memory Controller carries out automatically on consecutie rows. The refresh period is defined in number of system clocks periods 1/f HCLK Access...
Page 323 External Memory Interface Controller Chapter 9 9.6.2.6 MEMSCSLRn - Chip select base address registers These registers hold the base address that correspond to each chip select. A separate chip select base address register is available for each chip select n. Access These registers can be read/written in 32-bit units.
Page 324 Chapter 9 External Memory Interface Controller 9.6.2.7 MEMSMSKRn - Chip select address mask registers These registers define the memory type and its size for each chip select. In case of static memory types, a certain set of timing registers is selected. A separate chip select address mask register is available for each chip select n.
Page 325 External Memory Interface Controller Chapter 9 Bit name Function MEMSIZE[4:0] Memory size MEMSIZE[4:0] Memory size 16 MB 00000 01001 none (MCS0 default) 00001 00111 64 KB 4 MB 00010 01000 128 KB 8 MB 00011 01010 256 KB 32 MB 64 MB 00100 01011...
Page 326 Chapter 9 External Memory Interface Controller 9.6.2.8 MEMCSALIASn - Chip select alias address registers These registers hold the alias address that correspond to each chip select. A separate chip select alias address register is available for each chip select n. Access These registers can be read/written in 32-bit units.
Page 327 External Memory Interface Controller Chapter 9 9.6.2.9 MEMSMTMGRk - Static memory timing registers Each of these 3 registers define a complete set of timing parameters for static memories. MEMSMTMGRk can be assigned to each chip select, that is associated with external static memory by the chip select dedicated mask register bits MEMSMSKR.REGSEL[2:0].
Page 328 Chapter 9 External Memory Interface Controller Bit name Function The page mode read cycle time parameter TPRC[3:0] defines the number of system clocks of all page read cycles after the first read. 1 clock 2 clocks 22 to 19 TPRC[3:0] 4 clocks (MEMSMTMGR2 default) 16 clocks The bus idle time parameter TBTA[2:0] defines the number of system clocks after...
Page 329 External Memory Interface Controller Chapter 9 Bit name Function 13 clocks (MEMSMTMGR2 default) 64 clocks Caution: Set TRC[5:0] one clock higher than required by the connected memory. Preliminary User's Manual S19203EE1V3UM00...
Page 330 Chapter 9 External Memory Interface Controller 9.6.2.10 MEMSMCTRL - Static memory control register This register defines the size of the data bus of the static memories, associated with each of the three timing registers MEMSTMGRk. Access This register can be read/written in 32-bit units. Address <MemC_Base>...
Page 331 External Memory Interface Controller Chapter 9 Preliminary User's Manual S19203EE1V3UM00...
Page 332: Chapter 10 Register List
Chapter 10 Register List Access width in Address Register name Shortcut 0000 0000H Host-I/F status HOSTSTATUS 0000 000CH Host-I/F version HOSTVERSION 0000 0010H Interrupt status HOSTINTSTAT 0000 0014H Interrupt enable HOSTINTENAB – – 0000 0018H Interrupt input HOSTINTFLAG – – 0000 001CH DMA control HOSTCONTROL...
Page 333 Register List Chapter 10 Access width in Address Register name Shortcut 0000 1D40H Limiter 1 y-axis increment DRWL1YADD – – 0000 1D44H Limiter 2 y-axis increment DRWL2YADD – – 0000 1D48H Limiter 3 y-axis increment DRWL3YADD – – 0000 1D4CH Limiter 4 y-axis increment DRWL4YADD –...
Page 334 Chapter 10 Register List Access width in Address Register name Shortcut 0000 1E20H Video Input status VI0STATUS – – 0000 1E24H Active scanline VI0ACTSCANLINE – – 0000 1E28H Scanline interrupt control VI0SCANLINEINT – – 0000 1E2CH VCSYNC separator control VI0SYNCDECODE –...
Page 335 Register List Chapter 10 Access width in Address Register name Shortcut 0000 4020H VO1 Raw interrupt status VO1LCDRIS – – 0000 4024H VO1 Masked interrupt status VO1LCDMIS – – 0000 4028H VO1 Interrupt clear VO1LCDICR – – 0000 402CH VO1 Current address VO1LCDUPCURR –...
Page 336 Revision History This revision list shows all functional changes of this document S19203EE1V2UM00 compared to the previous version S19203EE1V1UM00 (date published December 02, 2008). Chapter Page Description generation of VInSCLINT in case of interlaced video changed FLD1EN/FLD2EN settings corrected generation of VInSCLINT in case of interlaced video changed description of SDRAM feedback clock added Preliminary User's Manual S19203EE1V3UM00...
Page 337 Index Data hold time (SRAM/flash) 327 Data units 5 Display list based mode 247 Display list index 248 Abbreviations 5 Dithering 167 ADBus-I/F 133 Drawing Engine 234 Address offset function 133 Band filter 234 Data access 134 Base address (DrwE_Base) 215 Signals 133 Base colour register (DRWCOLOR1) 265 Wait function (HADWAIT) 136...
Page 338 Performance counter k (DRWPERFCOUNTk) DRWLUXADD 276 DRWLUYADD 277 Performance counters control register DRWLVSTARTF 279 (DRWPERFTRIGGER) 288 DRWLVSTARTI 278 Rasterization 225 DRWLVXADDI 280 Rasterization optimization 237 DRWLVYADDI 281 Register based mode 247 DRWLVYXADDF 282 Secondary colour register (DRWCOLOR2) 266 DRWORIGIN 286 Status control register (DRWSTATUS) 263 DRWPATTERN 267 Surface control register (DRWCONTROL2) 258...
Page 339 Interrupts 119 CAS latency 317 Interrupt status register (HOSTINTSTAT) 146 Chip select address mask register Pin functions 119 (MEMSMSKRn) 324 HOSTINTENAB 147 Chip select alias address registers HOSTINTFLAG 148 (MEMCSALIASn) 326 HOSTINTSTAT 146 Chip select base address registers HOSTSTATUS 144 (MEMSCSLRn) 323 HOSTVERSION 145 Chip select configuration 307...
Page 340 MEMSTMG1R 319 Write protection 100 MSMTMGRk 302 System Controller 86 Base address (SysC_Base) 86 Boot mode register (SYSBOOTMODE) 108 Numeric notation 5 Clock control register (SYSCLKCTRL) 104 Control Registers 100 Pin multiplex control register (SYSPINMUX) 110 Performance counter 252 PLL control register (SYSPLLCTRL) 101 Pixel counter (Video Input) 159 Reset control register (SYSRESET) 107 Preface 5...
Page 341 Interlaced scan 157 FIFO 197 Interrupts 169 Framebuffer base address 197 ITU-R656 data 154 Framebuffer base address register Line counter 159 (VOnLCDUPBASE) 208 Pin functions 151 Horizontal axis display control register Pixel counter 159 (VOnLCDTIMING0) 202 Progressive scan 156 Interrupt controller 199 Scaled lines/field register (VInSCALEDHEIGHT) Interrupt mask register (VOnLCDIMSC) 211 Interrupts 197...
Page 342 VInSCALING 176 VInSCANLINEINT 186 VInSCLINT 169 VInSTARTADDR1 168, 174 VInSTARTADDR2 168, 175 VInSTARTX 159, 179 VInSTARTY 159, 180 VInSTATUS 156, 168, 184 VInSTRIDEX 164, 181 VInSYNCDECODE 155, 183 VInSYNC polarity 156 VOn_Base 188 VOnCSYNC 196 VOnEN 194 VOnFUFINT 198 VOnHSYNC 194 VOnINT 198 VOnLCDCONTROL 206 VOnLCDICR 199, 213...

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Μpd72256

NEC µPD72257 Preliminary User's Manual

Chapter 1 Introduction

Block Diagrams

Chapter 2 Pin Functions

Pin Lists

Pull-Up Resistor Pin Groups

Ravin-L Pin Functions

Ravin-M Pin Functions

Recommended Connection of Unused Pins

Pin States with Respect to Reset

Chapter 3 Memory and Register Map

Ravin-L Memory and Register Map

Ravin-M Memory and Register Map

Chapter 4 System Controller

Clock Generator

Resets

System Watchdog

Modules Control Functions

Boot Mode Function

System Controller Registers

Chapter 5 Host CPU Interface

Lbus Interface

Mode

Adbus Interface

Address Alignment

AHB Master Status and Interrupts

Host-I/F Registers

Chapter 6 Video Input (Ravin-M Only)

Data Format and Synchronization

Video Capturing

Scaling, Cropping and Storing

Colour Format Conversions

YUV Adjustment

Dithering

Interrupts

Video Input Registers

Chapter 7 Video Output

Functional Overview

Colour Formats

Timing Signals

DMA FIFO and Framebuffer Addressing

Interrupts

Start and Stop of Video Output

Video Output Registers

Chapter 8 Drawing Engine

Functional Overview

Introduction

Drawing Features

Input and Output Data Formats

Rendering Pipeline

Rendering Modes

Performance Counters

Drawing Engine Registers

Chapter 9 External Memory Interface Controller

SDRAM Interface

Static Memory Interface

Address Decoder

Memory Controller Power-Down

Memory Controller Registers

Chapter 10 Register List

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Summary of Contents for NEC µPD72257