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Preliminary 1(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Receiver: Info: M. CarstensBehrens mycable GmbH Manual EVB JADED Interface Board Version PA4.2 October 5, 2009 http://www.fujitsu.com/emea/services/microelectronics...
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Preliminary 2(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Notice The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. Any information in this document, including functional descriptions and schematic diagrams, shall not be construed as license of the use or the exercising of any intellectual property rights, such as patent rights or copyright or any other right of FUJITSU or any third party or does FUJITSU warrant noninfringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured for general use, including unrestricted ordinary industrial use, general office use, personal use, and household use but are not designed, developed and manufactured for use accompanying fatal risks or dangers that, unless extremely high safety levels are ensured, could have a serious effect to the public and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon systems), or (2) for use requiring extremely high reliability (i.e., submarine or satellite technology). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by the Japanese government will be required for export of those products from Japan. All rights reserved and Copyright FUJITSU LIMITED 2009...
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Preliminary 3(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Developer’s Manual for EVB JADED Interface Board Summary This manual provides detailed technical information for system architects, hardware and software developers, who work with the EVB JADED Interface board version PA 4 for evaluation and development purpose. Enclosures None. Product Information A JADE Evaluation board was developed to demonstrate the versatile features from the JADE and its interfaces. The JADE together with DDR SDRAM and Flash memory is implemented as module which is called XXSvideo and can be plugged on the JADE Evaluation board. Now also a module with the JADED is available. It is called XXSvideoD. For using the XXSvideoD module with the JADE Evaluation board the EVB JADED Interface board was developed. ...
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Preliminary 4(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Revision History Revision Date Sign Description PA2.1 20090302 Document setup PA2.2 20090309 Pinning of APIX signals PA3.1 20090423 Documentation after finishing PCB PA3.2 20090515 Pin table of X804 added PA3.3 20090706 Pictures added PA4.1 20090814 PCB revision PA4 video connector X804 APIX connector X802 PA4.2 20091005 Picture change Contact Information mycable GmbH...
Preliminary 6(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Overview Manual Scope This manual provides detailed technical information about the EVB JADED Interface board for system architects, hardware and software developers covering: System architecture description and users manual • Hardware architecture • Mechanical information • References to further information like design data, data sheets, software documentation • It is the engineer’s reference for evaluation, system development and prototyping based on the board. This document covers all available hardware versions regarding their configuration options and revision state.
Preliminary 7(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2 EVB JADED Interface Board 2.1 System Architecture Picture 22 shows the top side of the EVB JADED Interface board and picture 23 shows the bottom side. Pic. 22: EVB JADED Interface board top side ...
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Preliminary 8(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Pic. 23: EVB JADED Interface board bottom side ...
Preliminary 9(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2.2 Function Units Overview in the available interfaces: RGB Input – 32 bit Flash memory – – Audio – Connectors – – Host SPI – –...
Preliminary 11(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2.2.2 XXSvideoD Interface Pic. 26: XXSvideoD interface The 120pin 0.5 mm connectors X101 ( CPU signals side ) and X201 ( IO signals side ) QTH 06005FDA from Samtec are the interfaces to the XXSvideoD module with the JADED and memory. Detailed information on the XXSvideo D module see the manual to this board. Do not plug the XXSvideoD module or EVBJADED when the power supply is on ! Following tables shows the assignment from pins, signals and function of these connectors. Mostly the function is no further elucidated and only the name of the connected pin of the JADED is stated. For further details see the datasheet from the JADED and the schematic of the XXSvideoD module. The signal order is the result of optimisation for a good layout of the XXSvideoD module.
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Preliminary 12(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function VCC33 Power Supply 3.3 V for XXSvideoD VCC33 Power Supply 3.3 V for XXSvideoD MEM_XCS4 Chip Select 4 for Flash Memory VCC33 Power Supply 3.3 V for XXSvideoD CPU_D15 Data VCC33 Power Supply 3.3 V for XXSvideoD CPU_A1 Address Ground CPU_A3 Address CPU_D0 Data CPU_A4 Address CPU_D3 Data CPU_A7 Address CPU_D4 Data CPU_A8...
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Preliminary 13(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function MEM_XCS2 Chip Select 2 CPU_D10 Data MEM_XCS0 Chip Select 0 CPU_D13 Data CPU_A22 Address CPU_A2 Address CPU_A21 Address CPU_A6 Address MEM_XWR0 Write Strobe CPU_A5 Address CPU_A24 Address CPU_A10 Address MEM_RDY Ready input for slow device CPU_A9 Address...
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Preliminary 14(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function APIXGND Ground for APIX signals SPI_SS0 SPI0 Master Slave Select VIN0_7 Video Capture Data Input 0 bit 7 SPI_SCK0 SPI0 Master serial clock VIN0_4 Video Capture Data Input 0 bit 4 TSG_R_4 TCON Timing Signal VIN0_3 Video Capture Data Input 0 bit 3 TSG_R_5 TCON Timing Signal VIN0_5 Video Capture Data Input 0 bit 5 TSG_R_6 TCON Timing Signal VIN0_6 Video Capture Data Input 0 bit 6 DCLKP RSDS Clock Output CLKp, in TTL Mode VIN0_1 Video Capture Data Input 0 bit 1 DCLKN RSDS Clock Output CLKn, in TTL Mode...
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Preliminary 15(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function DOUTR1_R_5 Digital RGB output1 with serial resistor DOUTG1_R_6 Digital RGB output1 with serial resistor DOUTR1_R_2 Digital RGB output1 with serial resistor DOUTR1_R_3 Digital RGB output1 with serial resistor DCLKO1_R Video output interface 1 dot clock output w. s. r. DOUTR1_R_4 Digital RGB output1 with serial resistor Video output interface 1 graphics / video switch DOUTR1_R_7 Digital RGB output1 with serial resistor VINHSYNC0 Video Capture 0 Horizontal Syncronisation DOUTR1_R_6 Digital RGB output1 with serial resistor VINVSYNC1 Video Capture 1 Vertical Syncronisation VSYNC1 Video output interface 1 vertical sync output vertical sync input in external sync mode VINFID0 Video input 0 field identification signal HSYNC1 Video output interface 1 horizontal sync output...
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Preliminary 16(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Following table shows the assignment from pins, signals and function of connector X201 I/O signals side: Signal Function VCC33 Power Supply 3.3 V for XXSvideoD VCC33 Power Supply 3.3 V for XXSvideoD VCC33 Power Supply 3.3 V for XXSvideoD VCC33 Power Supply 3.3 V for XXSvideoD Ground Ground INT_A0 Interrupt 0 I2C_SDA0 I2C 0 Data INT_A1 Interrupt 1 I2C_SCL0 I2C 0 Clock I2C_SDA1 I2C 1 Data I2C_SCL1 I2C 1 Clock INT_A3 Interrupt 3 SPI_DO1 SPI1 Master Data Output ( MOSI )
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Preliminary 17(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function ADCGND Ground for ADC signals AD_VRL0 Reference voltage "L" input AD_VRH1 Reference voltage "H" input 1 AD_VR0 Reference output AD_VIN1 A/D analog input, channel 1 AD_VIN0 A/D analog input, channel 0 AD_VRH0 Reference voltage "H" input 0 Ground OPT_PIN_0 A/D analog input, channel 2 or TESTMODE 2 DISP_P_R_10 RSDS Output 10p, in TTL Mode Default=DOUTB0_4 OPT_PIN_1 A/D analog input, channel 3 or VINITHI DISP_N_R_10 RSDS Output 10n, in TTL Mode ...
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Preliminary 18(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function CAN_TX0 CAN Transmission 0 DISP_N_R_2 RSDS Output 2n, in TTL Mode Default=DOUTR0_5 CAN_RX0 CAN Reception 0 DISP_P_R_3 RSDS Output 3p, in TTL Mode Default=DOUTR0_6 DISP_P_R_11 RSDS Output 11p, in TTL Mode Default=DOUTB0_6 DISP_N_R_3 RSDS Output 3n, in TTL Mode Default=DOUTR0_7 DISP_N_R_11 RSDS Output 11n, in TTL Mode Default=DOUTB0_7 CAN_RX1 CAN Reception 1 TSG_R_12 TCON Timing Signal 12 CAN_TX1 CAN Transmission 1 VIN1_9 Video Capture Data Input 1 bit 6 DISP_P_R_5...
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Media LB Control Pin CCLK1 Video Capture 1 Clock MLB_CLK Media LB Clock Pin VIN1_2 Video Capture Data Input 1 bit 2 MLB_DAT Media LB Data Pin MPX_MODE_1_0 Multiplex Mode Pin RTCK Return test clock MPX_MODE_1_1 Multiplex Mode Pin JTAG Test Clock VINFID1 Video input 1 field identification signal JTAG TMS JTAGSEL JTAG Selector ( 0 = Fujitsu TAP Controller, 1 = ARM Tap Controller ) JTAG TDO XSRST ICE System reset TRACEDATA_0 Trace data used by the trace tool such as RealView supplied by ARM Limited. XTRST Test reset TRACEDATA_2 Trace data used by the trace tool such as RealView supplied by ARM Limited. JTAG TDI TRACECTL TRACE control VCC_CORE_PG Power good CPU core voltage TRACEDATA_1 Trace data used by the trace tool such as RealView supplied by ARM Limited.
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Preliminary 20(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function VCC18 1.8 V, regulated on XXSvideoD for DDR2 SDRAM TRACECLK Trace clock VCC18 1.8 V, regulated on XXSvideoD for DDR2 SDRAM Ground at center pin Ground at center pin Ground at center pin Ground at center pin Ground at center pin Ground at center pin Ground at center pin Ground at center pin Tab. 22: Pin assignment of connector X201, I/O signals side ...
Preliminary 21(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2.2.3 XXSvideo Interface Pic. 27: XXSvideo interface The connectors X301 ( CPU signals side ) and X401 ( I/O signals side ) DF17(3.0)120DS 0.5V(51) from Hirose are the interfaces to the JADE Evaluation board. These interfaces are specified for the XXSvideo module with the JADE Evaluation board. Mostly the function is no further elucidated and only the name of the connected pin of the JADE is stated. For further details see the datasheet from the JADE and the schematic of the module. video Signals with the name JADE_IO_Gn are connected to multi function pins of the JADE. N indicate the function group. Following table shows the assignment from pins, signals and function of connector X301 CPU signals side:...
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Preliminary 22(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function VCC33 Power Supply 3.3 V for XXS video VCC33 Power Supply 3.3 V for XXS video VCC33 Power Supply 3.3 V for XXS video VCC33 Power Supply 3.3 V for XXS video Ground Ground Ground Ground CPU_D15 Data CPU_D0 Data CPU_A1 Address CPU_D3 Data CPU_A3 Address CPU_D4 Data...
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Preliminary 23(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function CPU_D9 Data MEM_XWR1 Write Strobe CPU_D10 Data MEM_XRD Read Strobe CPU_D13 Data MEM_CS2 Chip Select 2 CPU_A2 Address MEM_CS0 Chip Select 0 CPU_A6 Address CPU_A22 Address CPU_A5 Address CPU_A21 Address CPU_A10 Address MEM_XWR0 Write Strobe...
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Preliminary 24(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function JADE_VO0_13 Digital RGB output 0 Data G3 VIN0_5 Video Capture Data JADE_VO0_20 Digital RGB output 0 Data B4 VIN0_6 Video Capture Data JADE_VO0_17 Digital RGB output 0 Data G7 VIN0_1 Video Capture Data JADE_VO0_12 Digital RGB output 0 Data G2 VIN0_2 Video Capture Data JADE_VO0_8 Digital RGB output 0 Data R4 CCLK0 Video Capture Input Clock JADE_VO0_16 Digital RGB output 0 Data G6 VIN0_0 Video Capture Data DCLKO0 Video output interface dot clock output DCLKIN0 Video output interface dot clock input...
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Preliminary 25(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function JADE_IO_G1_15 DOUTG1_4 / MEM_ED_22 / GPIO_PD_8 JADE_IO_G1_10 DOUTR1_3 / MEM_ED_27 / I2S_SDO0 JADE_IO_G1_8 DOUTR1_5 / MEM_ED_29 / I2S_WS0 JADE_IO_G1_9 DOUTR1_4 / MEM_ED_28 / I2S_SDI0 JADE_IO_G1_11 DOUTR1_2 / MEM_ED_26 / GPIO_PD_12 JADE_IO_G1_6 DOUTR1_7 / MEM_ED_31 / I2S_ECLK0 JADE_IO_G1_1 DCLKO1 JADE_IO_G1_7 DOUTR1_6 / MEM_ED_30 / I2S_SCK0 JADE_IO_G1_5 GV1 / DREQ_7 / DREQ_7 JADE_IO_G1_4 VSYNC1 / XDACK_6 / XDACK_6 USB_PWR_CTRL USB Port Power Control JADE_IO_G1_3 HSYNC1 / DREQ_6 / DREQ_6 USB_DP D+ for HS and FS JADE_IO_G1_2 DE1 / XDACK_7 / XDACK_7 ...
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Preliminary 26(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Following table shows the assignment from pins, signals and function of connector X401 I/O signals side: Signal Function VCC33 Power Supply 3.3 V for XXS video VCC33 Power Supply 3.3 V for XXS video VCC33 Power Supply 3.3 V for XXS video VCC33 Power Supply 3.3 V for XXS video Ground Ground Ground Ground INT_A0 INT_A0 I2C1 I2C_SDA0 INT_A1 INT_A1 I2C0 I2C_SCL0 I2C3 ...
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Preliminary 27(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function UART1 UART_SOUT0 ADC1 AD_VRL0 ADC4 AD_VRH1 ADC3 AD_VR0 ADC6 AD_VIN1 ADC2 AD_VIN0 ADC0 AD_VRH0 JADE_IO_G4_13 IDE_XDIOW / BIGEND BIGEND JADE_IO_G4_12 IDE_XDIOR / VINITHI VINITHI Ground VCC12 1.2 V JADE core voltage, regulated on video JADE_IO_G4_7 ...
Preliminary 30(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function VCC18 1.8 V, regulated on XXS for DDR2 video SDRAM Tab. 24: Pin assignment of connector X401, I/O signals side 2.2.4 Configuration R201 R204 R301 R306 R401 – R408 2.2.5 ADC Interface Pic. 28: ADC interface The pins of the ADC interface from the JADED on the XXSvideoD are available at connector X805, FTSH10601LDV from Samtec. At AD_VR0 and AD_VR1 are capacitors with 100 nF to Ground connected. Resistors ( R840 – R845 ) with connection to AD_VRH0, AD_VRL0, AD_VRH1 and AD_VRL1 can be populated. As default these resistors are not populated. Details see schematic. ...
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Preliminary 31(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Following table shows the assignment of pins, signals and function from the connector X805. Signal Function AD_VRH0 AD_VRL0 AD_VIN0 AD_VR0 AD_VRH1 AD_VRL1 AD_VIN1 AD_VINR1 AD_VIN2 AD_VIN3 ADCGND ADC Ground ADCGND ADC Ground Tab. 25: Pin assignment of connector X805...
Preliminary 32(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2.2.5 I2C and Host SPI Interface Pic. 29: I2C and Host SPI interface, X806 The pins of the I2C 1and Host SPI interface from the JADED on the XXSvideoD are available at connector X806, FTSH10601LDV from Samtec. Following table shows the assignment of pins, signals and function from the connector X806. Signal Function Not connected I2C_SDA1 SDA from I2C interface 1 I2C_SCL1 SCL from I2C interface 1 Ground HOST_SPI_SCK Ground HOST_SPI_DI Ground HOST_SPI_DO Ground HOST_SPI_SS VCC33 + 3.3 V output Tab. 26: Pin assignment of connector X805...
Preliminary 33(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2.2.6 32 bit Flash Memory For evaluation reasons two 256 MBit MirrorBit Flash memories ( S29GL256N10FFI02 from Spansion, U503 and U504 ) which can be configured for the 32 bit bus of the JADED are available on the EVB JADED Interface board. The 32bit mode can be configured by setting the MPX_MODE_1 [1:0] pins b'10'. See config switch SW901 on JADE Evaluation board. 2.2.7 USB A USB 2.0 highspeed mode host and device controller LSI with 16bit width standard CPU bus S1R72V18 ( U601 ) from Seiko Epson Corporation is populated. The S1R72V18 has two host ports to function as a USB root hub. One of the ports can be used as a USB device port after setting. On the EVB JADED Interface board only the host port will be used. The interrupt output from the USB controller is connected to the JADED interrupt A1 over 0 Ohm resistor R605, A2 over 0 Ohm resistor R606 and A3 over 0 Ohm resistor R607. Remove the corresponding resistor to disconnect the connection which shall not be used ! ...
Preliminary 34(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2.2.8 Audio CODEC Pic. 210: Audio connectors A 104 dB, 24Bit, 192 kHz Stereo Audio CODEC CS4245 ( U701 ) from Cirrus Logic is populated. The CS4245 is a highly integrated stereo audio CODEC. The CS4245 performs stereo analog todigital ( A / D ) and digitaltoanalog ( D / A ) conversion of up to 24bit serial values at sample rates up to 192 kHz. A 6:1 stereo input multiplexer is included for selecting between linelevel or microphonelevel inputs. The microphone input path includes a +32 dB gain stage and a lownoise bias voltage supply. The PGA is available for line or microphone inputs and provides gain / attenuation of ±12 dB in 0.5 dB steps. The output of the PGA is followed by an advanced 5th order, multibit delta sigma modulator and digital filtering / decimation. Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either Slave or Master Mode. The D/A converter is based on a 4thorder multibit delta sigma modulator with an ultralinear lowpass filter and offers a volume control that operates with a 0.5 dB step size. It incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops. Standard 50 / 15 μs deemphasis is available for a 44.1 kHz sample rate for compatibility with digital audio programs mastered using the 50 / 15 μs preemphasis technique. The analog input of the CODEC is available at audio connector X701. The microphone input is available at connector X703. The auxiliary output is available at connector X702. And the DAC output is available at audio connector X704. The interrupt output from the CODEC is connected to the JADED interrupt A1 over 0 Ohm resistor R735, A2 over 0 Ohm resistor R736 and A3 over 0 Ohm resistor R737. Remove the corresponding resistor to disconnect the connection which shall not be used ! ...
Preliminary 35(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2.2.9 APIX Pic. 211: APIX connectors APIX is a serial Gbit/s link for incar infotainment and driver assistance systems. It features unidirectional pixel and fullduplex sideband data transmission over one single pair of a shielded twisted pair ( STP ) copper cable. The downlink channel provides a sustained data rate of up to 1 Gbit / s, another 18 Mbit / s can be transmitted simultaneously in uplink direction. The APIX interface 0 from the JADED is connected to connector X801 with pinning for input side. The APIX interface 1 from the JADED is connected to connector X802 with pinning for output side. On revision PA3 both connectors have input pinning. The lines have no external ESD protection diodes because the 1.2 V APIX power supply is not available on this board. The internal protection of the JADED is for up to 2 kV.
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Preliminary 36(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Following tables shows the assignment of pins, signals and function from the APIX connectors. Signal Function CML serial data interface downstream. SDIN0_P Interface to differential transmission line CML serial data interface downstream. SDIN0_M Interface to differential transmission line Not connected CML serial data interface upstream. SDOUT0_P Interface to differential transmission line CML serial data interface upstream. SDOUT0_M Interface to differential transmission line Not connected Not connected Not connected Tab. 27: Pin assignment of input connector X801 Signal Function CML serial data interface upstream. SDOUT1_P Interface to differential transmission line CML serial data interface upstream. SDOUT1_M Interface to differential transmission line ...
Preliminary 37(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2.2.10 Video Output Pic. 212: Video output connector, X804 The video output 0 signals from the JADED are connected to connector X804, FTSH12501L DV from Samtec, for direct interconnect to column and row drivers via LVTTL or RSDS from a display. Additional these signals are connected to the JADE Evaluation board connector X301 over 0 Ohm resistors. So the RGB interface 0 on the JADE Evaluation board can be used. If the TCON interface will be used and the long connection to the JADE Evaluation board make disruptions remove the 0 Ohm resistors. On revision PA3 the pin 3 to 14 have another order. Signal Function Ground Testpoint 801 DISP_N_R_11 DOUTB0_7 DISP_P_R_11 DOUTB0_6 DISP_N_R_10 DOUTB0_5 DISP_P_R_10 DOUTB0_4 DISP_N_R_9 DOUTB0_3 DISP_P_R_9 DOUTB0_2 DISP_N_R_7 DOUTG0_7 DISP_P_R_7 DOUTG0_6...
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Preliminary 38(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function DISP_P_R_6 DOUTG0_4 DISP_N_R_5 DOUTG0_3 DISP_P_R_5 DOUTG0_2 DISP_SYNC_R_3 DCLKP DISP_SYNC_R_4 DCLKN Testpoint 802 Testpoint 800 DISP_P_R_3 DOUTR0_6 DISP_N_R_3 DISP_P_R_2 DOUTR0_4 DISP_N_R_2 DISP_P_R_1 DOUTR0_2 DISP_N_R_1 DISP_P_R_8 DISP_N_R_8 DISP_P_R_4 DISP_N_R_4 DISP_P_R_0 DISP_N_R_0 TSG_R_4...
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Preliminary 39(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Function DISP_SYNC_R_0 HSYNC0 DISP_SYNC_R_1 VSYNC0 DISP_SYNC_R_2 GVO0 Testpoint 803 Ground Testpoint 804 DISP_SYNC_R_5 VCC33 + 3.3 V output voltage Tab. 29: Pin assignment of connector X804...
Preliminary 40(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 2.2.11 RGB Input Pic. 213: RGB input, X900 X900 ( CT0915P5K27, HDDSUBConnector from Yamaichi ) is the connector for the RGB graphic signal which will be captured from the AD9883A from Analog Devices ( U900 ) on the EVB JADED Interface board. The AD9883A is a complete 8bit, 140 MSPS, monolithic analog interface optimized for capturing RGB graphics signals. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA ( 1280 × 1024 at 75 Hz ). The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. This interface is fully programmable via a 2wire serial interface. Following table shows the assignment of pins, signals and function from the RGB Input connector.
Preliminary 41(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Signal Description AVIN2_RED Analog Red Signal AVIN2_GREEN Analog Green Signal AVIN2_BLUE Analog Blue Signal Not connected Ground Ground Ground Ground Not connected Ground Not connected Not connected AVIN2_HSYNC Horizontal Sync Signal AVIN2_VSYNC Vertical Sync Signal Not connected Tab. 210: Pin assignment of connector X900 Hardware Variants Prototypes have the version PA3. For this revision PA4 hardware variants are not designated.
Preliminary 42(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Placement of Components The placement of components on the EVB JADED Interface board is shown below. Pictures from placement of components with a better resolution are available as separate pdf documents. Pic. 26: EVB JADED Interface board placement of components, top side...
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Preliminary 43(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Pic. 27: EVB JADED Interface board placement of components, bottom side...
Preliminary 44(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Mechanical Dimensions The EVB JADED Interface board has a size of 142.0 x 100.0 mm. Pictures from mechanical dimensions with a better resolution are available as separate pdf documents. Pic. 28: EVB JADED Interface board mechanical dimensions, top side...
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Preliminary 45(45) Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 20091005 PA 4.2 Mycable01 Pic. 28: EVB JADED Interface board mechanical dimensions, bottom side...