Signal Requirements Concerning Transition Between Bus Phases - Fujitsu MBA3073 SERIES Technical Manual

(2) MESSAGE OUT phase
In a MESSAGE OUT phase, the TARG requests to transfer message information from the INIT to
the TARG. The TARG keeps the C/D and MSG signals true and I/O signal false during
REQ/ACK handshaking in this phase.
The TARG executes this phase in response to the ATTENTION condition (described in Section
1.7.1) created by the INIT, and must remain in the MESSAGE OUT phase.
Note:
The TARG can terminate the MESSAGE OUT phase even when the ATN signal is true when
it returns a MESSAGE REJECT message to reject an illegal or invalid message, when it enters
the BUS FREE phase as directed by the received message, or when it returns a message
immediately in response to a received message (such as the SYNCHRONOUS DATA
TRANSFER REQUEST).
The TARG can process a received message immediately if no parity error is detected. If a parity
error is detected, the TARG shall ignore all messages which have been received after the parity
error detected in the MESSAGE OUT phase.
When the TARG receives all message information correctly without detecting a parity error, the
TARG shall enter the INFORMATION TRANSFER phase other than the MESSAGE OUT phase
and execute at least one byte of information transfer in order to request the INIT not to retry
message transfer. During some message transfer, the TARG may report the normal completion of
message reception by switching to the BUS FREE phase (for example, ABORT TASK SET and
TARGET RESET messages).
1.6.10

Signal requirements concerning transition between bus phases

If an SCSI bus is at an intermediate point of two INFORMATION TRANSFER phases (during
transition of bus phase), the interface signals must satisfy the following requirements.
a) The BSY, SEL, and ACK signals must not change.
b) The REQ signal must not change until it is asserted to qualify the start of a new phase.
c) The C/D, I/O, MSG and DB(15-0, P_CRCA, P1) signals may change.
d) Switching the DB(15-0, P_CRCA) signals direction from OUT (INIT driving) to IN (TARG
driving)
1) The transition of the I/O signal to true.
2) The TARG delays driving the DB(15-0, P_CRCA, and/or P1) by at least one Data Release
Delay plus one Bus Settle Delay after asserting the I/O signal.
3) The INIT releases the DB(15-0, P_CRCA, and/or P1) within one Data Release Delay
e) Switching the DB(15-0, P_CRCA and/or P1) direction from IN (TARG driving) to OUT
(INIT driving)
1-29 C141-C007