Kenwood KC-Z1 Service Manual page 13

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3 7 63 1515 0
XTI, XTO
Crystal oscillator input/output pins. A parallel resonance
oscillator for clock signal generation and two tuning capaci-
tors are connected to these pins. The clock signal generated
at the pins is sent to the internal PLL circuit. A clock signal
can also be directly input to the XTI pin. The maximum fre-
quency of an input clock signal is 33 MHz, and the minimum
frequency is 7 MHz.
A(15:0)
Address buses. These address buses are usually active.
ROM
Memory selection selection signal (A18 pin of ROM/RAM and
38001DSP address bits). This signal is set active-high after
reset and set low after the EROM boot program processing is
completed.
D(19:0)
Data buses. These data buses are a bidirectional data bus
for external memory access.
RD_
Read strobe pin. This pin is asserted when external memory
is read.
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WR_
Write strobe pin. This pin is asserted when data is written in
external memory.
RESET_
Reset input pin. Using this reset signal, the execution starts
from the prescribed status and address.
During the power-on sequence, this input pin must be assert-
ed by more than 200 clocks so as to initialize a processor
(cold start). VCC and XTI (clock input or crystal oscillator)
pins must satisfy the prescribed DC and AC characteristics
until the rising edge of a reset signal is reached. To secure
the guard time until the normal operation is initialed after that,
a processor is put into the idle state for 4,096 clocks. For
other resets, that is, all resets after the power-on sequence,
the device is reset when a reset input signal become active
between four clocks (minimum) and 127 clock
(maximum)(warm start). A processor is released from the
reset state at the rising edge of a reset signal and put into
the normal operation mode after two clocks.
INT_
External interrupt input pin. This interrupt signal is enabled
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when it is asserted by more than two XTI cycles.
WSA/FSA
Word selection or frame synchronization input/output pin of
.
A-group serial port (for input). The direction and function of
this signal are set by the SA, MA, and TA parameters (corre-
sponding to the parameter in an SPMODE register for
38001DSP) of a CFG command described later.
CIRCUIT DESCRIPTION
x ao
y
i
8
SCK A
Clock input/output pin for A-group serial port. The direction of
this signal is set by the MA bit of a CFG command.
SDA
Data input pin for serial port A
SCKIN
Clock input/output pin for B-group serial port. The direction of
this signal is set by the CB bit of a CFG command.
WSB/FSB
Word selection or frame synchronization input/output pin for
B-group serial port. The direction and function of this signal
are set by the SB and MB bits of a CFG command.
SCKB
Clock input/output pin for B-group serial port. The direction of
this signal is set by the MB bit of a CFG command.
SDB
Data output pin for serial port B
SDC
Data output pin for serial port C
Q Q
3 6 7 1 3
SDD
Data output pin for serial port D
GPIO0, GPIO1
General-purpose pins. These pins can be set to the input or
output state using a SETIO command.
GPI4
General-purpose input pin
GPI5/MUTE_
General-purpose input/mute pin. "1" is set to the MPE field of
a CFG command when this pin is used as a mute pin.
SS_
Serial port interface: Slave select input (SPI).
SCK
Serial port interface: Clock input (SPI).
SO
Serial port interface: Serial data output (SPI).
SI
Serial port interface: Serial data input (SPI).
u163
TCK
.
ICE interface clock (JTAG)
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
m
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9 9
2 8 9 9