Cy8C21434 - LG FB162-A0U Service Manual

4. CY8C21434

• PIN CONFIGURATION
A , I, M, P0[1] 1
M, P2[7]
2
M, P2[5]
3
M, P2[3] 4
M, P2[1]
5
(Top View )
M, P3[3]
6
M, P3[1]
7
M, I2C SCL, P1[7] 8
• PIN DESCRIPTION
Type
Pin No.
Digital
1 IO
2 IO
3 IO
4 IO
5 IO
6 IO
6 Power
7 IO
7 Power
8 IO
9 IO
10 IO
11 IO
12 Power
13 IO
14 IO
15 IO
16 IO
17 Input
18 IO
19 IO
20 IO
21 IO
22 IO
23 IO
24 IO
25 IO
26 IO
27 IO
28 Power
29 IO
30 IO
31 IO
32 Power
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
P0[0], A , I, M
24
23 P2[6], M
22
P2[4], M
QFN
21 P2[2], M
20 P2[0], M
P3[2], M
19
18 P3[0], M
17 XRES
SYMBOL
Analog
I, M P0[1]
M P2[7]
M P2[5]
M P2[3]
M P2[1]
M P3[3]
SMP
M P3[1]
Vss
M P1[7]
M P1[5]
M P1[3]
M P1[1]
Vss
M P1[0]
M P1[2]
M P1[4]
M P1[6]
XRES
M P3[0]
M P3[2]
M P2[0]
M P2[2]
M P2[4]
M P2[6]
I, M P0[0]
I, M P0[2]
I, M P0[4]
I, M P0[6]
Vdd
I, M P0[7]
I, M P0[5]
I, M P0[3]
Vss
Description
Analog column mux input, integrating input.
In CY8C21434 part.
Switch Mode Pump (SMP) connection to required external
components in CY8C21634 part.
In CY8C21434 part.
Ground connection in CY8C21634 part.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
I2C Serial Clock (SCL), ISSP-SCLK*.
Ground connection.
I2C Serial Data (SDA), ISSP-SDATA*.
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Analog column mux input.
Analog column mux input.
Analog column mux input, integrating input.
Ground connection.
3-7 LGE Internal Use Only