Canon A-200 series Service Manual page 58

Since this RAMLE signal is connected to the RAS terminals of each RAM chip whose addreses
is OOOOOH to 1FFFEH, the address signals MAO to MA7 assign RAMs as they are of row address.
These MAO to MA7 signals are separated into row addresses and column addresses by the sig­
nal that is delayed the RAMLE signal in 20 nano seconds by DL1 (Delay Logic) at the selectors
U47, U48 and U40. After 80 nano seconds when the RAMLE signal has become LOW, a HIGH
level signal is output from the pin 10 of the DL1. This signal is inverted at U92, and is sent to
the CAS terminal. Since the select signals of U47, U48 and U40 are already LOW, the column
addresses are output to the MAO through MA7.
Refreshment for the D-RAMs by the DMAC begins with the DMA Request signal DREQO gener­
ated from the PIT at every 15 micro seconds. When the DMAC receives this signal, it sets the
CPU in WAIT mode, and then makes DACKO to LOW. Then U97 and U90 generate RAMLE,
RAMLO, RAMHE and RAMHO signals from the MRD signal inverted the MRD-N signal output
from DMAC and the inverted signal of DACKO. Finally, DMAC outputs refresh addresses of
AO to A7 to the address bus as row,addresses.
In this case, since U47 (Row/Column address selector) has already selected the row address
and usually D-RAMs do not use the AO signal as row address directly, the buffer of U40 is made
enable, and only the period of refreshment, the buffer of U40 converts the AO signal to the MA6
signal.
The procedure mentioned above is a one cycle refreshment operation. The DMAC increments
and counts up the row address with every 15 micro seconds of interruption from the PIT
MWRN>-----------~·~~--------~~------~
WE
D·RAM
RAS
U7, 11, 15,20,24,28,33,38,3
CAS
WE D-RAM
RAS
UB, 12, 16,21,25,29.34,39,4
CAS
WE
D-RAM
RAS
U5,9, 13, 18, 22, 26, 31, 36, 1
CAS
MRD"--~
......
'----+---+
WE
D-RAM
MWR~--«L...""
RAS
U6, 10. 14, 19,23,27,32,37,2
I!
CAS
A17
> ­
A18
"
"
1;;
'"
A19
...
0
C
c
<J>
Iii t
DACKO>-+-+---------------~
>-
>- > ­
0;
~
'"
I
.:.
"
Figure 6-9
55