PAD through PA7 terminals of the port A determines whether it selects a shift register U94 or
the status of the DIP switch, depending on the logical level of the PB7 terminal. When this termi
nal is LOW, it selects the former, and when HIGH, the later:
For more detailed information concerning the DIP switches, refer to "Summary of DIP Switch
Setting" in Part IV of this manual.
PPI
OIP Sw1
Interrupt [
PC7
Control
Circuit
PC6
PIT·OUT2
PC5
NC
PC4
PC3
PC2
PC1
PCO
] K/B
Interface
07
06
PB6
05
PB5
] Interrupt
Control
D4
PB4
Circuit
D3
PB3
NC
02
PB2
NC
01
PB1
To
70
Speaker
Oriver
00
PBO
PIT·G2
AO or BAO
AO
A 1 or BA 1
A1
10R·N
RO
10W·N
WR
PPI
CS
Figure 6-22
74