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MB91F109 FR30
Fujitsu MB91F109 FR30 Manuals
Manuals and User Guides for Fujitsu MB91F109 FR30. We have
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Fujitsu MB91F109 FR30 manual available for free PDF download: Hardware Manual
Fujitsu MB91F109 FR30 Hardware Manual (461 pages)
FR30 Series 32-Bit Microcontroller
Brand:
Fujitsu
| Category:
Computer Hardware
| Size: 1.96 MB
Table of Contents
Table of Contents
11
Chapter 1 Overview
25
MB91F109 Characteristics
26
General Block Diagram of MB91F109
30
Figure 1.2-1 General Block Diagram of MB91F109
30
Outside Dimensions
31
Figure 1.3-1 Outside Dimensions of FPT-100P-M06
31
Figure 1.3-2 Outside Dimensions of FPT-100P-M05
32
Figure 1.3-3 Outside Dimensions of BGA-112P-M01
33
Pin Arrangement Diagrams
34
Figure 1.4-1 QFP-100 Pin Arrangements
34
Figure 1.4-2 LQFP-100 Pin Arrangements
35
Figure 1.4-3 FBGA-112 Pin Arrangements
36
Table 1.4-1 FBGA Package Pin Names
37
Pin Functions
38
Table 1.5-1 Pin Functions (1/5)
38
Table 1.5-2 Pin Functions (2/5)
40
Table 1.5-3 Pin Functions (3/5)
41
Table 1.5-4 Pin Functions (4/5)
42
Table 1.5-5 Pin Functions (5/5)
44
I/O Circuit Format
46
Table 1.6-1 I/O Circuit Format (1/2)
46
Table 1.6-2 I/O Circuit Format (1/2)
47
Memory Address Space
48
Figure 1.7-1 MB91F109 Memory Map
48
Handling of Devices
50
Figure 1.8-1 Example of Using an External Clock (Normal Method)
50
Figure 1.8-2 Example of Using an External Clock (Possible at 12.5 Mhz or Lower)
51
Chapter 2 Cpu
53
CPU Architecture
54
Internal Architecture
55
Figure 2.2-1 Internal Architecture
55
Figure 2.2-2 Instruction Pipeline
56
Programming Model
57
Figure 2.3-1 Configuration of General-Purpose Registers
57
Figure 2.3-2 Configuration of Special Registers
58
Figure 2.3-3 Configuration of General-Purpose Registers
59
General-Purpose Registers
59
Figure 2.3-4 Configuration of Special Registers
60
Special Registers
60
Program Status Register (PS)
63
Data Structure
66
Figure 2.4-1 Data Mapping in Bit Ordering Mode
66
Figure 2.4-2 Data Mapping in Byte Ordering Mode
66
Word Alignment
67
Memory Map
68
Figure 2.6-1 MB91F109 Memory Map
68
Figure 2.6-2 Memory Map Common to the FR Series
69
Instruction Overview
70
Branch Instructions with Delay Slots
72
Branch Instructions Without Delay Slots
75
EIT (Exception, Interrupt, and Trap)
76
EIT Interrupt Levels
78
Table 2.8-1 Interrupt Level
78
Interrupt Control Register (ICR)
80
Table 2.8-2 Assignments of Interrupt Causes and Interrupt Vectors
80
System Stack Pointer (SSP)
81
Interrupt Stack
82
Figure 2.8-1 Example of Interrupt Stack
82
Table Base Register (TBR)
83
EIT Vector Table
84
Table 2.8-3 Vector Table
85
Multiple EIT Processing
86
Table 2.8-4 Priority for EIT Event Acceptance and Masking Other Events
86
Figure 2.8-2 Example of Multiple EIT Processing
87
Table 2.8-5 EIT Handler Execution Order
87
EIT Operation
88
Reset Sequence
92
Operation Mode
93
Table 2.10-1 Mode Pins and Setting Modes
93
Figure 2.10-1 Mode Register Configuration
94
Table 2.10-2 Bus Mode Setting Bit and the Function
94
Chapter 3 Clock Generator and Controller
97
Outline of Clock Generator and Controller
98
Figure 3.1-1 Clock Generator and Controller Registers
98
Figure 3.1-2 Block Diagram of the Clock Generator and Controller
99
Reset Reason Resister (RSRR) and Watchdog Cycle Control Register (WTCR)
100
Table 3.2-1 Watchdog Timer Cycles Specified by WT1 and WT0
101
Standby Control Register (STCR)
102
Table 3.3-1 Oscillation Stabilization Wait Time Specified by OSC1 and OSC0
103
DMA Request Suppression Register (PDRR)
104
Timebase Timer Clear Register (CTBR)
105
Gear Control Register (GCR)
106
Table 3.6-1 CPU Machine Clock
106
Table 3.6-2 Peripheral Machine Clock
107
Watchdog Timer Reset Delay Register (WPR)
109
Table 3.7-1 Watchdog Timer Cycles Specified by WT1 and WT0
109
PLL Control Register (PCTR)
110
Gear Function
111
Figure 3.9-1 Gear Controller Block Diagram
111
Figure 3.9-2 Clock Selection Timing Chart
113
Standby Mode (Low Power Consumption Mechanism)
114
Table 3.10-1 Types of Operation in Standby Mode
114
Figure 3.10-1 Stop Controller Block Diagram
116
Stop State
116
Figure 3.10-2 Sleep Controller Block Diagram
119
Sleep State
119
Figure 3.10-3 Standby Mode State Transition
122
Standby Mode State Transition
122
Watchdog Function
123
Figure 3.11-1 Watchdog Timer Block Diagram
123
Figure 3.11-2 Watchdog Timer Operating Timing
124
Figure 3.11-3 Timebase Timer Counter
124
Reset Source Hold Circuit
125
Figure 3.12-1 Block Diagram of Reset Source Hold Circuit
125
DMA Suppression
127
Figure 3.13-1 DMA Suppression Circuit Block Diagram
127
Clock Doubler Function
129
Table 3.14-1 Operating Frequency Combinations Depending on Whether the Clock Doubler Function Is Enabled or Disabled
131
Example of PLL Clock Setting
132
Figure 3.15-1 Example of PLL Clock Setting
133
Figure 3.15-2 Clock System Reference Diagram
133
Chapter 4 Bus Interface
135
Outline of Bus Interface
136
Figure 4.1-1 Bus Interface Registers
137
Figure 4.1-2 Bus Interface Block Diagram
138
Chip Select Area
139
Figure 4.2-1 Example of Setting Chip Select Areas
139
Bus Interface
140
Table 4.3-1 Correspondence between Chip Select Areas and Selectable Bus Interfaces
140
Area Select Register (ASR) and Area Mask Register (AMR)
142
Figure 4.4-1 Sample Maps of the Chip Select Areas
144
Area Mode Register 0 (AMD0)
145
Area Mode Register 1 (AMD1)
147
Area Mode Register 32 (AMD32)
148
Area Mode Register 4 (AMD4)
149
Area Mode Register 5 (AMD5)
150
DRAM Control Register 4/5 (DMCR4/5)
151
Table 4.10-1 Page Size of DRAM Connected
151
Table 4.10-2 Combinations of Bus Widths Available in Areas 4 and 5
153
Refresh Control Register (RFCR)
154
External Pin Control Register 0 (EPCR0)
156
External Pin Control Register 1 (EPCR1)
159
DRAM Signal Control Register (DSCR)
160
Little Endian Register (LER)
162
Table 4.15-1 Mode Setting Using the Combination of Bits (LE2, LE1, and LE0)
162
Relationship between Data Bus Widths and Control Signals
163
Figure 4.16-1 Data Bus Widths and Control Signals in Usual Bus Interface
163
Figure 4.16-2 Data Bus Widths and Control Signals in DRAM Interface
163
Table 4.16-1 Relationship between Data Bus Widths and Control Signals
164
Bus Access with Big Endians
165
Figure 4.16-3 Relationship between Internal Register and External Data Bus for Word Access
165
Figure 4.16-4 Relationship between Internal Register and External Data Bus for Half-Word Access
165
Figure 4.16-5 Relationship between Internal Register and External Data Bus for Byte Access
166
Figure 4.16-6 Relationship between Internal Register and External Data Bus for 16-Bit Bus Width
166
Figure 4.16-7 Relationship between Internal Register and External Data Bus for 8-Bit Bus Width
167
Figure 4.16-8 External Bus Access for 16-Bit Bus Width
168
Figure 4.16-9 External Bus Access for 8-Bit Bus Width
169
Figure 4.16-10 Example of Connection between MB91F109 and External Devices
170
Bus Access with Little Endians
171
Figure 4.16-11 Relationship between Internal Register and External Data Bus for Word Access
171
Figure 4.16-12 Relationship between Internal Register and External Data Bus for Half-Word Access
172
Figure 4.16-13 Relationship between Internal Register and External Data Bus for Byte Access
172
Figure 4.16-14 Relationship between Internal Register and External Data Bus for 16-Bit Bus Width
173
Figure 4.16-15 Relationship between Internal Register and External Data Bus for 8-Bit Bus Width
173
Figure 4.16-16 Example of Connection between MB91F109 and External Devices (16-Bit Bus Width)
174
Figure 4.16-17 Example of Connection between MB91F109 and External Devices (8-Bit Bus Width)
174
External Access
175
Bus Width
176
DRAM Relationships
179
Table 4.16-2 Functions and Bus Widths of DRAM Control Pins
179
Figure 4.16-18 Example of Connection between MB91F109 and One 8-Bit Output DRAM (8-Bit Data Bus)
180
Table 4.16-3 Page Size Select Bits
180
Figure 4.16-19 Example of Connection between MB91F109 and Two 8-Bit Output Drams (16-Bit Data Bus)
181
Figure 4.16-20 Example of Connection between MB91F109 and Two 16-Bit Output Drams (16-Bit Data Bus)
182
Bus Timing
183
Basic Read Cycle
186
Figure 4.17-1 Example of Basic Read Cycle Timing Chart
186
Basic Write Cycles
188
Figure 4.17-2 Example for Basic Write Cycle Timing
188
Read Cycles in each Mode
190
Figure 4.17-3 Example 1 of Read Cycle Timing Chart
190
Figure 4.17-4 Example 2 of Read Cycle Timing Chart
190
Figure 4.17-5 Example 3 of Read Cycle Timing Chart
190
Figure 4.17-6 Example 4 of Read Cycle Timing Chart
191
Figure 4.17-7 Example 5 of Read Cycle Timing Chart
191
Write Cycles in each Mode
192
Figure 4.17-8 Example 1 of Write Cycle Timing Chart
192
Figure 4.17-9 Example 2 of Write Cycle Timing Chart
192
Figure 4.17-10 Example 3 of Write Cycle Timing Chart
192
Figure 4.17-11 Example 4 of Write Cycle Timing Chart
193
Figure 4.17-12 Example 5 of Write Cycle Timing Chart
193
Read and Write Combination Cycles
194
Figure 4.17-13 Example of Read and Write Combination Cycle Timing Chart
194
Automatic Wait Cycles
195
Figure 4.17-14 Example of Automatic Wait Cycle Timing Chart
195
External Wait Cycles
196
Figure 4.17-15 Example of External Wait Cycle Timing Chart
196
Usual DRAM Interface: Read
197
Figure 4.17-16 Example of Usual DRAM Interface Read Timing Chart
197
Usual DRAM Interface: Write
199
Figure 4.17-17 Example of Usual DRAM Interface Write Timing Chart
199
Usual DRAM Read Cycles
201
Figure 4.17-18 Example 1 of Usual DRAM Read Cycle Timing Chart
201
Figure 4.17-19 Example 2 of Usual DRAM Read Cycle Timing Chart
202
Figure 4.17-20 Example 3 of Usual DRAM Read Cycle Timing Chart
202
Usual DRAM Write Cycles
203
Figure 4.17-21 Example 1 of Usual DRAM Write Cycle Timing Chart
203
Figure 4.17-22 Example 2 of Usual DRAM Write Cycle Timing Chart
204
Figure 4.17-23 Example 3 of Usual DRAM Write Cycle Timing Chart
204
Automatic Wait Cycles in Usual DRAM Interface
205
Figure 4.17-24 Example of Automatic Wait Cycle Timing Chart in Usual DRAM Interface
205
DRAM Interface in High-Speed
206
Figure 4.17-25 Example 1 of DRAM Interface Timing Chart in High-Speed Page Mode
206
Figure 4.17-26 Example 2 of DRAM Interface Timing Chart in High-Speed Page Mode
206
Figure 4.17-27 Example 3 of DRAM Interface Timing Chart in High-Speed Page Mode
207
Figure 4.17-28 Example 4 of DRAM Interface Timing Chart in High-Speed Page Mode
208
Single DRAM Interface: Read
209
Figure 4.17-29 Example of Single DRAM Interface Read Timing Chart
209
Single DRAM Interface: Write
210
Figure 4.17-30 Example of Single DRAM Interface Write Timing Chart
210
Single DRAM Interface
211
Figure 4.17-31 Example of Single DRAM Interface Timing Chart
211
Hyper DRAM Interface: Read
212
Figure 4.17-32 Example of Hyper DRAM Interface Read Timing Chart
212
Hyper DRAM Interface: Write
213
Figure 4.17-33 Example of Hyper DRAM Interface Write Timing Chart
213
Hyper DRAM Interface
214
Figure 4.17-34 Example of Hyper DRAM Interface Timing Chart
214
DRAM Refresh
215
Figure 4.17-35 Example of CAS before RAS (CBR) Refresh Timing Chart
215
Figure 4.17-36 Example of Timing Chart of CBR Refresh Automatic Wait Cycle
216
Figure 4.17-37 Example of Selfrefresh Timing Chart
216
External Bus Request
217
Figure 4.17-38 Example of Bus Control Release Timing Chart
217
Figure 4.17-39 Example of Bus Control Acquisition Timing
217
Internal Clock Multiplication (Clock Doubler)
218
Figure 4.18-1 Example of Timing Chart for 2X Clock (BW-16Bit, Access-Word Read)
218
Figure 4.18-2 Example of Timing for 1X Clock (BW-16Bit, Access-Word Read)
219
Program Example for External Bus Operation
220
Chapter 5 I/O Ports
225
Outline of I/O Ports
226
Figure 5.1-1 Basic I/O Port Block Diagram
226
Port Data Register (PDR)
227
Data Direction Register (DDR)
228
Using External Pins as I/O Ports
229
Table 5.4-1 External Bus Functions to be Selected (1/4)
229
Table 5.4-2 External Bus Functions to be Selected (2/4)
230
Table 5.4-3 External Bus Functions to be Selected (3/4)
231
Table 5.4-4 External Bus Functions to be Selected (4/4)
233
Chapter 6 External Interrupt/Nmi Controller
235
Overview of External Interrupt/Nmi Controller
236
Figure 6.1-1 External Interrupt/Nmi Controller Registers
236
Figure 6.1-2 External Interrupt/Nmi Controller Block Diagram
236
Enable Interrupt Request Register (ENIR)
237
External Interrupt Request Register (EIRR)
238
External Level Register (ELVR)
239
Table 6.4-1 External Interrupt Request Mode
239
External Interrupt Operation
240
Figure 6.5-1 External Interrupt Operation
240
External Interrupt Request Levels
241
Figure 6.6-1 Clearing the Interrupt Cause Hold Circuit at Level Setting for the Interrupt Request Mode
241
Figure 6.6-2 Input of an Interrupt Cause in Interrupt Enable Mode and a Request Issued to the Interrupt Controller
241
Nonmaskable Interrupt (NMI) Operation
242
Figure 6.7-1 NMI Request Detection Block
242
Chapter 7 Delayed Interrupt Module
243
Overview of Delayed Interrupt Module
244
Figure 7.1-1 Delayed Interrupt Module Register
244
Figure 7.1-2 Delayed Interrupt Module Block Diagram
244
Delayed Interrupt Control Register (DICR)
245
Operation of Delayed Interrupt Module
246
Chapter 8 Interrupt Controller
247
Overview of Interrupt Controller
248
Figure 8.1-1 Interrupt Controller Registers (1/2)
249
Figure 8.1-2 Interrupt Controller Registers (2/2)
250
Interrupt Controller Block Diagram
251
Figure 8.2-1 Block Diagram of the Interrupt Controller
251
Interrupt Control Register (ICR)
252
Table 8.3-1 Correspondences between the Interrupt Level Setting Bits and Interrupt Levels
253
Hold Request Cancel Request Level Setting Register (HRCL)
254
Priority Check
255
Table 8.5-1 Relationships Among Interrupt Causes, Numbers, and Levels (1/2)
255
Table 8.5-2 Relationships Among Interrupt Causes, Numbers, and Levels (2/2)
256
Returning from the Standby Mode (Stop/Sleep)
258
Hold Request Cancel Request
259
Table 8.7-1 Settings for the Interrupt Levels for Which a Hold Request Cancel Request Is Issued
259
Example of Using the Hold Request Cancel Request Function (HRCR)
260
Figure 8.8-1 Example of Hardware Configuration for Using the Hold Request Cancel Request Function
260
Figure 8.8-2 Example of Timing for Hold Request Cancel Request Sequence (Interrupt Level: HRCL > A)
261
Figure 8.8-3 Example of Timing for Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a > B)
261
Chapter 9 U-Timer
263
Overview of U-TIMER
264
Figure 9.1-1 U-TIMER Registers
264
Figure 9.1-2 U-TIMER Block Diagram
264
U-TIMER Registers
265
U-TIMER Operation
267
Figure 9.3-1 Example of Using U-TIMER Channels 0 and 1 in Cascade Mode
267
Chapter 10 Uart
269
Overview of UART
270
Figure 10.1-1 UART Registers
270
Figure 10.1-2 UART Block Diagram
271
Serial Mode Register (SMR)
272
Table 10.2-1 Selection of UART Operation Modes
272
Serial Control Register (SCR)
274
Serial Input Data Register (SIDR) and Serial Output Data Register (SODR)
276
Serial Status Register (SSR)
277
UART Operation
279
Table 10.6-1 UART Operation Modes
279
Asynchronous (Start-Stop) Mode
281
Figure 10.7-1 Format of Data Transferred in Asynchronous (Start-Stop) Mode (Mode 0 or 1)
281
CLK Synchronous Mode
282
Figure 10.8-1 Format of Data Transferred in CLK Synchronous Mode (Mode 2)
282
UART Interrupt Occurrence and Flag Setting Timing
284
Figure 10.9-1 ORE, FRE, and RDRF Set Timing (Mode 0)
284
Figure 10.9-2 ORE, FRE, and RDRF Set Timing (Mode 1)
285
Figure 10.9-3 ORE and RDRF Set Timing (Mode 2)
285
Figure 10.9-4 TDRE Set Timing (Mode 0 or 1)
286
Figure 10.9-5 TDRE Set Timing (Mode 2)
286
Notes on Using the UART and Example for Using the UART
287
Figure 10.10-1 Sample System Structure for Mode 1
287
Figure 10.10-2 Communication Flowchart for Mode 1
288
Setting Examples of Baud Rates and U-TIMER Reload Values
289
Table 10.11-1 Baud Rates and U-TIMER Reload Values in Asynchronous (Start-Stop) Mode
289
Table 10.11-2 Baud Rates and U-TIMER Reload Values in CLK Synchronous Mode
289
CHAPTER 11 A/D CONVERTER (Successive Approximation Type)
291
Overview of A/D Converter (Successive Approximation Type)
292
Figure 11.1-1 A/D Converter Registers
292
Figure 11.1-2 Block Diagram of the A/D Converter
293
Control Status Register (ADCS)
294
Table 11.2-1 Selecting the Causes for Starting the A/D Converter
295
Table 11.2-2 Selecting the A/D Converter Operation Mode
296
Table 11.2-3 Setting the A/D Conversion Start Channel
297
Table 11.2-4 Setting the A/D Conversion End Channel
297
Data Register (ADCR)
299
A/D Converter Operation
300
Conversion Data Protection Function
302
Figure 11.5-1 Workflow of the Data Protection Function When DMA Transfer Is Used
303
Notes on Using the A/D Converter
304
Chapter 12 16-Bit Reload Timer
305
Overview of 16-Bit Reload Timer
306
Figure 12.1-1 16-Bit Reload Timer Registers
306
Figure 12.1-2 16-Bit Reload Timer Block Diagram
307
Control Status Register (TMCSR)
308
Table 12.2-1 CSL Bit Setting Clock Source
308
16-Bit Timer Register (TMR) and 16-Bit Reload Register (TMRLR)
310
Operation of 16-Bit Reload Timer
311
Figure 12.4-1 Counter Start and Operation Timing
311
Figure 12.4-2 Underflow Operation Timing
312
Counter States
313
Figure 12.5-1 Counter States Transition
313
Chapter 13 Bit Search Module
315
Overview of the Bit Search Module
316
Figure 13.1-1 Bit Search Module Registers
316
Figure 13.1-2 Block Diagram of the Bit Search Module
316
Bit Search Module Registers
317
Bit Search Module Operation and Save/Restore Processing
319
Table 13.3-1 Bit Positions and Returned Values (Decimal)
320
Chapter 14 Pwm Timer
323
Overview of PWM Timer
324
Figure 14.1-1 PWM Timer Registers
325
PWM Timer Block Diagram
326
Figure 14.2-1 General Block Diagram of PWM Timer
326
Figure 14.2-2 Block Diagram of Single PWM Timer Channel
327
Control Status Register (PCNH, PCNL)
328
Table 14.3-1 Selection of the Count Clock
329
Table 14.3-2 PWM Output When "1" Is Written to PGMS
329
Table 14.3-3 Selection of Trigger Input Edge
329
Table 14.3-4 Selection of Interrupt Causes
330
Table 14.3-5 Specification of the Polarity of the PWM Output and the Edge
330
PWM Cycle Setting Register (PCSR)
332
PWM Duty Cycle Setting Register (PDUT)
333
PWM Timer Register (PTMR)
334
General Control Register 1 (GCN1)
335
Table 14.7-1 Selection of Ch3 Trigger Input
336
Table 14.7-2 Selection of Ch2 Trigger Input
336
Table 14.7-3 Selection of Ch1 Trigger Input
337
Table 14.7-4 Selection of Ch0 Trigger Input
337
General Control Register 2 (GCN2)
338
PWM Operation
339
Figure 14.9-1 PWM Operation Timing Chart (Trigger Restart Disabled)
340
Figure 14.9-2 PWM Operation Timing Chart (Trigger Restart Enabled)
340
One-Shot Operation
341
Figure 14.10-1 One-Shot Operation Timing Chart (Trigger Restart Disabled)
342
Figure 14.10-2 One-Shot Operation Timing Chart (Trigger Restart Enabled)
342
Interrupt
343
Figure 14.11-1 Causes of Interrupts and Their Timing (PWM Output: Normal Polarity)
343
Constant "L" or Constant "H" Output from PWM Timer
344
Figure 14.12-1 Example of Keeping PWM Output at a Lower Level
344
Figure 14.12-2 Example of Keeping PWM Output at a High Level
344
Starting Multiple PWM Timer Channels
345
Chapter 15 Dmac
347
Overview of DMAC
348
Figure 15.1-1 DMAC Registers
348
Figure 15.1-2 DMAC Block Diagram
349
DMAC Parameter Descriptor Pointer (DPDP)
350
Table 15.2-1 Channel Descriptor Addresses
350
DMAC Control Status Register (DACSR)
351
DMAC Pin Control Register (DATCR)
353
Table 15.4-1 Selection of Transfer Input Detection Levels
354
Table 15.4-2 Specification of Transfer Request Acknowledgment Output
354
Table 15.4-3 Specification of Transfer End Output
355
Descriptor Register in RAM
356
Table 15.5-1 Specification of Transfer Source or Destination Address Update Modes
357
Table 15.5-2 Address Increment/Decrement Unit
357
Table 15.5-3 Specification of Transfer Data Size
357
Table 15.5-4 Transfer Mode Specification
358
DMAC Transfer Modes
359
Output of Transfer Request Acknowledgment and Transfer End Signals
362
Notes on DMAC
363
DMAC Timing Charts
366
Table 15.9-1 Codes Used in the Timing Charts
366
Timing Charts of the Descriptor Access Block
367
Timing Charts of Data Transfer Block
369
Transfer Stop Timing Charts in Continuous Transfer Mode
371
Transfer Termination Timing Charts
373
Chapter 16 Flash Memory
375
Outline of Flash Memory
376
Figure 16.1-1 Flash Memory Registers
376
Block Diagram of Flash Memory
378
Figure 16.2-1 Block Diagram of the Flash Memory
378
Flash Memory Status Register (FSTR)
379
Sector Configuration of Flash Memory
381
Figure 16.4-1 Memory Map and Sector Configuration
381
Table 16.4-1 Sector Addresses
382
Flash Memory Access Modes
383
Starting the Automatic Algorithm
385
Table 16.6-1 Commands
385
Execution Status of the Automatic Algorithm
388
Figure 16.7-1 Structure of the Hardware Sequence Flag
388
Table 16.7-1 Statuses of the Hardware Sequence Flag
389
Appendix
393
APPENDIX A I/O Maps
394
Table A-1 I/O Map
395
Table A-2 I/O Map (2/6)
396
Table A-3 I/O Map (3/6)
397
Table A-4 I/O Map (4/6)
399
Table A-5 I/O Map (5/6)
400
Table A-6 I/O Map
401
APPENDIX B Interrupt Vectors
403
Table B-1 Interrupt Vectors (1/2)
403
Table B-2 Interrupt Vectors (2/2)
405
APPENDIX C Pin Status for each CPU Status
407
Table C-1 Explanation of Terms Used in the Pin Status List
407
Table C-2 Pin Status for 16-Bit External Bus Length and 2CA1WR Mode
408
Table C-3 Pin Status for 16-Bit External Bus Length and 2CA1WR Mode
411
Table C-4 Pin Status in 8-Bit External Bus Mode
414
Table C-5 Pin Status in Single Chip Mode
417
APPENDIX D Notes on Using Little Endian Areas
419
C Compiler (Fcc911)
420
D.1 C Compiler (Fcc911)
420
Assembler (Fsm911)
423
D.2 Assembler (Fsm911)
423
D.3 Linker (Flnk911)
425
Linker (Flnk911)
425
Debuggers (Sim911, Eml911, and Mon911)
426
APPENDIX E Instructions
427
Table E-1 Explanation of Addressing Mode Codes
429
Table E-2 Instruction Formats
431
FR-Series Instructions
433
Table E.1-1 Addition and Subtraction Instructions
433
Table E.1-2 Compare Operation Instructions
433
Table E.1-3 Logical Operation Instructions
433
Table E.1-4 Bit Operation Instructions
433
Table E.1-5 Multiplication and Division Instructions
433
Table E.1-6 Shift Instructions
433
Table E.1-7 Immediate Value Setting or 16/32-Bit Immediate Value Transfer Instruction
433
Table E.1-8 Memory Load Instructions
433
Table E.1-9 Memory Store Instructions
433
Index
449
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