Fujitsu MB91F109 FR30 Hardware Manual

Fr30 series 32-bit microcontroller

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CM71-10106-1E

FUJITSU SEMICONDUCTOR

CONTROLLER MANUAL

FR30

32-Bit Microcontroller

MB91F109

Hardware Manual

Table of Contents

Summary of Contents for Fujitsu MB91F109 FR30

Page 1 CM71-10106-1E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL FR30 32-Bit Microcontroller MB91F109 Hardware Manual...
Page 3 FR30 32-Bit Microcontroller MB91F109 Hardware Manual FUJITSU LIMITED...
Page 5 MB91F109. Read this manual thoroughly. Refer to the instruction manual for details on individual instructions. Trademarks FR stands for FUJITSU RISC controller, a product of Fujitsu Limited. Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
Page 6 Organization of This Manual This manual consists of 16 chapters and an appendix. Chapter 1 Overview Chapter 1 provides basic general information on the MB91F109, including its characteristics, a block diagram, and function overview. Chapter 2 CPU Chapter 2 provides basic information on the FR series CPU core functions including the architecture, specifications, and instructions.
Page 7 Chapter 14 PWM Timer Chapter 14 provides an overview of the PWM timer, explains the register configuration and functions, and operations of the PWM timer. Chapter 15 DMAC Chapter 15 provides an overview of the DMAC, explains the register configuration and functions, and operations of the DMAC.
Page 8 2. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.
Page 9 How to Read This Manual Description Format of this Manual Major terms used in this manual are explained below: Term I-BUS D-BUS C-BUS R-BUS E-unit 16-bit wide bus used for internal instructions. Since the FR series uses an internal Harvard architecture, independent buses are used for instructions and data.
Page 11: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ... 1 MB91F109 Characteristics ... 2 General Block Diagram of MB91F109 ... 6 Outside Dimensions ... 7 Pin Arrangement Diagrams ... 10 Pin Functions ... 14 I/O Circuit Format ... 22 Memory Address Space ... 24 Handling of Devices ...
Page 12 Gear Function ... 87 3.10 Standby Mode (Low Power Consumption Mechanism) ... 90 3.10.1 Stop State ... 92 3.10.2 Sleep State ... 95 3.10.3 Standby Mode State Transition ... 98 3.11 Watchdog Function ... 99 3.12 Reset Source Hold Circuit ... 101 3.13 DMA Suppression ...
Page 13 4.17.17 Hyper DRAM Interface: Read ... 188 4.17.18 Hyper DRAM Interface: Write ... 189 4.17.19 Hyper DRAM Interface ... 190 4.17.20 DRAM Refresh ... 191 4.17.21 External Bus Request ... 193 4.18 Internal Clock Multiplication (Clock Doubler) ... 194 4.19 Program Example for External Bus Operation ... 196 CHAPTER 5 I/O PORTS ...
Page 14 10.5 Serial Status Register (SSR) ... 253 10.6 UART Operation ... 255 10.7 Asynchronous (Start-Stop) Mode ... 257 10.8 CLK Synchronous Mode ... 258 10.9 UART Interrupt Occurrence and Flag Setting Timing ... 260 10.10 Notes on Using the UART and Example for Using the UART ... 263 10.11 Setting Examples of Baud Rates and U-TIMER Reload Values ...
Page 15 15.5 Descriptor Register in RAM ... 332 15.6 DMAC Transfer Modes ... 335 15.7 Output of Transfer Request Acknowledgment and Transfer End signals ... 338 15.8 Notes on DMAC ... 339 15.9 DMAC Timing Charts ... 342 15.9.1 Timing Charts of the Descriptor Access Block ... 343 15.9.2 Timing Charts of Data Transfer Block ...
Page 16 FIGURES Figure 1.2-1 General Block Diagram of MB91F109 ... 6 Figure 1.3-1 Outside Dimensions of FPT-100P-M06 ... 7 Figure 1.3-2 Outside Dimensions of FPT-100P-M05 ... 8 Figure 1.3-3 Outside Dimensions of BGA-112P-M01 ... 9 Figure 1.4-1 QFP-100 Pin Arrangements ... 10 Figure 1.4-2 LQFP-100 Pin Arrangements ...
Page 17 Figure 3.15-1 Example of PLL Clock Setting ... 108 Figure 3.15-2 Clock System Reference Diagram ... 109 Figure 4.1-1 Bus Interface Registers ... 113 Figure 4.1-2 Bus Interface Block Diagram ... 114 Figure 4.2-1 Example of Setting Chip Select Areas ... 115 Figure 4.4-1 Sample Maps of the Chip Select Areas ...
Page 18 Figure 4.17-12 Example 5 of Write Cycle Timing Chart ... 169 Figure 4.17-13 Example of Read and Write Combination Cycle Timing Chart ... 170 Figure 4.17-14 Example of Automatic Wait Cycle Timing Chart ... 171 Figure 4.17-15 Example of External Wait Cycle Timing Chart ... 172 Figure 4.17-16 Example of Usual DRAM Interface Read Timing Chart ...
Page 19 Figure 7.1-1 Delayed Interrupt Module Register ... 220 Figure 7.1-2 Delayed Interrupt Module Block Diagram ... 220 Figure 8.1-1 Interrupt Controller Registers (1/2) ... 225 Figure 8.1-2 Interrupt Controller Registers (2/2) ... 226 Figure 8.2-1 Block Diagram of the Interrupt Controller ... 227 Figure 8.8-1 Example of Hardware Configuration for Using the Hold Request Cancel Request Function ..
Page 20 Figure 14.10-1 One-Shot Operation Timing Chart (Trigger Restart Disabled) ... 318 Figure 14.10-2 One-Shot Operation Timing Chart (Trigger Restart Enabled) ... 318 Figure 14.11-1 Causes of Interrupts and Their Timing (PWM Output: Normal Polarity) ... 319 Figure 14.12-1 Example of Keeping PWM Output at a Lower Level ... 320 Figure 14.12-2 Example of Keeping PWM Output at a High Level ...
Page 21 TABLES Table 1.4-1 FBGA Package Pin Names ... 13 Table 1.5-1 Pin Functions (1/5) ... 14 Table 1.5-2 Pin Functions (2/5) ... 15 Table 1.5-3 Pin Functions (3/5) ... 17 Table 1.5-4 Pin Functions (4/5) ... 18 Table 1.5-5 Pin Functions (5/5) ... 20 Table 1.6-1 I/O circuit format (1/2) ...
Page 22 Table 8.3-1 Correspondences between the Interrupt Level Setting Bits and Interrupt Levels ... 229 Table 8.5-1 Relationships among Interrupt Causes, Numbers, and Levels (1/2) ... 231 Table 8.5-2 Relationships among Interrupt Causes, Numbers, and Levels (2/2) ... 232 Table 8.7-1 Settings for the Interrupt Levels for which a Hold Request Cancel Request is Issued ...
Page 23 Table A-4 I/O Map (4/6) ... 375 Table A-5 I/O Map (5/6) ... 376 Table A-6 I/O Map ... 377 Table B-1 Interrupt Vectors (1/2) ... 379 Table B-2 Interrupt Vectors (2/2) ... 380 Table C-1 Explanation of Terms Used in the Pin Status List ... 383 Table C-2 Pin Status for 16-bit External Bus Length and 2CA1WR Mode ...
Page 25: Chapter 1 Overview
CHAPTER 1 OVERVIEW This chapter provides basic general information on the MB91F109, including its characteristics, block diagram, and function overview. 1.1 MB91F109 Characteristics 1.2 General Block Diagram of MB91F109 1.3 Outside Dimensions 1.4 Pin Arrangement Diagrams 1.5 Pin Functions 1.6 I/O Circuit Format 1.7 Memory Address Space 1.8 Handling of Devices...
Page 26: Mb91F109 Characteristics
CHAPTER 1 OVERVIEW MB91F109 Characteristics The MB91F109 is a standard single-chip microcontroller using a 32-bit RISC CPU (FR30 series) as its core. It contains various I/O resources and bus control mechanisms for embedded control applications that require high-speed CPU processing. This microcontroller contains 254-kilobyte flash ROM and 4-kilobyte RAM.
Page 27 • Automatic wait cycle: Any number of cycles (0 to 7) can be set for each area. • Unused data and address terminals can be used as I/O ports. • Support for little endian mode (selecting one of areas 1 to 5) DRAM interface •...
Page 28 CHAPTER 1 OVERVIEW conversion • Starting: Selectable from software, external trigger, and internal timer Reload timer • 16-bit timer: Three channels • Internal clock: 2-clock cycle resolution. Selectable from 2-, 8-, and 32-frequency division mode Other interval timers • 16-bit timer: Three channels (U-Timer) •...
Page 29 Available Types MB91V106 IROM IRAM CROM CRAM Others MB91106 MB91F109 63 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 2 Kbyte 2 Kbyte 1.1 MB91F109 Characteristics 254 Kbyte 2 Kbyte 2 Kbyte...
Page 30: General Block Diagram Of Mb91F109
CHAPTER 1 OVERVIEW General Block Diagram of MB91F109 Figure 1.2.1 is a general MB91F109 block diagram. General Block Diagram of MB91F109 Figure 1.2-1 General Block Diagram of MB91F109 RAM 2KB Bit Search Module DMAC (8ch) DREQ0 DREQ1 DREQ2 DACK0 DACK1 DACK2 EOP0 EOP1 EOP2 Clock Control Unit X0 X1...
Page 31: Outside Dimensions
(FPT-100P-M06) Plastic QFP with 100 pins (F PT -100P -M06 ) 23.90 0.40 (.941 .016) 20.00 0.20 (.787 .008) INDEX LEAD No. 0.65(.0256)TYP 1994 FUJITSU LIMITED F100008-3C-2 EIAJ code Lead pitch Package width x length Lead shape Sealing Flat terminal section length 14.00 0.20...
Page 32: Figure 1.3-2 Outside Dimensions Of Fpt-100P-M05
Plastic LQFP with 100 pins (FPT-100P-M05) Plastic LQFP with 100 pins (FPT-100P-M05) 16.00 0.20(.630 .008)SQ 14.00 0.10(.551 .004)SQ INDEX LEAD No. 0.50(.0197)TYP 0.10(.004) 1995 FUJITSU LIMITED F100007S-2C-3 Lead pitch Package width x length Lead shape Sealing 1.50 .059 "B" "A"...
Page 33: Figure 1.3-3 Outside Dimensions Of Bga-112P-M01
Figure 1.3-3 Outside Dimensions of BGA-112P-M01 Plastic FBGA with 112 pins (BGA-112P-M01) Plastic FBGA with 112 pins (BGA-112P-M01) 10.00 0.10(.394 .004)SQ INDEX C0.80(.031) 1998 FUJITSU LIMITED B112001S-2C-2 Ball pitch Ball matrix Package width x length Sealing Mount height Ball size Note: The actual corner shape may differ from the drawing.
Page 34: Pin Arrangement Diagrams
CHAPTER 1 OVERVIEW Pin Arrangement Diagrams Figures 1.4.1 to 1.4.3 show the pin arrangements of the MB91F109. Pin Arrangements (QFP-100) PB2/CS0H PB3/DW0X EOP2/PB4/RAS1 DREQ2/PB5/CS1L DACK2/PB6/CS1H PB7/DW1X PA6/CLK PA5/CS5X PA4/CS4X EOP1/PA3/CS3X PA2/CS2X PA1/CS1X PA0/CS0X NMIX RSTX P80/RDY P81/BGRNTX P82/BRQ P83/RDX P84/WR0X P85/WR1X P20/D16 P21/D17...
Page 35: Figure 1.4-2 Lqfp-100 Pin Arrangements
Pin Arrangements (LQFP-100) Figure 1.4-2 LQFP-100 Pin Arrangements DREQ2/PB5/CS1L DACK2/PB6/CS1H PB7/DW1X PA6/CLK PA5/CS5X PA4/CS4X EOP1/PA3/CS3X PA2/CS2X PA1/CS1X PA0/CS0X NMIX RSTX P80/RDY P81/BGRNTX P82/BRQ P83/RDX P84/WR0X P85/WR1X P20/D16 MB91F109 (TOP VIEW) FPT-100P-M05 1.4 Pin Arrangement Diagrams AVSS/AVRL AVRH AVCC A24/EOP0/P70 A23/P67 A22/P66 A21/P65 A20/P64...
Page 36: Figure 1.4-3 Fbga-112 Pin Arrangements
CHAPTER 1 OVERVIEW Pin Arrangements (FBGA-112) INDEX Table 1.4.1 shows the cross-references of the FBGA package pin names. Figure 1.4-3 FBGA-112 Pin Arrangements TOP VIEW...
Page 37: Table 1.4-1 Fbga Package Pin Names
Table 1.4-1 FBGA Package Pin Names BALL-No. PIN-NAME RAS1/ PB4/ EOP2 CS0L/ PB1 INT1/ PE1 INT3/ SC2/ PE3 DACK1/ PE7 SI2/ OCPA1/ PF5 SC0/ OCPA3/ PF2 SI0/ TRG0/ PF0 N.C. CS1L/ PB5/ DREQ2 CS1H/ PB6/ DACK2 CS0H/ PB2 INT0/ PE0 INT2/ SC1/ PE2 DACK0/ PE6 SO2/ OPCA2/ PF6...
Page 38: Pin Functions
CHAPTER 1 OVERVIEW Pin Functions Tables 1.5.1 to 1.5.5 lists the MB91F109 pin functions. The numbers shown in the tables has nothing to do with the package pin numbers. Since pins have different pin numbers among QFP, LQFP, and FBGA, see Section 1.4, "Pin Arrangement Diagrams."...
Page 39 Table 1.5-1 Pin Functions (1/5) Pin name A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 Table 1.5-2 Pin Functions (2/5) Pin name A24/P70/EOP0 RDY/P80 BGRNTX/P81 BRQ/P82 RDX/P83 WR0X/P84 I/O circuit format Bits 16 to 23 of external address bus. When these pins are not used for the address bus, they can be used as general-purpose I/O ports (P60 to P67).
Page 40: Table 1.5-2 Pin Functions (2/5)
CHAPTER 1 OVERVIEW Table 1.5-2 Pin Functions (2/5) Pin name WR1X/P85 CS0X/PA0 CS1X/PA1 CS2X/PA2 CS3X/PA3/EOP1 CS4X/PA4 CS5X/PA5 CLK/PA6 I/O circuit format 16-bit bus width D15 to D08 WR0X D07 to D00 WR1X Note: WR1X is Hi-Z while it is in reset state. When it is used as a 16-bit bus, attach a pull-up resistor to the outside.
Page 41: Table 1.5-3 Pin Functions (3/5)
Table 1.5-3 Pin Functions (3/5) Pin name RAS0/PB0 CS0L/PB1 CS0H/PB2 DW0X/PB3 RAS1/PB4/EOP2 CS1L/PB5/DREQ2 CS1H/PB6/DACK2 DW1X/PB7 RSTX NMIX INT0/PE0 INT1/PE1 I/O circuit format RAS output of DRAM bank 0 CASL output of DRAM bank 0 CASH output of DRAM bank 0 WE output of DRAM bank 0 (Low active) RAS output of DRAM bank 1 CASL output of DRAM bank 1...
Page 42: Table 1.5-4 Pin Functions (4/5)
CHAPTER 1 OVERVIEW Table 1.5-3 Pin Functions (3/5) Pin name INT2/SC1/PE2 INT3/SC2/PE3 Table 1.5-4 Pin Functions (4/5) Pin name DREQ0/PE4 DREQ1/PE5 DACK0/PE6 I/O circuit format [INT2] Input of external interrupt request. This input is used from time to time while the corresponding external interrupt is enabled.
Page 43 Table 1.5-4 Pin Functions (4/5) Pin name DACK1/PE7 SI0/TRG0/PF0 SO0/TRG1/PF1 SC0/OCPA3/PF2 SI1/TRG2/PF3 I/O circuit format [DACK1] Output of DMAC external transfer request acceptance (ch1). This function is valid when the output of DMAC transfer request acceptance is enabled. [PE7] General-purpose I/O port. This function is valid when the output of DMAC transfer request acceptance or DACK1 output is disabled.
Page 44: Table 1.5-5 Pin Functions (5/5)
CHAPTER 1 OVERVIEW Table 1.5-4 Pin Functions (4/5) Pin name SO1/TRG3/PF4 Table 1.5-5 Pin Functions (5/5) Pin name SI2/OCPA1/PF5 SO2/OCPA2/PF6 OCPA0/PF7/ATGX AN0 to AN3 AVCC I/O circuit format [SO1] UART1 data output. This function is valid when UART1 data output is enabled. [TRG3] External trigger input of PWM timer.
Page 45 Table 1.5-5 Pin Functions (5/5) Pin name AVRH AVSS/AVRL Note: An I/O port and resource I/O are multiplexed, as shown like xxxx/Pxx, at most pins listed above. If the port conflicts with resource output at this type of pin, the resource output is given priority. I/O circuit format Reference voltage of A/D converter (high potential...
Page 46: I/O Circuit Format
CHAPTER 1 OVERVIEW I/O Circuit Format Tables 1.6.1 and 1.6.2 shows I/O circuit formats. I/O Circuit Format Table 1.6-1 I/O circuit format (1/2) Classification Diffused resistor Circuit format Clock input STANDBY P-channel transistor N-channel transistor Digital input CMOS Control signal Mode input Diffused resistor Remarks...
Page 47: Table 1.6-2 I/O Circuit Format (1/2)
Table 1.6-1 I/O circuit format (1/2) Classification Diffused resistor Table 1.6-2 I/O circuit format (1/2) Classification Diffused resistor STANDBY Diffused resistor STANDBY Diffused resistor Circuit format P-channel transistor N-channel transistor Digital input CMOS Circuit format Digital output Digital output Digital input Digital output Digital output Digital input...
Page 48: Memory Address Space
CHAPTER 1 OVERVIEW Memory Address Space The logical address space of the FR series consists of 4 gigabytes (2 the CPU accesses them linearly. Memory map Figure 1.7.1 shows the memory address space of the MB91F109. External-ROM external-bus mode 0000 0000 0000 0400 0000 0800 Access inhibited...
Page 49 Direct addressing area The following area in the address space is used for I/O. addressing area. The addresses in this area can be directly specified for instruction operands. The direct addressing area varies depending on the size of accessed data as follows: •...
Page 50: Handling Of Devices
CHAPTER 1 OVERVIEW Handling of Devices This section provides notes on using devices. Device Handling Latchup prevention If voltage higher than Vcc or lower than Vss is applied to a CMOS IC input or output pin or if voltage exceeding the rating is applied between Vcc and Vss, latchup may be caused. Latchup rapidly increases supply current and may cause thermal damage to the device.
Page 51: Figure 1.8-2 Example Of Using An External Clock (Possible At 12.5 Mhz Or Lower)
Figure 1.8-2 Example of Using an External Clock (Possible at 12.5 MHz or Lower) Connection of power pins (Vcc and Vss) When two or more Vcc or Vss pins are used, the device is designed so that the pins, which should be at the same potential, are connected to one another inside the device to prevent a malfunction such as a latchup.
Page 52 CHAPTER 1 OVERVIEW Initialization by power-on reset Devices contain registers that are initialized only by power-on reset. registers, turn the power off and turn it on again to execute power-on resetting. Recovery from sleep or stopped state To recover from the sleep or stopped state that has been entered from a program in C-bus RAM, do not use an interrupt but execute resetting.
Page 53: Chapter 2 Cpu
CHAPTER 2 This chapter provides basic information on the FR series CPU core functions including the architecture, specifications, and instructions. 2.1 CPU Architecture 2.2 Internal Architecture 2.3 Programming Model 2.4 Data Structure 2.5 Word Alignment 2.6 Memory Map 2.7 Instruction Overview 2.8 EIT (Exception, Interrupt, and Trap) 2.9 Reset Sequence 2.10 Operation Mode...
Page 54: Cpu Architecture
CHAPTER 2 CPU CPU Architecture The FR30 CPU is a high performance core that uses the RISC architecture and supports advanced functional instructions geared to embedding applications. Characteristics of CPU Architecture RISC architecture • Basic instruction: One instruction per cycle 32-bit architecture •...
Page 55: Internal Architecture
Internal Architecture The FR CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other. The "32 bits <--> 16 bits" bus converter is connected to the data bus (D-BUS) to implement the interface between the CPU and peripheral resources. The "Harvard <--> Princeton"...
Page 56: Figure 2.2-2 Instruction Pipeline
CHAPTER 2 CPU Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instructions are always executed in order. That is, instruction A that is put into the pipeline before instruction B always reaches the write back stage before instruction B. Instructions are normally executed at a rate of one instruction per cycle.
Page 57: Programming Model
Programming Model This section explains the CPU registers that are essential for programming. The CPU registers are classified into the following two groups: • General-purpose registers • Special registers General-Purpose Registers Figure 2.3.1 shows the configuration of general-purpose registers. Figure 2.3-1 Configuration of general-purpose registers R 12 R 13 R 14...
Page 58: Figure 2.3-2 Configuration Of Special Registers
CHAPTER 2 CPU Figure 2.3-2 Configuration of special registers Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplication/division result register 32 bits...
Page 59: General-Purpose Registers
2.3.1 General-Purpose Registers Registers R0 to R15 are general-purpose registers. They are used as accumulators for various types of operation or memory access pointers. General-Purpose Registers Figure 2.3.3 shows the configuration of general-purpose registers. Figure 2.3-3 Configuration of General-Purpose Registers R 12 R 13 R 14...
Page 60: Special Registers
CHAPTER 2 CPU 2.3.2 Special Registers The special registers are used for special purposes. They are the program counter (PC), program status (PS), table base register (TBR), return pointer (RP), system stack pointer (SSP), user stack pointer (USP), and multiplication/division result register (MDH/MDL).
Page 61 Program status (PS) The program status register holds the program status in three parts, CCR, SCR, and ILM. See Section 2.3.3 for more information. The undefined bits are all reserved. When the register is read, 0 is always read from these bits. No data can be written to this register.
Page 62 CHAPTER 2 CPU [Division] When calculation begins, a dividend is stored in the MDL. The result of division by the DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction is stored in the MDL and MDH as follows: • MDH: Remainder • MDL: Quotient...
Page 63: Program Status Register (Ps)
2.3.3 Program Status Register (PS) The program status register holds the program status in three parts, ILM, SCR, and CCR. The undefined bits are all reserved. When the register is read, 0 is always read from these bits. No data can be written to this register. Program Status Register (PS) The configuration of the program status register (PS) is shown below: Condition code register (CCR)
Page 64 CHAPTER 2 CPU [bit 3] N: Negative flag This bit indicates a sign applicable when the operation result is assumed to be an integer that is represented in two’s complement. 0: Indicates that the operation result is a positive value. 1: Indicates that the operation result is a negative value.
Page 65 [bit 8] T: Step-trace-trap flag This flag specifies whether to enable step-trace-trap. 0: Disables step-trace-trap. 1: Enables step-trace-trap. Setting the bit to 1 inhibits all user NMIs and user interrupts. The flag is cleared to 0 by resetting. The step-trace-trap function is used by an emulator. It cannot be used in user programs while it is used by the emulator.
Page 66: Data Structure
CHAPTER 2 CPU Data Structure FR-series data is mapped as follows: • Bit ordering: Little endian • Byte ordering: Big endian Bit Ordering The FR series uses little endian for bit ordering. Figure 2.4.1 shows data mapping in bit ordering mode. Figure 2.4-1 Data Mapping in Bit Ordering Mode Byte Ordering The FR series uses big endian for byte ordering.
Page 67: Word Alignment
Word Alignment Since instructions and data are accessed in bytes, mapping addresses vary depending on instruction length or data width. Program Access A program running in the FR series must be placed at an address consisting of a multiple of two.
Page 68: Memory Map
CHAPTER 2 CPU Memory Map This section shows an MB91F109 memory map and a memory map common to the FR series. MB91F109 Memory Map The address space is 32 bits long linearly. Figure 2.6.1 shows an MB91F109 memory map. 0000 0000 0000 0100 0000 0200 0000 0400...
Page 69: Figure 2.6-2 Memory Map Common To The Fr Series
Memory Map Common to the FR Series The FR series defines the following memory map. This memory map is common throughout the FR series regardless of types (except in single chip mode). Figure 2.6.2 shows the memory map common to the FR series. Figure 2.6-2 Memory Map Common to the FR Series.
Page 70: Instruction Overview
CHAPTER 2 CPU Instruction Overview The FR series supports logical operation, bit manipulation, and direct addressing instructions, which are optimized for embedding applications, in addition to general RISC instructions. Each instruction, which is 16 bits long (some are 32 bits or 48 bits long), shows excellent memory use efficiency.
Page 71 2.7 Instruction Overview Logical operation and bit manipulation A logical operation instruction can execute AND, OR, or EOR logical operation between general-purpose registers or between a general-purpose register and memory (or I/O). A bit manipulation instruction can directly manipulate the contents of memory (or I/O). These instructions use general register indirect memory addressing.
Page 72: Branch Instructions With Delay Slots
CHAPTER 2 CPU 2.7.1 Branch Instructions with Delay Slots A branch instruction causes the program to branch and execute the instruction at the branch destination after the instruction (called the delay slot) placed immediately after the branch instruction is executed. Branch Instructions with Delay Slots The following instructions execute branch operation with a delay slot: JMP:D...
Page 73 Ri that is referenced by the JMP:D @Ri or CALL:D @Ri instruction is not affected even when the instruction in the delay slot updates the Ri. [Example] LDI:32 #Label, JMP:D LDI:8 RP that is referenced by the RET:D instruction is not affected even when the instruction in the delay slot updates the RP.
Page 74 CHAPTER 2 CPU Restrictions on Branch Instructions with Delay Slots Instructions that can be placed in delay slots An instruction that can be executed in the delay slot must satisfy all of the following conditions: • One-cycle instruction • Non-branch instruction •...
Page 75: Branch Instructions Without Delay Slots
2.7.2 Branch Instructions without Delay Slots Instructions including branch instructions without delay slots are executed in order of coding. Branch Instructions Without Delay Slots The instructions represented as follows execute branching without delay slots: label9 label9 label9 label9 Theory of Operation of Branch Instructions Without Delay Slots Instructions including branch instructions without delay slots are executed in order of coding.
Page 76: Eit (Exception, Interrupt, And Trap)
CHAPTER 2 CPU EIT (Exception, Interrupt, and Trap) EIT indicates that the program being executed is interrupted by an event and another program is executed. EIT is a generic name coined from the words: exception, interrupt, and trap. An exception is an event that occurs in connection with the context of the current execution.
Page 77 2.8 EIT (Exception, Interrupt, and Trap) Note on EIT Delay slot The delay slot of a branch instruction has restrictions on EIT. See Section 2.7, "Instruction Overview," for details of the restrictions.
Page 78: Eit Interrupt Levels
CHAPTER 2 CPU 2.8.1 EIT Interrupt Levels The EIT interrupt levels range from 0 to 31, which are managed using five bits. Interrupt Levels Table 2.8.1 summarizes the assignments of the EIT interrupt levels. Table 2.8-1 Interrupt Level Level Binary Decimal 00000 00011...
Page 79 I Flag The I flag specifies whether to enable or disable interrupts. It is provided at bit 4 of PS register CCR. Value Disables interrupts. The bit is cleared to 0 when the INT instruction is executed. (The value before the bit is cleared is saved to the stack.) Enables interrupts.
Page 80: Interrupt Control Register (Icr)
CHAPTER 2 CPU 2.8.2 Interrupt Control Register (ICR) The interrupt control register, which is provided in the interrupt controller, is used to set the level for each interrupt request. The ICR is divided to correspond to individual interrupt causes. The ICR is mapped in the I/O address space and accessed from the CPU via the bus.
Page 81: System Stack Pointer (Ssp)
2.8.3 System Stack Pointer (SSP) The system stack pointer (SSP) indicates the stack used to save data for EIT processing or restore data for returning from EIT. System Stack Pointer (SSP) The configuration of the system stack pointer (SSP) register is shown below: bit31 Value 8 is subtracted from the stack pointer during EIT processing, and 8 is added to it during returning from EIT.
Page 82: Interrupt Stack
CHAPTER 2 CPU 2.8.4 Interrupt Stack The interrupt stack is the area indicated by the system stack pointer (SSP). The PC or PS value is saved to it or restored from it. After an interrupt is caused, the PC value is stored at the address indicated by the SSP and the PS value is stored at the address "SSP + 4."...
Page 83: Table Base Register (Tbr)
2.8.5 Table Base Register (TBR) The table base register (TBR) indicates the first address of the EIT vector table. Table Base Register (TBR) The configuration of the table base register (TBR) is shown below: bit31 The address obtained by adding the offset defined for each EIT cause to the TBR is a vector address.
Page 84: Eit Vector Table
CHAPTER 2 CPU 2.8.6 EIT Vector Table The 1-kilobyte area beginning from the address, indicated by the table base register (TBR), is the EIT vector area. EIT Vector Table The area size per vector is 4 bytes. The relationship between a vector number and vector address is represented as follows: vctadr vctadr:...
Page 85: Table 2.8-3 Vector Table
Table 2.8.3 is the vector table in the architecture. Special functions are assigned to some vectors. Table 2.8-3 Vector Table Vector offset Vector number (hexadecimal) Hexadecima Fixed address 000FFFFC See Appendix B, "Interrupt Vector," for the vector table for the MB91F109. Decimal Reset (*1) Reserved by the system...
Page 86: Multiple Eit Processing
CHAPTER 2 CPU 2.8.7 Multiple EIT Processing When multiple EIT events occur concurrently, the CPU selects one EIT event, accepts it, executes the EIT sequence, and then detects another EIT event. It repeats this operation for all EIT events. When no more acceptable EIT event is detected, the CPU executes the instruction of the handler of the EIT event accepted last.
Page 87: Figure 2.8-2 Example Of Multiple Eit Processing
Table 2.8-5 EIT Handler Execution Order Handler execution order The other EIT events are discarded. The INTE instruction cannot be used in an environment where a step-trace-trap EIT event occurs. Figure 2.8.2 shows an example of multiple EIT processing. Figure 2.8-2 Example of Multiple EIT Processing Main routine Priority (High) NMI occurrence...
Page 88: Eit Operation
CHAPTER 2 CPU 2.8.8 EIT Operation This section explains EIT operation. Suppose the transfer source "PC" appearing in the following explanation indicates the address of the instruction that detected an EIT event. "Next instruction address" appearing in the following explanation means the address of the instruction that detected EIT as follows: •...
Page 89 [Operation] SSP - 4 --> SSP PS --> (SSP) SSP - 4 --> SSP Next instruction address --> (SSP) Interrupt level of accepted request --> ILM "0" --> S flag (TBR + vector offset of accepted interrupt request) --> PC Before executing the first instruction of the handler after the end of an interrupt sequence, the CPU detects another EIT.
Page 90 CHAPTER 2 CPU Operation for Step-trace-trap After the T flag in the PS SCR is set to enable the step-trace function, a trap occurs every time an instruction is executed, resulting in a break. A step-trace-trap is detected under the following conditions: •...
Page 91 Coprocessor Nonexistent Trap If a coprocessor instruction that attempts to use a coprocessor that is not installed is executed, a coprocessor nonexistent trap occurs. [Operation] SSP - 4 --> SSP PS --> (SSP) SSP - 4 --> SSP Next instruction address --> (SSP) "0"...
Page 92: Reset Sequence
CHAPTER 2 CPU Reset Sequence This section explains CPU resetting. Causes of Resetting The causes of resetting are as follows: • Input from an external reset pin • Software reset by manipulation of the SRST bit of standby control register (STCR) •...
Page 93: Operation Mode
2.10 Operation Mode Two operation modes, bus mode and access mode, are available. The mode pins (MD2, MD1, and MD0) and mode register (MODR) are used to control the operation mode. Operation Mode Two operation modes, bus mode and access mode, are available. Bus mode Single chip Internal-ROM-external bus...
Page 94: Figure 2.10-1 Mode Register Configuration
CHAPTER 2 CPU Mode Data Data that the CPU writes at 0000 07FF The mode register (MODR) exists at 0000 07FF CPU operates based on the mode set to the register. Mode data can be written to the mode register only once after resetting. The mode set to the register is validated immediately after it is set.
Page 95 2.10 Operation Mode MODR writing RSTX (reset) MD2,1,0 Bus width specification BW1 and BW0 of AMD0 to AMD5...
Page 96 CHAPTER 2 CPU...
Page 97: Chapter 3 Clock Generator And Controller
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER This chapter provides detailed information on the generation and control of clock pulses that control the MB91F109. 3.1 Outline of Clock Generator and Controller 3.2 Reset Reason Resister (RSRR) and Watchdog Cycle Control Register (WTCR) 3.3 Standby Control Register (STCR) 3.4 DMA Request Suppression Register (PDRR)
Page 98: Outline Of Clock Generator And Controller
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Outline of Clock Generator and Controller The clock generator and controller are the modules that have the following functions: • CPU clock generation (including the gear function) • Peripheral clock generation (including the gear function) •...
Page 99: Figure 3.1-2 Block Diagram Of The Clock Generator And Controller
Clock Generator and Controller Block Diagram Figure 3.1.2 is a block diagram of the clock generator and controller. Figure 3.1-2 Block Diagram of the Clock Generator and Controller Oscilla- tion circuit Internal interrupt Internal reset CPU hold permission DMA request Power-on reset RSTX pin 3.1 Outline of Clock Generator and Controller...
Page 100: Reset Reason Resister (Rsrr) And Watchdog Cycle Control Register (Wtcr)
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Reset Reason Resister (RSRR) and Watchdog Cycle Control Register (WTCR) The reset reason register (RSRR) holds the type of the reset event that occurred, and the watchdog cycle control register (WTCR) specifies the cycle of the watchdog timer. Configuration of Reset Reason Register (RSRR) and Watchdog Cycle Control Register (WTCR) The configuration of the reset reason register (RSRR) and watchdog cycle control register (WTCR) is shown below:...
Page 101: Table 3.2-1 Watchdog Timer Cycles Specified By Wt1 And Wt0
3.2 Reset Reason Resister (RSRR) and Watchdog Cycle Control Register (WTCR) [bit 09, 08] WT1, 0 These bits specify the cycle of the watchdog timer. The bits and the cycles selected by the bits have the relationships shown in Table 3.2.1. These bits are initialized when the entire register is reset.
Page 102: Standby Control Register (Stcr)
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Standby Control Register (STCR) The standby control register (STCR) is used to control standby operation and specify the oscillation stabilization wait time. Configuration of Standby Control Register (STCR) The configuration of standby control register (STCR) is shown below: 00000481 STOP SLEP HIZX SRST OSC1 OSC0 Bit Functions of the Standby Control Register (STCR)
Page 103: Table 3.3-1 Oscillation Stabilization Wait Time Specified By Osc1 And Osc0
Table 3.3-1 Oscillation Stabilization Wait Time Specified by OSC1 and OSC0 OSC1 OSC0 is twice as large as X0 when GCR CHC is 1, and is the cycle of PLL oscillation frequency when CHC is 0. [bit 01, 00] (Reserved) These bits are reserved.
Page 104: Dma Request Suppression Register (Pdrr)
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER DMA Request Suppression Register (PDRR) The DMA request suppression register (PDRR) is used to temporarily suppress DMA requests to lighten the load to the CPU. Configuration of the DMA Request Suppression Register (PDRR) The configuration of the DMA request suppression register (PDRR) is shown below: 00000482 Bit Functions of the DMA Request Suppression Register (PDRR) [bit 11 to bit 08] D3 to D0...
Page 105: Timebase Timer Clear Register (Ctbr)
Timebase Timer Clear Register (CTBR) The timebase timer clear register (CTBR) clears the timebase timer to 0 for initialization. Configuration of the Timebase Timer Clear Register (CTBR) The configuration of the timebase timer clear register (CTBR) is shown below: 00000483 Bit Functions of the Timebase Timer Clear Register (CTBR) [bit 07 to bit 00] When A5...
Page 106: Gear Control Register (Gcr)
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Gear Control Register (GCR) The gear control register (GCR) controls the gear functions of the CPU and peripheral clocks. Configuration of the Gear Control Register (GCR) The configuration of the gear control register (GCR) is shown below: 00000484 CCK1 CCK0 DBLAK DBLON PCK1 Bit Functions of the Gear Control Register (GCR)
Page 107: Table 3.6-2 Peripheral Machine Clock
DBLAK Internal : external operating frequency Operating at 1:1 [Initial value] Operating at 2:1 [bit 12] DBLON This bit specifies the clock doubler operation mode. This bit is initialized by resetting. This model does not support the clock doubler function. DBLON Internal : external operating frequency Operating at 1:1 [Initial value]...
Page 108 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER When the clock doubler is set to ON, the CPU gear is fixed regardless of the GCR value and therefore the gear can also be set directly to the desired value. [Example of programming] #0×484, #0×0d, #0×484,...
Page 109: Watchdog Timer Reset Delay Register (Wpr)
Watchdog Timer Reset Delay Register (WPR) The watchdog timer reset delay register (WPR) clears the flip-flop for the watchdog timer. This register can be used to delay watchdog timer resets. Configuration of Watchdog Timer Reset Delay Register (WPR) The configuration of the watchdog timer reset delay register (WPR) is shown below: 00000485 Bit Functions of Watchdog Timer Reset Delay Register (WPR) Bits 07 to 00 (D7 to D0)
Page 110: Pll Control Register (Pctr)
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER PLL Control Register (PCTR) The PLL control register (PCTR) is used to control PLL oscillation. The setting of this register can be changed only when GCR CHC is 1. Configuration of PLL Control Register (PCTR) The PLL control register (PCTR) is used to control PLL oscillation.
Page 111: Gear Function
Gear Function The gear function supplies clock pulses by slowing down the clock pulse intervals. The function uses two independent circuits for the CPU and peripherals. Data can be transferred between the CPU and peripherals even when both circuits use different gear ratios.
Page 112 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] LDI:20 #GCR,R2 LDI:8 #11111110b,R1 R1.@R2 LDI:8 #01111010b,R1 R1,@R2 LDI:8 #00111010b,R1 R1,@R2 LDI:8 #00110010b,R1 R1,@R2 LDI:8 #10110010b,R1 R1,@R2 The output from the divide-by-two frequency circuit can be selected as the source clock by setting the CHC bit of the gear control register to 1. Setting the CHC bit to 0 selects the clock having the same cycle as the clock generated from the oscillation circuit.
Page 113: Figure 3.9-2 Clock Selection Timing Chart
Figure 3.9-2 Clock Selection Timing Chart Source clock CPU clock (a) CPU clock (b) Peripheral clock (a) Peripheral clock (b) CCK value PCK value Blocks That Use the Peripheral Clock The blocks listed below use the peripheral clock, which can be set by the gear function, as the operating clock.
Page 114: Standby Mode (Low Power Consumption Mechanism)
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10 Standby Mode (Low Power Consumption Mechanism) The standby mode implies the stop state and sleep state. Outline of Stop State In the stop state, all internal clocks and the operation of the oscillation circuit are stopped so as to minimize power consumption.
Page 115 *: When STCR HIZX is "0", the previous state is held. Setting HIZX to "1" puts the pin to Hi-Z. <Note> Reset: RSTX = "0" SRST bit of STCR register = "0" Watchdog timer reset Power-on reset Mapping Addresses of Programs Used to Put Systems into Stop or Sleep State Place programs which are used to put clock systems into stop or sleep state into C-bus ROM or external memory address areas.
Page 116: Stop State
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10.1 Stop State This section provides information on transition to and returning from the stop state. Figure 3.10.1 shows a stop controller block diagram. Stop Controller Block Diagram Internal bus STOP Internal interrupt .or. Internal reset CPU hold enabled CPU hold request...
Page 117 [Example of setting the maximum gear speed:] LDI:20 LDI:8 loop BTSTH LDI:20 LDI:8 Returning from the Stop State An interrupt or resetting can be used to return from the stop state. Return by way of an interrupt When the interrupt enable bit, which is one of the peripheral functions, is on, a peripheral interrupt can be caused to return from the stop state.
Page 118 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER L level application to RSTX pin --> occurrence of internal reset --> restart of oscillation circuit operation --> wait for oscillation stabilization --> restart of internal peripheral clock supply after stabilization --> restart of internal DMA clock supply --> restart of internal bus clock supply -->...
Page 119: Sleep State
3.10.2 Sleep State This section provides information on transition to the sleep state and returning from the sleep state. Figure 3.10.2 shows a block diagram of the sleep controller. Sleep Controller Block Diagram Internal bus SLEP Internal interrupt .or. Internal reset CPU hold enabled CPU hold request Sleep state...
Page 120 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example of setting the maximum gear speed] LDI:20 #GCR,R0 LDI:8 #00000011b,R1 R1,@R0 LDI:20 #STCR,R0 LDI:8 #01010000b,R1 R1,@R0 Returning from the Sleep State An interrupt or resetting can be used to return from the sleep state. Return by way of an interrupt When the enable bit for the interrupt, which is one of the peripheral functions, is on, a peripheral interrupt can be used to return from the sleep state.
Page 121 3.10 Standby Mode (Low Power Consumption Mechanism) request occur simultaneously, the DMA request is given priority. • When transition to the sleep state has been caused by a C-bus RAM program, do not use an interrupt, but reset instead to return from the sleep state.
Page 122: Standby Mode State Transition
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.10.3 Standby Mode State Transition Figure 3.10.3 is a standby mode state transition diagram. Standby Mode State Transition Oscillation stabilization wait state Stop state (1) End of oscillation stabilization wait time (2) Cancel of reset state (3) Input of reset Figure 3.10-3 Standby Mode State Transition Oscillation...
Page 123: Watchdog Function
3.11 Watchdog Function The watchdog function detects program crashes. If A5 and 5A are not written to the watchdog reset postpone register within the specified time due to a program crash, the watchdog timer issues a watchdog reset request. Watchdog Controller Block Diagram Figure 3.11.1 is a watchdog controller block diagram.
Page 124: Figure 3.11-2 Watchdog Timer Operating Timing
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Figure 3.11-2 Watchdog Timer Operating Timing Timebase timer overflow Watchdog flip-flop WTE write <Note> • The time interval between the first A5 resetting is postponed only if the time interval from one 5A specified by the WT bits and one A5 •...
Page 125: Reset Source Hold Circuit
3.12 Reset Source Hold Circuit The reset source hold circuit holds the source of previous resetting. Reading the circuit clears all flags to 0. Once a source flag is set, it is not cleared unless the circuit is read. Block Diagram of Reset Source Hold Circuit Figure 3.12.1 is a block diagram of the reset source hold circuit.
Page 126 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] RESET-ENTRY LDI:20 LDI:8 LDUB <Notes> • When the PONR bit is 1, assume that the contents of the other bits are undefined. When it is required to check reset sources, place a power-on reset check instruction at the beginning. •...
Page 127: Dma Suppression
3.13 DMA Suppression If an interrupt with a higher priority occurs during DMA transfer, the FR series interrupts DMA transfer and branches to the corresponding interrupt routine. This feature remains effective as long as an interrupt request continues. When the interrupt cause is cleared, the suppression feature is canceled and DMA transfer resumes in the interrupt processing routine.
Page 128 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] INT-ENTRY LDI:20 LDI:20 LDI:8 interrupt execute routine LDI:20 ADD2 RETI <Note> Since the register consists of four bits, the DMA suppression function cannot be used for more than 15 concurrent interrupts. Always give a DMA task a priority that is at least 15 levels higher than that of other interrupts.
Page 129: Clock Doubler Function
3.14 Clock Doubler Function As the internal operating frequency goes higher, the external bus timing normally becomes more complicated. To prevent this, the ratio of the external bus frequency to the internal operating frequency can be adjusted to 1 to 2 (1 : 2). This model does not support this function.
Page 130 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER [Example] DOUBLER-OFF LDI:20 BORL BANDH Code as follows to use the PLL clock after the clock doubler function is disabled: [Example] DOUBLER-OFF LDI:20 BORL BANDH LDI:20 LDI:8 BANDL Note on Enabling or Disabling the Clock Doubler Function Enabling or disabling the clock doubler function may cause a dead cycle in the internal clock.
Page 131: Table 3.14-1 Operating Frequency Combinations Depending On Whether The Clock Doubler Function Is Enabled Or Disabled
register. (Table 3.14.1 shows an example for the case that a 12.5 MHz oscillation is used.) Table 3.14-1 Operating Frequency Combinations Depending on whether the Clock Doubler Function is Enabled or Disabled oscillation Gear frequency (MHz) Divide- by-two (*1) PLL * 50.0 25.0 25.0...
Page 132: Example Of Pll Clock Setting
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3.15 Example of PLL Clock Setting This section provides an example of PLL clock setting and an example of the assembler source. Example of PLL Clock Setting An example of the procedure for switching to 25 MHz operation using PLL (in the case of 12.5 MHz oscillation) is shown below: CHC = 1 DBLON = 0...
Page 133: Figure 3.15-1 Example Of Pll Clock Setting
• The peripheral operating frequency must not exceed 25 MHz. • Design software so that 100 microseconds or more are allowed until oscillation stabilizes after the PLL VC0 restarts. Do not allow cache on/off to cause a wait time shortage. Clock System Reference Diagram Figure 3.15-2 Clock System Reference Diagram 12.5MHz...
Page 134 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER CHC_1: call VCO_RUN PLL_SET_END: @R15+, PS ; ************************************************************ VCO Setting ; ************************************************************ VCO_RUN: R3, @-R15 ldi:8 #PCTR _MASK, R3 R5, R3 LOOP_100US_END bandl #0111B, @r1 R2, @-R15 ldi:20 #0x15E, R2 WAIT_100US: add2 #(-1), R2 WAIT_100US LOOP_100US_END: @R15+, R2...
Page 135: Chapter 4 Bus Interface
CHAPTER 4 BUS INTERFACE This chapter explains the basic items of the external bus interface, register configuration and functions, bus operations, and bus timing and provides bus operation program samples. 4.1 Outline of Bus Interface 4.2 Chip Select Area 4.3 Bus Interface 4.4 Area Select Register (ASR) and Area Mask Register (AMR) 4.5 Area Mode Register 0 (AMD0) 4.6 Area Mode Register 1 (AMD1)
Page 136: Outline Of Bus Interface
CHAPTER 4 BUS INTERFACE Outline of Bus Interface The bus interface controls the interface between external memory and I/O. Features of the Bus Interface • 25-bit (32 megabytes) address output • 6 independent banks to be set by chip select function •...
Page 137: Figure 4.1-1 Bus Interface Registers
Bus Interface Registers Figure 4.1.1 shows the bus interface registers. 31 -------- 24 23 -------- ASR 1 (Area Select Reg. 1) ASR 2 (Area Select Reg. 2) (Area Select Reg. 3) ASR 3 (Area Select Reg. 4) ASR 4 ASR 5 (Area Select Reg.
Page 138: Figure 4.1-2 Bus Interface Block Diagram
CHAPTER 4 BUS INTERFACE Block Diagram of the Bus Interface Figure 4.1.2 shows a block diagram of the bus interface ADDRESS BUS DATA BUS write read buffer address buffer from TBT Figure 4.1-2 Bus Interface Block Diagram buffer switch switch +1or+2 inpage shifter...
Page 139: Chip Select Area
Chip Select Area A total of six types of chip select area are prepared for the bus interface. Setting Chip Select Areas Each area can be optionally located in units of at least 64 kilobytes in a 4 gigabyte area using the area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5).
Page 140: Bus Interface
CHAPTER 4 BUS INTERFACE Bus Interface The bus interface include the following: • Usual bus interface • DRAM interface These interfaces can only be used in the predetermined area. Chip Select Areas and Bus Interfaces Table 4.3.1 shows the correspondence between each chip select area and available interface functions.
Page 141 4.3 Bus Interface Bus size specification A bus width can be optionally specified for each area by register setting. A bus width, set by pins MD2, MD1, and MD0 at reset time, is specified for area 0. After writing to the mode register (MODR), a bus size is specified by the value set in the AMD0 register.
Page 142: Area Select Register (Asr) And Area Mask Register (Amr)
CHAPTER 4 BUS INTERFACE Area Select Register (ASR) and Area Mask Register (AMR) The area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5) specify the range of address space for chip select areas 1 to 5. Configuration of Area Select Register (ASR) and Area Mask Register (AMR) The area select register (ASR) and area mask register (AMR) are configured as shown below.
Page 143 4.4 Area Select Register (ASR) and Area Mask Register (AMR) The area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5) specify the range of address space for chip select areas 1 to 5. ASR1 to ASR5 specify the upper 16 bits (A31 to A16) of each address, and AMR1 to AMR5 mask the corresponding address bits.
Page 144: Figure 4.4-1 Sample Maps Of The Chip Select Areas
CHAPTER 4 BUS INTERFACE Figure 4.4.1 shows a map of the areas set in the 64 kilobytes by initial values during reset and a map of the areas set in Examples 1 and 2. Figure 4.4-1 Sample Maps of the Chip Select Areas Initial value 00000000 Area 0...
Page 145: Area Mode Register 0 (Amd0)
Area Mode Register 0 (AMD0) Area mode register 0 (AMD0) specifies the operation mode of chip select area 0 (area other that those specified by ASR1 to ASR5 and AMR1 to AMR5). At reset time, area 0 is selected. Configuration of Area Mode Register 0 (AMD0) Area mode register 0 (AMD0) is configured as follows: AMD0 Address: 0000 0620...
Page 146 CHAPTER 4 BUS INTERFACE <Note> Before writing to the MODR, set the bus width, equal to that set by the MD2, MD1, and MD0 pins, in BW1 and BW0 of AMD0. The bus width of area 0 is specified by the MD2, MD1, and MD0 pins at reset time. After setting the mode register (MODR), the bus width set in AMD0 becomes valid.
Page 147: Area Mode Register 1 (Amd1)
Area Mode Register 1 (AMD1) Area mode register 1 (AMD1) specifies the operation mode of chip select area 1 (area specified by ASR1 and AMR1). Configuration of Area Mode Register 1 (AMD1) Area mode register 1 (AMD1) is configured as follows: AMD1 Address: 0000 0621...
Page 148: Area Mode Register 32 (Amd32)
CHAPTER 4 BUS INTERFACE Area Mode Register 32 (AMD32) Area mode register 32 (AMD32) controls the operation mode of chip select area 2 (area specified by ASR2 and AMR2) and chip select area 3 (area specified by ASR3 and AMR3). These areas are accessed only via the usual bus and do not allow the use of special DRAM interfaces.
Page 149: Area Mode Register 4 (Amd4)
Area Mode Register 4 (AMD4) Area mode register 4 (AMD4) specifies the operation mode of chip select area 4 (area specified by ASR4 and AMR4). Area 4 allows the use of the DRAM interface. Configuration of Area Mode Register 4 (AMD4) Area mode register 4 (AMD4) is configured as follows: AMD4 Address: 0000...
Page 150: Area Mode Register 5 (Amd5)
CHAPTER 4 BUS INTERFACE Area Mode Register 5 (AMD5) Area mode register 5 (AMD5) specifies the bus mode of chip select area 5 (area specified by ASR5 and AMR5). Area 5 allows the use of the DRAM interface. Configuration of Area Mode Register 5 (AMD5) Area mode register 5 (AMD5) is configured as follows: AMD5 Address: 0000...
Page 151: Dram Control Register 4/5 (Dmcr4/5)
4.10 DRAM Control Register 4/5 (DMCR4/5) DRAM control registers 4 and 5 (DMCR4 and DMCR5) control the DRAM interface for areas 4 and 5 and are valid only when the DRME bits of AMD4 and AMD5 are set to "1". Configuration of DRAM Control Register 4/5 (DMCR4/5) DRAM control register 4/5 are configured as follows: DMCR4...
Page 152 CHAPTER 4 BUS INTERFACE [bit 11] Q1W (Q1 wait bit) The Q1W bit specifies whether to extend the Q1cycle (the "H" interval of RAS), specified at DRAM access time, by one cycle. 0: Does not extend Q1 cycle (initial value). 1: Extends Q1 cycle.
Page 153: Table 4.10-2 Combinations Of Bus Widths Available In Areas 4 And 5
[bit 4] REFE (REFresh Enable bit) The REFE bit specifies whether to perform the cyclic refresh operation of the CAS before RAS (CBR) type. When starting the cyclic refresh, regardless of areas 4 and 5, set the REFE bit of DMCR4 or DMCR5 to "1" and set the STR bit of the refresh control register (RFCF).
Page 154: Refresh Control Register (Rfcr)
CHAPTER 4 BUS INTERFACE 4.11 Refresh Control Register (RFCR) The refresh control register (RFCR) controls the CBR (CAS before RAS) refresh operation when the DRAM interface is used. This register has a 6-bit downward counter that uses the divide-by-32 output of a timebase timer as a clock source and specifies a refresh interval by controlling its reload value by the RFCR.
Page 155 [bit 2] STR (STaRt bit) The STR bit controls or starts and stops the downward counter. 0: STOP (initial value) 1: START When the STR is set, the REL value is loaded into the downward counter. When the REFE bit of the DMCR and the STR bit are set to "1", the CRB refresh operation is performed.
Page 156: External Pin Control Register 0 (Epcr0)
CHAPTER 4 BUS INTERFACE 4.12 External Pin Control Register 0 (EPCR0) External pin control register 0 (EPCR0) controls the output of each signal. When output is permitted, this register outputs a desired timing signal in each bus mode. When the input is valid, it receives an input signal from the outside. When output is inhibited or the input is invalid, the register can be used as an I/O port.
Page 157 [bit 8] BRE (Bus Request Enable bit) The BRE bit controls the BRQ and BGRNTX signals as described below. When this bit is reset, the BRQ input becomes invalid and the BGRNTX output is inhibited. 0: Validates BRQ input and inhibits BGRNTX output (corresponding pins function as I/O ports).
Page 158 CHAPTER 4 BUS INTERFACE [bit 0] COE0 (Chip select Output Enable 0) The C0E0 bit controls the CS0X output. When this bit is reset, output is permitted. 0: Inhibits output. 1: Permits output (initial value). When the external bus mode is used, the C0E0 bit performs no I/O port control for the CS0X pin.
Page 159: External Pin Control Register 1 (Epcr1)
4.13 External Pin Control Register 1 (EPCR1) External pin control register 1 (EPCR1) controls address signal output. Configuration of External Pin Control Register 1 (EPCR1) External pin control register 1 (EPCR1) is configured as follows: EPCR1 Address: 0000 062A AE23 AE22 AE21 AE20 AE19 AE18 AE17 AE16 Bit Functions of External Pin Control Register 1 (EPCR1) [bit 8 to 0] AE24 to AE16 (Address output Enable 24 to 16) The AE24 to AE16 bits specify whether to output the corresponding addresses.
Page 160: Dram Signal Control Register (Dscr)
CHAPTER 4 BUS INTERFACE 4.14 DRAM Signal Control Register (DSCR) The DRAM signal control register (DSCR) controls the output of each DRAM control signal. When the output is inhibited, this register can be used as an I/O port. Configuration of DRAM Signal Control Register (DSCR) The DRAM signal control register (DSCR) is configured as follows: DSCR Address: 0000 0625...
Page 161 [bit 3] C0HE The C0HE bit controls the CS0H output. When this bit is reset, the output is inhibited. 0: Inhibits output (initial value). 1: Permits output. [bit 2] C0LE The C0LE bit controls the CS0L output. When this bit is reset, the output is inhibited. 0: Inhibits output (initial value).
Page 162: Little Endian Register (Ler)
CHAPTER 4 BUS INTERFACE 4.15 Little Endian Register (LER) When bus access by the MB91F109 is performed, the whole area is usually composed of big endians. However, setting the little endian register (LER) makes it possible to handle one of areas 1 to 5 as a little endian area. This register is supported for all bus modes independently of the usual, time sharing, and DRAM interfaces.
Page 163: Relationship Between Data Bus Widths And Control Signals
4.16 Relationship between Data Bus Widths and Control Signals Data bus control signals (WR0X-WR1X, CS0H, CS0L, CS1L, CS1H, DW0X, and DW1X) always correspond to data bus byte locations on a one-to-one basis, regardless of big and little endians and data bus widths. Relationship between Data Bus Widths and Control Signals The following outlines the byte locations of the data buses of this part number used in the specified data bus width and the control signals corresponding to those locations for each bus...
Page 164: Table 4.16-1 Relationship Between Data Bus Widths And Control Signals
CHAPTER 4 BUS INTERFACE Table 4.16-1 Relationship between Data Bus Widths and Control Signals Bus width Data bus D31-D24 WR0X D23-D16 WRIX 16-bit bus width 2CAS/1WE 1CAS/2WE CASL CASH 8-bit bus width 2CAS/1WE 1CAS/2WE WR0X...
Page 165: Bus Access With Big Endians
4.16.1 Bus Access with Big Endians When external bus access is performed for areas not set by the little endian register (LER), those areas are handled as big endians. The FR series usually employs big endians. Data Format The following shows the relationship between the internal register and external data bus for each data format.
Page 166: Figure 4.16-5 Relationship Between Internal Register And External Data Bus For Byte Access
CHAPTER 4 BUS INTERFACE Byte access (during execution of LDUB and STB instructions) Figure 4.16-5 Relationship between Internal Register and External Data Bus for Byte Access (a) Lower bits of output address "0" Internal register Data Bus Width The following shows the relationship between the internal register and external data bus for each data bus width.
Page 167: Figure 4.16-7 Relationship Between Internal Register And External Data Bus For 8-Bit Bus Width
8-bit bus width Figure 4.16-7 Relationship between Internal Register and External Data Bus for 8-bit Bus Width Lower part of the output address External Bus Access Figure 4.16-8 and Figure 4.16-9 show external bus access (in a 16-bit or 8-bit bus width) in words, half-words, and bytes.
Page 168: Figure 4.16-8 External Bus Access For 16-Bit Bus Width
CHAPTER 4 BUS INTERFACE 16-bit bus width Figure 4.16-8 External Bus Access for 16-bit Bus Width (A) Word access (a) PA1/PA0='00' Output A1/A0='00' Output A1/A0='10' 00 01 10 11 16bit (B) Half-word access (a) PA1/PA0='00' Output A1/A0='00' 00 01 10 11 (C) Byte access (a) PA1/PA0='00' Output...
Page 169: Figure 4.16-9 External Bus Access For 8-Bit Bus Width
8-bit bus width Figure 4.16-9 External Bus Access for 8-bit Bus Width (A) Word access PA1/PA0= '00' PA1/PA0= '01' 1)Output A1/A0 = '00' 1)Output A1/A0 = '00' 2)Output A1/A0 = '01' 2)Output A1/A0 = '01' 3)Output A1/A0 = '10' 3)Output A1/A0 = '10' 4)Output A1/A0 = '11' 4)Output A1/A0 = '11' MSB LSB...
Page 170: Figure 4.16-10 Example Of Connection Between Mb91F109 And External Devices
CHAPTER 4 BUS INTERFACE Example of Connection to External Devices Figure 4.16-10 Example of Connection between MB91F109 and External Devices D31 R D24 X D15 D08D07 D00 16-bit device* ("0"/"1" is the lower 1 bit of the address; the lower 1 bit of the address in "X" can be set to "0" or "1".) * For the 16/8-bit device, the data bus on the MSB side of the MB91F109 is used.
Page 171: Bus Access With Little Endians
4.16.2 Bus Access with Little Endians When external bus access is performed for areas set by the little endian register (LER), those areas are handled as little endians. Outline of Little Endians Little endian bus access by the MB91F109 uses the bus access operation for big endians. The address output sequence and control signal output for big endians are basically the same as those for little endians, which are implemented by swapping data bus byte locations according to the bus width.
Page 172: Figure 4.16-12 Relationship Between Internal Register And External Data Bus For Half-Word Access
CHAPTER 4 BUS INTERFACE Half-word access (during execution of LDUH and STH instructions) Figure 4.16-12 Relationship between Internal Register and External Data Bus for Half-word Access Byte access (during execution of LDUB and STB instructions) Figure 4.16-13 Relationship between Internal Register and External Data Bus for Byte Access (a) Lower bits of output address "0"...
Page 173: Figure 4.16-14 Relationship Between Internal Register And External Data Bus For 16-Bit Bus Width
Data Bus Width The following shows the relationship between the internal register and external data bus for each data bus width: 16-bit bus width Figure 4.16-14 Relationship between Internal Register and External Data Bus for 16-bit Bus Width Lower part of the output address 8-bit bus width Figure 4.16-15 Relationship between Internal Register and External Data Bus for 8-bit Bus Width Lower part of the output address...
Page 174: Figure 4.16-16 Example Of Connection Between Mb91F109 And External Devices (16-Bit Bus Width)
CHAPTER 4 BUS INTERFACE Example of Connection to External Devices 16-bit bus width Figure 4.16-16 Example of Connection between MB91F109 and External Devices (16-Bit Bus Width) MB91F109 D31 R D23 R D24 X D16 X Big endian area WR0X D31-24 D23-16 D15 D08D07 D00 8-bit bus width Figure 4.16-17 Example of Connection between MB91F109 and External Devices (8-Bit Bus Width)
Page 175: External Access
4.16.3 External Access This section lists several external accesses. Word Access Bus width 16-bit bus width 8-bit bus width 4.16 Relationship between Data Bus Widths and Control Signals Big endian mode Internal register External pin Control pin address: '0' '2' AA CC WR0X CASL WEL BB DD...
Page 176: Bus Width
CHAPTER 4 BUS INTERFACE Half-Word Access Bus width 16-bit bus width 8-bit bus width Big endian mode Internal register External pin Control pin address: 0 WR0X CASL WEL WR1X CASH WEH Internal register External pin Control pin address: 2 WR0X CASL WEL WR1X CASH WEH Internal register External pin Control pin...
Page 177 Byte Access Bus width 16-bit bus width 4.16 Relationship between Data Bus Widths and Control Signals Big endian mode Internal register External pin Control pin address: '0' WR0X CASL WEL Internal register External pin Control pin address: '1' WR1X CASH WEH Internal register External pin Control pin address: '2'...
Page 178 CHAPTER 4 BUS INTERFACE Bus width 8-bit bus width Big endian mode Internal register External pin Control pin address: WR0X CAS WE Internal register External pin Control pin address: WR0X CAS WE Internal register External pin Control pin address: WR0X CAS WE Internal register External pin Control pin address:...
Page 179: Dram Relationships
4.16.4 DRAM Relationships This section explains the DRAM relationships. DRAM Control Pins Table 4.16-2 lists the relationship between the pin functions and bus widths used in the DRAM interface. Table 4.16-2 Functions and Bus Widths of DRAM Control Pins Pin name RAS0 Area 4 RAS RAS1...
Page 180: Figure 4.16-18 Example Of Connection Between Mb91F109 And One 8-Bit Output Dram (8-Bit Data Bus)
CHAPTER 4 BUS INTERFACE Row and Column Addresses The page size select bits (PGS3 to PGS0) of DRAM control registers 4 and 5 (DMCR4 and DMCR5) determines whether to create DRAM interface addresses. When the high-speed page mode is used, PGS3 to PGS0 and the data bus width determine whether access is within a page.
Page 181: Figure 4.16-19 Example Of Connection Between Mb91F109 And Two 8-Bit Output Drams (16-Bit Data Bus)
16-bit data bus (using 2 DRAMs) Figure 4.16-19 Example of Connection between MB91F109 and Two 8-Bit Output DRAMs (16-Bit Data COLUMN Address A08 A07 A06 A05 A04 A03 A02 A01 A00 ROW Address A16 A15 A14 A13 A12 A11 A10 A09 A08 External pin A08 A07 A06 A05 A04 A03 A02 A01 A00 A07 A06 A05 A04 A03 A02 A01 A00...
Page 182: Figure 4.16-20 Example Of Connection Between Mb91F109 And Two 16-Bit Output Drams (16-Bit Data Bus)
CHAPTER 4 BUS INTERFACE Connection Example of DRAM Device • DRAM: 2CAS/1WE, page size 512, × 16-bit product • Bus width: 16 bits • Number of banks: 2 (areas 4 and 5) Figure 4.16-20 Example of Connection between MB91F109 and Two 16-Bit Output DRAMs (16-Bit Data This LSI (Area4 RAS) RAS0 (Area4 CASL) CSOL...
Page 183: Bus Timing
4.17 Bus Timing This section provides bus access timing charts used in each mode and explains bus access operation for the following items: • Usual bus access • Wait cycle • DRAM interfaceDRAM interface • DRAM refresh • External bus request Usual Bus Access The usual bus interface handles read cycles and write cycles in the same way, as 2-clock cycles.
Page 184 CHAPTER 4 BUS INTERFACE Usual DRAM interface The usual DRAM interface converts the CAS cycle to a 2-clock cycle by setting the DSAS and HYPR bits of DMCR4 and DCMR5 to "0". It handles "5-clock cycles" as basic bus cycles during read and write operations.
Page 185 • Hyper DRAM interface: Read • Hyper DRAM interface: Write • Hyper DRAM interface DRAM Refresh • CAS before RAS (CBR) refresh • Automatic wait cycle of CBR refresh • Selfrefresh External Bus Request • Bus control release • Bus control acquisition 4.17 Bus Timing...
Page 186: Basic Read Cycle
CHAPTER 4 BUS INTERFACE 4.17.1 Basic Read Cycle This section provides a chart of the basic read cycle timing. Basic Read Cycle Timing Chart Bus width: 16 bits, access: words, CS0 area access Figure 4.17-1 Example of Basic Read Cycle Timing Chart A24-00 D31-24 D23-16...
Page 187 • Output of CS0X to CS5X (area chip select) signals is asserted from the beginning (BA1) of bus cycles; that is, at the same time as A24-A00. The CS0X to CS5X signals are generated from decoded output addresses and remain unchanged unless those addresses change, thereby changing the chip select areas set by the ASR and AMR.
Page 188: Basic Write Cycles
CHAPTER 4 BUS INTERFACE 4.17.2 Basic Write Cycles This section provides a chart of the basic write cycle timing. Basic Write Cycle Timing Chart Bus width: 8 bits, access: words, CS0 area access Figure 4.17-2 Example for Basic Write Cycle Timing A24-00 D31-24 D23-16...
Page 189 specified areas are 8 bits wide, D23 to D16 automatically become I/O ports, which are set to High-Z. The above example shows the case, where D23 to D16 and WR1X are used as I/O ports. If the bus width of at least one of chip select areas 0 to 5 is set to 16 bits, D23 to D16 and WR1X cannot be used as I/O ports.
Page 190: Read Cycles In Each Mode
CHAPTER 4 BUS INTERFACE 4.17.3 Read Cycles in Each Mode This section provides read cycle timing charts in each mode. Read Cycle Timing Charts Bus width: 16 bits, access: half-words Figure 4.17-3 Example 1 of Read Cycle Timing Chart A24-00 D31-24 D23-16 Bus width: 16 bits, access: bytes...
Page 191: Figure 4.17-6 Example 4 Of Read Cycle Timing Chart
Bus width: 8 bits, access: half-words Figure 4.17-6 Example 4 of Read Cycle Timing Chart A24-00 D31-24 D23-16 Bus width: 8 bits, access: bytes Figure 4.17-7 Example 5 of Read Cycle Timing Chart A24-00 D31-24 D23-16 4.17 Bus Timing...
Page 192: Write Cycles In Each Mode
CHAPTER 4 BUS INTERFACE 4.17.4 Write Cycles in Each Mode This section provides write cycle timing charts in each mode. Write Cycle Timing Chart Bus width: 16 bits, access: words Figure 4.17-8 Example 1 of Write Cycle Timing Chart Bus width: 16 bits, access: half-words Figure 4.17-9 Example 2 of Write Cycle Timing Chart A24-00 D31-24...
Page 193: Figure 4.17-11 Example 4 Of Write Cycle Timing Chart
Bus width: 8 bits, access: half-words Figure 4.17-11 Example 4 of Write Cycle Timing Chart A24-00 D31-24 D23-16 WR0X WR1X Bus width: 8 bits, access: bytes Figure 4.17-12 Example 5 of Write Cycle Timing Chart A24-00 D31-24 D23-16 WR0X WR1X 4.17 Bus Timing...
Page 194: Read And Write Combination Cycles
CHAPTER 4 BUS INTERFACE 4.17.5 Read and Write Combination Cycles This section provides a read and write combination cycle timing chart. Read and Write Combination Cycle Timing Chart CS0 area: 16-bit bus width, word read CS1 area: 8-bit bus width, half-word read Figure 4.17-13 Example of Read and Write Combination Cycle Timing Chart A24-00 D31-24...
Page 195: Automatic Wait Cycles
4.17.6 Automatic Wait Cycles This section provides an automatic wait cycle timing chart. Automatic Wait Cycle Timing Chart Bus width: 16 bits, access: half-word read/write Figure 4.17-14 Example of Automatic Wait Cycle Timing Chart A24-00 D31-16 WR0X,1X (DACK0) (EOP0) [Explanation of operation] •...
Page 196: External Wait Cycles
CHAPTER 4 BUS INTERFACE 4.17.7 External Wait Cycles This section provides an external wait cycle timing chart. External Wait Cycle Timing Chart Bus width: 16 bits, access: half-words Figure 4.17-15 Example of External Wait Cycle Timing Chart A24-00 Read D31-16 Write D31-16 WR0X,1X...
Page 197: Usual Dram Interface: Read
4.17.8 Usual DRAM Interface: Read This section provides a usual DRAM interface read timing chart. Usual DRAM Interface: Read Timing Chart Bus width: 16 bits, access: words, CS4 area access Figure 4.17-16 Example of Usual DRAM Interface Read Timing Chart 1)1CAS/2WE A24-00 #0 row.adr.
Page 198 CHAPTER 4 BUS INTERFACE edge of CASL or CASH for the 2CAS/1WE. For the 1CAS/2WE, CAS corresponds to D31 to D16. corresponds to D31 to D24, and CASH corresponds to D23 to D16. In read cycles, all of D31 to D16 are fetched, irrespective of the bus width and word, half- word, and byte access.
Page 199: Usual Dram Interface: Write
4.17.9 Usual DRAM Interface: Write This section provides a usual DRAM interface write timing chart. Usual DRAM Interface: Write Timing Chart Bus width: 16 bits, access: words, CS4 area access Figure 4.17-17 Example of Usual DRAM Interface Write Timing Chart 1)1CAS/2WE A24-00 #0 row.adr.
Page 200 CHAPTER 4 BUS INTERFACE In an 8-bit data bus width, write data is output from D31 to D24. • RAS is similar to that at read cycles. • CAS is also similar to that at read cycles. • WE is a write strobe signal to the DRAM. For the 1CAS/2WE, WEL represents WE of the upper address side ("0"...
Page 201: Usual Dram Read Cycles
4.17.10 Usual DRAM Read Cycles This section provides usual DRAM read cycle timing charts. Usual DRAM Read Cycle Timing Charts Bus width: 16 bits, access: half-words Figure 4.17-18 Example 1 of Usual DRAM Read Cycle Timing Chart 1CAS/2WE 2CAS/1WE A24-00 #0 row.adr.
Page 202: Figure 4.17-19 Example 2 Of Usual Dram Read Cycle Timing Chart
CHAPTER 4 BUS INTERFACE Bus width: 16 bits, access: bytes Figure 4.17-19 Example 2 of Usual DRAM Read Cycle Timing Chart 1)1CAS/2WE A24-00 #0 row.adr. D31-24 D23-16 2)2CAS/1WE A24-00 #0 row.adr. D31-24 D23-16 CASL CASH Bus width: 8 bits, access: half-words Figure 4.17-20 Example 3 of Usual DRAM Read Cycle Timing Chart A24-00 #0 row.adr.
Page 203: Usual Dram Write Cycles
4.17.11 Usual DRAM Write Cycles This section provides usual DRAM write cycle timing charts. Usual DRAM Write Cycle Timing Charts Bus width: 16 bits, access: half-words Figure 4.17-21 Example 1 of Usual DRAM Write Cycle Timing Chart 1CAS/2WE A24-00 D31-24 D23-16 2CAS/1WE A24-00...
Page 204: Figure 4.17-22 Example 2 Of Usual Dram Write Cycle Timing Chart
CHAPTER 4 BUS INTERFACE Bus width: 16 bits, access: bytes Figure 4.17-22 Example 2 of Usual DRAM Write Cycle Timing Chart 1)1CAS/2WE A24-00 #0 row.adr. D31-24 D23-16 Upper address side 2)2CAS/1WE A24-00 #0 row.adr. D31-24 D23-16 CASL CASH Bus width: 8 bits, access: half-words Figure 4.17-23 Example 3 of Usual DRAM Write Cycle Timing Chart A24-00 #0 row.adr.
Page 205: Automatic Wait Cycles In Usual Dram Interface
4.17.12 Automatic Wait Cycles in Usual DRAM Interface This section provides an automatic wait cycle timing chart in the usual DRAM interface. Automatic Wait Cycle Timing Chart in Usual DRAM Interface Bus width: 8 bits, access: bytes Figure 4.17-24 Example of Automatic Wait Cycle Timing Chart in Usual DRAM Interface 1)Read A24-00 D31-24...
Page 206: Dram Interface In High-Speed
CHAPTER 4 BUS INTERFACE 4.17.13 DRAM Interface in High-Speed Page Mode This section provides DRAM interface operation timing charts in high-speed page mode. DRAM Interface Timing Charts in High-Speed Page Mode Read cycle, bus width: 16 bits, access: words Figure 4.17-25 Example 1 of DRAM Interface Timing Chart in High-Speed Page Mode 1CAS/2WE A24-00 #0 row.adr.
Page 207: Figure 4.17-27 Example 3 Of Dram Interface Timing Chart In High-Speed Page Mode
[Explanation of operation] • Write control is performed with only the CAS control signals (including CASL and CASH) while RAS is lowered to "L", and then WE (including WEL and WEH) is lowered to "L". • Column addresses and output data are output in Q4 and Q5 cycles. CS area (CS4/CS5) switch-over in high-speed page mode, read and write combination, 2CAS/1WE Figure 4.17-27 Example 3 of DRAM Interface Timing Chart in High-Speed Page Mode...
Page 208: Figure 4.17-28 Example 4 Of Dram Interface Timing Chart In High-Speed Page Mode
CHAPTER 4 BUS INTERFACE Combination of high-speed page mode and basic bus cycle Figure 4.17-28 Example 4 of DRAM Interface Timing Chart in High-Speed Page Mode A24-00 CS4X col.adr CS2X basic bus CS2X basic bus Read D31-24 Read D23-16 CS2X CS4X WR0X CS4:RAS...
Page 209: Single Dram Interface: Read
4.17.14 Single DRAM Interface: Read This section provides a read timing chart for a single DRAM interface. Single DRAM Interface: Read Timing Chart Bus width: 16 bits, access: words Figure 4.17-29 Example of Single DRAM Interface Read Timing Chart 1)1CAS/2WE A24-00 row.adr.
Page 210: Single Dram Interface: Write
CHAPTER 4 BUS INTERFACE 4.17.15 Single DRAM Interface: Write This section provides a single DRAM interface write timing chart. Single DRAM Interface: Write Timing Chart Bus width: 16 bits, access: words Figure 4.17-30 Example of Single DRAM Interface Write Timing Chart 2)2CAS/1WE A24-00 row.adr.
Page 211: Single Dram Interface
4.17.16 Single DRAM Interface This section provides a single DRAM interface timing chart. Single DRAM Interface Timing Chart Combination of single DRAM and basic bus cycle, CS switch-over Figure 4.17-31 Example of Single DRAM Interface Timing Chart Q4SR Idle A24-00 col.
Page 212: Hyper Dram Interface: Read
CHAPTER 4 BUS INTERFACE 4.17.17 Hyper DRAM Interface: Read This section provides a hyper DRAM interface timing chart. Hyper DRAM Interface: Read Timing Chart Bus width: 16 bits, access: words Figure 4.17-32 Example of Hyper DRAM Interface Read Timing Chart 1CAS/2WE A24-00 row.adr.
Page 213: Hyper Dram Interface: Write
4.17.18 Hyper DRAM Interface: Write This section provides a hyper DRAM interface write timing chart. Hyper DRAM Interface: Write Timing chart Bus width: 16 bits, access: words Figure 4.17-33 Example of Hyper DRAM Interface Write Timing Chart 2CAS/1WE A24-00 row.adr. D31-24 D23-16 CASL...
Page 214: Hyper Dram Interface
CHAPTER 4 BUS INTERFACE 4.17.19 Hyper DRAM Interface This section provides a hyper DRAM interface timing chart. Hyper DRAM Interface Timing Chart Combination of hyper DRAM and basic bus cycle, CS switch-over Figure 4.17-34 Example of Hyper DRAM Interface Timing Chart A24-00 CS2X basic bus D31-24...
Page 215: Dram Refresh
4.17.20 DRAM Refresh This section provides DRAM refresh timing charts. CAS before RAS (CBR) Refresh Figure 4.17-35 Example of CAS before RAS (CBR) Refresh Timing Chart A24-00 col.adr. D31-16 [Explanation of operation] • When executing CBR refresh, set the REFE bit of DMCR4 and DMCR5 and the STR bit of the RFCR.
Page 216: Figure 4.17-36 Example Of Timing Chart Of Cbr Refresh Automatic Wait Cycle
CHAPTER 4 BUS INTERFACE Automatic Wait Cycle of CBR Refresh Figure 4.17-36 Example of Timing Chart of CBR Refresh Automatic Wait Cycle [Explanation of operation] • When inserting a CBR refresh automatic wait cycle, set the R3W bit of the RFCR. Selfrefresh Figure 4.17-37 Example of Selfrefresh Timing Chart SLFR bit...
Page 217: External Bus Request
4.17.21 External Bus Request This section provides external bus request timing charts. Bus Control Release Figure 4.17-38 Example of Bus Control Release Timing Chart A24-00 D31-16 BGRNTX [Explanation of operation] • When performing bus arbitration by BRQ and BGRNTX, set the BRE bit of EPCR0 to "1". •...
Page 218: Internal Clock Multiplication (Clock Doubler)
CHAPTER 4 BUS INTERFACE 4.18 Internal Clock Multiplication (Clock Doubler) The MB91F109 has a clock multiplication circuit with which the inside of the CPU operates at a frequency one or two times that of the bus interface. The bus interface operates synchronously with the CLK output pin regardless of which clock is chosen.
Page 219: Figure 4.18-2 Example Of Timing For 1X Clock (Bw-16Bit, Access-Word Read)
4.18 Internal Clock Multiplication (Clock Doubler) Figure 4.18-2 Example of Timing for 1X Clock (BW-16bit, Access-Word Read) Internal clock Internal instruction N + 2 address Internal instruction D + 2 data CLK output External address bus N + 4 D + 2 External data bus D + 2 External RDX...
Page 220: Program Example For External Bus Operation
CHAPTER 4 BUS INTERFACE 4.19 Program Example for External Bus Operation This section provides a simple program example for external bus operation. Program Specification Examples for External Bus Operation Register settings are as follows: Areas • Area 0 (AMD0): 16 bits, usual bus, automatic wait 0 •...
Page 221 r0,@r1 init_amd0 ldi:8 #0x08,r0 ldi:20 #0x620,r1 r0,@r1 init_amd1 ldi:8 #0x0a,r0 ldi:20 #0x621,r1 r0,@r1 init_amd32 ldi:8 #0x49,r0 ldi:20 #0x622,r1 r0,@r1 init_amd4 ldi:8 #0x88,r0 ldi:20 #0x623,r1 r0,@r1 init_amd5 ldi:8 #0x88,r0 ldi:20 #0x624,r1 r0,@r1 init_dmcr4 ldi:20 #0x0c90,r0 ldi:20 #0x62c,r1 r0,@r1 init_dmcr5 ldi:20 #0x10c0,r0 ldi:20 #0x62e,r1 r0,@r1...
Page 222 CHAPTER 4 BUS INTERFACE init_asr init_ler init_modr //External bus access adr_set ldi:20 #0x626,r1 r0,@r1 ldi:32 #0x0013001,r0 ldi:32 #0x0015001,r1 ldi:32 #0x0017001,r2 ldi:32 #0x0019001,r3 ldi:32 #0x001b001,r4 ldi:20 #0x60c,r5 ldi:20 #0x610,r6 ldi:20 #0x614,r7 ldi:20 #0x618,r8 ldi:20 #0x61C,r9 r0,@r5 r1,@r6 r2,@r7 r3,@r8 r4,@r9 ldi:8 #0x02,r0 ldi:20 #0x7fe,r1...
Page 223 ldi:32 #0x001a6b8c, r6 ldi:32 #0x001a6c00, r7 bus_acc @r0, r8 lduh @r1, r9 @r2, r10 ldub @r3, r11 r8, @r4 r9, @r5 r10, @r6 r11, @r7 4.19 Program Example for External Bus Operation CS5 address (within the page) CS5 address (outside of the page) CS1 data word load CS2 data half word load CS4 data word load...
Page 224 CHAPTER 4 BUS INTERFACE...
Page 225: Chapter 5 I/O Ports
CHAPTER 5 I/O PORTS This chapter outlines the I/O ports and explains the register configuration and the requirements for using external pins as I/O pins. 5.1 Outline of I/O Ports 5.2 Port Data Register (PDR) 5.3 Data Direction Register (DDR) 5.4 Using External Pins as I/O Ports...
Page 226: Outline Of I/O Ports
CHAPTER 5 I/O PORTS Outline of I/O Ports When a resource is not allowed to use the corresponding pin as an I/O, the MB91F109 allows the pin to be used as an I/O port. Basic Block Diagram of I/O Ports Figure 5.1-1 shows the basic I/O port configuration.
Page 227: Port Data Register (Pdr)
Port Data Register (PDR) The port data registers (PDR2 to PDRF) are I/O port I/O data registers. The corresponding data direction registers (DDR2 to DDRF) perform I/O control. Configuration of Port Data Register (PDR) The port data register (PDR) is configured as follows: PDR2 Address: 000001 PDR3...
Page 228: Data Direction Register (Ddr)
CHAPTER 5 I/O PORTS Data Direction Register (DDR) The data direction registers (DDR2 to DDRF) control the I/O direction of the corresponding I/O ports in bit units. Set 0 to perform input control, and set 1 to perform output control. Configuration of Data Direction Register (DDR) The data direction register (DDR) is configured as follows: DDR2...
Page 229: Using External Pins As I/O Ports
Using External Pins as I/O Ports Table 5.4-1 lists the relationship between the initial value for each external pin and the register specifying whether to use the external pin as an I/O port or control pin. "Single chip: --- " and "External bus: --- " indicated in the table mean that the pin function differs for the operation mode to be used.
Page 230: Table 5.4-2 External Bus Functions To Be Selected (2/4)
CHAPTER 5 I/O PORTS Table 5.4-1 External Bus Functions to be Selected (1/4) Pin No. Pin code BGRNTX Table 5.4-2 External Bus Functions to be Selected (2/4) Pin No. Pin code 26 to 27 P84 to P85 WR0X, WR1X 14 to 12 PA 0 to PA2 CS0X to CS2X CS3X...
Page 231: Table 5.4-3 External Bus Functions To Be Selected (3/4)
Table 5.4-2 External Bus Functions to be Selected (2/4) Pin No. Pin code CS1L DREQ2 CS1H DACK2 DW1X 19 to 21 MD0 to MD2 NMIX 75 to 78 AN0 to AN3 98 to 97 PE0 to PE1 INT0 to INT1 Table 5.4-3 External Bus Functions to be Selected (3/4) Pin No.
Page 232 CHAPTER 5 I/O PORTS Table 5.4-3 External Bus Functions to be Selected (3/4) Pin No. Pin code OPCA3 TRG2 TRG3 OPCA1 OPCA2 OPCA0 AVCC AVRH Initial value Switch-over register PF2/SC0 PCNL (POEN) (input) 0: PF2 1: OPCA3 SMR (SCKE) 0: pin values are input to SC0 during operation.
Page 233: Table 5.4-4 External Bus Functions To Be Selected (4/4)
Table 5.4-4 External Bus Functions to be Selected (4/4) Pin No. Pin code AVSS (AVRL) RSTX 7, 16, 96, 46 18, 43, 68, 93 5.4 Using External Pins as I/O Ports Initial value Switch-over register AVSS (AVRL) RSTX...
Page 234 CHAPTER 5 I/O PORTS...
Page 235: Chapter 6 External Interrupt/Nmi Controller
CHAPTER 6 EXTERNAL INTERRUPT/NMI CONTROLLER This chapter explains the general outlines of the external interrupt/NMI controller, configuration/functions of registers, and operations of the external interrupt/NMI controller. 6.1 Overview of External Interrupt/NMI Controller 6.2 Enable Interrupt Request Register (ENIR) 6.3 External Interrupt Request Register (EIRR) 6.4 External Level Register (ELVR) 6.5 External Interrupt Operation 6.6 External Interrupt Request Levels...
Page 236: Overview Of External Interrupt/Nmi Controller
CHAPTER 6 EXTERNAL INTERRUPT/NMI CONTROLLER Overview of External Interrupt/NMI Controller The external interrupt/NMI controller is a block that controls an external interrupt request input to NMIX or INT0 to INT3. The levels of interrupt requests to be detected can be selected from "H", "L", and the "rising"...
Page 237: Enable Interrupt Request Register (Enir)
Enable Interrupt Request Register (ENIR) The enable interrupt request register (ENIR) is used to mask the output of an external interrupt request. Enable Interrupt Request Register (ENIR) The configuration of the enable interrupt request register (ENIR) is shown below: ENIR Address:000095 The enable interrupt request register (ENIR) is used to mask the output of an external interrupt request.
Page 238: External Interrupt Request Register (Eirr)
CHAPTER 6 EXTERNAL INTERRUPT/NMI CONTROLLER External Interrupt Request Register (EIRR) When the external interrupt request register (EIRR) is read, it indicates that there are external interrupt requests. When it is written, the flip-flops indicating these requests are cleared. External Interrupt Request Register (EIRR) The configuration of the external interrupt request register (EIRR) is shown below: EIRR Address:000094...
Page 239: External Level Register (Elvr)
External Level Register (ELVR) The external level register (ELVR) selects the request detection mode. External Level Register (ELVR) The configuration of the external level register (ELVR) is shown below: ELVR Address:000099 The external level register (ELVR) selects the request detection mode. Two bits each are assigned to INT0 to INT3 and defined as shown in Table 6.4-1.
Page 240: External Interrupt Operation
CHAPTER 6 EXTERNAL INTERRUPT/NMI CONTROLLER External Interrupt Operation After the external level register and enable interrupt request register are set, the request set in the ELVR register is input to the corresponding pin. This module then issues an interrupt request signal to the interrupt controller. External Interrupt Operation If multiple interrupt requests are issued to the interrupt controller, their priorities are checked.
Page 241: External Interrupt Request Levels
External Interrupt Request Levels When an edge is selected for the interrupt request mode, a pulse width of at least three machine cycles (peripheral clock machine cycles) is required to detect an edge. When a level is selected for the interrupt request mode, an external request that has been input may be canceled later, though the request issued to the interrupt controller remains active because an interrupt cause hold circuit exists inside.
Page 242: Nonmaskable Interrupt (Nmi) Operation
CHAPTER 6 EXTERNAL INTERRUPT/NMI CONTROLLER Nonmaskable Interrupt (NMI) Operation NMI is the interrupt with the highest priority among other user interrupts. It can only be masked during the period from immediately after a reset to the completion of the ILM setting. NMI Operation NMI is accepted as follows: •...
Page 243: Chapter 7 Delayed Interrupt Module
CHAPTER 7 DELAYED INTERRUPT MODULE This chapter provides an overview of the delayed interrupt module and explains the register configuration and functions and the operations of the delayed interrupt module. 7.1 Overview of Delayed Interrupt Module 7.2 Delayed Interrupt Control Register (DICR) 7.3 Operation of Delayed Interrupt Module...
Page 244: Overview Of Delayed Interrupt Module
CHAPTER 7 DELAYED INTERRUPT MODULE Overview of Delayed Interrupt Module The delayed interrupt module causes an interrupt for changing a task. Software can use this module to issue or cancel an interrupt request to the CPU. Delayed Interrupt Module Register Figure 7.1-1 shows the delayed interrupt module register.
Page 245: Delayed Interrupt Control Register (Dicr)
Delayed Interrupt Control Register (DICR) The delayed interrupt control register (DICR) is used to control delayed interrupts. Configuration of the Delayed Interrupt Control Register (DICR) The configuration of the delayed interrupt control register (DICR) is shown below: bit7 Bit Function of the Delayed Interrupt Control Register (DICR) [bit 0] DLYI Clear the cause of a delayed interrupt respectively do not issue a delayed interrupt request.
Page 246: Operation Of Delayed Interrupt Module
CHAPTER 7 DELAYED INTERRUPT MODULE Operation of Delayed Interrupt Module The delayed interrupt module causes an interrupt for changing a task. Software can use this module to issue or cancel an interrupt request to the CPU. Interrupt Number A delayed interrupt is assigned to the interrupt having the largest interrupt number. This model assigns the delayed interrupt to interrupt number 63 (3F DICR DLYI Bit Writing "1"...
Page 247: Chapter 8 Interrupt Controller
CHAPTER 8 INTERRUPT CONTROLLER This chapter provides an overview of the interrupt controller and explains the register configuration and functions and the operations of the interrupt controller. The chapter also explains the hold request cancel request function using examples. 8.1 Overview of Interrupt Controller 8.2 Interrupt Controller Block Diagram 8.3 Interrupt Control Register (ICR) 8.4 Hold Request Cancel Request Level Setting Register (HRCL)
Page 248: Overview Of Interrupt Controller
CHAPTER 8 INTERRUPT CONTROLLER Overview of Interrupt Controller The interrupt controller accepts interrupts and performs arbitration over them. Interrupt Controller Hardware Configuration The interrupt controller consists of the following: • ICR register • Interrupt priority check circuit • Interrupt level and number (vector) generator •...
Page 249: Figure 8.1-1 Interrupt Controller Registers (1/2)
Interrupt Controller Registers Figure 8.1-1 shows the interrupt controller registers. Figure 8.1-1 Interrupt Controller Registers (1/2) Address:00000400 Address:00000401 Address:00000402 Address:00000403 Address:00000404 Address:00000405 Address:00000406 Address:00000407 Address:00000408 Address:00000409 Address:0000040A Address:0000040B Address:0000040C Address:0000040D Address:0000040E Address:0000040F Address:00000410 Address:00000411 Address:00000412 Address:00000413 Address:00000414 Address:00000415 Address:00000416 Address:00000417 Address:00000418 Address:00000419 Address:0000041A...
Page 250: Figure 8.1-2 Interrupt Controller Registers (2/2)
CHAPTER 8 INTERRUPT CONTROLLER Figure 8.1-2 Interrupt Controller Registers (2/2) Address:00000420 Address:00000421 Address:00000422 Address:00000423 Address:00000424 Address:00000425 Address:00000426 Address:00000427 Address:00000428 Address:00000429 Address:0000042A Address:0000042B Address:0000042C Address:0000042D Address:0000042E Address:0000042F Address:00000431 bit7 ICR4 ICR3 LVL4 LVL3 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42...
Page 251: Interrupt Controller Block Diagram
Interrupt Controller Block Diagram Figure 8.2-1 is an interrupt controller block diagram. Interrupt Controller Block Diagram Figure 8.2-1 Block Diagram of the Interrupt Controller INTO RI00 RI47 (DLYIRQ) DLYI *1: DLYI is the delayed interrupt module (See Chapter 7, "Delayed Interrupt Module," for more information.) *2: INT0 is a wakeup signal for the clock controller in sleep or stop state.
Page 252: Interrupt Control Register (Icr)
CHAPTER 8 INTERRUPT CONTROLLER Interrupt Control Register (ICR) One interrupt control register is provided for each type of interrupt input and is used to set the interrupt level of the corresponding interrupt request. Configuration of Interrupt Control Register (ICR) The configuration of the interrupt control register (ICR) is shown below: bit7 Bit Functions of Interrupt Control Register (ICR) [bit 4 to 0] ICR 4 to 0...
Page 253: Table 8.3-1 Correspondences Between The Interrupt Level Setting Bits And Interrupt Levels
Table 8.3-1 Correspondences between the Interrupt Level Setting Bits and Interrupt Levels ICR4 ICR3 ICR2 ICR1 ICR4 is fixed to "1" and cannot be set to "0". 8.3 Interrupt Control Register (ICR) ICR0 Interrupt level Highest level that can be set System reserved (High) (Low)
Page 254: Hold Request Cancel Request Level Setting Register (Hrcl)
CHAPTER 8 INTERRUPT CONTROLLER Hold Request Cancel Request Level Setting Register (HRCL) The HRCL register is used to set the interrupt level for issuing a hold request cancel request. Configuration of Hold Request Cancel Request Level Setting Register (HRCL) The register configuration of the hold request cancel request/level setting register (HRCL) is as follows: bit7 Address...
Page 255: Priority Check
Priority Check IWhen multiple interrupt causes are generated simultaneously, this module selects one having the highest priority and posts the interrupt level and number of the cause to the CPU. NMI is given the highest priority among the interrupt causes handled by this module. Priority Check The criteria for checking the priority of interrupt causes are as follows: 1.
Page 256: Table 8.5-2 Relationships Among Interrupt Causes, Numbers, And Levels (2/2)
CHAPTER 8 INTERRUPT CONTROLLER Table 8.5-1 Relationships among Interrupt Causes, Numbers, and Levels (1/2) Cause of interrupt DMAC 2 (end, error) DMAC 3 (end, error) DMAC 4 (end, error) DMAC 5 (end, error) DMAC 6 (end, error) DMAC 7 (end, error) Reload timer 0 Reload timer 1 Reload timer 2...
Page 257 Table 8.5-2 Relationships among Interrupt Causes, Numbers, and Levels (2/2) Cause of interrupt Reserved by the system Reserved by the system Reserved by the system Reserved by the system Reserved by the system Reserved by the system Reserved by the system Reserved by the system Reserved by the system Delayed interrupt cause bit...
Page 258: Returning From The Standby Mode (Stop/Sleep)
CHAPTER 8 INTERRUPT CONTROLLER Returning from the Standby Mode (Stop/Sleep) This module implements the function to return from standby mode when an interrupt request is issued. Returning from Standby Mode (Stop or Sleep State) When a peripheral interrupt request including NMI occurs, a request to return from standby mode is issued to the clock controller.
Page 259: Hold Request Cancel Request
Hold Request Cancel Request For processing a high-priority interrupt while the CPU is in hold state, cancellation of the hold request must be requested from the source for the hold request. The interrupt level used to determine whether to issue a cancel request must be set in the HRCL register.
Page 260: Example Of Using The Hold Request Cancel Request Function (Hrcr)
CHAPTER 8 INTERRUPT CONTROLLER Example of Using the Hold Request Cancel Request Function (HRCR) When the CPU is to perform priority processing during DMA transfer, the DMA side must cancel the hold request and release the CPU from the hold state. An example of an interrupt occurring for DMA to cancel the hold request and allow CPU priority operation is as follows.
Page 261: Figure 8.8-2 Example Of Timing For Hold Request Cancel Request Sequence (Interrupt Level: Hrcl > A)
Hold Request Cancel Request Sequence Example of interrupt routine Figure 8.8-2 Example of Timing for Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a) RU N Bus hold CP U DH R Q HR Q HA C K I R Q L E VE L HR C R P D R R...
Page 262 CHAPTER 8 INTERRUPT CONTROLLER Example of interrupt routines The above example indicates that a priority interrupt is caused during execution of interrupt routine I. In this case, incrementing PDRR at the beginning of each interrupt routine and decrementing it at the exit of each routine can also prevent a hold request from being issued accidentally.
Page 263: Chapter 9 U-Timer
CHAPTER 9 U-TIMER This chapter provides an overview of the U-TIMER and explains the register configuration and functions and the operations of the U-TIMER. 9.1 Overview of U-TIMER 9.2 U-TIMER Registers 9.3 U-TIMER Operation...
Page 264: Overview Of U-Timer
CHAPTER 9 U-TIMER Overview of U-TIMER The U-TIMER is a 16-bit timer that generates a UART baud rate. Combining the chip operating frequency and U-TIMER reload value can generate a desired baud rate. Since a count underflow causes an interrupt, the U-TIMER can also be used as an interval timer.
Page 265: U-Timer Registers
U-TIMER Registers The following three U-TIMER registers are used: • U-TIMER (UTIM) • Reload register (UTIMR) • U-TIMER control register (UTIMC) U-TIMER (UTIM) The UTIM indicates the timer value. Access it using a 16-bit transfer instruction. UTIM ch0 Address:0000 0078 ch1 Address:0000 007C ch2 Address:0000...
Page 266 CHAPTER 9 U-TIMER In addition to a normal 2(n+1) cycle clock, an odd frequency clock can be set for the UART. Setting 1 in UCC1 generates 2n+3 cycle clock pulses. [Example of setting] UTIMR = 5, UCC1 = 0 --> Generation cycle = 2n+2 = 12 cycles UTIMR = 25, UCC1 = 1 -->...
Page 267: U-Timer Operation
U-TIMER Operation This section explains how to calculate the U-TIMER baud rate and also explains the cascade mode. Calculating the Baud Rate The UART uses the underflow flip-flop (f.f. in the figure) of the corresponding U-TIMER (U- TIMERx --> UARTx, x = 0, 1, 2) as the baud rate clock source. Asynchronous (start-stop) mode The UART uses the U-TIMER output by dividing it by 16.
Page 268 CHAPTER 9 U-TIMER...
Page 269: Chapter 10 Uart
CHAPTER 10 UART This chapter provides an overview of the UART and explains the register configuration, functions and the operations of the UART. 10.1 Overview of UART 10.2 Serial Mode Register (SMR) 10.3 Serial Control Register (SCR) 10.4 Serial Input Data Register (SIDR) and Serial Output Data Register (SODR) 10.5 Serial Status Register (SSR) 10.6 UART Operation...
Page 270: Overview Of Uart
CHAPTER 10 UART 10.1 Overview of UART The UART is a serial I/O port used to implement asynchronous (start-stop) communication or CLK synchronous communication. The MB91F109 contains three UART channels. UART Characteristics • Full duplex double buffer • Support of both asynchronous (start-stop) and CLK synchronous communication •...
Page 271: Figure 10.1-2 Uart Block Diagram
UART Block Diagram Figure 10.1-2 is a UART block diagram. Control signal Clock From U-TIMER selection circuit External clock (received data) Reception status check circuit Reception error generation signal for DMA (to DMAC) register SCKE Figure 10.1-2 UART Block Diagram Transmission clock Reception clock Reception...
Page 272: Serial Mode Register (Smr)
CHAPTER 10 UART 10.2 Serial Mode Register (SMR) The serial mode register (SMR) specifies the UART operation mode. Set the operation mode while UART operation is stopped. Do not write to the register during UART operation. Configuration of Serial Mode Register (SMR) The configuration of the serial mode register (SMR) is shown below: 00001F Address: 000023...
Page 273 [bit 1] SCKE (SCLK Enable) When communication is performed in CLK synchronous mode (mode 2), this bit specifies whether to use the SC pin as a clock input pin or a clock output pin. Set this bit to "0" in CLK asynchronous mode or external clock mode. 0: Clock input pin (initial value) 1: Clock output pin <Note>...
Page 274: Serial Control Register (Scr)
CHAPTER 10 UART 10.3 Serial Control Register (SCR) The serial control register (SCR) controls the transfer protocol used for serial communication. Configuration of Serial Control Register (SSR) The configuration of the serial control register (SCR) is shown below: 00001E Address:000022 000026 Bit Function of Serial Control Register (SSR) [bit 7] PEN (Parity Enable)
Page 275 <Note> Seven-bit data can be used only in normal mode (mode 0) for asynchronous (start-stop) communication. Use eight-bit data in multiprocessor mode (mode 1) or CLK synchronous communication mode (mode 2). [bit 3] A/D (Address/Data) This bit specifies the data format of frames that are transmitted in multiprocessor mode (mode 1) for asynchronous (start-stop) communication.
Page 276: Serial Input Data Register (Sidr) And Serial Output Data Register (Sodr)
CHAPTER 10 UART 10.4 Serial Input Data Register (SIDR) and Serial Output Data Register (SODR) The serial input data register (SIDR) is a data buffer register for receiving data, and the serial output data register (SODR) is a data buffer register for transmitting data. When 7-bit data is used, bit 7 (D7) is invalid.
Page 277: Serial Status Register (Ssr)
10.5 Serial Status Register (SSR) The serial status register (SSR) consists of flags that show the UART operating status. Configuration of Serial Status Register (SSR) The configuration of the serial status register (SSR) is shown below: SSR 00001C Address:000020 000024 Bit Function of Serial Status Register (SSR) [bit 7] PE (Parity Error) This bit is an interrupt request flag that is set when a parity error is detected for received...
Page 278 CHAPTER 10 UART [bit 4] RDRF (Receive Data Register Full) This bit is an interrupt request flag indicating that received data is stored in the SIDR register. The bit is set when received data is loaded to the SIDR register and cleared automatically when the received data is read from the SIDR register.
Page 279: Uart Operation
10.6 UART Operation UART has the following three operation modes, which can be changed by setting a value in the SMR or SCR register. • Asynchronous (start-stop) normal mode • Asynchronous (start-stop) multiprocessor mode • CLK synchronous mode UART Operation Modes Table 10.6-1 summarizes the UART operation modes.
Page 280 CHAPTER 10 UART External clock When the external clock is selected with "1" set in CS0, the baud rate is determined as follows (f is the external clock frequency): • Asynchronous (start-stop): f/16 • CLK synchronous: f f can be up to 3.125 MHz.
Page 281: Asynchronous (Start-Stop) Mode
10.7 Asynchronous (Start-Stop) Mode The UART handles data of only NRZ (nonreturn-to-zero) format. Data transfer begins with a start bit (L-level data) for the specified number of data bits in LSB first mode and ends with a stop bit (H-level data). When the external clock is selected, always input the clock signal.
Page 282: Clk Synchronous Mode
CHAPTER 10 UART 10.8 CLK Synchronous Mode The UART handles only data of NRZ (nonreturn-to-zero) format. Figure 10.8-1 shows the relationship between the transmission/reception clock and the data. Format of Data Transferred in CLK Synchronous Mode Figure 10.8-1 Format of Data Transferred in CLK Synchronous Mode (Mode 2) SODR write RXE,TXE SI,SO...
Page 283 • SCR register • PEN: 0 • P, SBL, A/D: These bits are invalid. • CL: 1 • REC: 0 (for initialization) • RXE, TXE: At least one must be set to 1. • SSR register • 1 for using interrupts or 0 for using no interrupt •...
Page 284: Uart Interrupt Occurrence And Flag Setting Timing
CHAPTER 10 UART 10.9 UART Interrupt Occurrence and Flag Setting Timing The UART has five flags and two interrupt causes. The five flags are PE, ORE, FRE, RDRF, and TDRE. One of the two interrupt causes is for data reception and the other is for data transmission.
Page 285: Figure 10.9-2 Ore, Fre, And Rdrf Set Timing (Mode 1)
Interrupt Flag Set Timing for Data Recepion in Mode 1 When the last stop bit is detected after data reception/transfer is completed, the ORE, FRE, and RDRF flags are set to issue an interrupt request to the CPU. Since the length of data items that can be received is eight bits, the data at the last bit, bit 9, indicates an address or that data is invalid.
Page 286: Figure 10.9-4 Tdre Set Timing (Mode 0 Or 1)
CHAPTER 10 UART Interrupt Flag Set Timing for Data Transmission in Mode 0, 1, or 2 TDRE is cleared when data is written to the SODR register. After the written data is transferred to the internal shift register and the SODR register is ready to accept the next item of write data, TDRE is set again to issue an interrupt request to the CPU.
Page 287: Notes On Using The Uart And Example For Using The Uart
10.10 Notes on Using the UART and Example for Using the UART This section provides an example for use of the UART and notes on using the UART. Notes on Using the UART Set the communication mode while UART operation is stopped. Data transmitted during mode setting cannot be assured.
Page 288: Figure 10.10-2 Communication Flowchart For Mode 1
CHAPTER 10 UART Figure 10.10-2 Communication Flowchart for Mode 1 (Host CPU) START Set transfer mode to 1 Set address data in D0 to D7 to select the slave CPU and set A/D to "1", then transfer one byte Set "0" in A/D Enable the receive operation Communication with slave CPU Is the communication...
Page 289: Setting Examples Of Baud Rates And U-Timer Reload Values
10.11 Setting Examples of Baud Rates and U-TIMER Reload Values Tables 10.11-1 and 10.11-2 are sample settings for baud rates and U-TIMER reload values. The frequencies in the tables indicate peripheral machine clock frequencies. UCC1 indicates the value to set in the UCC1 bit of the U-TIMER control register (UTIMC). A hyphen "-"...
Page 290 CHAPTER 10 UART...
Page 291: Chapter 11 A/D Converter (Successive Approximation Type)
CHAPTER 11 A/D CONVERTER (Successive approximation type) This chapter provides an overview of the A/D converter and explains the register configuration and functions and the operations of the A/D converter. 11.1 Overview of A/D Converter (Successive Approximation Type) 11.2 Control Status Register (ADCS) 11.3 Data Register (ADCR) 11.4 A/D Converter Operation 11.5 Conversion Data Protection Function...
Page 292: Overview Of A/D Converter (Successive Approximation Type)
CHAPTER 11 A/D CONVERTER (Successive approximation type) 11.1 Overview of A/D Converter (Successive Approximation Type) The A/D converter converts analog input voltage to digital values. Characteristics of A/D Converter • Minimum conversion time: 5.6 s/ch (for 25 MHz system clock) •...
Page 293: Figure 11.1-2 Block Diagram Of The A/D Converter
A/D Converter Block Diagram Figure 11.1-2 is an A/D converter block diagram. Figure 11.1-2 Block Diagram of the A/D Converter. Sample & hold circuit Trigger activation ATGX TIMO (internal connection) [Reload timer channel 2] (Peripheral clock) 11.1 Overview of A/D Converter (Successive Approximation Type) Comparator A/D control register Timer activation...
Page 294: Control Status Register (Adcs)
CHAPTER 11 A/D CONVERTER (Successive approximation type) 11.2 Control Status Register (ADCS) The control status register (ADCS) controls the A/D converter and displays status information. Do not rewrite the ADCS during A/D conversion. Do not use a Read Modify Write (RMW) instruction to access it.
Page 295: Table 11.2-1 Selecting The Causes For Starting The A/D Converter
<Note> Set the bit to "0" for clearing it while A/D conversion is stopped. The bit is initialized to "0" when the register is reset. A Read Modify Write instruction reads "1" from this bit. [bit 13] INTE (INTerrupt Enable) This bit specifies whether to enable issuing interrupt request at the end of conversion.
Page 296: Table 11.2-2 Selecting The A/D Converter Operation Mode
CHAPTER 11 A/D CONVERTER (Successive approximation type) <Notes> The external pin trigger signal is detected on the falling edge. If the bit setting is changed to select an external trigger mode while the external trigger input level is low, the A/D converter may start. In timer start mode, reload timer channel 2 is selected.
Page 297: Table 11.2-3 Setting The A/D Conversion Start Channel
<Note> A/D conversion that is started in continuous conversion mode or convert-and-stop mode continues until the BUSY bit stops it. Writing "0" to the BUSY bit stops A/D conversion. "No restart is enabled" in single conversion, continuous conversion, or convert-and-stop mode applies to all start causes including the timer, external trigger signal, and software.
Page 298 CHAPTER 11 A/D CONVERTER (Successive approximation type) If the same channel as that set by ANS2 to ANS0 is set, only one channel is subjected to A/ D conversion (single conversion mode). After A/D conversion is finished over the channel set by these bits in continuous conversion or convert-and-stop mode, the A/D converter returns to the start channel set by ANS2 to ANS0.
Page 299: Data Register (Adcr)
11.3 Data Register (ADCR) The data register (ADCR) is used to store a digital value that is the conversion result. Configuration of Data Register (ADCR) The configuration of the data register (ADCR) is shown below: ADCR Address:000038 The value stored in this register is updated whenever one cycle of conversion is completed. Normally, the value converted last is stored.
Page 300: A/D Converter Operation
CHAPTER 11 A/D CONVERTER (Successive approximation type) 11.4 A/D Converter Operation The A/D converter operates in successive approximation mode and features a 10-bit resolution. The A/D converter has only one register (16 bits) to store the conversion results. Therefore, the data register (ADCR) is updated whenever conversion is completed. For performing continuous conversion, DMA transfer should be used.
Page 301 In continuous conversion mode, the A/D converter continues conversion until the BUSY bit is set to "0". Writing "0" to the BUSY bit forcibly terminates A/D conversion. Note that forced termination interrupts conversion in progress. When conversion is forcibly terminated, the data register contains previously converted data. Convert-and-stop mode In convert-and-stop mode, the A/D converter sequentially converts the analog inputs specified by the ANS and ANE bits of the ADCS register and stops whenever conversion of the analog...
Page 302: Conversion Data Protection Function
CHAPTER 11 A/D CONVERTER (Successive approximation type) 11.5 Conversion Data Protection Function The A/D converter of the MB91F109 has a conversion data protection function that features continuous conversion using DMAC and securing multiple data items. Conversion Data Protection Function The A/D converter has only one conversion data register. That means that in continuous conversion mode, new conversion data overwrites the previously stored data in the register each time one cycle of A/D conversion is finished.
Page 303: Figure 11.5-1 Workflow Of The Data Protection Function When Dma Transfer Is Used
Figure 11.5-1 Workflow of the Data Protection Function when DMA Transfer is Used Set DMAC Start of continuous A/D conversion End of one cycle of conversion Store conversion data in data register End of 2nd cycle of conversion End of transfer? Store conversion data in data register End of third...
Page 304: Notes On Using The A/D Converter
CHAPTER 11 A/D CONVERTER (Successive approximation type) 11.6 Notes on Using the A/D Converter This section provides notes on using the A/D converter Notes on Using the A/D Converter Using an external trigger or internal timer to start the A/D converter The A/D start cause bits STS1 and STS0 of the ADCS register specify whether an external trigger or the internal timer is used to start the A/D converter.
Page 305: Chapter 12 16-Bit Reload Timer
CHAPTER 12 16-BIT RELOAD TIMER This chapter provides an overview of the 16-bit reload timer, and explains the register configuration and functions, and operations of the 16-bit reload timer. 12.1 Overview of 16-Bit Reload Timer 12.2 Control Status Register (TMCSR) 12.3 16-Bit Timer Register (TMR) and 16-bit Reload Register (TMRLR) 12.4 Operation of 16-Bit Reload Timer 12.5 Counter States...
Page 306: Overview Of 16-Bit Reload Timer
CHAPTER 12 16-BIT RELOAD TIMER 12.1 Overview of 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit decrementing counter, 16-bit reload register, internal count clock pulse generation prescaler, and control register. An input clock can be selected from three types of internal clock frequencies (machine clock frequency divided by 2, 8, or 32).
Page 307: Figure 12.1-2 16-Bit Reload Timer Block Diagram
16-Bit Reload Timer Block Diagram Figure 12.1-2 is a 16-bit reload timer block diagram. Figure 12.1-2 16-Bit Reload Timer Block Diagram 16-bit reload register 16-bit decrementing counter Clock selector Internal clock GATE CSL1 CSL0 Retrigger IN CTL. EXCK Prescaler clearing MOD2 MOD1 MOD0...
Page 308: Control Status Register (Tmcsr)
CHAPTER 12 16-BIT RELOAD TIMER 12.2 Control Status Register (TMCSR) The control status register is used to control the 16-bit timer operation mode and interrupts. Set the bits other than UF, CNTE, and TRG again when CNTE is 0. Simultaneous writing is enabled. Configuration of Control Status Register (TMCSR) The configuration of the control status register (TMCSR) is shown below: TMCSR...
Page 309 [bit 3] INTE This is an interrupt enable bit. When the UF bit changes to "1" while this bit is "1", an interrupt request is issued. No interrupt request is issued while this bit is "0". [bit 2] UF This is a timer interrupt request flag, which is set to "1" when the counter value underflows 0000 to FFFF .
Page 310: 16-Bit Timer Register (Tmr) And 16-Bit Reload Register (Tmrlr)
CHAPTER 12 16-BIT RELOAD TIMER 12.3 16-Bit Timer Register (TMR) and 16-Bit Reload Register (TMRLR) The 16-bit timer register (TMR) is used to read the count value of the 16-bit timer. The 16-bit reload register (TMRLR) stores the initial count value. 16-Bit Timer Register (TMR) Address :00002A...
Page 311: Operation Of 16-Bit Reload Timer
12.4 Operation of 16-Bit Reload Timer The 16-bit reload timer performs the following two types of operation: • Internal clock operation • Underflow operation Internal Clock Operation When a frequency division clock of the internal clock is used to run the timer, a machine clock frequency divided by 2, 8, or 32 can be selected as the clock source.
Page 312: Figure 12.4-2 Underflow Operation Timing
CHAPTER 12 16-BIT RELOAD TIMER Count clock Counter Data loading Underflow setting Count clock Counter Underflow set Figure 12.4-2 Underflow Operation Timing 0000 Reload data (RELD=1) 0000 FFFF (RELD=0)
Page 313: Counter States
12.5 Counter States The states of the counter are determined by the CNTE bit of the control register and the internal Wait signal as follows: CNTE = "0", Wait = "1": Stop state CNTE = "1", Wait = "1": Wait state (start trigger wait state) CNTE = "1", Wait = "0": Run state Figure 12.5-1 is a state transition diagram.
Page 314 CHAPTER 12 16-BIT RELOAD TIMER...
Page 315: Chapter 13 Bit Search Module
CHAPTER 13 BIT SEARCH MODULE This chapter provides an overview of the bit search module. It explains the register configuration, functions, operations, and the save/restore processing of the bit search module. 13.1 Overview of the Bit Search Module 13.2 Bit Search Module Registers 13.3 Bit Search Module Operation and Save/Restore Processing...
Page 316: Overview Of The Bit Search Module
CHAPTER 13 BIT SEARCH MODULE 13.1 Overview of the Bit Search Module The bit search module searches the data written to the input register for 0, 1, or a change point, and returns the detected bit position. Bit Search Module Registers Figure 13.1-1 shows the bit search module registers.
Page 317: Bit Search Module Registers
13.2 Bit Search Module Registers The bit search module uses the following four registers: • 0-detection data register (BSD0) • 1-detection data register (BSD1) • Change-point detection data register (BSDC) • Detection result register (BSRR) 0-Detection Data Register (BSD0) 000003F0 Read/write Initial value Undefined...
Page 318 CHAPTER 13 BIT SEARCH MODULE Read Data saved for the internal status of the bit search module is read from this register. When the interrupt handler uses the bit search module, the register is used to save the current status and restore it.
Page 319: Bit Search Module Operation And Save/Restore Processing
13.3 Bit Search Module Operation and Save/Restore Processing This section explains the operations of the bit search module for 0-detection, 1-detection, and change-point detection and also explains save and restore processing. 0-Detection The module scans the data written to the 0-detection data register from MSB to LSB and returns the position where the first "0"...
Page 320: Table 13.3-1 Bit Positions And Returned Values (Decimal)
CHAPTER 13 BIT SEARCH MODULE Change-Point Detection The module scans the data written to the change-point detection data register from bit 30 to LSB while comparing each bit with the MSB value and returns the position where the value different from the MSB was first detected.
Page 321 13.3 Bit Search Module Operation and Save/Restore Processing Save/Restore Processing When the internal status of the bit search module must be saved and restored, such as when the module is used in the interrupt handler, proceed as follows: 1. Read the 1-detection data register and store the read data. (Save) 2.
Page 322 CHAPTER 13 BIT SEARCH MODULE...
Page 323: Chapter 14 Pwm Timer
CHAPTER 14 PWM TIMER This chapter provides an overview of the PWM timer and explains the register configuration and functions and the operations of the PWM timer. 14.1 Overview of PWM Timer 14.2 PWM Timer Block Diagram 14.3 Control Status Register (PCNH, PCNL) 14.4 PWM Cycle Setting Register (PCSR) 14.5 PWM Duty Cycle Setting Register (PDUT) 14.6 PWM Timer Register (PTMR)
Page 324: Overview Of Pwm Timer
CHAPTER 14 PWM TIMER 14.1 Overview of PWM Timer The PWM timer can efficiently output accurate PWM waveforms. The MB91F109 contains four channels of PWM timer. Each channel consists of a 16-bit counter, a 16-bit data register with a cycle setting buffer, a 16-bit compare register with a duty cycle setting buffer, and a pin controller.
Page 325: Figure 14.1-1 Pwm Timer Registers
PWM Timer Registers Figure 14.1-1 shows the PWM timer registers. Address 000000DC 000000DF 000000E0 000000E2 000000E4 000000E6 PCNH 000000E8 000000EA 000000EC 000000EE PCNH 000000F0 000000F2 000000F4 000000F6 PCNH 000000F8 000000FA 000000FC PCNH 000000FE Figure 14.1-1 PWM Timer Registers GCN1 GCN2 PTMR PCSR PDUT...
Page 326: Pwm Timer Block Diagram
CHAPTER 14 PWM TIMER 14.2 PWM Timer Block Diagram Figure 14.2-1 is a general block diagram of the PWM timer. Figure 14.2-2 is a block diagram of a single PWM timer channel. General Block Diagram of PWM Timer Figure 14.2-1 General Block Diagram of PWM Timer 16-bit reload timer ch0 16-bit reload...
Page 327: Figure 14.2-2 Block Diagram Of Single Pwm Timer Channel
Block Diagram of Single PWM Timer Channel Figure 14.2-2 Block Diagram of Single PWM Timer Channel Prescaler 16-bit decrementing 1/16 counter 1/64 Start Peripheral clock Enable Edge TRG input detection Software trigger PCSR PDUT Load Borrow 14.2 PWM Timer Block Diagram PPG mask PWM output Inverse bit...
Page 328: Control Status Register (Pcnh, Pcnl)
CHAPTER 14 PWM TIMER 14.3 Control Status Register (PCNH, PCNL) The control status register (PCNH, PCNL) is used to control the PWM timer or indicate the timer status. Note that the register has a bit that cannot be rewritten during PWM timer operation.
Page 329: Table 14.3-1 Selection Of The Count Clock
[bit 12] RTRG: Restart enable bit This bit enables or disables restart by a software trigger or trigger input. Disable restart (Initial value) Enable restart [bits 11, 10] CKS1, CKS0: Counter clock select bit These bits select the counter clock for the 16-bit decrementing counter. Table 14.3-1 Selection of the Count Clock CKS1 CKS0...
Page 330: Table 14.3-4 Selection Of Interrupt Causes
CHAPTER 14 PWM TIMER [bit 5] IREN: Interrupt request enable bit This bit enables or disables interrupt requests. [bit 4] IRQF: Interrupt request flag When the interrupt cause selected by bits 3 and 2 (IRS1 and IRS0) is generated while bit 5 (IREN) is set to 1 (Enable), this bit is set to cause an interrupt request to the CPU.
Page 331 14.3 Control Status Register (PCNH, PCNL) Polarity After Duty cycle matching Counter borrow resetting Normal Output of L polarity Inverse Output of H polarity...
Page 332: Pwm Cycle Setting Register (Pcsr)
CHAPTER 14 PWM TIMER 14.4 PWM Cycle Setting Register (PCSR) The PWM cycle setting register (PCSR) is used to set a cycle. This register has a buffer. A borrow occurring in the counter triggers a transfer from the buffer. PWM Cycle Setting Register (PCSR) The configuration of the PWM cycle setting register (PCSR) is shown below.
Page 333: Pwm Duty Cycle Setting Register (Pdut)
14.5 PWM Duty Cycle Setting Register (PDUT) The PWM duty cycle setting register (PDUT) is used to set a duty cycle. This register has a buffer. A borrow occurring in the counter triggers a transfer from the buffer. PWM Duty Cycle Setting Register (PDUT) The configuration of the PWM duty cycle setting register (PDUT) is shown below.
Page 334: Pwm Timer Register (Ptmr)
CHAPTER 14 PWM TIMER 14.6 PWM Timer Register (PTMR) The PWM timer register (PTMR) is used to read the value of the 16-bit decrementing counter. PWM Timer Register (PTMR) The configuration of the PWM timer register (PTMR) is shown below. PTMR Address: ch0 0000E0 ch1 0000E8...
Page 335: General Control Register 1 (Gcn1)
14.7 General Control Register 1 (GCN1) The general control register 1 (GCN1) is used to select the source of PWM timer trigger input. Configuration of General Control Register 1 (GCN1) The configuration of the general control register 1 (GCN1) is shown below. GCN1 Address: 0000DC TSEL33:30...
Page 336: Table 14.7-1 Selection Of Ch3 Trigger Input
CHAPTER 14 PWM TIMER Bit Functions of General Control Register 1 (GCN1) [bits 15-12] TSEL 33-30: ch3 trigger input select bits Table 14.7-1 Selection of Ch3 Trigger Input TSEL33-30 [bits 11-8] TSEL 23-20: ch2 trigger input select bits Table 14.7-2 Selection of Ch2 Trigger Input TSEL23-20 ch3 trigger input GCN2 EN0 bit...
Page 337: Table 14.7-3 Selection Of Ch1 Trigger Input
[bits 7-4] TSEL 13-10: ch1 trigger input select bits Table 14.7-3 Selection of Ch1 Trigger Input TSEL13-10 [bits 3-0] TSEL 03-00: ch0 trigger input select bits Table 14.7-4 Selection of Ch0 Trigger Input TSEL03-00 14.7 General Control Register 1 (GCN1) ch1 trigger input GCN2 EN0 bit GCN2 EN1 bit (Initial value)
Page 338: General Control Register 2 (Gcn2)
CHAPTER 14 PWM TIMER 14.8 General Control Register 2 (GCN2) The general control register 2 (GCN2) is used for generating a start trigger by software. General Control Register 2 (GCN2) The configuration of the general control register 2 (GCN2) is shown below. GCN2 Address: 0000DF When an EN bit of this register is selected by the general control register 1 (GCN1), the value of...
Page 339: Pwm Operation
14.9 PWM Operation PWM operation outputs pulses continuously. PWM Operation. Upon detection of a start trigger, the PWM timer outputs pulses continuously. The cycle of output pulses can be controlled by changing the PCSR value, and the duty ratio can be controlled by changing the PDUT value. After writing data to the PCSR, write to the PDUT.
Page 340: Figure 14.9-1 Pwm Operation Timing Chart (Trigger Restart Disabled)
CHAPTER 14 PWM TIMER Trigger restart disabled Figure 14.9-1 PWM Operation Timing Chart (Trigger Restart Disabled) Start trigger Trigger restart disabled Figure 14.9-2 PWM Operation Timing Chart (Trigger Restart Enabled) Start trigger A rising edge is detected. = T (n + 1) = T (m + 1) A rising edge is detected.
Page 341: One-Shot Operation
14.10 One-Shot Operation One-shot operation outputs a single pulse. One-Shot Operation Upon detection of a trigger in one-shot operation mode, the PWM timer can output a single pulse of arbitrary width. When an edge is detected during operation while restart is enabled, the counter is reloaded. Figure 14.10-1 shows a timing chart for one-short operation performed while trigger restart is disabled.
Page 342: Figure 14.10-1 One-Shot Operation Timing Chart (Trigger Restart Disabled)
CHAPTER 14 PWM TIMER Trigger restart disabled Figure 14.10-1 One-Shot Operation Timing Chart (Trigger Restart Disabled) Start trigger Trigger restart enabled Figure 14.10-2 One-Shot Operation Timing Chart (Trigger Restart Enabled) Start trigger A rising edge is detected. = T (n + 1) = T (m + 1) A rising edge is detected.
Page 343: Interrupt
14.11 Interrupt Figure 14.11-1 shows the causes of interrupts and their timing. Interrupt Figure 14.11-1 Causes of Interrupts and Their Timing (PWM Output: Normal Polarity) Start trigger Up to 2.5T Load Clock Count value Interrupt Effective edge Effective edge *: A maximum of 2.5T (T = count clock cycle) is required until the count value is loaded after detection of a start trigger. 0003 0002 0001...
Page 344: Constant "L" Or Constant "H" Output From Pwm Timer
CHAPTER 14 PWM TIMER 14.12 Constant "L" or Constant "H" Output from PWM Timer Figure 14.12-1 shows how the PWM timer can keep output at a low level. Figure 14.12- 2 shows how the PWM timer can keep output at a high level. Constant "L"...
Page 345: Starting Multiple Pwm Timer Channels
14.13 Starting Multiple PWM Timer Channels General control registers 1 and 2 (GCN1 and GCN2) can be used to start multiple PWM timer channels. Selecting a start trigger with the GCN1 register enables simultaneous start of multiple channels. This section provides an example of starting multiple channels using software (based on the GCN2 register) and another using the 16-bit reload timer.
Page 346 CHAPTER 14 PWM TIMER Starting Multiple PWM Timer Channels Using the 16-Bit Reload Timer In step 3) of the foregoing setting procedure, select the 16-bit reload timer as the start trigger in GCN1 and then start the 16-bit reload timer instead of GCN2 in step 5). The PWM timer can be restarted at regular intervals by setting toggle output for the 16-bit reload timer by setting the following in the control status register: RTRG:1 -->...
Page 347: Chapter 15 Dmac
CHAPTER 15 DMAC This chapter provides an overview of the DMAC and explains the register configuration and functions and the operations of the DMAC. 15.1 Overview of DMAC 15.2 DMAC Parameter Descriptor Pointer (DPDP) 15.3 DMAC Control Status Register (DACSR) 15.4 DMAC Pin Control Register (DATCR) 15.5 Descriptor Register in RAM 15.6 DMAC Transfer Modes...
Page 348: Overview Of Dmac
CHAPTER 15 DMAC 15.1 Overview of DMAC The DMAC is a built-in module of the MB91F109 that implements direct memory access (DMA). DMAC Characteristics • Eight channels • Three modes: Single/block transfer, burst transfer, and continuous transfer • Transfers from the total address area to the total address area •...
Page 349: Figure 15.1-2 Dmac Block Diagram
DMAC Block Diagram Figure 15.1-2 is a DMAC block diagram. Edge/level detection circuit DREQ0-2 Internal resource transfer request Data buffer BLK DEC INC/DEC Figure 15.1-2 DMAC Block Diagram Sequencer Switcher DPDP DACSR DATCR Mode DMACT SADR DADR 15.1 Overview of DMAC DACK0-2 EOP0-2 Interrupt request...
Page 350: Dmac Parameter Descriptor Pointer (Dpdp)
CHAPTER 15 DMAC 15.2 DMAC Parameter Descriptor Pointer (DPDP) The DMAC parameter descriptor pointer (DPDP) is an internal register of the DMAC and is used to store the first address of the DMAC descriptor table in RAM. DPDP bits 6 to 0 are always 0, and the first address of the descriptor that can be set is 128 bytes.
Page 351: Dmac Control Status Register (Dacsr)
15.3 DMAC Control Status Register (DACSR) The DMAC control status register (DACSR) is an internal register of the DMAC that specifies control status information on the entire DMAC. Configuration of DMAC Control Status Register (DACSR) The configuration of the DMAC control status register (DACSR) is shown below. 00000204H Initial value: 00000000H Bit Functions of DMAC Control Status Register (DACSR)
Page 352 CHAPTER 15 DMAC These bits are initialized to "0" by resetting. These bits can be both read and written, but can only be set to "0". A Read Modify Write instruction always reads "1" from each of these bits. [bit 30, 26, 22, 18, 14, 10, 6, 2] DEDn (DMA EnD) Each of these bits indicates whether DMA transfer in the corresponding channel (n) is finished.
Page 353: Dmac Pin Control Register (Datcr)
15.4 DMAC Pin Control Register (DATCR) The DMAC pin control register (DATCR) is an internal register of the DMAC and is used to control the external transfer request input pins, external transfer request acknowledgment output pins, and external transfer end output pins. Configuration of DMAC Pin Control Register (DATCR) The configuration of the DMAC pin control register (DATCR) is shown below.
Page 354: Table 15.4-1 Selection Of Transfer Input Detection Levels
CHAPTER 15 DMAC Bit Functions of DMAC Pin Control Register (DATCR) [bit 21,20, 13, 12, 5, 4] LSn1, LSn0: Transfer request input detect level select Each of these bits selects the detection level of the corresponding external transfer request input pin DREQn as shown in Table 15.4-1. Table 15.4-1 Selection of Transfer Input Detection Levels LSn1 The values of these bits are undefined after resetting.
Page 355: Table 15.4-3 Specification Of Transfer End Output
[bit 16, 8, 0] EPDEn These bits specifies the time when the transfer end output signal is to be generated from the corresponding output pin and also specify whether to enable the output function of the corresponding transfer end output signal pin. Table 15.4-3 Specification of Transfer End Output EPSEn EPDEn...
Page 356: Descriptor Register In Ram
CHAPTER 15 DMAC 15.5 Descriptor Register in RAM This descriptor register has the setup information for the corresponding channel in DMA transfer mode. The descriptor register has a 12-byte area for each channel that is allocated to the memory address specified by DPDP. See Table 15.2-1, "...
Page 357: Table 15.5-1 Specification Of Transfer Source Or Destination Address Update Modes
[bits 5, 4] DCS1, DCS0: Transfer destination address update mode These bits specify the mode in which the transfer source or destination address is updated each time DMA transfer is performed. Table 15.5-1 lists the available combinations of these bits. Table 15.5-1 Specification of Transfer Source or Destination Address Update Modes SCS1 SCS0...
Page 358: Table 15.5-4 Transfer Mode Specification
CHAPTER 15 DMAC [bits 1, 0] MOD1, MOD0: Transfer mode These bits specify the transfer mode. Table 15.5-4 Transfer Mode Specification MOD1 MOD0 The continuous transfer mode can be used for channels 0 to 2 only. Second Word of a Descriptor The second word contains the transfer source address.
Page 359: Dmac Transfer Modes
15.6 DMAC Transfer Modes The DMAC supports the following three transfer modes: This section explains the operation in these modes. • Single/block transfer mode • Continuous transfer mode • Burst transfer mode Single/Block Transfer Mode 1. The initialization routine sets the descriptor. 2.
Page 360 CHAPTER 15 DMAC Continuous Transfer Mode 1. The initialization routine sets the descriptor. 2. The program initializes the DMA transfer request source. Set the external transfer request input pin to the H-level or L-level detection mode. 3. The program sets the target DOEn bit of the DACSR to 1. --- This completes the setting for DMA.
Page 361 Burst Transfer Mode 1. The initialization routine sets the descriptor. 2. The program initializes the DMA transfer request source. To use the internal peripheral circuit as the transfer request source, enable interrupt requests and disable interrupts in the ICR of the interrupt controller. 3.
Page 362: Output Of Transfer Request Acknowledgment And Transfer End Signals
CHAPTER 15 DMAC 15.7 Output of Transfer Request Acknowledgment and Transfer End signals Channels 0, 1, and 2 have a function that outputs transfer request acknowledgment and transfer end signals from the corresponding pins. When a transfer request input from the pin is received and DMA transfer is performed, the DMAC outputs a transfer request acknowledgment signal.
Page 363: Notes On Dmac
15.8 Notes on DMAC This section provides notes on using the DMAC. Interchannel Priority Order Once the DMAC starts with a DMA transfer request from one channel, DMA transfer requests from another channel are suspended until the current transfer ends. When the DMAC detects DMA transfer requests from multiple channels which are active simultaneously, these requests are accepted in the following priority order: (High) ch 0>...
Page 364 CHAPTER 15 DMAC PDRR register The suppression function for a DMA transfer operation specified via the HRCL register is valid only when an interrupt request with higher priority is active. Therefore, if the interrupt request is cleared by the interrupt handler program, suppression of the DMA transfer operation via the HRCL register is canceled and the CPU may lose bus control.
Page 365 itself continues. External Transfer from Internal Memory In block transfer mode, DMA transfer is performed twice for a single DREQ. In continuous transfer mode, DMA transfer is performed even if DREQ is canceled. To prevent this, select one of the following countermeasures: •...
Page 366: Dmac Timing Charts
CHAPTER 15 DMAC 15.9 DMAC Timing Charts This section provides the following DMAC timing charts: • Timing charts for the descriptor access block • Timing charts for the data transfer block • Transfer stop timing charts in continuous transfer mode •...
Page 367: Timing Charts Of The Descriptor Access Block
15.9.1 Timing Charts of the Descriptor Access Block This section shows timing charts of the descriptor access block. Descriptor Access Block Required pin input mode: level, descriptor address: external DREQn Addr pin Data pin RDXD WRnX DACK Required pin input mode: level, descriptor address: internal Interanl KB DREQn Addr pin...
Page 368 CHAPTER 15 DMAC Required pin input mode: edge, descriptor address: external DREQn Addr pin Data pin RDXD WRnX DACK Required pin input mode: edge, descriptor address: internal DREQn Addr pin Data pin RDXD WRnX DACK <Note> The section from when a DREQn is generated to when the DMAC operation starts shows the case where the DMAC operation starts first.
Page 369: Timing Charts Of Data Transfer Block
15.9.2 Timing Charts of Data Transfer Block This section shows timing charts of the data transfer block. Data Transfer Block for 16-Bit or 8-Bit Data Transfer source area: external, transfer destination area: external DREQn Addr pin Data pin RDXD WRnX DACK Transfer source area: external, transfer destination area: external RAM DREQn...
Page 370 CHAPTER 15 DMAC Transfer source area: internal RAM, transfer destination area: external DREQn Addr pin Data pin RDXD WRnX DACK...
Page 371: Transfer Stop Timing Charts In Continuous Transfer Mode
15.9.3 Transfer Stop Timing Charts in Continuous Transfer Mode This section shows transfer stop timing charts in continuous transfer mode. Transfer Stop in Continuous Transfer Mode (When Either Address is Unchanged) for 16-Bit or 8-Bit Data Transfer source area: external, transfer destination area: external DREQn Addr pin Data pin...
Page 372 CHAPTER 15 DMAC Transfer Stop in Continuous Transfer Mode (When Both Addresses are Changed) for 16-Bit or 8-Bit Data Transfer source area: external, transfer destination area: external DREQn Addr pin Data pin RDXD WRnX DACK Transfer source area: external, transfer destination area: internal RAM DREQn Addr pin Data pin...
Page 373: Transfer Termination Timing Charts
15.9.4 Transfer Termination Timing Charts This section shows transfer termination timing charts. Transfer Termination (When Either Address is Unchanged.) Bus width: 16 bits, data length: 8/16 bits Addr pin Data pin RDXD WRnX AKSE=1 DACK AKDE=1 Both are 1 EPSE=1 EPDE=1 Both are 1 Bus width: 16 bits, data length: 32 bits...
Page 374 CHAPTER 15 DMAC Transfer Termination (When Both Addresses are Changed.) Bus width: 16 bits, data length: 8/16 bits Addr pin Data pin RDXD WRnX AKSE=1 DACK AKDE=1 Both are 1 EPSE=1 EPDE=1 Both are 1 Bus width: 16 bits, data length: 32 bits Addr pin Data pin RDXD...
Page 375: Chapter 16 Flash Memory
CHAPTER 16 FLASH MEMORY This chapter explains the flash memory functions and operations. The chapter provides information on using the flash memory from the FR-CPU. For information on using the flash memory from the ROM writer, refer to the user’s guide for the ROM writer.
Page 376: Outline Of Flash Memory
(16 bits) units via the FR-CPU. The flash memory employed here is basically the same as the Fujitsu 2-megabit (254 kilobits × 8 or 127 kilobits × 16) flash memory MBM29LV200T (except for a part of the sector configuration) and enables writing with a device-external ROM writer.
Page 377 Execution Status of the Automatic Algorithm When the automatic algorithm is started in CPU programming mode, its operation status can be checked with the internal Busy or Ready signal (RDY/BUSYX). The level of this signal can be read from the "RDY" bit of the flash memory status register. When the "RDY"...
Page 378: Block Diagram Of Flash Memory
CHAPTER 16 FLASH MEMORY 16.2 Block Diagram of Flash Memory Figure 16.2-1 is a block diagram of the flash memory. Block Diagram of Flash Memory Figure 16.2-1 Block diagram of the Flash Memory INTE RDYINT Rising edge detection Control signal generation FR-C bus (instruction/data) RDY/BUSYX...
Page 379: Flash Memory Status Register (Fstr)
16.3 Flash Memory Status Register (FSTR) The flash memory status register (FSTR) indicates the operation status of the flash memory. This register also controls interrupts to the CPU and writing to the flash memory. Only the CPU can access this register. Even if a writer is provided, it cannot access this register.
Page 380 CHAPTER 16 FLASH MEMORY When this bit is "1", writing data and commands to the flash memory becomes valid and the automatic algorithm can be started. However, data from flash memory is read in 16-bit access mode, during which flash memory cannot be used as program memory because 32- bit access is inhibited.
Page 381: Sector Configuration Of Flash Memory
16.4 Sector Configuration of Flash Memory Figure 16.4-1 shows the sector configuration of the flash memory. Table 16.4.1 lists the respective sector addresses. Sector Configuration of the Flash Memory Flash memory address mapping for access from the FR-CPU is different from the mapping for access from the ROM writer.
Page 382: Table 16.4-1 Sector Addresses
CHAPTER 16 FLASH MEMORY Table 16.4-1 Sector Addresses Sector address 000C0800-1h to 000DFFFC-Dh (MSB side 16 bits) 000E0000-1h to 000EFFFC-Dh (MSB side 16 bits) 000F0000-1h to 000F3FFC-Dh (MSB side 16 bits) 000F4000-1h to 000F7FFC-Dh (MSB side 16 bits) 000F8000-1h to 000FFFFC-Dh (MSB side 16 bits) 000C0802-3h to 000DFFFE-Fh (LSB side 16 bits) 000E0002-3h to 000EFFFE-Fh (LSB side 16 bits) 000F0002-3h to 000F3FFE-Fh (LSB side 16 bits)
Page 383: Flash Memory Access Modes
16.5 Flash Memory Access Modes The following two types of access mode are available for the FR-CPU: • ROM mode: One word (32 bits) can be read in one cycle, but not written. • Programming mode: Access to data with a length in words (32 bits) is inhibited but writing data with a length in half-words (16 bits) is enabled.
Page 384 CHAPTER 16 FLASH MEMORY For details on the automatic algorithm, see Section 16.6, "Starting the Automatic Algorithm." Restrictions Address assignment and endians in this mode differ from those for writing with the ROM writer. This mode inhibits reading data in words (32 bits).
Page 385: Starting The Automatic Algorithm
16.6 Starting the Automatic Algorithm For writing data to or erasing data from flash memory, start the automatic algorithm stored in flash memory. Command Operation At the start of the automatic algorithm, one to six half-words (16 bits) are written. This data is called the command.
Page 386 CHAPTER 16 FLASH MEMORY Program (Write) In CPU programming mode, data is basically written in half-word units. The write operation is performed in four cycles of bus operation. The command sequence has two "unlock" cycles, which are followed by a Write Setup command and a write data cycle. Writing to memory starts in the last write cycle.
Page 387 16.6 Starting the Automatic Algorithm During the time-out period, any command other than Sector Erase and Temporarily Stop Erase is reset at read time, and the preceding command sequence is ignored. In the case of the Temporary Stop Erase command, the contends of the sector are erased again and the erase operation is completed.
Page 388: Execution Status Of The Automatic Algorithm
CHAPTER 16 FLASH MEMORY 16.7 Execution Status of the Automatic Algorithm This flash memory has two hardware components for performing a Write or Erase sequence in the automatic algorithm. These components indicate the internal operation status of flash memory and the completion of operations to external components.
Page 389: Table 16.7-1 Statuses Of The Hardware Sequence Flag
Table 16.7-1 lists the possible statuses of the hardware sequence flag. Table 16.7-1 Statuses of the Hardware Sequence Flag Status Executing Automatic read operation Automatic erase operation Temporary Temporary erase erase stop stop and read mode (from sectors in temporary erase stop) Temporary erase stop and read...
Page 390 CHAPTER 16 FLASH MEMORY Temporary sector erase stop status When a read operation is performed during temporary sector erase stop, flash memory outputs "1" if the address indicated by the address signal is included in the sector in erase state. If the address is not included in the sector in erase state, flash memory outputs the data of bit 7 of the read value at the address indicated by the address signal.
Page 391 16.7 Execution Status of the Automatic Algorithm Suppose that the data polling and toggle bit functions indicate that the erase algorithm is running. If this flag is "1" in this case, an internally controlled erase operation has started and succeeding command entries are ignored until the data polling or toggle bit indicates the end of the erase operation.
Page 392 CHAPTER 16 FLASH MEMORY...
Page 393: Appendix
APPENDIX The appendices provide more details and programming references concerning the I/O maps, interrupt vectors, pin statuses in CPU states, precautions on using the little endian area, and instructions. A I/O Maps B Interrupt Vectors C. Pin Status for Each CPU Status D.
Page 394: Appendix A I/O Maps
APPENDIX A I/O Maps APPENDIX A I/O Maps The addresses listed from Table A.1 to Table A.6 are assigned to the registers of the functions for peripherals that are built-in in the MB91F109. How to Read the I/O Maps Address 000000 PDR3 [R/W]...
Page 395: Table A-1 I/O Map
I-O Maps Table A-1 I/O Map (1/6) Address 000000 PDR3 [R/W] XXXXXXXX 000004 PDR7 [R/W] -------X 000008 PDRB [R/W] XXXXXXXX 00000C 000010 000014 000018 00001C [R/W] 00001-00 000020 [R/W] 00001-00 000024 [R/W] 00001-00 000028 TMRLR XXXXXXXX 00002C 000030 TMRLR XXXXXXXX 000034 00038 ADCR...
Page 396: Table A-2 I/O Map (2/6)
APPENDIX A I/O Maps Table A-1 I/O Map (1/6) Address 000054 000058 Table A-2 I/O Map (2/6) Address 00005C 000060 000064 000068 00006C 000070 000074 000078 UTIM/UTIMR 00000000 0007C UTIM/UTIMR 00000000 000080 UTIM/UTIMR 00000000 000084 000088 00008C 000090 000094 EIRR [R/W] 00000000 000098 Register...
Page 397: Table A-3 I/O Map (3/6)
Table A-2 I/O Map (2/6) Address 00009C 0000A0 0000A4 0000A8 0000AC 0000B0 0000B4 0000B8 Table A-3 I/O Map (3/6) Address 0000BC 0000C0 0000C4 0000C8 0000CC 0000D0 0000D4 0000D8 Register Register DDRE 00000000 APPENDIX A I/O Maps Internal resource Reserved Internal resource Reserved DDRF Data direction...
Page 398 APPENDIX A I/O Maps Table A-3 I/O Map (3/6) Address 0000DC GCN1 00110010 00010000 0000E0 PTMR 11111111 11111111 0000E4 PDUT XXXXXXXX 0000E8 PTMR 11111111 11111111 0000EC PDUT XXXXXXXX 0000F0 PTMR 11111111 11111111 000F4 PDUT XXXXXXXX 0000F8 PTMR 11111111 11111111 0000FC PDUT XXXXXXXX 000100...
Page 399: Table A-4 I/O Map (4/6)
Table A-4 I/O Map (4/6) Address 000254 000258 00025C 000260 000264 000268 00026C 000270 000274 000278 0002FC 000300 0003E3 0003E4 0003E8 0003EC 0003F0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register BSD0 BSD1...
Page 400: Table A-5 I/O Map (5/6)
APPENDIX A I/O Maps Table A-5 I/O Map (5/6) Address 000400 ICR00 [R/W] ---11111 000404 ICR04 [R/W] ---11111 000408 ICR08 [R/W] ---11111 00040C ICR12 [R/W] ---11111 000410 ICR16 [R/W] ---11111 000414 ICR20 [R/W] ---11111 000418 ICR24 [R/W] ---11111 00041C ICR28 [R/W] ---11111 000420...
Page 401: Table A-6 I/O Map
Table A-5 I/O Map (5/6) Address 000600 DDR3 00000000 000604 DDR7 -------0 000608 DDRB 00000000 Table A-6 I/O Map Address 00060C ASR1 00000000 000610 ASR2 00000000 000614 ASR3 00000000 000618 ASR4 00000000 00061C ASR5 00000000 000620 AMD0 [R/W] ---XX111 000624 AMD5 [R/W] 0--00000...
Page 402 APPENDIX A I/O Maps <Note> Do not execute RMW instructions for registers for which a write-only bit is set. RMW instructions (RMW: Read Modify Write) AND Rj, @Ri ANDH Rj, @Ri ANDB Rj, @Ri BANDL #u4, @Ri BANDH #u4, @Ri Data in areas marked as "Reserved"...
Page 403: Appendix B Interrupt Vectors
APPENDIX B Interrupt Vectors Table B.1 and Table B.2 list the interrupt vectors. The interrupt vector tables list causes for MB91F109 interrupts together with interrupt vector or interrupt control register assignments. Interrupt Vectors Table B-1 Interrupt Vectors (1/2) Cause for the interrupt Reset Reserved for the system Reserved for the system...
Page 404 APPENDIX B Interrupt Vectors Table B-1 Interrupt Vectors (1/2) Cause for the interrupt UART 2 reception completion UART 0 send completion UART 1 send completion UART 2 send completion DMAC 0 (end, error) DMAC 1 (end, error) DMAC 2 (end, error) DMAC 3 (end, error) DMAC 4 (end, error) DMAC 5 (end, error)
Page 405: Table B-2 Interrupt Vectors (2/2)
Table B-2 Interrupt Vectors (2/2) Interrupt cause Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system Reserved for the system...
Page 406 APPENDIX B Interrupt Vectors Reference: The area 1 kilobyte after the address indicated by the TBR is a vector address for EIT. Each vector is 4 bytes in size. The relationship between the vector number and vector address is as follows: vctadr TBR + vctofs TBR + (3FC...
Page 407: Appendix C Pin Status For Each Cpu Status
APPENDIX C Pin Status for Each CPU Status Table C.1 explains the terms used in the pin status list. Table C-2 to Table C-5 list the pin status for each CPU status. Note that the pin status at reset differs between the external bus mode and single chip mode.
Page 408: Table C-2 Pin Status For 16-Bit External Bus Length And 2Ca1Wr Mode
APPENDIX C Pin Status for Each CPU Status Pin Status for Each CPU Status Table C-2 Pin Status for 16-bit External Bus Length and 2CA1WR Mode Pin name Function During sleep P20 to P27 D16-23 Output retained or Hi-Z D24-31 A00-15 Output retained (Address...
Page 409 Table C-2 Pin Status for 16-bit External Bus Length and 2CA1WR Mode (Continued) Pin name Function During sleep P: Previous status retained F: CLK output RAS0 P: Previous status retained CS0L F: Previous value retained CS0H Executed when DRAM pin is DW0X set.
Page 410 APPENDIX C Pin Status for Each CPU Status Table C-2 Pin Status for 16-bit External Bus Length and 2CA1WR Mode (Continued) Pin name Function During sleep SO1, Previous status TRG3 retained SI2, OCPA1 SO2, OCPA2 OCPA0, ATGX when a general-purpose port is specified, F: when the specified function is selected Selfrefresh status is entered at selfrefresh start time.
Page 411: Table C-3 Pin Status For 16-Bit External Bus Length And 2Ca1Wr Mode
Table C-3 Pin Status for 16-bit External Bus Length and 2CA1WR Mode Pin name Function During sleep P20 to P27 D16-23 Output retained or Hi-Z D24-31 A00-15 Output retained (Address output) P60 to P67 A16-23 P: Previous status retained F: Address output A24, Previous status...
Page 412 APPENDIX C Pin Status for Each CPU Status Table C-3 Pin Status for 16-bit External Bus Length and 2CA1WR Mode (Continued) Pin name Function During sleep P: Previous status retained F: CLK output RAS0 P: Previous status retained CS0L F: Previous value retained CS0H Executed when...
Page 413 Table C-3 Pin Status for 16-bit External Bus Length and 2CA1WR Mode (Continued) Pin name Function During sleep SO1, Previous status TRG3 retained SI2, OCPA1 SO2, OCPA2 OCPA0, ATGX when a general-purpose port is specified, F: when the specified function is selected Selfrefresh status is entered at selfrefresh start time.
Page 414: Table C-4 Pin Status In 8-Bit External Bus Mode
APPENDIX C Pin Status for Each CPU Status Table C-4 Pin Status in 8-bit External Bus Mode Pin name Function During sleep P20 to P27 Port Previous status retained D24-31 Output Hi-Z/ Input fixed to 0 A00-15 Output retained (Address output) P60 to P67 A16-23...
Page 415 Table C-4 Pin Status in 8-bit External Bus Mode (Continued) Pin name Function During sleep P: Previous status retained F: CLK output RAS0 P: Previous status retained CS0L F: Previous value retained (*2) CS0H P: Previous status retained F: Previous value retained DW0X P: Previous...
Page 416 APPENDIX C Pin Status for Each CPU Status Table C-4 Pin Status in 8-bit External Bus Mode (Continued) Pin name Function During sleep SC0, Previous status OCPA3 retained SI1, TRG2 SO1, TRG3 SI2, OCPA1 SO2, OCPA2 OCPA0, ATGX when a general-purpose port is specified, F: when the specified function is selected Selfrefresh status is entered at selfrefresh start time.
Page 417: Table C-5 Pin Status In Single Chip Mode
Table C-5 Pin Status in Single Chip Mode Pin name Function During sleep P20 to P27 Port Previous status retained P30 to P37 P40 to P47 P50 to P57 P60 to P67 EOP0 P: Previous status retained F: EOP output Port Previous status retained...
Page 418 APPENDIX C Pin Status for Each CPU Status Table C-5 Pin Status in Single Chip Mode (Continued) Pin name Function During sleep DREQ2 Previous status retained DACK2 P: Previous status retained F: DACK output Port Previous status retained AN0 to AN0-3 Previous status retained...
Page 419: Appendix D Notes On Using Little Endian Areas
APPENDIX D Notes on Using Little Endian Areas This section contains notes on using little endian areas for each item below. D.1 C Compiler (fcc911) D.2 Assembler (fasm911) D.3 Linker (flnk911) D.4 Debugger (sim911, eml1911, mon911) APPENDIX D Notes on Using Little Endian Areas...
Page 420: C Compiler (Fcc911)
APPENDIX D Notes on Using Little Endian Areas C Compiler (fcc911) When the operations described below are performed for little endian areas from programs in C, the results of the respective operations may be rendered uncertain. • Allocating variables with initial values •...
Page 421 #define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i; void main(void) { STRMOVE(little_st,normal_st); Moreover, as the member allocation for a structure is different for each compiler, it may differ from that of another compiler. In this a case, the correct result cannot be acquired. When the member allocations for structures differ, do not allocate the corresponding structure variables to a little endian area.
Page 422 APPENDIX D Notes on Using Little Endian Areas Do not allocate double and long double type variables to little endian areas. [Example of incorrect processing] Transfer of double type data double big = 1.0; /* Big endian area extern int little; little = big;...
Page 423: Assembler (Fsm911)
Assembler (fsm911) The following two items require caution when using little endian areas during programming in FR-series Assembler: • Sections • Data Access Sections Little endian areas are allocated primarily for data exchange data with little endian type CPUs. Therefore, define little endian areas as data sections that store no initial value. If a little endian area is specified as data section storing a code or initial stack value, the result of an access by the MB91F109 cannot be guaranteed.
Page 424 APPENDIX D Notes on Using Little Endian Areas /* 32-bit data is accessed with a ST (or LD) instruction.*/ r0, @r1 /* 16-bit data is accessed with a STH (or LDH) instruction. */ r2, @r3 /* 8-bit data is accessed with a STB (or LDB) instruction. */ r4, @r5 If the MB91F109 accesses data with an operation for of a different size, the data value cannot be guaranteed.
Page 425: Linker (Flnk911)
Linker (flnk911) The following two items require caution with respect to link-time section allocation during program design when employing little endian areas. • Restriction on section types • No detection of errors Restriction on Section Types Only data sections with no initial value can be allocated to little endian areas. If data, stack, and code sections with initial values are allocated to little endian areas, the result of subsequent operations cannot be guaranteed because operations such as resolving addresses are executed by the linker in big endian areas.
Page 426: Debuggers (Sim911, Eml911, And Mon911)
APPENDIX D Notes on Using Little Endian Areas Debuggers (sim911, eml911, and mon911) This section provides notes on the simulator debugger and emulator or monitor debugger. Simulator Debugger There is no memory area specification command indicating little endian areas. Memory manipulation commands and instructions to be executed are handled as if they applied to big endian areas.
Page 427: Appendix E Instructions
APPENDIX E Instructions This section lists the instructions for the FR-series. Before the instructions are listed, the following items are explained: • How to read instructions • Addressing mode codes • Instruction formats How to Read Instructions Mnemonic Type *ADD #s5, Indicates the instruction names An asterisk (*) indicates extended or assembler instructions that were added to the...
Page 428 APPENDIX E Instructions Indicates flag changes Flag change C ... Changes Does not change Cleared Indicates the operation for the instruction Flag meaning Negative flag Zero flag Overflow flag Carry flag...
Page 429: Table E-1 Explanation Of Addressing Mode Codes
Addressing Mode Codes Table E-1 Explanation of Addressing Mode Codes Code #i20 #i32 #s10 #u10 @dir8 @dir9 @dir10 label9 label12 label20 label32 Register using direct addressing (R0 toR15, AC, FP, SP) Register using direct addressing (R0 to R15,AC,FP,SP) Register using direct addressing (R13,AC) Register using direct addressing (Program status register) Register using direct addressing (TBR,RP,SSP,USP,MDH,MDL) Register using direct addressing (CR0 to CR15)
Page 430 APPENDIX E Instructions Table E-1 Explanation of Addressing Mode Codes @(R13, Rj) @(R14 ,disp10) @(R14, disp9) @(R14, disp8) @(R15, udisp6) @Ri+ @R13+ @SP+ @-SP (reglist) Register using relative and indirect addressing (Rj: R0 to R15, AC, FP, and SP) Register using relative and indirect addressing (disp10: -0X200 to 0X1FC, multiple of 4 only) Register using relative and indirect addressing (disp9: -0X100 to 0XFE, multiple of 2 only)
Page 431: Table E-2 Instruction Formats
Instruction Formats Table E-2 Instruction Formats Type *C’ Instruction format 16bit i8/o8 u4/m4 ADD,ADDN,CMP,LSL,LSR and ASR instructions only s5/u5 u8/rel8/dir/reglist SUB-OP APPENDIX E Instructions...
Page 432 APPENDIX E Instructions Table E-2 Instruction Formats rel11...
Page 433: Fr-Series Instructions
FR-Series Instructions This section describes the FR-series instructions in the following order: FR-Series Instructions Table E.1-1 Addition and Subtraction Instructions Table E.1-2 Compare Operation Instructions Table E.1-3 Logical Operation Instructions Table E.1-4 Bit Operation Instructions Table E.1-5 Multiplication and Division Instructions Table E.1-6 Shift Instructions Table E.1-7 Immediate Value Setting or 16/32-Bit Immediate Value Transfer Instruction Table E.1-8 Memory Load Instructions...
Page 434 APPENDIX E Instructions Addition and Subtraction Instructions Table E.1-1 Addition and Subtraction Instructions Mnemonic Type Rj, Ri *ADD #s5, Ri C’ #i4, Ri ADD2 #i4, Ri ADDC Rj, Ri ADDN Rj, Ri *ADDN #s5, Ri ADDN #i4, Ri ADDN2#i4, Ri Rj, Ri SUBC Rj, Ri SUBN Rj, Ri...
Page 435 Logical Operation Instructions Table E.1-3 Logical Operation Instructions Mnemonic Type Rj, Ri Rj, @Ri ANDH Rj, @Ri ANDB Rj, @Ri Rj, Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, Ri Rj, @Ri EORH Rj, @Ri EORB Rj, @Ri Bit Operation Instructions Table E.1-4 Bit Operation Instructions Mnemonic Type...
Page 436 APPENDIX E Instructions The assembler creates BEORL if the bit is ON in u8&0x0F and BEORH if the bit is ON in u8&0xF0. Both BEORL and BEORH may be created. Multiplication and Division Instructions Table E.1-5 Multiplication and Division Instructions Mnemonic Type Rj,Ri...
Page 437 Immediate Value Setting or 16/32-Bit Immediate Value Transfer Instruction Table E.1-7 Immediate Value Setting or 16/32-Bit Immediate Value Transfer Instruction Mnemonic Type LDI:32 #i32, Ri LDI:20 #i20, Ri LDI:8 #i8, Ri *LDI #{i8|i20|i32},Ri* When the immediate value is an absolute value, the assembler automatically selects i8, i20, or i32. If the immediate value includes a relative value or external reference symbol, i32 is selected.
Page 438 APPENDIX E Instructions Memory Store Instructions Table E.1-9 Memory Store Instructions Mnemonic Type Ri, @Rj Ri, @(R13,Rj) Ri, @(R14,disp10) Ri, @(R15,udisp6) Ri, @-R15 Rs, @-R15 PS, @-R15 Ri, @Rj Ri, @(R13,Rj) Ri, @(R14,disp9) Ri, @Rj Ri, @(R13,Rj) Ri, @(R14,disp8) *: Special register Rs: TBR, RP, USP, SSP, MDH, MDL (Notes) The assembler calculates and sets values in the o8 and o4 fields of hardware specifications as follows:...
Page 439 Standard Branch (Without Delay) Instructions Table E.1-11 Standard Branch (Without Delay) Instructions Mnemonic Type 97-0 CALL label12 CALL 97-1 97-2 INTE 9F-3 RETI 97-3 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 (Notes) •...
Page 440 APPENDIX E Instructions Delayed-Branch Instructions Table E.1-12 Delayed Branch Instructions Mnemonic Type JMP:D @Ri 9F-0 CALL:D label12 CALL:D @Ri 9F-1 RET:D 9F-2 BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9 BC:D label9 BNC:D label9 BN:D label9 BP:D label9 BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9...
Page 441 Other Instructions Table E.1-13 Other Instructions Mnemonic Type 9F-A ANDCCR#u8 ORCCR #u8 STILM ADDSP #s10*1 EXTSB Ri 97-8 EXTUB Ri 97-9 EXTSH Ri 97-A EXTUH Ri 97-B LDM0 (reglist) LDM1 (reglist) *LDM (reglist)*2 STM0 (reglist) STM1 (reglist) *STM (reglist)*3 ENTER #u10*4 LEAVE 9F-9 XCHB...
Page 442 APPENDIX E Instructions (Notes) • LDM0 (reglist) and LDM1 (reglist) have a*(n-1) +b+1 execution cycles when the specified number of registers is n. • STM0 (reglist) and STM1 (reglist) have a*n+1 execution cycles when the specified number of registers is n. 20-Bit Standard Branch Macro Instructions Table E.1-14 20-Bit Standard Branch Macro Instructions Mnemonic...
Page 443 When label20-PC-2 is outside of the range in 1) and includes an external reference symbol, an instruction is created as follows: Bxcc LDI:20 #label20,Ri false: 20-Bit Delayed-Branch Macro Instructions Table E.1-15 20-Bit Delayed-Branch Macro Instructions Mnemonic *CALL20:D label20,Ri *BRA20:D label20,Ri *BEQ20:D label20,Ri *BNE20:D...
Page 444 APPENDIX E Instructions When label20-PC-2 is outside of the range in 1) and includes an external reference symbol, an instruction is created as follows: Bxcc LDI:20 #label20,Ri JMP:D @Ri false: 32-Bit Standard Branch Macro Instructions Table E.1-16 32-Bit Standard Branch Macro Instructions Mnemonic *CALL32 label32,Ri...
Page 445 When label32-PC-2 is outside of the range in 1) and includes an external reference symbol, an instruction is created as follows: Bxcc LDI:32 #label32,Ri false: 32-Bit Delayed-Branch Macro Instructions Table E.1-17 32-Bit Delayed-Branch Macro Instructions Mnemonic *CALL32:D label32,Ri *BRA32:D label32,Ri *BEQ32:D label32,Ri *BNE32:D...
Page 446 APPENDIX E Instructions When label32-PC-2 is outside of the range in 1) and includes an external reference symbol, an instruction is created as follows: Bxcc LDI:32 #label32,Ri JMP:D @Ri false: Direct Addressing Instructions Table E.1-18 Direct Addressing Instructions Mnemonic DMOV @dir10, R13 DMOV R13,...
Page 447 Coprocessor Control Instructions Table E.1-20 Coprocessor Control Instructions Mnemonic COPOP #u4,#u8,CRj,CRi COPLD #u4,#u8,Rj, CRi COPST #u4,#u8,CRj,Ri COPSV #u4,#u8,CRj,Ri Notes: • {CRi|CRj}:= CR0|CR1|CR2|CR3|CR4|CR5|CR6|CR7|CR8|CR9|CR10|CR11|CR12|CR13|CR14|CR15 u4:= Channel specification u8:= Command specification • As this device type does not have coprocessors, these instructions cannot be used. Type CYCLE NZVC...
Page 448 APPENDIX E Instructions...
Page 449: Index
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
Page 450 INDEX Index Numerics 0-detection ... 295 16/31-bit immediate value transfer or immediate value setting ... 413 16/8-bit data, data transfer block for ... 345 16-bit bus width ... 142, 144, 149, 150 16-bit data bus ... 157 16-bit reload register (TMRLR)... 286 16-bit reload time register ...
Page 451 bus control acquisition ... 193 bus control release... 193 bus converter, 32 bits - 16 bits... 32 bus converter, Harvard-Princeton ... 32 bus interface ... 2 bus interface register ... 113 bus interface, block diagram of ... 114 bus interface, feature of ... 112 bus mode ...
Page 452 INDEX descriptor, first word of... 332 descriptor, second word of ... 334 descriptor, third word of... 334 detection data register 0 (BSD0) ... 293 detection data register 1 (BSD1) ... 293 detection of error not found ... 401 detection result register (BSRR)... 294 detection, 0...
Page 453 external trigger or internal timer to start A/D converter, using ... 280 external wait cycle timing chart ... 172 FBGA-112, outside dimension ... 9 FBGA-112, pin arrangement... 12 first word of descriptor... 332 flag and interrupt occurrence ... 260 flash memory register ... 352 flash memory status register (FSTR) ...
Page 454 INDEX interrupt flag set timing for data reception in mode 1 ... 261 interrupt flag set timing for data reception in mode 2 ... 261 interrupt flag set timing for data tranmission in mode 0, 1 or 2 ... 262 interrupt level...
Page 455 power-on, input of source oscillation at... 27 power-on, pin condition at... 27 PPDR register ... 340 priority check... 231 program (read) ... 362 program access ... 43 program counter (PC) ... 36 program status (PS)... 37 program status register (PS)... 39 PWM cycle setting register (PCSR) ...
Page 456 INDEX standby mode (stop or sleep state), returning from... 234 standby mode state transition ... 98 standby mode, type of operation in ... 90 starting multiple PWM timer channel using 16-bit reload timer ... 322 starting multiple PWM timer channel via software321 step-trace-trap...
Page 457 wait cycle ... 159 watchdog controller block diagram ... 99 watchdog timer reset delay register (WPR), bit function of ... 85 watchdog timer reset delay register (WPR), configuration of ... 85 watchdog timer, starting ...99 word access...141, 147, 151 write cycle timing chart ...168 write timing chart, hyper DRAM interface ...189 write timing chart.
Page 458 INDEX...
Page 459 FUJITSU SEMICONDUCTOR • CONTROLLER MANUALl FR30 32-Bit Microcontroller MB91F109 Hardware Manual FUJITSU LIMITED Published Edited Technical Communication Dept. CM71-10106-1E February 2000 the first edition Electronic Devices...
Page 461 FUJITSU SEMICONDUCTOR FR30 32-Bit Microcontroller MB91F109 Hardware Manual...

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Mb91f109

Fujitsu MB91F109 FR30 Hardware Manual

Chapter 1 Overview

Chapter 2 Cpu

Chapter 3 Clock Generator and Controller

Chapter 4 Bus Interface

Chapter 5 I/O Ports

Chapter 6 External Interrupt/Nmi Controller

Chapter 7 Delayed Interrupt Module

Chapter 8 Interrupt Controller

Chapter 9 U-Timer

Chapter 10 Uart

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