Page 1 FUJITSU SEMICONDUCTOR CM25-10146-1E CONTROLLER MANUAL MC-8L 8-BIT MICROCONTROLLER MB89950/950A Series HARDWARE MANUAL...
Page 3 MC-8L 8-BIT MICROCONTROLLER MB89950/950A Series HARDWARE MANUAL FUJITSU LIMITED...
Page 5 MC-8L MB89600 Series Programming Manual for details on the MB89950/950A instruction set. I Trademarks MC is the abbreviation of FUJITSU Flexible Microcontroller. Other system and product names in this manual are trademarks of respective companies or organizations. The symbols and ® are sometimes omitted in this manual.
Page 6 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Page 7 READING THIS MANUAL I Notations of the Register Name and Pin Name Example for description of register name and bit name Notations of a double-purpose pin P22/SCK pin Some pins can be used by switching their functions using, for example, settings by a program. Each double-purpose pin is represented by separating the name of each function using "/".
Page 8 Documents and Development Tools Required for Development Items necessary for the development of this product are as follows. To obtain the necessary documents and development tools, contact a company sales representative. Manuals required for development [Check field] MC-8L MB89950/950A series data sheet (provides a table of electrical characteristics and vari- ous examples of this product) MC-8L Programming Manual (manual including instructions for the F MC-8L family)
Page 9 ❍ What is needed for evaluation on the one-time PROM microcomputer (if the programming operation is performed at your side) [Check field] MB89P955 EPROM programmer (Programmer available for the MBM27C1001) Package conversion adapter ROM-64QF2-28DP-8L3 Development tools [Check field] MB89PV950 (piggyback/evaluation device) Development tool Main unit Probe...
Page 11: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ....................1 MB89950/950A Series Features ......................2 MB89950/950A Series Product Range ....................4 Differences among Products ........................ 6 Block Diagram of MB89950/950A Series .................... 7 Pin Assignment ............................. 8 Package Dimensions .......................... 10 I/O Pins and Pin Functions ......................... 12 CHAPTER 2 HANDLING DEVICES ................
Page 12 CHAPTER 4 I/O PORTS ....................69 Overview of I/O Ports .......................... 70 Port 0 ..............................72 4.2.1 Port 0 Data Register (PDR0) ......................74 4.2.2 Operation of Port 0 ........................75 Port 1 ..............................77 4.3.1 Port 1 Data Register (PDR1) ......................79 4.3.2 Operation of Port 1 ........................
Page 13 Program Example for 8-bit PWM Timer .................... 138 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ........... 141 Overview of Pulse Width Count Timer ....................142 Block Diagram of Pulse Width Count Timer ..................144 Structure of Pulse Width Count Timer ....................146 8.3.1 PWC Pulse Width Control Register 1 (PCR1) ................
Page 14 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) ..........223 11.1 Overview of the External Interrupt Circuit ..................224 11.2 Block Diagram of the External Interrupt Circuit ................. 225 11.3 Structure of the External Interrupt Circuit ..................226 11.3.1 External Interrupt Control Register (EIC) ..................228 11.4 External Interrupt Circuit Interrupts ....................
Page 15: Chapter 1 Overview
CHAPTER 1 OVERVIEW This chapter describes the main features and basic specifications of the MB89950/950A series. 1.1 "MB89950/950A Series Features" 1.2 "MB89950/950A Series Product Range" 1.3 "Differences among Products" 1.4 "Block Diagram of MB89950/950A Series" 1.5 "Pin Assignment" 1.6 "Package Dimensions" 1.7 "I/O Pins and Pin Functions"...
Page 16: Mb89950/950A Series Features
CHAPTER 1 OVERVIEW MB89950/950A Series Features The MB89950/950A series is a line of the general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as an LCD controller/driver, UART, a serial I/O, PWC timer, PWM timer and external interrupts.
Page 17 CHAPTER 1 OVERVIEW External interrupts (2 channels) • Two channels are independent and capable of wake-up from low-power consumption mode (with an edge detection function). Standby mode (low-power mode) • Stop mode (oscillation stops so as to minimize the current consumption). •...
Page 18: Mb89950/950A Series Product Range
CHAPTER 1 OVERVIEW MB89950/950A Series Product Range The MB89950/950A series contains 4 different models. Table 1.2-1 "MB89950/950A series product line-up" lists the product range and Table 1.2-2 "Common specifications for the MB89950/950A series" lists the common specifications. I MB89950/950A series product range Table 1.2-1 MB89950/950A series product line-up Part number MB89951A...
Page 19 CHAPTER 1 OVERVIEW Table 1.2-2 Common specifications for the MB89950/950A series Parameter Specification CPU functions Number of instructions: 136 Instruction bit length: 8 bits Instruction length: 1 to 3 bytes Data bit length: 1, 8, 16 bits Minimum execution time: 0.80 µs to 12.8 µs at 5 MHz Interrupt processing time: 7.26 µs to 115.2 µs at 5 MHz Peripheral Ports...
Page 20: Differences Among Products
CHAPTER 1 OVERVIEW Differences among Products This section describes the differences among the 4 products in the MB89950/950A series and lists points to note in product selection. I Differences among products and points to note for product selection Table 1.3-1 Package and corresponding products Package Part number MB89951A...
Page 21: Block Diagram Of Mb89950/950A Series
CHAPTER 1 OVERVIEW Block Diagram of MB89950/950A Series Figure 1.4-1 "MB89950/950A series overall block diagram" shows the block diagram of the MB89950/950A series. I MB89950/950A series block diagram Figure 1.4-1 MB89950/950A series overall block diagram 8-bit PWM timer P41/PWM Main oscillator circuit External interrupt Clock control circuit...
Page 22: Pin Assignment
CHAPTER 1 OVERVIEW Pin Assignment Figure 1.5-1 "FPT-64P-M09 pin assignment" and Figure 1.5-2 "MQP-64C-P01 pin assignment" show the pin assignment diagrams for the MB89950/950A series. I FPT-64P-M09 pin assignment Figure 1.5-1 FPT-64P-M09 pin assignment SEG4 P00/SEG20 SEG3 P01/SEG21 SEG2 P02/SEG22 SEG1 P03/SEG23 SEG0...
Page 23 CHAPTER 1 OVERVIEW I MQP-64C-P01 pin assignment Figure 1.5-2 MQP-64C-P01 pin assignment SEG5 SEG18 SEG4 SEG19 SEG3 P00/SEG20 SEG2 P01/SEG21 SEG1 P02/SEG22 SEG0 P03/SEG23 COM3 P04/SEG24 COM2 P05/SEG25 COM1 P06/SEG26 COM0 P07/SEG27 P10/SEG28 V2/P33 P11/SEG29 V1/P32 P12/SEG30 P13/SEG31 P14/SEG32 P15/SEG33 P41/PWM P16/SEG34 P42/PWC/INT1...
Page 24: Package Dimensions
(FPT-64P-M09) 14.00±0.20(.551±.008)SQ 12.00±0.10(.472±.004)SQ 0.145±0.055 (.0057±.0022) 0.10(.004) 0.10(.004) Details of "A" part +0.20 1.50 (Mounting height) +.008 .059 0.25(.010) INDEX 0.50±0.20 0.10±0.10 (.020±.008) (.004±.004) "A" (Stand off) 0.60±0.15 (.024±.006) 0.65(.026) 0.32±0.05 0.13(.005) (.013±.002) Dimensions in mm (inches). 2001 FUJITSU LIMITED F64018S-c-2-4...
Page 25: Chapter 1 Overview
.047 (.039±.010) 1.27±0.13 (.050±.005) 18.12±0.20 22.30±0.33 12.02(.473) (.713±.008) (.878±.013) 18.00(.709) 10.16(.400) 14.22(.560) 0.30(.012) 24.70(.972) 0.40±0.10 (.016±.004) +0.40 1.27±0.13 0.30(.012)TYP 0.40±0.10 1.20 (.050±.005) (.016±.004) +.016 .047 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 10.82(.426) 0.15±0.05 0.50(.020)TYP (.006±.002) Dimensions in mm (inches). 1994 FUJITSU LIMITED M64004SC-1-3...
Page 26: I/O Pins And Pin Functions
CHAPTER 1 OVERVIEW I/O Pins and Pin Functions Table 1.7-1 "Pin description" and Table 1.7-2 "Pin description for external ROM (for MB89PV950 only)" list the MB89950/950A series I/O pins and their functions. Table 1.7-3 "I/O circuit type" lists the I/O circuit types. The letter in the "I/O circuit type"...
Page 27 CHAPTER 1 OVERVIEW Table 1.7-1 Pin description (2/2) Pin no. Pin name circuit Function type LQFP MQFP General-purpose I/O port. P41/PWM Also serves as PWM timer toggle output (PWM). A pull-up resistor option is provided. General-purpose I/O port. Also serves as pulse-width count timer input (PWC) and external P42/PWC/INT1 interrupt input (INT1).
Page 28 CHAPTER 1 OVERVIEW Table 1.7-2 Pin description for external ROM (for MB89PV950 only) Pin no. Pin name Function For high-level output. For address output. For data input. For power supply (GND). For data input. For ROM chip enable. The High level is output in standby mode. For address output.
Page 29 CHAPTER 1 OVERVIEW Table 1.7-3 I/O circuit type (1/2) Type Circuit Remarks • Crystal oscillator • Feedback resistor: About 1 MΩ (5 V) N-ch P-ch P-ch N-ch N-ch tandby control signal • CMOS input • Pull-down resistor (N-ch): About 50 kΩ (5 V) •...
Page 30 CHAPTER 1 OVERVIEW Table 1.7-3 I/O circuit type (2/2) Type Circuit Remarks • CMOS output • CMOS input • Hysteresis input (peripheral input) • The pull-up resistor is optional: About 50 kΩ (5 V) P-ch P-ch N-ch • N-ch open-drain output •...
Page 31: Chapter 2 Handling Devices
CHAPTER 2 HANDLING DEVICES This chapter describes points to note when using the general-purpose single-chip microcontroller. 2.1 "Notes on Handling Devices"...
Page 32: Notes On Handling Devices
CHAPTER 2 HANDLING DEVICES Notes on Handling Devices This section lists points to note regarding the power supply voltage, pins, and other device handling aspects. I Notes on handling devices Preventing latch-up Latch-up may occur on CMOS ICs if voltage higher than V or lower than V is applied to input and output pins other than medium to high-voltage pins or if higher than the voltage which shows on Absolute...
Page 33 CHAPTER 2 HANDLING DEVICES Recommended screening conditions The OTPROM product should be screened by high-temperature aging before mounting. Verify program High-temperature aging (150 C, 48Hrs) Read Mount The programming test cannot be performed for all bits of the preprogrammed OTPROM product due to its characteristics.
Page 34 CHAPTER 2 HANDLING DEVICES...
Page 35: Chapter 3 Cpu
CHAPTER 3 This chapter describes the functions and operation of the CPU. 3.1 "Memory Space" 3.2 "Dedicated Registers" 3.3 "General-purpose Registers" 3.4 "Interrupts" 3.5 "Resets" 3.6 "Clocks" 3.7 "Standby Modes (Low-power Consumption)" 3.8 "Memory Access Mode"...
Page 36: Memory Space
CHAPTER 3 CPU Memory Space The microcontrollers of the MB89950/950A series offer a memory space of 64 Kbytes. The memory space contains the I/O area, RAM area, ROM area, and external area. The memory space contains areas used for special purposes such as the general-purpose registers and vector table.
Page 37: Memory Map
CHAPTER 3 CPU I Memory map Figure 3.1-1 Memory map MB89951A MB89953A MB89P955 MB89PV950 0000 0000 0000 0000 0080 0080 0080 0080 Reserved 00C0 0100 0100 0100 0100 Registers Registers Registers Registers 0140 0180 0200 0200 0280 0480 Access Access Access prohibited prohibited...
Page 38: Special Areas
CHAPTER 3 CPU 3.1.1 Special Areas In addition to the I/O area, the special purpose areas in the memory space include the general-purpose register area and the vector table area. I General-purpose register areas (addresses: 0100 to 01FF • Provides auxiliary registers for 8-bit arithmetic operation and transfer instructions. •...
Page 39 CHAPTER 3 CPU I Vector table area (addresses: FFC0 to FFFF • Used as the vector table for the vector call instruction, interrupts, and resets. • The vector table is allocated at the top of the ROM area. The start address of the corresponding processing routine is set as data at each vector table address.
Page 40: Storing 16-Bit Data In Memory
CHAPTER 3 CPU 3.1.2 Storing 16-bit Data in Memory For 16-bit data and the stack, store the upper data in the lower memory address value. I Storing 16-bit data in RAM When writing 16-bit data to memory, store the upper byte at the lower address and the lower byte at the next address.
Page 41: Dedicated Registers
CHAPTER 3 CPU Dedicated Registers The dedicated registers in the CPU consist of the program counter (PC), two arithmetic operation registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS). All registers are 16 bits. I Dedicated register configuration The dedicated registers in the CPU consist of seven 16-bit registers.
Page 42 CHAPTER 3 CPU Temporary accumulator (T) The temporary accumulator is an auxiliary 16-bit arithmetic operation register used to perform arithmetic operations with the data in the accumulator (A). The content of the temporary accumulator is treated as word data (16-bit) for word-length arithmetic operations with the accumulator and as byte data (8-bit) for byte-length arithmetic operations.
Page 43: Condition Code Register (Ccr)
CHAPTER 3 CPU 3.2.1 Condition Code Register (CCR) The condition code register (CCR) located in the lower 8 bits of the program status (PS) consists of the C, V, Z, N, and H bits indicating the results of arithmetic operations and the contents of transfer data, and the I, IL1, and IL0 bits for control whether or not the CPU accepts interrupt requests.
Page 44: Interrupt Acceptance Control Bit
CHAPTER 3 CPU Carry flag (C) Set to "1" when a carry from bit 7 or borrow to bit 7 occurs as a result of an arithmetic operation. Clear to "0" otherwise. Set to the shift-out value in case of a shift instruction. Figure 3.2-3 "Change of carry flag by shift instruction"...
Page 45 CHAPTER 3 CPU Reference: The interrupt level bits (IL1, IL0) are normally "11 " when the CPU is not processing an interrupt (during main program execution). See Section 3.4 "Interrupts" for details on interrupts.
Page 46: Register Bank Pointer (Rp)
CHAPTER 3 CPU 3.2.2 Register Bank Pointer (RP) The register bank pointer (RP) located in the upper 8 bits of the program status (PS) indicates the address of the general-purpose register bank currently in use. The RP is converted to form the actual address in general-purpose register addressing. I Structure of register bank pointer (RP) Figure 3.2-4 "Structure of register bank pointer"...
Page 47: General-Purpose Registers
CHAPTER 3 CPU General-purpose Registers The general-purpose registers are a memory block made up of banks, with 8 x 8-bit registers per bank. The register bank pointer (RP) is used to specify the register bank. The function permits the use of up to 32 banks, but the number of banks that can actually be used depends on how much RAM the device has.
Page 48 CHAPTER 3 CPU I Features of general-purpose registers General-purpose registers have the following features: • RAM can be accessed at high-speed using short instructions (general-purpose register addressing). • Registers are grouped in blocks in the form of register banks. This simplifies the process of saving register contents and dividing registers by function.
Page 49: Interrupts
CHAPTER 3 CPU Interrupts The MB89950/950A series has 12 interrupt request inputs corresponding to peripheral functions. The interrupt level can be set independently. If an interrupt request output is enabled in the peripheral function, an interrupt request from a peripheral function is compared with the interrupt level in the interrupt controller.
Page 50: Interrupt Level Setting Registers (Ilr1, Ilr2, Ilr3)
CHAPTER 3 CPU 3.4.1 Interrupt Level Setting Registers (ILR1, ILR2, ILR3) The interrupt level setting registers (ILR1, ILR2, ILR3) together contain 12 blocks of 2-bit data, with each data corresponding to an interrupt request from a peripheral function. The interrupt level for each interrupt is set in that interrupt’s corresponding 2-bit data (interrupt level setting bits).
Page 51: Interrupt Processing
CHAPTER 3 CPU 3.4.2 Interrupt Processing The interrupt controller transmits the interrupt level to the CPU when an interrupt request is generated by a peripheral function. If the CPU is able to receive the interrupt, the CPU temporarily halts the currently executing program and executes the interrupt processing routine.
Page 52 CHAPTER 3 CPU 1. After a reset, all interrupt requests are disabled. - Initialize the peripheral functions that are to generate interrupts in the peripheral function initialization program, set the interrupt levels in the appropriate interrupt level setting registers (ILR1, ILR2, ILR3), and start peripheral function.
Page 53: Multiple Interrupts
CHAPTER 3 CPU 3.4.3 Multiple Interrupts Multiple interrupts can be performed by setting different interrupt levels to the interrupt level setting register for two or more interrupt requests from peripheral functions. I Multiple interrupts If the interrupt request having the higher interrupt levels occurs during the interrupt processing routines, the CPU halts the current interrupt process and switches to accept the interrupt with the higher priority.
Page 54: Interrupt Processing Time
CHAPTER 3 CPU 3.4.4 Interrupt Processing Time The total time from the generation of an interrupt request until control passes to the interrupt processing routine is the sum of the time required to complete execution of the current instruction and the interrupt handling time (the time required to prepare for interrupt processing).
Page 55: Stack Operation During Interrupt Processing
CHAPTER 3 CPU 3.4.5 Stack Operation during Interrupt Processing This section describes the saving of the register contents to the stack and restore operation during interrupt processing. I Stack operation at start of interrupt processing The CPU automatically saves the current contents of the program counter (PC) and program status (PS) to the stack when an interrupt is accepted.
Page 56: Stack Area For Interrupt Processing
CHAPTER 3 CPU 3.4.6 Stack Area for Interrupt Processing Interrupt processing execution uses the stack area in RAM. The contents of the stack pointer (SP) specifies the top address of the stack area. I Stack area for interrupt processing The subroutine call instruction (CALL) and vector call instruction (CALLV) use the stack area to save and restore the program counter (PC).
Page 57: Resets
CHAPTER 3 CPU Resets The MB89950/950A series supports the following four types of reset source: • External reset • Software reset • Watchdog reset • Power-on reset (optional) At reset, main clock oscillation stabilization delay time may or may not occur by the operating mode and option settings.
Page 58 CHAPTER 3 CPU Power-on reset Products can be set to with or without power-on reset (optional). On products with power-on reset, turning on the power generates a reset. The reset operation is performed after the oscillation stabilization delay time has passed. Moreover, external reset signal is outputted by the reset output option. On products without power-on reset, an external reset circuit is required to generate a reset when the power is turned on.
Page 59: External Reset Pin
CHAPTER 3 CPU 3.5.1 External Reset Pin Inputting an "L" level to the external reset pin generates a reset. If products are set to with the reset output (optional), the pin outputs an "L" level depending on internal reset sources. I Block diagram of external reset pin The external reset pin (RST) on products with the reset output is a hysteresis input type and N-ch open- drain output type with a pull-up resistor.
Page 60: Reset Operation
CHAPTER 3 CPU 3.5.2 Reset Operation When the CPU wakes up from a reset, the CPU selects the read address of the mode data and reset vector according to the mode pin settings, then performs a mode fetch. The mode fetch is performed after the oscillation stabilization delay time has passed when power is turned on to a product with power-on reset, or on wake-up from stop mode by a reset.
Page 61: Mode Pin
CHAPTER 3 CPU I Mode pin The MB89950/950A series devices are single-chip mode devices. The mode pin (MODA) must be tied to . The mode pin settings determine whether the mode data and reset vector are read from internal ROM. Do not change the mode pin settings, even after the reset has completed.
Page 62: Pin States During Reset
CHAPTER 3 CPU 3.5.3 Pin States during Reset Reset initializes the pin states. I Pin states during reset When a reset source occurs, with a few exceptions, all I/O pins (peripheral pins) go to the high-impedance state and the mode data is read from internal ROM (pins with a pull-up resistor (optional) go to the "H" level).
Page 63: Clocks
CHAPTER 3 CPU Clocks The clock generator provides an internal oscillation circuit. By connecting with external resonator, the circuits generate the high speed main clock sources. Alternatively, externally generated clock input can be used. Clock controller controls the speed and supply of the clock signal according to the standby mode.
Page 64 CHAPTER 3 CPU Figure 3.6-1 Clock supply map Peripheral functions Main clock Timebase timer Divide-by-two Watchdog timer oscillator 8-bit PWC timer Clock controller Clock mode Stop mode 8-bit PWM timer Divide-by-four UART Sleep/stop mode Serial I/O oscillation stabilization delay Supply to the CPU inst LCD controller/driver Free-run counter...
Page 65: Clock Generator
CHAPTER 3 CPU 3.6.1 Clock Generator Enable and stop of the main clock oscillation are controlled by clock and stop mode respectively. I Clock generator Crystal or ceramic resonator Connect as shown in Figure 3.6-2 "Connection example for a crystal or ceramic resonator". Figure 3.6-2 Connection example for a crystal or ceramic resonator MB89950/950A series Main clock...
Page 66 CHAPTER 3 CPU External clock Connect the external clock to the X0 pin and leave X1 pin open, as shown in Figure 3.6-3 "Connection example for external clock". Figure 3.6-3 Connection example for external clock MB89950/950A series Main clock oscillator Open...
Page 67: Clock Controller
CHAPTER 3 CPU 3.6.2 Clock Controller The clock controller contains the following four blocks: • Main clock oscillator • Clock controller • Oscillation stabilization delay time selector • Standby control register (STBC) I Block diagram of clock controller Figure 3.6-4 "Block diagram of clock controller" shows the block diagram of the clock controller. Figure 3.6-4 Block diagram of clock controller STBC STP SLP SPL RST —...
Page 68 CHAPTER 3 CPU Clock controller This circuit controls the supply of operating clocks to the CPU and peripheral circuits, selecting the clock based on the active mode: normal (RUN), or standby (sleep/stop) mode. Supply of the clock to the CPU is stopped until the clock supply stop signal in the oscillation stabilization delay time selector is released.
Page 69: Oscillation Stabilization Delay Time
CHAPTER 3 CPU 3.6.3 Oscillation Stabilization Delay Time When the system goes to run mode from a state in which the main clock is stopped (such as at power-on, and in stop mode and etc.), a delay time is required for oscillation to stabilize before starting any operation.
Page 70 CHAPTER 3 CPU Oscillation stabilization delay time at reset The oscillation stabilization delay time at reset (the initial values of WT1 and WT0) is selected as an option setting. Products with power-on reset require an oscillation stabilization delay time when exit from stop mode is triggered by resets in power-on reset, or external reset.
Page 71: Standby Mode (Low-Power Consumption)
CHAPTER 3 CPU Standby Mode (Low-power Consumption) The standby mode consists of sleep mode and stop mode. Main run mode is switched to sleep mode or stop mode by setting the standby control register (STBC). Standby mode reduces the power consumption by stopping the operation of the CPU and peripheral functions.
Page 72: Operating States In Standby Mode
CHAPTER 3 CPU 3.7.1 Operating States in Standby Mode This section describes the operating states of the CPU and peripheral functions in standby mode. I Operating states during standby mode Table 3.7-1 Operating states of the CPU and peripheral functions in standby mode Main clock mode Function Stop...
Page 73: Sleep Mode
CHAPTER 3 CPU 3.7.2 Sleep Mode This section describes the operations of sleep mode. I Operation of sleep mode Entering sleep mode Sleep mode stops the CPU operating clock. The CPU stops while maintaining all register contents, RAM contents, and pin states at their values immediately prior to entering sleep mode. However, peripheral functions except the watchdog timer continue to operate.
Page 74: Stop Mode
CHAPTER 3 CPU 3.7.3 Stop Mode This section describes the operations of stop mode. I Operation of stop mode Entering stop mode Stop mode stops the oscillation source. Almost all functions stop while maintaining all register and RAM contents at their value immediately before entering stop mode. Writing "1"...
Page 75: Standby Control Register (Stbc)
CHAPTER 3 CPU 3.7.4 Standby Control Register (STBC) The standby control register (STBC) controls the CPU to enter to sleep mode, stop mode, sets the pin states in stop mode, and initiates software reset. I Standby control register (STBC) Figure 3.7-1 Standby control register (STBC) Address Bit 7 Bit 6...
Page 76 CHAPTER 3 CPU Table 3.7-2 Standby control register (STBC) bits Function Bit 7 STP: • Sets the CPU entering stop mode. Stop bit • Writing "1" to this bit sets the CPU entering stop mode. • Writing "0" to this bit has no effect on operation. •...
Page 77: State Transition Diagram
CHAPTER 3 CPU 3.7.5 State Transition Diagram This section shows two state transition diagrams: one diagram for "with power-on reset" option products and the other for "without power-on reset" products. I State transition diagrams Figure 3.7-2 State transition diagram (products with power-on reset) Power-on Power-on reset Oscillation stabilization...
Page 78 CHAPTER 3 CPU Go to normal state (RUN) and reset Table 3.7-3 Go to main clock mode run state and reset Conditions/events required for transition State transition Products with power-on reset Products without power-on reset (Figure 3.7-2 ) (Figure 3.7-3 ) Go to normal state [1] Main clock oscillation stabilization delay [1] External reset input must be held asserted...
Page 79: Notes On Using Standby Mode
CHAPTER 3 CPU 3.7.6 Notes on Using Standby Mode The CPU does not go to standby mode if an interrupt request occurs from a peripheral function when a standby mode bit is set in the standby control register (STBC). Also, if an interrupt is used to wake up from a standby mode to the normal operating state, the operation after wake-up differs depending on whether or not the interrupt request is accepted.
Page 80 CHAPTER 3 CPU I Oscillation stabilization delay time As the oscillator that provides the oscillation source is stopped during stop mode, a delay time is required for oscillation to stabilize after the oscillator restarts operation. In main clock mode, the main clock oscillation stabilization delay time is selected from one of two possible delay times defined by the timebase timer.
Page 81: Memory Access Mode
CHAPTER 3 CPU Memory Access Mode In the MB89950/950A series, the only memory access mode is the single-chip mode. I Single-chip mode In single-chip mode, the device uses internal RAM and ROM only. Therefore, the CPU can access no areas other than the internal I/O area, RAM area, and ROM area (internal access).
Page 82: Memory Access Mode Selection Operation
CHAPTER 3 CPU I Memory access mode selection operation Only the single-chip mode can be selected. Table 3.8-2 "Mode pin and mode data" lists the mode pin and mode data options. Table 3.8-2 Mode pins and mode data Memory access mode Mode pin (MODA) Mode data Single-chip mode...
Page 83: Chapter 4 I/O Ports
CHAPTER 4 I/O PORTS This chapter describes the functions and operation of the I/O ports. 4.1 "Overview of I/O Ports" 4.2 "Port 0" 4.3 "Port 1" 4.4 "Port 2" 4.5 "Port 3" 4.6 "Port 4" 4.7 "Program Example for I/O Ports"...
Page 84: Overview Of I/O Ports
CHAPTER 4 I/O PORTS Overview of I/O Ports The I/O ports consist of five ports (33 pins) including N-ch open-drain and CMOS general-purpose I/O ports (parallel I/O ports). The ports also serve as peripherals (I/O pins of peripheral functions). I I/O port functions The functions of the I/O ports are to output data from the CPU via the I/O pins and to fetch signals input to the I/O pins into the CPU.
Page 85 CHAPTER 4 I/O PORTS Table 4.1-2 Port registers Register Read/Write Address Initial value Port 0 data register (PDR0) 0000 11111111 Port 1 data register (PDR1) 0002 11111111 Port 2 data register (PDR2) 0004 --111111 Port 3 data register (PDR3) 000C ----1111 Port 4 data register (PDR4) 000E...
Page 86: Port 0
CHAPTER 4 I/O PORTS Port 0 Port 0 is N-ch open-drain I/O port that also serves as LCD segment driver outputs. Port 0 pins can be switched between LCD segment driver output and port operation by mask option. This section principally describes the port functions when operating as N-ch open-drain I/O port.
Page 87: Port 0 Register
CHAPTER 4 I/O PORTS I Block diagram of port 0 pins Figure 4.2-1 Block diagram of port 0 pins Mask option LCD segment driver output Segment driver output select register PDR (Port data register) Stop mode (SPL = 1) PDR read PDR read (for bit manipulation instructions) Output latch PDR write...
Page 88: Port 0 Data Register (Pdr0)
CHAPTER 4 I/O PORTS 4.2.1 Port 0 Data Register (PDR0) This section describes the port 0 data register. I Port 0 data register functions Port 0 data register (PDR0) The PDR0 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0"...
Page 89: Operation Of Port 0
CHAPTER 4 I/O PORTS 4.2.2 Operation of Port 0 This section describes the operations of the port 0. I Operation of port 0 Operation as an output port • When the output latch value is "0", the output transistor turns "ON" and an "L" level is output from the pin.
Page 90 CHAPTER 4 I/O PORTS Operation in stop mode • The output transistors are forcibly turned "OFF" regardless of the PRD0 register value and the pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC: SPL) is "1"...
Page 91: Port 1
CHAPTER 4 I/O PORTS Port 1 Port 1 is N-ch open-drain I/O port that also serves as LCD segment driver outputs. Port 1 pins can be switched between LCD segment driver output and port operation by mask option. This section principally describes the port functions when operating as N-ch open-drain I/O port.
Page 92: Port 1 Register
CHAPTER 4 I/O PORTS I Block diagram of port 1 pins Figure 4.3-1 Block diagram of port 1 pins Mask option LCD segment driver output Segment driver output select register PDR (Port data register) Stop mode (SPL = 1) PDR read PDR read (for bit manipulation instructions) Output latch PDR write...
Page 93: Port 1 Data Register (Pdr1)
CHAPTER 4 I/O PORTS 4.3.1 Port 1 Data Register (PDR1) This section describes the port 1 data register. I Port 1 data register functions Port 1 data register (PDR1) The PDR1 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0"...
Page 94: Operation Of Port 1
CHAPTER 4 I/O PORTS 4.3.2 Operation of Port 1 This section describes the operations of the port 1. I Operation of port 1 Operation as an output port • When the output latch value is "0", the output transistor turns "ON" and an "L" level is output from the pin.
Page 95 CHAPTER 4 I/O PORTS Operation in stop mode • The output transistors are forcibly turned "OFF" regardless of the PRD0 register value and the pins go to the high-impedance state if the pin state specification bit in the standby control register (STBC: SPL) is "1"...
Page 96: Port 2
CHAPTER 4 I/O PORTS Port 2 Port 2 is N-ch open-drain I/O port that also serves as LCD segment driver outputs. Port 2 pins can be switched between LCD segment driver output and port operation by mask option. This section principally describes the port functions when operating as N-ch open-drain I/O port.
Page 97: Port 2 Register
CHAPTER 4 I/O PORTS I Block diagram of port 2 pins Figure 4.4-1 Block diagram of port 2 pins Mask option LCD segment driver output Segment driver output select register PDR (Port data register) Stop mode (SPL = 1) PDR read PDR read (for bit manipulation instructions) Output latch PDR write...
Page 98: Port 2 Data Register (Pdr2)
CHAPTER 4 I/O PORTS 4.4.1 Port 2 Data Register (PDR2) This section describes the port 2 data register. I Port 2 data register functions Port 2 data register (PDR2) The PDR2 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0"...
Page 99: Operation Of Port 2
CHAPTER 4 I/O PORTS 4.4.2 Operation of Port 2 This section describes the operations of the port 2. I Operation of port 2 Operation as an output port • Writing data to the PDR2 register stores the data in the output latch. When the output latch value is "0", the output transistor turns "ON"...
Page 100: Port 3
CHAPTER 4 I/O PORTS Port 3 Port 3 is N-ch open-drain I/O port. Two of them also serve as LCD bias input. Port 3 pins can be switched between LCD bias input and port operation. This section principally describes the port functions when operating as N-ch open-drain I/O port. The section describes the port structure and pins, the pin block diagram, and the port register for port 3.
Page 101 CHAPTER 4 I/O PORTS I Block diagram of port 3 pins Figure 4.5-1 Block diagram of port 3 pins (P30 and P31) PDR (Port data register) Stop mode (SPL = 1) PDR read PDR read (for bit manipulation instructions) Output latch PDR write N-ch Stop mode (SPL = 1)
Page 102: Port 3 Register
CHAPTER 4 I/O PORTS I Port 3 register The port 3 register consists of PDR3. Each bit in the register has a one-to-one relationship with a port 3 pin. Table 4.5-2 "Correspondence between pin and register for port 3" shows the correspondence between the pins and register for port 3.
Page 103: Port 3 Data Register (Pdr3)
CHAPTER 4 I/O PORTS 4.5.1 Port 3 Data Register (PDR3) This section describes the port 3 data register. I Port 3 data register functions Port 3 data register (PDR3) The PDR3 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be read as the same state ("0"...
Page 104: Operation Of Port 3
CHAPTER 4 I/O PORTS 4.5.2 Operation of Port 3 This section describes the operations of the port 3. I Operation of port 3 Operation as an output port • Writing data to the PDR3 register stores the data in the output latch. When the output latch value is "0", the output transistor turns "ON"...
Page 105 CHAPTER 4 I/O PORTS Table 4.5-4 Port 3 pin state Normal operation Pin name sleep mode Stop mode (SPL = "1") Reset stop mode (SPL = "0") P30 to P33/V2 General-purpose I/O ports/bias input Hi-Z Hi-Z SPL: Pin state specification bit in the standby control register (STBC) Hi-Z: High impedance...
Page 106: Port 4
CHAPTER 4 I/O PORTS Port 4 Port 4 is a general-purpose I/O port that also serves as the peripheral signal I/O pins. Individual pin can be switched between the port and resource function. This section principally describes the port functions when operating as a general-purpose I/O port. The section describes the port structure and pins, the pin block diagram, and the port registers for port 4.
Page 107: Port 4 Registers
CHAPTER 4 I/O PORTS I Block diagram of port 4 pins Figure 4.6-1 Block diagram of port 4 pins External interrupt enable To external interrupt To peripheral input PDR (Port data register) Pull-up resistor Stop mode (SPL = 1) Approx. 50 k (Mask option) PDR read Peripheral output...
Page 108: Port 4 Registers (Pdr4, Ddr4)
CHAPTER 4 I/O PORTS 4.6.1 Port 4 Registers (PDR4, DDR4) This section describes the port 4 registers. I Port 4 register functions Port 4 data register (PDR4) The PDR4 register holds the pin states. Therefore, when used as an output port that is not a peripheral output, it reads out as the same state ("0"...
Page 109 CHAPTER 4 I/O PORTS Table 4.6-3 Port 4 PDR and DDR register function Read/ Register Data Read Write Address Initial value Write Outputs an "L" level to the pin if the pin functions as an output Pin state is the port.
Page 110: Operation Of Port 4
CHAPTER 4 I/O PORTS 4.6.2 Operation of Port 4 This section describes the operations of the port 4. I Operation of port 4 Operation as an output port • Setting the corresponding DDR4 register bit to "1" sets a pin as an output port. •...
Page 111 CHAPTER 4 I/O PORTS Operation in stop mode • The pins go to the high-impedance state, if the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device goes to stop mode. This is achieved by forcibly setting the output transistor "OFF"...
Page 112: Program Example For I/O Ports
CHAPTER 4 I/O PORTS Program Example for I/O Ports This section gives an example program for using the I/O ports. I Program example for I/O ports Processing description • Port 0 and port 1 are used to illuminate all elements of seven segment LED (eight segments if the decimal point is included).
Page 113: Chapter 5 Timebase Timer
CHAPTER 5 TIMEBASE TIMER This chapter describes the functions and operation of the timebase timer. 5.1 "Overview of Timebase Timer" 5.2 "Block Diagram of Timebase Timer" 5.3 "Timebase Timer Control Register (TBTC)" 5.4 "Timebase Timer Interrupt" 5.5 "Operation of Timebase Timer" 5.6 "Notes on Using Timebase Timer"...
Page 114: Overview Of Timebase Timer
CHAPTER 5 TIMEBASE TIMER Overview of Timebase Timer The timebase timer provides interval timer functions. Four different interval times can be selected. The timebase timer uses a 20-bit free-run counter which counts up in synchronous with the internal count clock (divide-by-two the main clock oscillation frequency).
Page 115 CHAPTER 5 TIMEBASE TIMER I Clock supply function The clock supply function provides the timer output used for the main clock oscillation stabilization delay time (two values), and operation clock for some peripheral functions. Table 5.1-2 "Clocks supplied by timebase timer" lists the cycles of the clocks that the timebase timer supplies to various peripherals.
Page 116: Block Diagram Of Timebase Timer
CHAPTER 5 TIMEBASE TIMER Block Diagram of Timebase Timer The timebase timer consists of the following four blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) I Block diagram of timebase timer Figure 5.2-1 Block diagram of timebase timer To PWC To watchdog timer...
Page 117 CHAPTER 5 TIMEBASE TIMER TBTC register The TBTC register is used to select the interval timer bit, clear the counter, control interrupts, and check the state of the timebase timer.
Page 118: Timebase Timer Control Register (Tbtc)
CHAPTER 5 TIMEBASE TIMER Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) is used to select the interval times bit, clear the counter, control interrupts, and check the state of the timebase timer. I Timebase timer control register (TBTC) Figure 5.3-1 Timebase timer control register (TBTC) Address Bit 7...
Page 119 CHAPTER 5 TIMEBASE TIMER Table 5.3-1 Timebase timer control register (TBTC) bits Function Bit 7 Unused bits • The read value is indeterminate. Bit 6 • Writing to these bits has no effect on the operation. Bit 5 Bit 4 TBIF: •...
Page 120: Timebase Timer Interrupt
CHAPTER 5 TIMEBASE TIMER Timebase Timer Interrupt The timebase timer can generate an interrupt request when an overflow occurs on the specified bit of the timebase counter (for the interval timer function). I Interrupts for interval timer function The counter counts up on the internal count clock. When an overflow occurs on the selected interval timer bit, the overflow interrupt request flag bit (TBTC: TBIF) is set to "1".
Page 121: Operation Of Timebase Timer
CHAPTER 5 TIMEBASE TIMER Operation of Timebase Timer The timebase timer has the interval timer function and the clock supply function for some peripherals. I Operation of interval timer function (timebase timer) Figure 5.5-1 "Interval timer function settings" shows the settings required to operate the interval timer function.
Page 122 CHAPTER 5 TIMEBASE TIMER I Operation of timebase timer The state of following operations are shown in Figure 5.5-2 "Operation of timebase timer". • A power-on reset occurs. • Goes to sleep mode during operation of the interval timer function in the main clock mode. •...
Page 123: Notes On Using Timebase Timer
CHAPTER 5 TIMEBASE TIMER Notes on Using Timebase Timer This section lists points to note when using the timebase timer. I Notes on using timebase timer Notes on setting bits by program The system cannot recover from interrupt processing if the overflow interrupt request flag bit (TBTC: TBIF) is "1"...
Page 124: Program Example For Timebase Timer
CHAPTER 5 TIMEBASE TIMER Program Example for Timebase Timer This section gives a program example for the timebase timer. I Program example for timebase timer Processing description • Generates repeated interval timer interrupts at 2 : Main clock oscillation frequency) intervals.
Page 125: Chapter 6 Watchdog Timer
CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer. 6.1 "Overview of Watchdog Timer" 6.2 "Block Diagram of Watchdog Timer" 6.3 "Watchdog Timer Control Register (WDTC)" 6.4 "Operation of Watchdog Timer" 6.5 "Notes on Using Watchdog Timer" 6.6 "Program Example for Watchdog Timer"...
Page 126: Overview Of Watchdog Timer
CHAPTER 6 WATCHDOG TIMER Overview of Watchdog Timer The watchdog timer is a 2-bit counter that uses, as its count clock source, the timebase timer derived from the main clock. The watchdog timer resets the CPU if not cleared within a fixed time after activation. I Watchdog timer function The watchdog timer is a counter provided to guard against program runaway.
Page 127: Block Diagram Of Watchdog Timer
CHAPTER 6 WATCHDOG TIMER Block Diagram of Watchdog Timer The watchdog timer consists of the following four blocks: • Watchdog timer counter • Reset controller • Counter clear controller • Watchdog timer control register (WDTC) I Block diagram of watchdog timer Figure 6.2-1 Block diagram of watchdog timer WDTC register —...
Page 128 CHAPTER 6 WATCHDOG TIMER WDTC register The WDTC register is used to select the count clock, and to activate or clear the watchdog timer counter. As the register is write-only, the bit manipulation instructions cannot be used.
Page 129: Watchdog Timer Control Register (Wdtc)
CHAPTER 6 WATCHDOG TIMER Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) is used to activate or clear the watchdog timer. I Watchdog timer control register (WDTC) Figure 6.3-1 Watchdog timer control register (WDTC) Address Bit 7 Bit 6 Bit 5 Bit 4...
Page 130: Operation Of Watchdog Timer
CHAPTER 6 WATCHDOG TIMER Operation of Watchdog Timer The watchdog timer generates a watchdog reset when the watchdog timer counter overflows. I Operation of watchdog timer Activating watchdog timer The watchdog timer is activated by writing "0101 " to the watchdog control bits in the watchdog control register (WDTC: WTE3 to WTE0) for the first time after a reset.
Page 131 CHAPTER 6 WATCHDOG TIMER Figure 6.4-1 Watchdog timer clear and interval time Minimum time 419.43 ms Count clock output of the timebase timer Overflow Watchdog clear 1-bit watchdog counter Watchdog reset Maximum time 838.86 ms Count clock output of the timebase timer Overflow Watchdog clear 1-bit watchdog...
Page 132: Notes On Using Watchdog Timer
CHAPTER 6 WATCHDOG TIMER Notes on Using Watchdog Timer This section lists points to note when using the watchdog timer. I Notes on using watchdog timer Stopping watchdog timer Once activated, the watchdog timer cannot stop until a reset generates. Clearing watchdog timer Clearing the counter being used as a count clock of the watchdog timer (timebase timer or watch prescaler) also simultaneously clears the watchdog timer counter.
Page 133: Program Example For Watchdog Timer
CHAPTER 6 WATCHDOG TIMER Program Example for Watchdog Timer This section gives a program example for the watchdog timer. I Program example for watchdog timer Processing description Activates the watchdog timer immediately after the program. Clears the watchdog timer in each loop of the main program. The processing time for the main loop, including interrupt processing, must be less than the minimum interval time of the watchdog timer (approximately 419.43 ms at 5 MHz operation).
Page 134 CHAPTER 6 WATCHDOG TIMER...
Page 135: 8-Bit Pwm Timer
CHAPTER 7 8-BIT PWM TIMER This chapter describes the functions and operation of the 8-bit PWM timer. 7.1 "Overview of 8-bit PWM Timer" 7.2 "Block Diagram of 8-bit PWM Timer" 7.3 "Structure of 8-bit PWM Timer" 7.4 "8-bit PWM Timer Interrupts" 7.5 "Operation of Interval Timer Function"...
Page 136: Overview Of 8-Bit Pwm Timer
CHAPTER 7 8-BIT PWM TIMER Overview of 8-bit PWM Timer The 8-bit PWM timer can be selected to function as either an interval timer or PWM timer with 8-bit resolution. The interval timer function counts up in synchronous with PWC output clock or one of three internal count clocks.
Page 137: Pwm Timer Function
CHAPTER 7 8-BIT PWM TIMER I PWM timer function The PWM timer function has 8-bit resolution and can control the "H" and "L" width of one cycle. • As the resolution is 1/256, pulses can be output with duty ratio of between 0 and 99.6%. •...
Page 138: Block Diagram Of 8-Bit Pwm Timer
CHAPTER 7 8-BIT PWM TIMER Block Diagram of 8-bit PWM Timer The 8-bit PWM timer consists of the following six blocks: • Count clock selector • 8-bit counter • Comparator circuit • PWM generator and output controller • PWM compare register (COMR) •...
Page 139 CHAPTER 7 8-BIT PWM TIMER Count clock selector Selects a count-up clock for the 8-bit counter from the three internal count clocks and the PWC timer output cycle. 8-bit counter The 8-bit counter counts up on the count clock selected by the count clock selector. Comparator circuit The comparator circuit has a latch to hold the COMR register value.
Page 140: Structure Of 8-Bit Pwm Timer
CHAPTER 7 8-BIT PWM TIMER Structure of 8-bit PWM Timer This section describes the pin, pin block diagram, register source, and interrupts of the 8-bit PWM timer. I 8-bit PWM timer pin The 8-bit PWM timer uses the P41/PWM pin. This pin can function as a CMOS general-purpose I/O port (P41), or as the interval timer or PWM timer output (PWM).
Page 141 CHAPTER 7 8-BIT PWM TIMER I 8-bit PWM timer registers Figure 7.3-2 8-bit PWM timer registers CNTR (PWM control register) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0012 0-000000 COMR (PWM compare register) Address...
Page 142: Pwm Control Register (Cntr)
CHAPTER 7 8-BIT PWM TIMER 7.3.1 PWM Control Register (CNTR) The PWM control register (CNTR) is used to select the operating mode of the 8-bit PWM timer (interval timer operation or PWM timer operation), enable or disable operation, select the count clock, control interrupts, and check the state of the 8-bit PWM timer. I PWM control register (CNTR) Figure 7.3-3 PWM control register (CNTR) Address...
Page 143 CHAPTER 7 8-BIT PWM TIMER Table 7.3-1 PWM control register (CNTR) bits Function Bit 7 P/T: • This bit switches between the interval timer function (P/T = "0") and PWM timer Operating mode function (P/T = "1"). selection bit Note: Write to this bit when the counter operation is stopped (TPE = "0"), interrupts are disabled (TIE = "0"), and the interrupt request flag bit is cleared (TIR = "0").
Page 144: Pwm Compare Register (Comr)
CHAPTER 7 8-BIT PWM TIMER 7.3.2 PWM Compare Register (COMR) The PWM compare register (COMR) sets the interval time for the interval timer function. The register value sets the "H" width of the pulse for the PWM timer function. I PWM compare register (COMR) Figure 7.3-4 "PWM compare register (COMR)"...
Page 145: 8-Bit Pwm Timer Interrupts
CHAPTER 7 8-BIT PWM TIMER 8-bit PWM Timer Interrupts The 8-bit PWM timer can generate an interrupt request when a match is detected between the counter value and PWM compare register value for the interval timer function. Interrupt requests are not generated for the PWM timer function. 8-bit PWM timer generates the IRQ2 as an interrupt request.
Page 146: Operation Of Interval Timer Function
CHAPTER 7 8-BIT PWM TIMER Operation of Interval Timer Function This section describes the operation of the interval timer function of the 8-bit PWM timer. I Operation of interval timer function Figure 7.5-1 "Interval timer function settings" shows the settings required to operate as an interval timer function.
Page 147 CHAPTER 7 8-BIT PWM TIMER Note: Do not change the count clock cycle (CNTR: P1, P0) during operation of the interval timer function (CNTR: TPE = "1"). References: • Setting the COMR register value to "00 " causes the PWM pin output to be inverted with the cycle of the selected count clock.
Page 148: Operation Of Pwm Timer Function
CHAPTER 7 8-BIT PWM TIMER Operation of PWM Timer Function This section describes the operation of the PWM timer function of the 8-bit PWM timer. I Operation of PWM timer function Figure 7.6-1 "PWM timer function settings" shows the settings required to operate as the PWM timer function.
Page 149: States In Each Mode During 8-Bit Pwm Timer Operation
CHAPTER 7 8-BIT PWM TIMER States in Each Mode during 8-bit PWM Timer Operation This section describes the operation of the 8-bit PWM timer when the device goes to sleep or stop mode, or an operation halt request occurs during operation. I Operation during standby mode or operation halt Figure 7.7-1 "Counter operation during standby mode or operation halt (for interval timer function)"...
Page 150 CHAPTER 7 8-BIT PWM TIMER For PWM timer function Figure 7.7-2 Operation during standby mode or operation halt (for PWM timer function) PWM pin (PWM waveform) Maintains the level prior to halting. TPE bit Operation halts Operation restarts Sleep mode SLP bit (STBC register) Wake-up from sleep mode by an interrupt other than IRQ2 (IRQ2 is not generated).
Page 151: Notes On Using 8-Bit Pwm Timer
CHAPTER 7 8-BIT PWM TIMER Notes on Using 8-bit PWM Timer This section lists points to note when using the 8-bit PWM timer. I Notes on using 8-bit PWM timer Error Activating the counter by program is not synchronized with the start of counting-up using the selected count clock.
Page 152: Program Example For 8-Bit Pwm Timer
CHAPTER 7 8-BIT PWM TIMER Program Example for 8-bit PWM Timer This section gives program examples for the 8-bit PWM timer. I Program example for interval timer function Processing description • Generates repeated interval timer interrupts at 2.5 ms intervals. •...
Page 153 CHAPTER 7 8-BIT PWM TIMER Coding example CNTR 0012H ; Address of the PWM control register COMR 0013H ; Address of the PWM compare register CNTR:3 ; Define the counter operation enable bit. CNTR:2 ; Define the interrupt request flag bit. ILR1 007CH ;...
Page 154 CHAPTER 7 8-BIT PWM TIMER I Program example for PWM timer function Processing description • Generates a PWM wave with a duty ratio of 50%. Then, changes the duty ratio to 25%. • Does not generate interrupts. • For a 5 MHz main clock oscillation frequency (F ), selecting the interval 16 t count clock gives a inst...
Page 155: Pulse Width Count Timer (Pwc)
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) This chapter describes the functions and operation of the pulse width count timer (PWC). 8.1 "Overview of Pulse Width Count Timer" 8.2 "Block Diagram of Pulse Width Count Timer" 8.3 "Structure of Pulse Width Count Timer 8.4 "Pulse Width Count Timer Interrupts"...
Page 156: Overview Of Pulse Width Count Timer
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Overview of Pulse Width Count Timer The pulse width count timer (PWC) can be selected to function as either an interval timer or the pulse width measurement. The interval timer function counts down in synchronous with one of three internal count clocks.
Page 157: Pulse Width Measurement Function
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) I Pulse width measurement function The pulse width measurement function can measure the "H" width, "L" width, and one-cycle width of pulses input from an external pin (PWC pin). • The PWC can perform continuous pulse width measurement. •...
Page 158: Block Diagram Of Pulse Width Count Timer
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Block Diagram of Pulse Width Count Timer The pulse width count timer consists of the following nine blocks: • Count clock selector • 8-bit down counter • Input pulse edge detector • Noise filter circuit •...
Page 159 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Count clock selector Selects a count clock for the 8-bit down counter from the three available internal count clocks. 8-bit down counter The 8-bit down counter starts to count from the value set in the PWC reload buffer register (RLBR) when operating as an interval timer, and from FF when performing pulse width measurement.
Page 160: Structure Of Pulse Width Count Timer
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Structure of Pulse Width Count Timer This section describes the pins, pin block diagram, registers, and interrupt source of the pulse width count timer. I Pulse width count timer pin The pulse width count timer uses the P42/PWC/INT1 pin. This pin can function either as CMOS general- purpose I/O port (P42) or external interrupt (INT1), or as the measured pulse input (PWC).
Page 161: Pulse Width Count Timer Registers
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) I Pulse width count timer registers Figure 8.3-2 Pulse width count timer registers PCR1 (PWC pulse width control register 1) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value...
Page 162: Pwc Pulse Width Control Register 1 (Pcr1)
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.3.1 PWC Pulse Width Control Register 1 (PCR1) The PWC pulse width control register 1 (PCR1) is used to enable or disable functions, control interrupts and check the state of the pulse width count timer. I PWC pulse width control register 1 (PCR1) Figure 8.3-3 PWC pulse width control register 1 (PCR1) Address...
Page 163 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Table 8.3-1 PWC pulse width control register 1 (PCR1) bits Function Bit 7 • For the interval timer function: Counter operation Writing "1" to this bit starts the counter to count down from the PWC reload buffer register enable bit (RLBR) value.
Page 164: Pwc Pulse Width Control Register 2 (Pcr2)
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.3.2 PWC Pulse Width Control Register 2 (PCR2) The PWC pulse width control register 2 (PCR2) is used to select the operating mode (pulse width measurement or interval timer operation, etc.), select the count clock, set the measured pulse (measurement edges), and check the timer output state of the pulse width count timer.
Page 165 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Table 8.3-2 PWC pulse width control register 2 (PCR2) bits Function Bit 7 • This bit switches between the interval timer function (FC = "0") and pulse width Operating mode measurement function (FC = "1"). selection bit Note: When using the pulse width measurement function (FC = "1"), set the P42/PWC/INT1...
Page 166: Pwc Reload Buffer Register (Rlbr)
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.3.3 PWC Reload Buffer Register (RLBR) The PWC reload buffer register (RLBR) functions as a reload register for the interval timer function and as a measurement value storage register for the pulse width measurement function.
Page 167 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) For pulse width measurement function The register is used to store the pulse width measurement value. The counter value is transferred to this register when pulse width measurement completes on detection of the edge specified for measurement completion. At this time, the buffer full flag bit (PCR1: BF) and the measurement completion interrupt request flag bit (PCR1: IR) are set to "1".
Page 168: Pwc Noise Filter Control Register (Nccr)
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.3.4 PWC Noise Filter Control Register (NCCR) The PWC noise filter control register is used to select the sampling clock for the noise filter circuit. There are three type of selectable sampling clock from the timebase timer. I PWC noise filter control register (NCCR) Figure 8.3-6 PWC noise filter control register (NCCR) Address...
Page 169: Pulse Width Count Timer Interrupts
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Pulse Width Count Timer Interrupts The pulse width count timer has the following two interrupts: • Counter value underflow (01 --> 00 ) for the interval timer function • Measurement completion and buffer full for the pulse width measurement function I Interrupt for the interval timer function The counter counts down from the set value on the selected internal count clock.
Page 170: Operation Of Interval Timer Function
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Operation of Interval Timer Function This section describes the operation of the interval timer function of the pulse width count timer. I Operation of interval timer function The interval timer function can operate as a continuous timer (reload timer mode), or as a timer that operates for one timer-cycle and then stops (one-shot mode).
Page 171 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Figure 8.5-2 Operation in reload timer mode Counter value Reload Time Timer cycle RLBR value is modified* RLBR value Cleared by the program UF bit EN bit For an initial value of “0” TOE bit (TO bit) *: If the PWC reload buffer register (RLBR) value is modified during operation, the new value will be effective in next cycle.
Page 172 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Figure 8.5-4 Operation in one-shot timer mode Counter value Time Timer cycle RLBR value is modified (FF RLBR value Cleared by the program UF bit EN bit Reactivate Automatic clear Reactivate Automatic clear Automatic clear Invert TOE bit...
Page 173: Operation Of Pulse Width Measurement Function
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Operation of Pulse Width Measurement Function This section describes the operations of the pulse width measurement function of the pulse width count timer. I Operation of pulse width measurement function Figure 8.6-1 "Pulse width measurement function settings" shows the settings required to operate as the pulse width measurement function.
Page 174: Measuring Long Pulse Widths
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Figure 8.6-2 Example of "H" width measurement using pulse width measurement function "H" width Input pulse (Input waveform to the PWC pin) Counter value Time Cleared by the program EN bit Counter operation IR bit BF bit Data transferred from down...
Page 175 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Figure 8.6-3 Measuring long pulse width (falling edge to falling edge) One cycle Input pulse (Input waveform to the PWC pin) EN bit Counter value Software counter value Set "0" UF bit Cleared by the program Cleared by the program IR bit BF bit...
Page 176: Operation Of Noise Filter Circuit
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Operation of Noise Filter Circuit This section describes the operations of noise filter circuit function when the pulse width measurement function is selected. I Operation of noise filter circuit function Figure 8.7-1 "Noise filter circuit function settings" shows the settings required to operate as the noise filter circuit function.
Page 177: States In Each Mode During Pulse Width Count Timer Operation
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) States in Each Mode during Pulse Width Count Timer Operation This section describes the operation of the pulse width count timer when the device goes to sleep or stop mode, or an operation halt request occurs during operation. I Operation during standby mode or operation halt Figure 8.8-1 "Counter operation during standby mode or operation halt"...
Page 178: Notes On Using Pulse Width Count Timer
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Notes on Using Pulse Width Count Timer This section lists points to note when using the pulse width count timer. I Notes on using pulse width count timer Error When using the interval timer function, activating the counter by program is not synchronized with the start of counting-down using the selected internal count clock.
Page 179: Program Example For Timer Function Of Pulse Width Count Timer
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) 8.10 Program Example for Timer Function of Pulse Width Count Timer This section gives two program examples for the timer function of the pulse width count timer. I Program example 1 for interval timer function (reload timer mode) Processing description •...
Page 180 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Coding example PCR1 0014H ; Address of the PWC pulse width control register 1 PCR2 0015H ; Address of the PWC pulse width control register 2 RLBR 0016H ; Address of the PWC reload buffer register PCR1:7 ;...
Page 181 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) I Program example 2 for interval timer function (one-shot timer mode) Processing description • Generates a single 1.5 ms interval timer interrupt (one-shot timer mode). • The TO bit is initialized to "1" and inverted after the interval time. •...
Page 182 CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) Coding example PCR1 0014H ; Address of the PWC pulse width control register 1 PCR2 0015H ; Address of the PWC pulse width control register 2 RLBR 0016H ; Address of the PWC reload buffer register PCR1:7 ;...
Page 183: Chapter 9 8-Bit Serial I/O
CHAPTER 9 8-BIT SERIAL I/O This chapter describes the functions and operation of the 8-bit serial I/O. 9.1 "Overview of 8-bit Serial I/O" 9.2 "Block Diagram of 8-bit Serial I/O" 9.3 "Structure of 8-bit Serial I/O" 9.4 "8-bit Serial I/O Interrupts" 9.5 "Operation of Serial Output"...
Page 184: Overview Of 8-Bit Serial I/O
CHAPTER 9 8-BIT SERIAL I/O Overview of 8-bit Serial I/O The 8-bit serial I/O function is the serial transfer of 8-bit data, synchronized with the shift clock. The shift clock can be selected from one external and three internal clocks. The data shift direction can be selected as either LSB first or MSB first.
Page 185: Block Diagram Of 8-Bit Serial I/O
CHAPTER 9 8-BIT SERIAL I/O Block Diagram of 8-bit Serial I/O Each channel of the 8-bit serial I/O consists of the following four blocks: • Shift clock controller • Shift clock counter • Serial data register (SDR) • Serial mode register (SMR) I Block diagram of 8-bit serial I/O Figure 9.2-1 Block diagram of 8-bit serial I/O Internal data bus...
Page 186 CHAPTER 9 8-BIT SERIAL I/O Shift clock control circuit Selects the shift clock from one external and three internal clocks. If an internal shift clock is selected, the shift clock can be output to the SCK pin. If external shift clock is selected, the clock input from the SCK pin is used as the shift clock.
Page 187: Structure Of 8-Bit Serial I/O
CHAPTER 9 8-BIT SERIAL I/O Structure of 8-bit Serial I/O This section describes the pins, pin block diagram, registers, and interrupt source of 8- bit serial I/O. I 8-bit serial I/O pins 8-bit serial I/O uses the P43/SI, P44/SO, and P45/SCK. The pins are also used as UART I/O pins. To use the pins as serial I/O pins, set the UART/SIO selection bit RSEL of UART serial mode control register 2 (SMC2: RSEL = "1").
Page 188 CHAPTER 9 8-BIT SERIAL I/O I Block diagram of 8-bit serial I/O pins Figure 9.3-1 Block diagram of 8-bit serial I/O pin For P43/SI and P45/SCK To SIO input PDR (Port data register) Pull-up resistor Stop mode (SPL = 1) Approx.
Page 189 CHAPTER 9 8-BIT SERIAL I/O I 8-bit serial I/O interrupt source IRQ5: 8-bit serial I/O generates an interrupt request (IRQ5) if interrupt request output is enabled (SMR: SIOE = "1") when the I/O function completes input or output of 8-bit serial data.
Page 190: Serial Mode Register (Smr)
CHAPTER 9 8-BIT SERIAL I/O 9.3.1 Serial Mode Register (SMR) The serial mode register (SMR) is used to enable or disable operation, select the shift clock, set the transfer direction, control interrupts, and check the state of 8-bit serial I/O. I Serial mode register (SMR) Figure 9.3-3 Serial mode register (SMR) Address...
Page 191 CHAPTER 9 8-BIT SERIAL I/O Table 9.3-1 Serial mode register (SMR) bits Function Bit 7 SIOF: • This bit is set to "1" when the serial output operation has transmitted 8 serial data bits or the serial Interrupt request input operation has received 8 serial data bits. flag bit An interrupt request is generated when both this bit and the interrupt request enable bit (SIOE) are "1".
Page 192 CHAPTER 9 8-BIT SERIAL I/O Table 9.3-1 Serial mode register (SMR) bits Function Bit 0 SST: • This bit controls serial I/O transfer start and transfer enable. This bit can also be used to determine Serial I/O transfer whether transfer has completed. start bit •...
Page 193: Serial Data Register (Sdr)
CHAPTER 9 8-BIT SERIAL I/O 9.3.2 Serial Data Register (SDR) The serial data register (SDR) stores the transfer data for 8-bit serial I/O. The register can function as the transmit data register for serial output operation or as the receive data register for serial input operation. I Serial data register (SDR) Figure 9.3-4 "Serial data register (SDR)"...
Page 194: 8-Bit Serial I/O Interrupts
CHAPTER 9 8-BIT SERIAL I/O 8-bit Serial I/O Interrupts The 8-bit serial I/O can generate interrupt requests after completion of the serial input and output of the 8-bit data. I Interrupt for serial output operation The 8-bit serial I/O performs the serial input operation and serial output operation at the same time. When the serial transfer starts, the data in the serial data register (SDR) is input and output one bit at a time, synchronized with the cycle of the selected shift clock.
Page 195: Operation Of Serial Output
CHAPTER 9 8-BIT SERIAL I/O Operation of Serial Output The 8-bit serial I/O can perform serial output of 8-bit data synchronized with a shift clock. I Serial output operation Serial output can operate using an internal or external shift clock. When serial output operation is enabled, the contents of the SDR register are output to the serial data output pin (SO).
Page 196 CHAPTER 9 8-BIT SERIAL I/O When the device being communicated with has completed the serial input operation (on the rising edge), hold the external shift clock at the "H" level while waiting for next output data (idle state). Figure 9.5-3 "8-bit serial output operation" shows the 8-bit serial output operation. Figure 9.5-3 8-bit serial output operation For LSB first Bit 7...
Page 197: Operation Of Serial Input
CHAPTER 9 8-BIT SERIAL I/O Operation of Serial Input The 8-bit serial I/O can perform serial input of 8-bit data synchronized with a shift clock. I Serial input operation Serial input can operate using an internal or external shift clock. When serial in operation is enabled, input from the serial data input pin (SI) is stored in SDR register.
Page 198 CHAPTER 9 8-BIT SERIAL I/O During this time, hold the external shift clock at the "H" level while waiting for the next data (idle state). Figure 9.6-3 "8-bit serial input operation" shows the 8-bit serial input operation. Figure 9.6-3 8-bit serial input operation For MSB first Bit 7 Bit 6...
Page 199: States In Each Mode During 8-Bit Serial I/O Operation
CHAPTER 9 8-BIT SERIAL I/O States in Each Mode during 8-bit Serial I/O Operation This section describes the operation of the 8-bit serial I/O when the device goes to sleep or stop mode, or an operation halt request occurs during transfer. I Using internal shift clock Operation in sleep mode In sleep mode, serial I/O operation does not halt and transfer continues, as shown in Figure 9.7-1...
Page 200 CHAPTER 9 8-BIT SERIAL I/O Figure 9.7-3 Operation during halt (internal shift clock) SCK output SST bit Operation halts. Operation reactivates. Reset SDR register SIOF bit SO pin output I Using external shift clock Operation in sleep mode In sleep mode, serial I/O operation does not halt and transfer continues, as shown in Figure 9.7-4 "Operation in sleep mode (external shift clock)".
Page 201 CHAPTER 9 8-BIT SERIAL I/O Figure 9.7-5 Operation in stop mode (external shift clock) Clock for next data SCK input Oscillation SST bit stabilization Stop request Cleared by the program. delay time SIOF bit Interrupt request SO pin output Transfer error occurs Stop mode STP bit Wake-up from stop mode by an external interrupt.
Page 202: Notes On Using 8-Bit Serial I/O
CHAPTER 9 8-BIT SERIAL I/O Notes on Using 8-bit Serial I/O This section lists points to note using when the 8-bit serial I/O. I Notes on using 8-bit serial I/O Error on starting serial transfer Activating the serial transfer by software (SMR: SST = "1") is not synchronized with the falling edge (output) or rising edge (input) of the shift clock, there is a delay of up to one cycle of the selected shift clock before the first serial data I/O occurs.
Page 203: Connection Example For 8-Bit Serial I/O
CHAPTER 9 8-BIT SERIAL I/O Connection Example for 8-bit Serial I/O This section shows an example of connecting together two MB89950/950A series 8-bit serial I/O and performing bi-directional serial I/O. I Bi-directional serial I/O performing Figure 9.9-1 Connection example for 8-bit serial I/O (interface between two MB89950/950A) SIO-A SIO-A SIO-B...
Page 204: Program Example For 8-Bit Serial I/O
CHAPTER 9 8-BIT SERIAL I/O 9.10 Program Example for 8-bit Serial I/O This section gives program example for 8-bit serial I/O. I Program example for serial output Processing description • Outputs 8-bit serial data (55 ) from the SO pin of serial I/O, then generates an interrupt when transfer is completed.
Page 205 CHAPTER 9 8-BIT SERIAL I/O Coding example 001CH ; Serial mode register 001DH ; Serial data register SIOF SMR:7 ; Define the interrupt request flag bit. SMR:0 ; Define the serial I/O transfer start bit. ILR2 007DH ; Address of the interrupt level setting register 2 INT_V DSEG ;...
Page 206 CHAPTER 9 8-BIT SERIAL I/O I Program example for serial input Processing description • Inputs 8-bit serial data from the SI pin of serial I/O, then generates an interrupt when transfer is completed. • The interrupt processing routine reads the transferred data and continues transfer. •...
Page 207: Chapter 10 Uart
CHAPTER 10 UART This chapter describes the functions and operation of the UART. 10.1 "Overview of UART" 10.2 "Structure of UART" 10.3 "UART Pins" 10.4 "UART Registers" 10.5 "UART Interrupts" 10.6 "Operation of UART" 10.7 "Operation of Mode 0, 1, 3" 10.8 "Program Example for UART"...
Page 208: Overview Of Uart
CHAPTER 10 UART 10.1 Overview of UART The UART is a general-purpose data communication interface. The UART supports both synchronous clock and asynchronous clock mode and transmits variable-length serial data. The transmission format is the "NRZ" system and the transmission data rate is configurable by setting the proprietary baud rate generator, external clocks, internal timers.
Page 209 CHAPTER 10 UART I Selection of transfer clocks The transfer clock can selected from the external clock (SCK pin), PWM timer or dedicated baud rate generator by setting CS0 and CS1 bits of serial rate control register (SRC). In addition, the CR bit of SRC and SMDE bit of serial mode control register 1 (SMC1) can determine which divider for the selected transfer clock.
Page 210 CHAPTER 10 UART Table 10.1-4 "Transfer cycle and transfer rate by baud rate generator" is shown the example of baud rate when using the dedicated baud rate generator. Table 10.1-4 Transfer cycle and transfer rate by baud rate generator Baud rate (bps) 4.912 MHz 5 MHz Input clock...
Page 211 CHAPTER 10 UART Table 10.1-5 Transfer cycle and transfer rate by external clocks Asynchronous transfer mode Synchronous transfer mode Selected baud Selected baud Transfer rate Transfer rate Transfer Transfer rate division rate division (*1) (*1) cycle cycle (baud) (baud) value value 128/F CR = 0...
Page 212 CHAPTER 10 UART Table 10.1-6 Transfer cycle and transfer rate by 8-bit PWM timers Asynchronous transfer mode Synchronous transfer mode PWM timer count Transfer rate Transfer rate clock cycle Clock division Clock division (*1) (*1) value value (baud) (baud) CR = 0 39062 to 152.6 312.5k to 1.22k inst...
Page 213: Structure Of Uart
CHAPTER 10 UART 10.2 Structure of UART The UART consists of the following blocks: • Baud rate generator and serial clock generator • Data transmitter and data receiver • Registers (SMC1, SMC2, SRC, SSD, SIDR, SODR) I Block diagram of UART Figure 10.2-1 Block diagram of UART Internal data bus Registers:...
Page 214 CHAPTER 10 UART Baud rate generator and serial clock generator This block generates transmit/receive clocks from the outputs of baud rate generator, 8-bit PWM timer or external clock. Date receive control circuit The receive control circuit consists of the receive byte counter, the start bit detection circuit and the receive parity circuit.
Page 215 CHAPTER 10 UART Serial output data register (SODR) This register stores data to be transmitted. The data written in this register is converted to serial data and sent to serial output pin. When the data length is set to be 7 bits, bit 7 does not have meaning.
Page 216: Uart Pins
CHAPTER 10 UART 10.3 UART Pins This section describes the pins and pin block diagram of UART. I UART pins The pins for the UART function are shift clock input/output pin (P45/SCK), serial data output pin (P44/SO) and serial data input pin (P43/SI). P45/SCK: This pin function either as a general-purpose input/output port (P45) or a clock input output pin (hysteresis input) for the UART(SCK).
Page 217 CHAPTER 10 UART I Block diagram of UART pins Figure 10.3-1 Block diagram of UART pins For P45/SCK and P43/SI To peripheral input PDR (Port data register) Pull-up resistor Stop mode (SPL = 1) Approx. 50 k (Mask option) PDR read For P45/SCK and UART output P44/SO...
Page 218: Uart Registers
CHAPTER 10 UART 10.4 UART Registers This section describes the registers of the UART. I UART registers Figure 10.4-1 UART registers SMC1 (Serial mode control register 1) Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value...
Page 219: Serial Mode Control Register 1 (Smc1)
CHAPTER 10 UART 10.4.1 Serial Mode Control Register 1 (SMC1) Serial mode control register 1 (SMC1) sets synchronous mode, stop bit length, data length, parity/non-parity and select the port function of SCK and SO. I Serial mode control register 1 (SMC1) Figure 10.4-2 Serial mode control register 1 (SMC1) Address Bit 7...
Page 220 CHAPTER 10 UART Table 10.4-1 Serial mode control register 1 (SMC1) bits Function Bit 7 PEN: • In the clock asynchronous mode, sets whether there is parity data or not. Parity control bit Bit 6 SBL: • This bit determines the stop bit length. Stop bit length •...
Page 221: Serial Rate Control Register (Src)
CHAPTER 10 UART 10.4.2 Serial Rate Control Register (SRC) The serial rate control register (SRC) is to set the UART transmission speed (baud rate). I Serial rate control register (SRC) Figure 10.4-3 Serial rate control register (SRC) Address Bit 7 Bit 6 Bit 5 Bit 4...
Page 222 CHAPTER 10 UART Table 10.4-2 Serial rate control register (SRC) bits Function Bit 7 Unused bits • The read value is indeterminate. Bit 6 • Writing to these bits has no effect on the operation. Bit 5 • Used to select the asynchronous transfer clock rate. However, when the CS1 and Clock rate selection CS0 bit are "11 ", the 1/8 clock rate is selected in spite of the value of the CR bit.
Page 223: Serial Status And Data Register (Ssd)
CHAPTER 10 UART 10.4.3 Serial Status and Data Register (SSD) The serial status and data register (SSD) is used to set and monitor transmit/receive operation and error status. I Serial status and rate register (SSD) Figure 10.4-4 Serial status and data register (SSD) Address Bit 7 Bit 6...
Page 224 CHAPTER 10 UART Table 10.4-3 Serial status and data register (SSD) bits Function Bit 7 RDRF: • This flag represents the status of the serial input data register (SIDR). Receive data register • This flag is set when receiving data is loaded into the SIDR register. It is cleared full bit when the SIDR register is read.
Page 225: Serial Input Data Register (Sidr)
CHAPTER 10 UART 10.4.4 Serial Input Data Register (SIDR) The serial input data register (SIDR) is used to input (receive) serial data. I Serial input data register (SIDR) Figure 10.4-5 "Serial input data register (SIDR)" shows the bit allocations of the serial input data register. Figure 10.4-5 Serial input data register (SIDR) Address Address...
Page 226: Serial Output Data Register (Sodr)
CHAPTER 10 UART 10.4.5 Serial Output Data Register (SODR) The serial output data register (SODR) is used to output (transmit) serial data. I Serial output data register (SODR) Figure 10.4-6 shows the bit allocations of the serial output data register. Figure 10.4-6 Serial output data register (SODR) Address Bit 7...
Page 227: Serial Mode Control Register 2 (Smc2)
CHAPTER 10 UART 10.4.6 Serial Mode Control Register 2 (SMC2) Serial mode control register 2 (SMC2) selects the division ratio of the baud rate generator, selects to function as UART or SIO, and enables the baud rate generator. I Serial mode control register 2 (SMC2) Figure 10.4-7 Serial mode control register 2 (SMC2) Address Bit 7...
Page 228 CHAPTER 10 UART Table 10.4-4 Serial mode control register 2 (SMC2) bits Function Bit 7 Unused bits • The read value is indeterminate. Bit 6 • Writing to these bits has no effect on the operation. Bit 5 PSEN: • This bit enables baud rate generator. Baud rate generator is stopped by writing "0" to Operation enable bit this bit after transmitting/receiving the current serial data, then disabled thereafter.
Page 229: Uart Interrupts
CHAPTER 10 UART 10.5 UART Interrupts The UART has three interrupt causes -- transfer error interrupt, receive data full interrupt and transmit data empty interrupt: • When receive data is transferred from the receive shift register to the serial input data register (SIDR) (receive interrupt) •...
Page 230: Operation Of Uart
CHAPTER 10 UART 10.6 Operation of UART This section describes the operation of the UART. The UART has a serial communication function (operation mode 0,1,3). I Operation of UART Operation mode The UART has 3 operation modes. The mode 0, 1, 3 are standard serial transmission modes in which a data type from 4-bit data length/parity to 9-bit data length/non-parity is selected (See Table 10.1-1 "UART operating mode").
Page 231: Operation Of Mode 0, 1, 3
CHAPTER 10 UART 10.7 Operation of Mode 0, 1, 3 The operation mode 0, 1 and 3 provide a serial communication function. I Operation of operation mode 0, 1, 3 Settings shown in Figure 10.7-1 "Operation of operation mode 0, 1, 3" are necessary for the UART operation.
Page 232: Receive Operation
CHAPTER 10 UART Figure 10.7-2 Transmit operation in mode 0, 1, 3 SSD read Write to the SODR (Interrupt processing routine) Transmit buffer full TDRE Transmit interrupt Transfer the data to the transmit shift register. Transfer the data to the transmit shift register. Transmit data START STOP START...
Page 233 CHAPTER 10 UART Figure 10.7-3 Receive operation in mode 0, 1, 3 Data START STOP RDRF Receive interrupt Figure 10.7-4 Operation at overrun error in mode 0, 1, 3 Data STOP START RDRF=1 (Receive buffer full) ORFE Receive interrupt Figure 10.7-5 Operation at framing error in mode 0, 1, 3 Data START STOP...
Page 234: Program Example For Uart
CHAPTER 10 UART 10.8 Program Example for UART This section gives program example for UART. I Program example for UART Processing description • Perform serial transmit/receive operation using communication functions of the UART. • P45/SCK, P44/SO and P43/SI pins are used for communication. •...
Page 235 CHAPTER 10 UART Coding example PDR4 000EH ; Address of the port data register DDR4 000FH ; Address of the port direction register SMC1 0020H ; Address of the serial mode control register 1 0021H ; Address of the serial rate control register 0022H ;...
Page 236 CHAPTER 10 UART...
Page 237: Chapter 11 External Interrupt Circuit (Edge)
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) This chapter describes the functions and operation of the external interrupt circuit. 11.1 "Overview of the External Interrupt Circuit" 11.2 "Block Diagram of the External Interrupt Circuit" 11.3 "Structure of the External Interrupt Circuit" 11.4 "External Interrupt Circuit Interrupts"...
Page 238: Overview Of The External Interrupt Circuit
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.1 Overview of the External Interrupt Circuit The external interrupt circuit detects edges on the signals input to the two external interrupt pins and generates the corresponding interrupt requests to the CPU. I Functions of the external interrupt circuit The function of the external interrupt circuit is to detect specified edges on signals input to the external interrupt pins and to generate interrupt requests to the CPU.
Page 239: Block Diagram Of The External Interrupt Circuit
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.2 Block Diagram of the External Interrupt Circuit The external interrupt circuit consists of the following two elements: • Edge detect circuit 0, 1 • External interrupt control register (EIC) I Block diagram of the external interrupt circuit Figure 11.2-1 Block diagram of the external interrupt circuit Edge detect circuit 0 P46/INT0...
Page 240: Structure Of The External Interrupt Circuit
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.3 Structure of the External Interrupt Circuit This section describes the pins, pin block diagram, register, and interrupt sources of the external interrupt circuit. I External interrupt circuit pins The external interrupt circuit has two external interrupt pins. The external interrupt pins can function either as external interrupt inputs (hysteresis inputs) or general I/O ports.
Page 241 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) Reference: Pins with a pull-up resistor go to the "H" level (pull-up state) rather than to the high-impedance state when the output transistor is turned "OFF". I External interrupt circuit register Figure 11.3-2 External interrupt circuit register EIC (External interrupt control register) Bit 7 Bit 6...
Page 242: External Interrupt Control Register (Eic)
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.3.1 External Interrupt Control Register (EIC) External interrupt control register (EIC) is used to select the edge polarity and to control interrupts for external interrupt pins (INT0, INT1). I External interrupt control register (EIC) Figure 11.3-3 External interrupt control register (EIC) Bit 7 Bit 6...
Page 243 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) Table 11.3-2 External interrupt control register (EIC) bits Function Bit 7 EIR1: • This bit is set to "1" when the edge selected by INT1 edge polarity selection bits INT1 external (SL11, SL10) is input to external interrupt pin INT1. interrupt request flag •...
Page 244: External Interrupt Circuit Interrupts
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.4 External Interrupt Circuit Interrupts The external interrupt circuit can generate interrupt requests when it detects a specified edge on the signal input to an external interrupt pin. I Interrupts when the external interrupt circuit is operating On detecting a specified edge on an external interrupt input, the external interrupt circuit sets the corresponding external interrupt request flag bit (EIC: EIR0 - EIR1) to "1".
Page 245: Operation Of The External Interrupt Circuit
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.5 Operation of the External Interrupt Circuit The external interrupt circuit can detect a specified edge on a signal input to an external interrupt pin. I Operation of the external interrupt circuit Figure 11.5-1 "External interrupt circuit settings" shows the settings required to operate the external interrupt circuit.
Page 246: Program Example For The External Interrupt Circuit
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT (EDGE) 11.6 Program Example for the External Interrupt Circuit This section gives a program example for the external interrupt circuit. I Program example for the external interrupt circuit Processing description • Generates interrupts on detecting a rising edge on pulses input to the INT1 pin. Coding example EIC1 0030H...
Page 247: Chapter 12 Lcd Controller/Driver
CHAPTER 12 LCD CONTROLLER/DRIVER This chapter describes the functions and operation of the LCD controller/driver. 12.1 "Overview of LCD Controller/Driver" 12.2 "Block Diagram of LCD Controller/Driver" 12.3 "Structure of LCD Controller/Driver" 12.4 "Operation of LCD Controller/Driver" 12.5 "Program Example for LCD Controller/Driver"...
Page 248: Overview Of Lcd Controller/Driver
CHAPTER 12 LCD CONTROLLER/DRIVER 12.1 Overview of LCD Controller/Driver The LCD controller/driver includes 21 bytes of on-chip display data in memory, the contents of which control an LCD via 42 segment and 4 common outputs. The function can drive an LCD panel directly, using one of three selectable duty ratios. I LCD controller/driver function The LCD controller/driver function displays the contents of a display data memory directly to the LCD (Liquid Crystal Display) panel by segment and common outputs.
Page 249: Block Diagram Of Lcd Controller/Driver
CHAPTER 12 LCD CONTROLLER/DRIVER 12.2 Block Diagram of LCD Controller/Driver The LCD controller/driver is made up of seven blocks listed below. Functionally, the circuit can be broken into two major sections: the controller section, which generates LCD segment and common signals based on the current contents of display RAM, and the driver section, which develops sufficient drive to operate the display.
Page 250 CHAPTER 12 LCD CONTROLLER/DRIVER Display RAM This 42 x 4-bit block of RAM controls the segment output signals. Its contents are automatically read out to the segment outputs in synchronous with the timing of the selected common signal. Prescaler The prescaler generates one of the 4 frame frequencies according to the LCD control register setting. Timing controller This block controls the segment and common signals based on the frame frequency and LCD control register settings.
Page 251: Lcd Controller/Driver Internal Voltage Divider
CHAPTER 12 LCD CONTROLLER/DRIVER 12.2.1 LCD Controller/Driver Internal Voltage Divider LCD driver supply voltage can be taken from an internal voltage divider (external voltage divider may also be used). I Internal voltage divider In these devices, external voltage divider may also be connected at pins V1 through V3. The selection of internal or external voltage divider is made by the drive supply voltage control bit of LCD control register (LCDR: VSEL).
Page 252 CHAPTER 12 LCD CONTROLLER/DRIVER I Use of internal voltage divider Figure 12.2-3 "Use of internal voltage divider" shows the voltage divider circuits for 1/2 and 1/3 bias. As shown in this figure, in the 1/2 bias mode (with LCD enabled) V2 and V1 will be 1/2 of V3 (V3 is the LCD operating voltage, which is V in this configuration).
Page 253: Lcd Controller/Driver External Voltage Divider
CHAPTER 12 LCD CONTROLLER/DRIVER 12.2.2 LCD Controller/Driver External Voltage Divider External voltage divider can also be used with devices that have internal voltage divider. Display brightness can be adjusted by a variable resistor(VR) connected between the and V3 pins. I External voltage divider When you do not wish to use the internal voltage divider, external voltage divider resistors can be connected at the LCD drive voltage supply pins (V1 to V3).
Page 254 CHAPTER 12 LCD CONTROLLER/DRIVER I Use of external voltage divider Figure 12.2-6 "External voltage divider connection" shows an external voltage divider connection. Figure 12.2-6 External voltage divider connection LCD enable N-ch MB89950/950A series to V : Voltages at V1 to V3 pins. Note: To preclude the external voltage divider from being affected by the internal voltage divider, the LCD drive supply voltage control bit of LCD control register (LCDR: VSEL) must be written to "0"...
Page 255: Structure Of Lcd Controller/Driver
CHAPTER 12 LCD CONTROLLER/DRIVER 12.3 Structure of LCD Controller/Driver This section describes the pins, pin block diagrams, registers, and display RAM of the LCD controller/driver. I LCD controller/driver pins The LCD controller/driver uses 4 common output pins (COM0 to COM3), 42 segment output pin (SEG0 to SEG41), and 3 LCD driving power supply pins (V1 to V3).
Page 256 CHAPTER 12 LCD CONTROLLER/DRIVER I Block diagrams of LCD controller/driver pins Figure 12.3-1 Block diagram of LCD controller/driver pins (dedicated common/segment output pins COM0 to COM3 and SEG0 to SEG19) Dedicated common/segment output pins Common/segment control signal P-ch LCD drive voltage (V or V N-ch COM0 to COM3...
Page 257: Lcd Controller/Driver Ram
CHAPTER 12 LCD CONTROLLER/DRIVER Figure 12.3-3 Block diagram of LCD controller/driver pin (P32/V1 and P33/V2) PSEL bit of LCDR register V1 or V2 PDR (Port data register) N-ch P-ch Stop mode (SPL = 1) PDR read PDR read (for bit manipulation instructions) Output latch PDR write P32/V1...
Page 258: Lcd Control Register (Lcdr)
CHAPTER 12 LCD CONTROLLER/DRIVER 12.3.1 LCD Control Register (LCDR) LCD control register (LCDR) is used to select the frame cycle, control the LCD drive supply voltage, select display blanking/non-blanking, and select the display mode. I LCD control register (LCDR) Figure 12.3-5 LCD control register (LCDR) Address Bit 7 Bit 6...
Page 259 CHAPTER 12 LCD CONTROLLER/DRIVER Table 12.3-1 LCD control register (LCDR) bit functions Function Bit 7 Reserved bit • Always write "0" to this bit. Bit 6 PSEL: • Selects P32/V1 and P33/V2 to function either as N-ch open-drain I/O ports (P32, LCD power supply P33) or as LCD power supply pins (V1 and V2).
Page 260: Segment Output Select Register (Segr)
CHAPTER 12 LCD CONTROLLER/DRIVER 12.3.2 Segment Output Select Register (SEGR) Segment output select register (SEGR) is used to select N-ch open-drain I/O port function or segment output function for P00/SEG20 to P07/SEG27, P10/SEG28 to P17/ SEG35 and P20/SEG36 to P25/SEG41, in order to be consistent with mask option. I Segment output select register (SEGR) Figure 12.3-6 Segment output select register (SEGR) Address...
Page 261 CHAPTER 12 LCD CONTROLLER/DRIVER Table 12.3-2 Segment output select register bit functions Function Bit 7 Unused bit • The read value is indeterminate. • Writing to this bit has no effect on the operation. Bit 6 SEG15: • Selects P24/SEG40 to P25/SEG41 to function either as N-ch open-drain I/O ports Segment output (P24 to P25) or as LCD segment outputs (SEG40 to SEG41).
Page 262: Display Ram
CHAPTER 12 LCD CONTROLLER/DRIVER 12.3.3 Display RAM Display RAM consists of 42 x 4-bit (21 bytes) of display data memory used to generate the segment output signals. I Display RAM and output pins The contents of display RAM are automatically read out and output via the segment outputs in synchronous with the selected common signal timing.
Page 263 Locations in the display RAM area that are not required for display data can be used as regular RAM. If any customer wants to choose the mask option combination which is not shown in Table 12.3-3 "Segment outputs, display RAM locations, and sharing port pins", please inform Fujitsu for special testing arrangement.
Page 264: Operation Of Lcd Controller/Driver
CHAPTER 12 LCD CONTROLLER/DRIVER 12.4 Operation of LCD Controller/Driver The LCD controller/driver provides the necessary control and drive for an LCD. I Operation of LCD controller/driver Figure 12.4-1 "LCD controller/driver settings" shows the settings required to operate the LCD. Figure 12.4-1 LCD controller/driver settings Bit 7 Bit 6 Bit 5...
Page 265: Output Waveforms During Lcd Controller/Driver Operation (1/2 Duty Ratio)
CHAPTER 12 LCD CONTROLLER/DRIVER 12.4.1 Output Waveforms during LCD Controller/Driver Operation (1/2 Duty Ratio) The display drive output is a multiplex drive-type two-frame a.c. waveform. In the 1/2 duty ratio mode, the only common outputs are COM0 and COM1. (COM2 and COM3 are not used.) I 1/2 bias, 1/2 duty output waveform The maximum potential difference exists between a segment output and the corresponding common output...
Page 266 CHAPTER 12 LCD CONTROLLER/DRIVER Figure 12.4-2 Output waveforms, 1/2 bias and 1/2 duty ratio example COM0 COM1 COM2 COM3 (ON) Difference in potential between COM0 and SEG (ON) (ON) Difference in potential between (ON) COM1 and SEG (ON) Difference in potential between COM0 and SEG (ON)
Page 267 CHAPTER 12 LCD CONTROLLER/DRIVER LCD panel connections and display data example (1/2 duty ratio drive mode) Figure 12.4-3 Segment/common connections, data states and corresponding display Example) Using segments to represent "5". COM1 COM0 Address COM3 COM2 COM1 COM0 Address COM3 COM2 COM1 COM0 064H —...
Page 268: Output Waveforms During Lcd Controller/Driver Operation (1/3 Duty Ratio)
CHAPTER 12 LCD CONTROLLER/DRIVER 12.4.2 Output Waveforms during LCD Controller/Driver Operation (1/3 Duty Ratio) In the 1/3 duty ratio mode, the COM0, COM1 and COM2 outputs are used by the display. COM3 is not used. I 1/3 bias, 1/3 duty output waveform The maximum potential difference exists between a segment output and the corresponding common output when the segment (LCD cell) is turned on.
Page 269 CHAPTER 12 LCD CONTROLLER/DRIVER Figure 12.4-4 Output waveforms, 1/3 bias and 1/3 duty ratio example COM0 COM1 COM2 COM3 (ON) Difference in potential between COM0 and (ON) (ON) Difference in potential between COM1 and (ON) (ON) Difference in potential between COM2 and (ON) (ON)
Page 270 CHAPTER 12 LCD CONTROLLER/DRIVER LCD panel connections and display data example (1/3 duty ratio drive mode) Figure 12.4-5 Segment/common connections, data states and corresponding display Example) Using segments to represent "5". COM0 COM1 COM2 Address COM3 COM2 COM1 COM0 — SEG0 —...
Page 271: Output Waveforms During Lcd Controller/Driver Operation (1/4 Duty Ratio)
CHAPTER 12 LCD CONTROLLER/DRIVER 12.4.3 Output Waveforms during LCD Controller/Driver Operation (1/4 Duty Ratio) In the 1/4 duty ratio mode, all four common outputs, COM0, COM1, COM2, and COM3 are used. I 1/3 bias, 1/4 duty output waveforms The maximum potential difference exists between a segment output and the corresponding common output when the segment (LCD cell) is turned on.
Page 272 CHAPTER 12 LCD CONTROLLER/DRIVER Figure 12.4-6 Output waveforms, 1/3 bias and 1/4 duty ratio example COM0 COM1 COM2 COM3 (ON) Difference in potential between COM0 and SEG (ON) (ON) Difference in potential between COM1 and SEG (ON) (ON) Difference in potential between COM2 and SEG (ON)
Page 273 CHAPTER 12 LCD CONTROLLER/DRIVER 8-segment LCD panel connections and display data (1/4 duty ratio drive mode) Figure 12.4-7 Segment/common connections, data states and corresponding display Example) Using segments to represent "5". COM0 COM3 COM1 COM2 Address COM3 COM2 COM1 COM0 Address COM3 COM2 COM1 COM0...
Page 274: Program Example For Lcd Controller/Driver
CHAPTER 12 LCD CONTROLLER/DRIVER 12.5 Program Example for LCD Controller/Driver This section gives a program example for LCD controller/driver. I Program example for LCD controller/driver Processing description The process writes LCD data to display RAM. The data is that required to display the numbers "0" through "9"...
Page 275 CHAPTER 12 LCD CONTROLLER/DRIVER Coding example LCRAM 0064H ;Starting address of LCD display RAM LCDR 0079H ;Address of LCD control register (LCDR) SEGR 007AH ;Address of segment output select register (SEGR) CSEG ;8-segment LCD data LCDDATA DB 11011111B ;"0" 11001000B ;"1"...
Page 276 CHAPTER 12 LCD CONTROLLER/DRIVER...
Page 277: Appendix
APPENDIX This appendix includes I/O maps, instruction lists, and other information. APPENDIX A "I/O Map" APPENDIX B "Overview of Instructions" APPENDIX C "Mask Options" APPENDIX D "Programming Specifications for One-Time PROM And EPROM Microcontroller" APPENDIX E "MB89950/950A Series Pin States"...
Page 278: Appendix A I/O Map
APPENDIX APPENDIX A I/O Map Table A-1 "I/O map" lists the addresses of the registers of used by the internal peripheral functions of the MB89950/950A series. I I/O map Table A-1 I/O map (1/2) Address Register name Register description Read/Write Initial value PDR0 Port 0 data register...
Page 279 APPENDIX A I/O Map Table A-1 I/O map (2/2) Address Register name Register description Read/Write Initial value Serial data register XXXXXXXX (Vacancy) SMC1 UART serial mode control register 1 00000-00 UART serial rate control register --011000 UART serial status/data register 00100-1X SIDR/SODR UART serial data register...
Page 280: Appendix B Overview Of Instructions
APPENDIX APPENDIX B Overview of Instructions Appendix B describes the instructions used by the F MC-8L. B.1 "Overview of F MC-8L Instructions" B.2 "Addressing" B.3 "Special Instructions" B.4 "Bit Manipulation Instructions (SETB, CLRB)" B.5 "F MC-8L Instructions" B.6 "Instruction Map"...
Page 281: Overview Of Fmc-8L Instructions
APPENDIX B Overview of Instructions Overview of F MC-8L Instructions The F MC-8L supports 140 types of instructions. I Overview of F MC-8L instructions The F MC-8L has 140 1-byte machine instructions (256-byte instruction map). An instruction code consists of an instruction and zero or more operands that follow. Figure B.1-1 "Relationship between the instruction codes and the instruction map"...
Page 282 APPENDIX I Symbols used with Instructions Table B.1-1 "Symbols in the instruction list" lists the symbols used in the instruction code descriptions in Appendix B. Table B.1-1 Symbols in the instruction list Symbol Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) #vct Vector table number (3 bits)
Page 283: Addressing
APPENDIX B Overview of Instructions Addressing The F MC-8L has the following ten addressing modes: • Direct addressing • Extended addressing • Bit direct addressing • Index addressing • Pointer addressing • General-purpose register addressing • Immediate addressing • Vector addressing •...
Page 284 APPENDIX Bit direct addressing Bit direct addressing is indicated by dir:b in the instruction list. This addressing is used to access a particular bit in the area between 0000 and 00FF . In this addressing mode, the higher byte of the address is 00 and the lower byte is specified by the operand.
Page 285 APPENDIX B Overview of Instructions General-purpose register addressing General-purpose register addressing is indicated by Ri in the instruction list. This addressing is used to access a register bank in the general-purpose register area. In this addressing mode, the higher byte of the address is always 01 and the lower byte is specified based on the contents of RP (register bank pointer) and the lower three bits of the operation code.
Page 286 APPENDIX Vector addressing Vector addressing is indicated by vct in the instruction list. This addressing is used to branch to a subroutine address stored in the vector table. In this addressing mode, vct information is contained in the operation codes, and the corresponding table addresses are created as shown in Table B.2-1 "Vector table addresses corresponding to vct".
Page 287 APPENDIX B Overview of Instructions Relative addressing Relative addressing is indicated by rel in the instruction list. This addressing is used to branch to within the area between the address 128 bytes higher and that 128 bytes lower relative to the address contained in the PC (program counter).
Page 288: Special Instructions
APPENDIX Special Instructions This section describes the special instructions used for other than addressing. I Special instructions JMP @A This instruction sets the contents of A (accumulator) to PC (program counter) as the address, and causes a branch to that address. One of the N branch destination addresses is selected from a table, and then transferred to A.
Page 289 APPENDIX B Overview of Instructions MULU A This instruction performs an unsigned multiplication of AL (lower eight bits of the accumulator) and TL (lower eight bits of the temporary accumulator), and stores the 16-bit result in A. The contents of T (temporary accumulator) do not change.
Page 290 APPENDIX XCHW A, PC This instruction swaps the contents of A and PC, resulting in a branch to the address contained in A before execution of the instruction. After the instruction is executed, A contains the address that follows the address of the operation code of MOVW A, PC.
Page 291 APPENDIX B Overview of Instructions CALLV #vct This instruction is used to branch to a subroutine address stored in the vector table. The instruction saves the return address (contents of PC) in the location at the address contained in SP (stack pointer), and uses vector addressing to cause a branch to the address stored in the vector table.
Page 292: Bit Manipulation Instructions (Setb, Clrb)
APPENDIX Bit Manipulation Instructions (SETB, CLRB) Some bits of peripheral function registers include bits that are read by a bit manipulation instruction differently than usual. I Read-modify-write operation By using these bit manipulation instructions, only the specified bit in a register or RAM location can be set to 1 (SETB) or cleared to 0 (CLRB).
Page 293: F 2 Mc-8L Instructions
APPENDIX B Overview of Instructions MC-8L Instructions Table B.5-1 "Transfer instructions" to Table B.5-4 "Other instructions" list the instructions used with the F MC-8L. I Transfer instructions Table B.5-1 Transfer instructions Operation MNEMONIC OP CODE MOV dir, A (dir)<--(A) MOV @IX+off, A ((IX)+off)<--(A) MOV ext, A (ext)<--(A)
Page 294 APPENDIX Table B.5-1 Transfer instructions (Continued) Operation MNEMONIC OP CODE MOVW A, @IX+off (AH)<--((IX)+off), (AL)<--((IX)+off+1) MOVW A, ext (AH)<--(ext), (AL)<--(ext+1) MOVW A, @A (AH)<--((A)), (AL)<--((A)+1) MOVW A, @EP (AH)<--((EP)), (AL)<--((EP)+1) MOVW A, EP (A)<--(EP) MOVW EP, #d16 (EP)<--d16 MOVW IX, A (IX)<--(A) MOVW A, IX (A)<--(IX)
Page 295: Arithmetic Instructions
APPENDIX B Overview of Instructions I Arithmetic instructions Table B.5-2 Arithmetic operation instructions Operation MNEMONIC OP CODE ADDC A, Ri (A)<--(A)+(Ri)+C 28 to 2F ADDC A, #d8 (A)<--(A)+d8+C ADDC A, dir (A)<--(A)+(dir)+C ADDC A, @IX+off (A)<--(A)+((IX)+off)+C ADDC A, @EP (A)<--(A)+((EP))+C ADDCW A (A)<--(A)+(T)+C ADDC A...
Page 296 APPENDIX Table B.5-2 Arithmetic operation instructions (Continued) Operation MNEMONIC OP CODE CMPW A (T)-(A) RORC A C --> A ROLC A C <-- A CMP A, #d8 (A)-d8 CMP A, dir (A)-(dir) CMP A, @EP (A)-((EP)) CMP A, @IX+off (A)-((IX)+off) CMP A, Ri (A)-(Ri) 18 to 1F...
Page 297 APPENDIX B Overview of Instructions Table B.5-2 Arithmetic operation instructions (Continued) Operation MNEMONIC OP CODE OR A, @EP (A)<--(AL) ((EP)) OR A, @IX+off (A)<--(AL) ((IX)+off) OR A, Ri 78 to 7F (A)<--(AL) (Ri) CMP dir, #d8 (dir)-d8 CMP @EP, #d8 ((EP))-d8 CMP @IX+off, #d8 ((IX)+off)-d8...
Page 298: Branch Instructions
APPENDIX I Branch instructions Table B.5-3 Branch instructions MNEMONIC Operation C OP CODE BZ/BEQ rel if Z=1 then PC<--PC+rel BNZ/BNE rel if Z=0 then PC<--PC+rel BC/BLO rel if C=1 then PC<--PC+rel BNC/BHS rel if C=0 then PC<--PC+rel BN rel if N=1 then PC<--PC+rel BP rel if N=0 then PC<--PC+rel BLT rel...
Page 299 APPENDIX B Overview of Instructions I Other instructions Table B.5-4 Other instructions MNEMONIC Operation C OP CODE PUSHW A POPW A PUSHW IX POPW IX CLRC SETC CLRI SETI...
Page 300: Instruction Map
APPENDIX Instruction map Table B.6-1 "F MC-8L instruction map" shows the F MC-8L instruction map. I Instruction map Table B.6-1 F MC-8L instruction map...
Page 301: Appendix C Mask Options
APPENDIX C Mask Options APPENDIX C Mask Options This appendix lists the mask options for the MB89950/950A series. I Mask options Table C-1 Mask options MB89951A Part number MB89P955 MB89PV950 MB89953A Specify when Set with EPROM Specifying procedure Setting not possible ordering mask programmer Port pull-up resistor...
Page 302 *1: This column of numbers assume that all the multiplexed peripherals are disabled. If any customer wants to choose the mask option combination which is not shown in Table C-2 "Recommended port/segment mask option combinations", please inform Fujitsu for special testing arrangement.
Page 303: Appendix D Programming Specifications For One-Time Prom And Eprom Microcontroller
APPENDIX D Programming Specifications for One-Time PROM And EPROM Microcontroller APPENDIX D Programming Specifications for One-Time PROM And EPROM Microcontroller This appendix describes the programming specifications for one-time PROM and EPROM microcontroller. D.1 "Programming Specifications for One-time PROM and EPROM Microcontrollers" D.2 "Programming Yield and Erasure"...
Page 304: Programming Specifications For One-Time Prom And Eprom Microcontrollers
APPENDIX Programming Specifications for One-time PROM and EPROM Microcontrollers In EPROM mode, the MB89P955 function is equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer by using the dedicated adaptor. Note that the electronic signature mode cannot be used. I EPROM programmer socket adaptor Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between V and V...
Page 305 APPENDIX D Programming Specifications for One-Time PROM And EPROM Microcontroller I Recommended screening conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Table D.1-2 "Screening procedure" shows the screening procedure. Figure D.1-2 Screening procedure I Programming to the EPROM In EPROM mode, the MB89P955 function is equivalent to the MBM27C256A...
Page 306 APPENDIX I Bit map for PROM option Table D.1-2 "Bit map for PROM option" shows the bit map for PROM option. Table D.1-2 Bit map for PROM option 3FF0 Vacant Vacant Vacant Oscillation Reset pin Power-on Vacant Vacant stabilization Output Reset Readable/ Readable/...
Page 307: Programming Yield And Erasure
I Programming yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. I Notes on using and data erasure on EPROM microcomputer...
Page 308: Programming To The Eprom With Piggyback/Evaluation Device
APPENDIX Programming to the EPROM with Piggyback/Evaluation Device This section describes the programming to the EPROM with piggyback/evaluation device. I EPROM for use MBM27C256A-20TV I Programming socket adaptor To program to the PROM using an EPROM programmer, use the socket adaptor (manufacturer: Sun Hayato Co., Ltd.) listed below.
Page 309: Appendix E Mb89950/950A Series Pin States
APPENDIX E MB89950/950A Series Pin States APPENDIX E MB89950/950A Series Pin States This section describes the pin states of the MB89950/950A series in various modes. I MB89950/950A series pin states The state of each pin of the MB89950/950A series of microcontrollers at sleep, stop and reset is as follows: 1.
Page 310 APPENDIX...
Page 311: Index
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
Page 312 INDEX Index Numerics display RAM and output pin ......... 248 1/2 bias, 1/2 duty output waveform ...... 251 1/3 bias, 1/3 duty output waveform ...... 254 effect of reset on RAM content ......47 1/3 bias, 1/4 duty output waveform ...... 257 EPROM for use............
Page 313 INDEX I/O port function ............. 70 memory access mode selection operation .....68 memory map............23 I/O port, program example for........ 98 instruction cycle ............. 54 memory space ............294 instruction map............. 286 memory space structure .........22 instruction, symbol used with ....... 268 mode data...............67 internal shift clock, using........
Page 314 INDEX port 3 pins .............. 86 serial input data register (SIDR)......211 serial input operation..........183 port 3 register ............88 port 3, operation of ..........90 serial input, operation at completion of ....184 port 3, structure of ..........86 serial input, program example for ......
Page 315 INDEX UART pin, block diagram of ......... 203 UART registers ............ 204 watchdog timer control register (WDTC) ....115 UART, block diagram of........199 watchdog timer function........112 UART, operation of ..........216 watchdog timer, block diagram of......113 UART, program example for ........ 220 watchdog timer, note on using......118 watchdog timer, operation of ........116 watchdog timer, program example for ....119...
Page 316 INDEX...
Page 317 CM25-10146-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL MC-8L 8-BIT MICROCONTROLLER MB89950/950A Series HARDWARE MANUAL July 2002 the first edition FUJITSU LIMITED Electronic Devices Published Edited Technical Information Dept.

This manual is also suitable for:

Mb89950 series Mb89950a series

Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

Chapter 1 Overview

Chapter 2 Handling Devices

Chapter 3 Cpu

Chapter 4 I/O Ports

Chapter 5 Timebase Timer

Chapter 6 Watchdog Timer

Chapter 7 8-Bit Pwm Timer

Chapter 8 Pulse Width Count Timer (Pwc)

Chapter 9 8-Bit Serial I/O

Chapter 10 Uart

Chapter 11 External Interrupt Circuit (Edge)

Chapter 12 Lcd Controller/Driver

Appendix

APPENDIX A I/O Map

APPENDIX B Overview of Instructions

APPENDIX C Mask Options

APPENDIX D Programming Specifications for One-Time PROM and EPROM Microcontroller

APPENDIX E MB89950/950A Series Pin States

Index

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