Motorola MC68030 Manuals

Motorola MC68030 Manuals

Manuals and User Guides for Motorola MC68030. We have 2 Motorola MC68030 manuals available for free PDF download: User Manual

Motorola MC68030 User Manual

Motorola MC68030 User Manual (608 pages)

ENHANCED 32-811 MICROPROCESSOR

Brand: Motorola | Category: Computer Hardware | Size: 20.02 MB

Table of Contents

Table of Contents
5
Introduction
31
Features
33
MC68030 Extensions to the M68000 Family
34
Programming Model
34
Data Types and Addressing Modes
40
Instruction Set Overview
40
Addressing Modes
41
Virtual Memory and Virtual Machine Concepts
42
Virtual Memory
42
Instruction Set
43
Virtual Machine
44
The Memory Management Unit
45
Pipelined Architecture
46
The Cache Memories
46
Data Organization and Addressing Capabilities
47
Instruction Operands
47
Organization of Data in Registers
48
Data Registers
48
Address Registers
50
Control Registers
50
Organization of Data in Memory
51
Addressing Modes
54
Data Register Direct Mode
55
Address Register Direct Mode
56
Address Register Indirect Mode
56
Address Register Indirect with Postincrement Mode
56
Address Register Indirect with Predecrement Mode
57
Address Register Indirect with Displacement Mode
58
Address Register Indirect with Index (8-Bit Displacement) Mode
58
Address Register Indirect with Index (Base Displacement) Mode
59
Memory Indirect Postindexed Mode
60
Memory Indirect Preindexed Mode
61
Program Counter Indirect with Displacement Mode
62
Mode
62
Program Counter Indirect with Index (Base Displacement) Mode
63
Program Counter Memory Indirect Postindexed Mode
64
Program Counter Memory Indirect Preindexed Mode
65
Absolute Short Addressing Mode
66
Absolute Long Addressing Mode
66
Immediate Data
67
Effective Address Encoding Summary
68
IS-Ills Memory Indirection Encodings
68
Programmer's View of Addressing Modes
70
Effective Addressing Mode Categories
70
Addressing Capabilities
71
General Addressing Mode Summary
77
M68000 Family Addressing Compatibility
82
Other Data Structures
82
System Stack
82
User Program Stacks
84
Queues
85
Instruction Set Summary
87
Instruction Format
87
Instruction Summary
88
Data Movement Instructions
90
Integer Arithmetic Instructions
91
Data Movement Operations
91
Logical Instructions
92
Integer Arithmetic Operations
92
Shift and Rotate Instructions
93
Logical Operations
93
Bit Manipulation Instructions
94
Shift and Rotate Operations
94
Bit Field Instructions
95
Bit Manipulation Operations
95
Bit Field Operations
95
Binary-Coded Decimal Instructions
96
BCD Operations
96
Program Control Instructions
97
Program Control Operations
97
System Control Instructions
98
System Control Operations
98
Memory Management Unit Instructions
99
Multiprocessor Instructions
99
Multiprocessor Operations (Read-Modify-Write)
99
Integer Condition Codes
100
Condition Code Computation
101
Condition Code Computations
101
Conditional Tests
103
Instruction Set Summary
104
Instruction Set Summary
106
Instruction Examples
111
Using the CAS and CAS2 Instructions
111
Nested Subroutine Calls
116
Bit Field Operations
117
Pipeline Synchronization with the NOP Instruction
118
Processing States
119
Privilege Levels
120
Supervisor Privilege Level
120
User Privilege Level
121
Changing Privilege Level
122
Address Space Types
123
Address Space Encodings
123
Exception Processing
124
Exception Vectors
124
Exception Stack Frame
125
Signal Description
127
Signal Index
128
Function Code Signals (FCO-FC2)
130
Address Bus (AO-A31)
130
Transfer Size Signals (SIZO, SIZ1)
130
Bus Control Signals
131
Operand Cycle Start (OCS)
131
External Cycle Start (ECS)
131
Read/Write (R/W)
131
Read-Modify-Write Cycle (RMC)
131
Address Strobe (AS)
131
Data Strobe (OS)
132
Synchronous Termination (STERM)
132
Cache Control Signals
133
Cache Inhibit Input (CIIN)
133
Cache Inhibit Output (Clodf)
133
Cache Burst Request (CBREQ)
133
Cache Burst Acknowledge (CBACK)
133
Interrupt Control Signals
134
Interrupt Priority Level Signals
134
Interrupt Pending (Lpend)
134
Autovector (AVEC)
134
Bus Arbitration Control Signals
134
Bus Request (BR)
134
Bus Grant (BG)
135
Bus Grant Acknowledge (BGACK)
135
Bus Exception Control Signals
135
Reset (RESET)
135
Halt (HALT)
135
Bus Error (BERR)
135
Emulator Support Signals
136
Cache Disable (Cisls)
136
MMU Disable (MMUDIS)
136
Pipeline Refill (Refill)
136
Internal Microsequencer Status (STATUS)
136
Clock (Clk)
137
Power Supply Connections
137
Signal Summary
137
Signal Summary
138
On-Chip Cache Memories
139
On-Chip Cache Organization and Operation
141
Instruction Cache
142
Data Cache
144
Write Allocation
146
Read-Modify-Write Accesses
148
Cache Filling
148
Single Entry Mode
148
Burst Mode Filling
153
Cache Reset
158
Cache Control
158
Cache Control Register
158
Write Allocate
159
Data Burst Enable
159
Clear Data Cache
159
Clear Entry in Data Cache
159
Freeze Data Cache
160
Enable Data Cache
160
Instruction Burst Enable
160
Clear Instruction Cache
160
Clear Entry in Instruction Cache
160
Freeze Instruction Cache
161
Enable Instruction Cache
161
Cache Address Register
161
Bus Operation
163
Bus Transfer Signals
163
Bus Control Signals
165
Address Bus
166
Address Strobe
166
Data Bus
167
Data Strobe
167
Data Buffer Enable
167
Bus Cycle.termination Signals
167
Data Transfer Mechanism
168
DSACK Codes and Results
169
Size Signal Encoding
171
Data Bus Requirements for Read Cycles
172
MC68030 Internal to External Data Bus Multiplexer - Write Cycles
173
Misaligned Operands
175
Effects of Dynamic Bus Sizing and Operand Misalignment
181
Memory Alignment and Port Size Influence on Write Bus Cycles
181
Address, Size, and Data Bus Relationships
184
MC68030 Versus MC68020 Dynamic Bus Sizing
186
Cache Filling
186
Asynchronous Operation
189
Synchronous Operation with Dsackx
190
Synchronous Operation with STERM
191
Data Transfer Cycles
192
Asynchronous Read Cycle
193
Asynchronous Write Cycle
199
Asynchronous Read-Modify-Write Cycle
205
Synchronous Read Cycle
210
MMU Instructions
365

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Motorola MC68030 User Manual

Motorola MC68030 User Manual (254 pages)

ENHANCED 32-BIT MICROPROCESSOR

Brand: Motorola | Category: Computer Hardware | Size: 0.88 MB

Table of Contents

Table of Contents
4
Adapting the MC68030 to MC68020 Designs
21
Microsequencer
22
Features
26
MC68030 Extensions to the M68000 Family
27
Programming Model
27
Translation Table Structure
31
Data Types and Addressing Modes
32
Instruction Set Overview
32
Virtual Memory
34
Virtual Memory and Virtual Machine Concepts
34
Virtual Machine
36
The Memory Management Unit
37
Pipelined Architecture
38
The Cache Memories
38
Data Organization and Addressing Capabilities

39
Instruction Set Summary

79
- Instruction Format
  79
- Instruction Summary
  80
  - Format
    80
  - Format
    81
- Data Movement Instructions
  82
- Integer Arithmetic Instructions
  83
- Logical Instructions
  84
- Shift and Rotate Instructions
  85
- Bit Manipulation Instructions
  86
- Bit Field Operations
  87
- Binary-Coded Decimal Instructions
  88
- Program Control Instructions
  89
- System Control Instructions
  90
  - Format
    90
- Memory Management Unit Instructions
  91
- Multiprocessor Instructions
  91
- Integer Condition Codes
  92
- Condition Code Computation
  93
- Conditional Tests
  95
- Instruction Set Summary
  96
- Scanpc
  99
- Instruction Examples
  103
- Using the CAS and CAS2 Instructions
  103
- Nested Subroutine Calls
  108
- Bit Field Operations
  109
- Pipeline Synchronization with the Nop Instruction
  110
Processing States

111
- Exceptions
  111
- Privilege Levels
  112
- Supervisor Privilege Level
  112
- User Privilege Level
  113
- Changing Privilege Level
  114
- Address Space Types
  115
- Exception Processing
  116
  - Exception Vectors
    116
  - Protocol Violations
    116
  - Exception Stack Frame
    117
Signal Description

118
- Interrupts
  118
- Signal Index
  119
- Address Bus (A0-A31)
  121
- Data Bus (D0-D31)
  121
- Function Code Signals (FC0-FC2)
  121
- Transfer Size Signals (SIZ0, SIZ1)
  121
- Bus Control Signals
  122
  - Operand Cycle Start (OCS)
    122
  - External Cycle Start (ECS)
    122
  - Read/Write (R/W)
    122
  - Read-Modify-Write Cycle (RMC)
    122
  - Address Strobe (AS)
    122
  - Data Strobe (DS)
    123
  - Data Buffer Enable (DBEN)
    123
  - Data Transfer and Size Acknowledge (DSACK0, DSACK1)
    123
  - Synchronous Termination (STERM)
    123
- Cache Control Signals
  124
  - Cache Inhibit Input (CIIN)
    124
  - Cache Inhibit Output (CIOUT)
    124
  - Cache Burst Request (CBREQ)
    124
  - Cache Burst Acknowledge (CBACK)
    124
- Bus Arbitration Control Signals
  125
  - Bus Request (BR)
    125
  - Bus Grant (BG)
    126
  - Bus Grant Acknowledge (BGACK)
    126
- Interrupt Control Signals
  125
  - Interrupt Priority Level Signals
    125
  - Interrupt Pending (IPEND)
    125
  - Autovector (AVEC)
    125
- Bus Exception Control Signals
  126
  - Reset (RESET)
    126
  - Halt (HALT)
    126
  - Bus Error (BERR)
    126
- Emulator Support Signals
  127
  - Cache Disable (CDIS)
    127
  - MMU Disable (MMUDIS)
    127
  - Pipeline Refill (REFILL)
    127
  - Internal Microsequencer Status (STATUS)
    127
- Clock (CLK)
  128
- Power Supply Connections
  128
- Signal Summary
  128
  - On-Chip Cache Memories
    130
  - Instruction Cache
    130
- On-Chip Cache Organization and Operation
  132
  - Protection
    132
  - Instruction Cache
    133
  - Registers
    134
  - Data Cache
    135
    
    Write Allocation
    137
    
    Read-Modify-Write Accesses
    138
  - Cache Filling
    138
    
    Single Entry Mode
    138
    
    Burst Mode Filling
    142
- Cache Control
  144
  - Cache Control Register
    144
    
    Write Allocate
    145
    
    Data Burst Enable
    145
    
    Clear Data Cache
    145
    
    Clear Entry in Data Cache
    145
    
    Freeze Data Cache
    146
    
    Enable Data Cache
    146
    
    Instruction Burst Enable
    146
    
    Clear Instruction Cache
    146
    
    Clear Entry in Instruction Cache
    146
    
    Freeze Instruction Cache
    147
    
    Enable Instruction Cache
    147
  - Cache Address Register
    147
    
    Bus Operation
    148
- Cache Reset
  144
- Bus Transfer Signals
  148
  - Bus Control Signals
    150
  - Address Bus
    151
  - Address Strobe
    151
  - Data Bus
    152
  - Data Strobe
    152
  - Data Buffer Enable
    152
  - Bus Cycle Termination Signals
    152
- Data Transfer Mechanism
  153
  - Dynamic Bus Sizing
    153
  - Misaligned Operands
    160
  - Effects of Dynamic Bus Sizing and Operand Misalignment
    166
  - Address, Size, and Data Bus Relationships
    169
  - MC68030 Versus MC68020 Dynamic Bus Sizing
    171
  - Cache Filling
    171
  - Cache Interactions
    172
  - Asynchronous Operation
    174
  - Synchronous Operation with Dsackx
    175
  - Synchronous Operation with STERM
    176
- Data Transfer Cycles
  177
  - Asynchronous Read Cycle
    178
  - Asynchronous Write Cycle
    184
  - Asynchronous Read-Modify-Write Cycle
    191
  - Synchronous Read Cycle
    196
  - Synchronous Write Cycle
    199
  - Memory Interface
    199
  - Synchronous Read-Modify-Write Cycle
    202
  - Burst Operation Cycles
    207
- CPU Space Cycles
  216
- Bus Exception Control Cycles
  223
  - Bus Errors
    230
  - External Caches
    231
  - Retry Operation
    237
  - Halt Operation
    239
  - Double Bus Fault
    242
- Bus Synchronization
  243
- Bus Arbitration
  244
  - Bus Request
    246
  - Bus Grant
    247
  - Bus Grant Acknowledge
    248
  - Bus Arbitration Control
    248
- Reset Operation
  251

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