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Computer Hardware
MC68030
User manual
Motorola MC68030 User Manual
Enhanced 32-811 microprocessor
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User manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Introduction
Features
MC68030 Extensions to the M68000 Family
Programming Model
Data Types and Addressing Modes
Instruction Set Overview
Addressing Modes
Virtual Memory and Virtual Machine Concepts
Virtual Memory
Instruction Set
Virtual Machine
The Memory Management Unit
Pipelined Architecture
The Cache Memories
Data Organization and Addressing Capabilities
Instruction Operands
Organization of Data in Registers
Data Registers
Address Registers
Control Registers
Organization of Data in Memory
Addressing Modes
Data Register Direct Mode
Address Register Direct Mode
Address Register Indirect Mode
Address Register Indirect with Postincrement Mode
Address Register Indirect with Predecrement Mode
Address Register Indirect with Displacement Mode
Address Register Indirect with Index (8-Bit Displacement) Mode
Address Register Indirect with Index (Base Displacement) Mode
Memory Indirect Postindexed Mode
Memory Indirect Preindexed Mode
Program Counter Indirect with Displacement Mode
Mode
Program Counter Indirect with Index (Base Displacement) Mode
Program Counter Memory Indirect Postindexed Mode
Program Counter Memory Indirect Preindexed Mode
Absolute Short Addressing Mode
Absolute Long Addressing Mode
Immediate Data
Effective Address Encoding Summary
IS-Ills Memory Indirection Encodings
Programmer's View of Addressing Modes
Effective Addressing Mode Categories
Addressing Capabilities
General Addressing Mode Summary
M68000 Family Addressing Compatibility
Other Data Structures
System Stack
User Program Stacks
Queues
Instruction Set Summary
Instruction Format
Instruction Summary
Data Movement Instructions
Integer Arithmetic Instructions
Data Movement Operations
Logical Instructions
Integer Arithmetic Operations
Shift and Rotate Instructions
Logical Operations
Bit Manipulation Instructions
Shift and Rotate Operations
Bit Field Instructions
Bit Manipulation Operations
Bit Field Operations
Binary-Coded Decimal Instructions
BCD Operations
Program Control Instructions
Program Control Operations
System Control Instructions
System Control Operations
Memory Management Unit Instructions
Multiprocessor Instructions
Multiprocessor Operations (Read-Modify-Write)
Integer Condition Codes
Condition Code Computation
Condition Code Computations
Conditional Tests
Instruction Set Summary
Instruction Set Summary
Instruction Examples
Using the CAS and CAS2 Instructions
Nested Subroutine Calls
Bit Field Operations
Pipeline Synchronization with the NOP Instruction
Processing States
Privilege Levels
Supervisor Privilege Level
User Privilege Level
Changing Privilege Level
Address Space Types
Address Space Encodings
Exception Processing
Exception Vectors
Exception Stack Frame
Signal Description
Signal Index
Function Code Signals (FCO-FC2)
Address Bus (AO-A31)
Transfer Size Signals (SIZO, SIZ1)
Bus Control Signals
Operand Cycle Start (OCS)
External Cycle Start (ECS)
Read/Write (R/W)
Read-Modify-Write Cycle (RMC)
Address Strobe (AS)
Data Strobe (OS)
Synchronous Termination (STERM)
Cache Control Signals
Cache Inhibit Input (CIIN)
Cache Inhibit Output (Clodf)
Cache Burst Request (CBREQ)
Cache Burst Acknowledge (CBACK)
Interrupt Control Signals
Interrupt Priority Level Signals
Interrupt Pending (Lpend)
Autovector (AVEC)
Bus Arbitration Control Signals
Bus Request (BR)
Bus Grant (BG)
Bus Grant Acknowledge (BGACK)
Bus Exception Control Signals
Reset (RESET)
Halt (HALT)
Bus Error (BERR)
Emulator Support Signals
Cache Disable (Cisls)
MMU Disable (MMUDIS)
Pipeline Refill (Refill)
Internal Microsequencer Status (STATUS)
Clock (Clk)
Power Supply Connections
Signal Summary
Signal Summary
On-Chip Cache Memories
On-Chip Cache Organization and Operation
Instruction Cache
Data Cache
Write Allocation
Read-Modify-Write Accesses
Cache Filling
Single Entry Mode
Burst Mode Filling
Cache Reset
Cache Control
Cache Control Register
Write Allocate
Data Burst Enable
Clear Data Cache
Clear Entry in Data Cache
Freeze Data Cache
Enable Data Cache
Instruction Burst Enable
Clear Instruction Cache
Clear Entry in Instruction Cache
Freeze Instruction Cache
Enable Instruction Cache
Cache Address Register
Bus Operation
Bus Transfer Signals
Bus Control Signals
Address Bus
Address Strobe
Data Bus
Data Strobe
Data Buffer Enable
Bus Cycle.termination Signals
Data Transfer Mechanism
DSACK Codes and Results
Size Signal Encoding
Data Bus Requirements for Read Cycles
MC68030 Internal to External Data Bus Multiplexer - Write Cycles
Misaligned Operands
Effects of Dynamic Bus Sizing and Operand Misalignment
Memory Alignment and Port Size Influence on Write Bus Cycles
Address, Size, and Data Bus Relationships
MC68030 Versus MC68020 Dynamic Bus Sizing
Cache Filling
Asynchronous Operation
Synchronous Operation with Dsackx
Synchronous Operation with STERM
Data Transfer Cycles
Asynchronous Read Cycle
Asynchronous Write Cycle
Asynchronous Read-Modify-Write Cycle
Synchronous Read Cycle
MMU Instructions
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ENHANCED 32-BIT
MICROPROCESSOR
USER'S MANUAL
THIRD EDITIO
®
MOTOROLA
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