Table of Contents
Advertisement
KBR0, KBR1, KBR2, KBR3, KBR4
H2, H1, H3. G3, G5
to Keyboard
KBC0, KBC1, KBC2, KBC3, KBC4
J1, J2, J3, J4, J5
K3
BKLT_EN
to Display
DP_EN_L
A11
SIMPD0
A4
V2
LS1_IN
E9
LS2_IN
E7
F3
SIM_TX
BATT_THERM_AD
B5
SIM_RX
Q905
VIB_EN
K1
EXT_CHG_EN
C2
HEAD_INT_L
A1
N3
C1
A1
CLK_SELCT
C1
E2
TX_EN
DM_CS
E2
E1
E1
TX_KEY
E3
E3
RX_EN
E4
E4
RX_ACQ
P2
P2
RESET
( SDTX ) BDX
B6
( TX_CLK ) BCLKX
B3
from / to MAGIC
BCLKR
B4
( SDFS ) BFSR
D4
( SDRX ) BDR
A3
15 PIN EXT CONN.
J 600
K2
DSC_EN
13
7
RS232_RX
A5
6
A6
RS232_TX
4
BATT_FDBK
from Charger
2
MO_ST
N/C
8
RS232_EN
14
EXT_B+
EXT_B+
5
MAN_TEST_AD
1
GND
DSC_EN_AD
3
GND
DOWNLINK_AD
BATT_THERM_AD
GND
10
15
GND
9
ON / OFF
RESET
11
UPLINK
12
DOWNLINK
HEADSET
2
1
CON.
J504
V2
OPEN
R976
HEAD_INT_L
R977
V100 - BLOCK DIAGRAM - PAGE 2/2
VDDS
C14, F10, G4, H4, K5, P13
VCC_MEMIF
VDD
A9, A10, C5, K6, K10, M8, M11
KEYPAD
DISPLAY
WHITE_CAP
VCCA
INTERFACE
SPI
INTERFACE
SIM
INTER
M
U800
E
FACE
M
O
R
Y
I
CPU
N
CTM
C9
T
MODULE
E
E10
R
B11
F
A
C
D9
E
B9
SERIAL
INTER
DSP
F1
FACE
CTM
STBY_DL
H5
BATT_SER_DATA
PB6
DSC
CHARGE
L7
L6
BATT_FDBK
UART
to J600
SPI
TIMER
INTERF.
INTERFACE
B7
P4
H10
EXT_B+
MIDRATE_1
MIDRATE_2
ISENSE
F5
A7 B7
D9
C7
CHARGE
E8
D6
SPI
REAL TIME
SELECT F10
INTERFACE
CLOCK
F7
SENSE
D10
F6
U900
A1
LEVEL
J7
B2
SENSE
SHIFT
A2
J8
G_CAP2
B3
CNTL.
K7
G6
K10
H8
ON_2
G5
C8
C4
G4
Logic Control
VREF
D2
REG.
C2
V3
REG.
V2
REG.
V1
REG.
VSIM
Interface
REG.
Audio
H3
E18
Codec
VBOOST1
A5
REG.
H9
K6
H6 H7 K9
J9
E1
B10
SPR-
SR_VCC
4
CR902
5-8
1-3
Q903
L901
ALRT
ALRT_VCC
B+
V2
V3
MAGIC SPI
ADDRESS BUS
DATA BUS
SR_VCC
D6, E1
V2
CE2
B2
U702
RESET
CE3
A1
SRAM
R_W
G5
R_W
CE0
CE1
For description of Midrate Charger
BATT CON.
see document on:
J604
1
http://gsm-service.fle.css.mot.com/
2
4
3
B+
CHRG_EN
BATT+
4
2
3
Q902
CR903
1,2,5,6
1-3
4
6-8
Q905
Q901
3
4
4,6
2
2
4
Q909
Q904
5
3
7,8
R913
Q900
4
CHRGC
MAIN_FET
BATT+
EXT_B+
CLK
1
J803
RESET
SIM
2
Con.
SIM_I/O
6
3
4
VSIM1
LS1_IN
LS2_IN
SIM_TX
CLK_SELECT
SIM_RX
PWR_SW
STBY_DL
G9
VREF
2.775V,for Magic P1
B5
V3
1,8V, for WhiteCap
J5
V2
2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM
A6
V1
5.0V, for DSC Bus, Negative Voltage Regulator
C6
VSIM1
3.0 or 5.0V, for SIM Card Circuit
C5, B6
A10, C10
V_BOOST1
Internal GCap use only (VSIM1, LS_V1)
to Backlight
ALRT_VCC
P1
to MAGIC
A4, E1, F5
B4
U701
EPROM
EEPROM
B3
D7
F8
4
1
GND
U904
-10V
KBR0, KBR1, KBR2,
V1
U903
-5V
2
KBC0, KBC1, KBC2
1
BATT_SER_DATA
BATT_THERM_AD
VREF
STBY_DL
DEEP SLEEP
V1_SW
V1
V2
CIRCUIT
B+
1 - 10
( WhiteCap )
VIB_EN
N/C
11, 37
B+
12, 13, 15
17, 19, 21
23, 25, 27
28, 30, 32
34, 35, 36
38, 39, 40
41, 42, 43
44, 45, 47
48, 50, 52
53, 54, 56
58, 60 , 62
64, 66, 69
70, 71, 72
14
MAGIC 13Mhz
46
MQSPI_CS1
16
51
MQSPI_CLK
55
VREF
18
BDX
-5V
57
BCLKX
20
59
BCLKR
22
TX_EN
24
61
TX_KEY
BDR
63
STBY_DL
BFSR
26
65
V1_SW
RX_EN
29
-10V
67
DM_CS
33
V1
68
RX_ACQ
J1
Inter-PCB Connector
J902
Backlight
ALERT_VCC
27
LCD
26
BKLT_EN
A0
3
D0-D7
5-12
V1-V5
INT.
C702-C706
DIV.
13
V2
RESET
2
14
GND
R_W
4
DP_EN_L
15
( -10V )
1
KBR3, KBR4
KEYPAD
KBC3, KBC4
PWR_SW
from G CAP2
BACK
ALERT_VCC
LIGHT
from G CAP2
C
B
BKLT_EN
Q907
from WhiteCap
E
M1
1
4
U510
5
VIB MOTOR
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
Advertisement
Table of Contents
Troubleshooting
