Sharp 64LHP5000 Service Manual page 83

Pin No. Pin Name
46 AVDD
47 FSCO
48 AGND
49 AGND
50 FSCI
51 CPLL
52 RPLL
53 AVDD
54 CKMD
55 DGND
56 CLK8
57 RSTB
58 SLA0
59 SCL
60 SDA
61 ST0
62 ST1
63 NSTD
64 DVDD
DYCO0
65
(LSB)-(MSB)
DYCO1
66
(LSB)-(MSB)
DYCO2
67
(LSB)-(MSB)
DYCO3
68
(LSB)-(MSB)
DYCO4
69
(LSB)-(MSB)
DYCO5
70
(LSB)-(MSB)
DYCO6
71
(LSB)-(MSB)
DYCO7
72
(LSB)-(MSB)
DYCO8
73
(LSB)-(MSB)
DYCO9
74
(LSB)-(MSB)
75 ALTF
76 CSI
77 TEST
78 LINE
79 KIL
I/O
fsc generator DAC block power supply
–
fsc generator fsc output
–
fsc generator DAC block ground
–
8fsc-PLL ground
–
8fsc-PLL fsc input
–
8fsc-PLL filter output (Opened or connected to GND)
–
8fsc-PLL frequency compensation output
–
8fsc-PLL power supply
–
Clock mode test input (Opened or connected to GND)
I
Digital block ground
–
8fsc clock output
O
System reset input (Active Low) (Inputs active low reset pulses from outside)
I
I 2 C bus slave address selection input (L:B8/B9h, H:BA/BBh)
I
I 2 C bus clock input (Connected to system SCL line)
I
I 2 C bus data input/output (Connected to system SDA line)
I/O
Internal signal monitor output
O
Internal signal monitor output
O
Non-standard detection monitor output (L:Standard determination, H:Non-standard determination)
O
Digital block power supply
–
I/O
I/O
I/O
I/O
I/O
EXADINS=0, digital YC signal alternate output
EXADINS=1, external Y-ADC data input
I/O
I/O
I/O
I/O
I/O
EXADINS=0, digital YC signal alternate flag output (LY, HC)
O
EXADINS=1, external Y-ADC 4fsc clock output
Composite sync input (Active low)
I
IC selection test pin (Opened or connected to GND)
I
Forced inter-line processing selection input (L:Normal processing, H:Forced inter-line processing)
I
External killer input (L:Normal processing, H:Forced YC separation stop)
I
83
Function
64LHP5000
PROJECTOR UNIT