9-2. IC303 IX1517GE
Pin No. Terminal name
I/O
1
GND
–
2
P2TP
3
P2TN
4
LDO2
O Drive ouput
5
MDI2
6
VrA
O Analog VREF
7
VrD
O Digital VREF
8
Vdd
9
DPAC
–
10
DPBD
–
11
DPD1
–
12
DPD2
–
13
SCB
14
SCL
15
SCD
16
VRCK
17
VCKF
–
18
VccP
–
19
LVL
O Servo addition output
20
TEO
O TE output
21
FEO
O FE output
22
DFTN
23
VccS
–
24
RPZ
O RF ripple center voltage
25
RPO
O RF ripple output
26
RPB
O RF ripple bottom
27
RPP
O RF ripple peak
28
RFO
O Equalizing RF output
29
NC
–
30
NC
–
31
VccR
–
32
DPDB
33
TEB
34
FEB
35
PSC
36
Vcc2
–
37
NC
–
38
EQD
39
GND2
–
40
RFDC
–
41
RFA
O RF total addition output
42
EQB
43
EQF
44
MDI1
45
LDO1
O Drive output
46
P1TN
47
P1TP
48
NC
–
49
P1FN
50
P1FP
51
LDP1
52
P1DI
RF SIGNAL PROCESSOR
Operation function
GND terminal.
I
TE+input (CD)
I
TE–input (CD)
I
Monitor input
I
Power terminal
DPD AC combination capacity 1
DPD AC combination capacity 2
DPD integral capacity 1
DPD integral capacity 2
I
Control line (Bit clock)
I
Control line (Latch signal)
I
Control line (Sirial Data)
I
Reference clock input
Capacity for time constant adjustment
Power terminal
I
DPD difect
Power terminal (servo)
NC terminal
NC terminal
Power terminal (RF)
I
Pit depth adjustment
I
TE balance
I
FE balance
I
VRCK frequency division ON/OFF
Power terminal
NC terminal
I
Group delay correction
GND terminal.
DC feedback capacity
I
Boost adjustment
I
Frequency adjustment
I
Monitor input
I
TE–input (DVD)
I
TE+input (DVD)
NC terminal
I
FE–input (DVD)
I
FE+input (DVD)
I
APC polarity 1
I
D input (DVD)
Terminal DC Voltage(TYP.)
–
VrA
VrA
–
–
2.1[V]
–
–
–
–
–
2.2[V]
2.2[V]
2.2[V]
2.3[V]
–
–
Vrd x (1/2)
VrD
VrD
–
–
VrD
VrD
–
–
2.3[V]
–
–
–
VrD
VrD
VrD
–
–
VrD
VrD
–
–
2.2[V]
VrD
VrD
–
–
VrA
VrA
–
VrA
VrA
–
21
Remarks
Vdd 1/2
4.2V (3.3V)
When frequency is increased, the
filters excepting the servo LPF are
shifted to high frequency side.
Low DPD output: Mute
To be connected to GND
To be connected to GND
When D PDB is raised, the A/B
side delay increases.
When TEB is raised, the TP side
gain increases and the A+C side
delay increases.
When FEB is raised, the A+C (FP)
side gain increases.
High: Frequency division OFF
To be connected to VrD, or to GND
through C
When EQD is raised, the group
delay increases at the right side.
When EQB is raised, the boost increases.
When EQF is raised, shift to the
high frequency side occurs.
To be connected to GND
Positive polarity when this terminal
is connected to Vcc.
DV-L70S
DV-L70BL
DV-L70W