Sharp DV-L70S Service Manual page 32

DV-L70S
DV-L70BL
DV-L70W
9-10. IC602 IX0750TA
Terminal Name
Terminal
35 CLK
18 CS
34 CKE
21~24 A0~A10/AP
27~32
20
19 BA
17 RAS
16 CAS
15 WE
14, 36 DOML(U)
2, 3, 5, DQ0~15
6, 8, 9, 11, 12, 39, 40,
42, 43, 45, 46, 48, 49
Vcc/Vss
25, 1/26, 50
Vcc/VssO
44, 38, 13, 7/4, 10, 41, 47
33, 37 NC/RFU
• Block Diagram
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground Isolated power supply and ground for the output buffers to provide
No Connection/
Reserved for Future Use
Self Refresh Counter
Refresh Refresh
Interval Timer Counter
Address[0:10]
CLK
Precharge Address
CKE
Register
Row Active
BA(A11)
Column Active
CS
RAS
Burst Length
CAS
Counter
WE
UDQM
LDQM
Mode Register
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs
except CLK. CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in stanby.
Row/column address are multiplexed on the same pins.
Row address: RA0~RA10, column address: CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during clumn address latch time.
Latches row address on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches addresses on the positive going edge of the CLK with CAS low.
Enables row access.
Enable write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tsHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
improved noise immunity.
This pin is recommanded to be left No Connection on the device
512K x 16
Bank 0
Sense AMP & I/O gates
Column Decoder
Column Addr.
Latch & Counter
Overflow
Column Decoder
Sense AMP & I/O gates
512K x 16
Bank 1
Test Mode
32
Input Function
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O Control