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DV-L70S
DV-L70BL
DV-L70W
Pin1~15 ........ There is a possibility of simultaneous change.
Pin18~47 ..... There is a possibility of simultaneous change.(Static signal)
Pin50~57 ..... There is almost no possibility of simultaneous change.
Pin63 ............ Not used
• Block Diagram
VDD
SOUT(3)
SOUT(4)
SOUT(5)
MRST
MODE
SEL
TEST
CK
VSS
In/Output Pin
48
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD
49
EXPD(3)
50
Data Buffer
EXPD(4)
51
Latch D
EXPD(5)
52
BUFDO
53
BUFDI
54
SBUFBO
55
SBUFBI
56
57
SBUFAO
58
SBUFAI
59
MRST
60
MODE
61
BUFCO
62
TEST
63
BUFCI
R/W CTL
64
VSS
1
2
3
4
5
Input Pin
Operating frequency: Approx. 10 MHz
Operating frequency: Approx. 1 MHz
Operating frequency: Approx. 1 MHz
In/Output Pin
Output:
Open drain
In/Output Pin
Data Buffer
Latch C
Data Buffer
6
7
8
9
10
11
12
13
14
15
In/Output Pin
Output: Open drain
28
32
VSS
VSS
31
EXPBL(3)
Q2(3)
30
Q2(2)
EXPBL(2)
29
EXPBL(1)
Q2(1)
28
EXPBL(0)
Q2(0)
27
EXPAU(3)
Q1(7)
26
EXPAU(2)
Q1(6)
25
VDD
VDD
24
VSS
VSS
23
EXPAU(1)
Q1(5)
22
EXPAU(0)
Q1(4)
21
EXPAL(3)
Q1(3)
20
EXPAL(2)
Q1(2)
19
EXPAL(1)
Q1(1)
18
EXPAL(0)
Q1(0)
17
VDD
VDD
16
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