Motorola MSC8101 ADS User Manual page 104

CONSTANT TCPC_DEFAULT0
CONSTANT TCPC_DEFAULT1
CONSTANT BC1PC_DEFAULT0
CONSTANT BC1PC_DEFAULT1
CONSTANT RSVHR26
-- CONSTANT DLLDIS_DEFAULT= 0;
CONSTANT RSVHR31
SUBDESIGN bcsr
(
clock,
ExtClk,
CS1~,
W_R~,
A[27..29], A7,A8
EE0, EE1, EE2, EE3, EE4, EE5, EED
DBGEN~,
BTM0,
BTM1,
PRST~,
RstSoft~,
RstHard~,
RstNMI~
R_PORI~
MODCK[1..3],-- MODCK dip-switch bits 1 through 3
MODCK_H[1..3] -- MODCK dip-switch bits 4 through 6
MODCK_BNK[0..2],-- SDRAM BANK SELECT
NMI~ : OUTPUT;
HDSP,
H8BIT,
HOSTPD,
HOSTCFG~ : INPUT;
HDIMDEN~,
RSTCNF~
SRESET~,
HRESET~
HDILED~,
BPOE~,
WE0,
PSDVAL~
TEA~ : OUTPUT;
F_CFG_EN~,
F_CS0~,
AtmUniCsIn~,
ToolCs1~,
ToolCs2~,
FrmCs_In~,
DLLDIS
FrmCs_Out~,
ToolDataBufEn~,
DataBufEn~,
BCSR2_CS~,
MOTOROLA
Freescale Semiconductor, Inc.
= 1;
= 0;
= 0;
= 0;
= 0;
-- Get value from DIP-Switch
= 0;
-- Flash address
: INPUT;
-- EE pins
: BIDIR;
-- Power-on-Reset for Altera only
-- connected to SoftReset P.B.
-- connected to HardReset P.B.
: INPUT;
: BIDIR; -- Regular Power-On-Reset from voltage detector.
: INPUT;
-- HOST RD/WR polarity
-- HOST SPARE
-- HOST PRESENCE DETECT
-- HOSTCFG signal from DIP-SW
-- HOST SW ENABLE
: OUTPUT; -- RESET CONFIG to 8101
-- Soft Reset (O.D.)
: BIDIR; -- Hard Reset (O.D.)
-- HOST LED (O.D.)
-- FLASH OE *** Option ***
-- WE0
-- PSDVAL *** Option ***
: BIDIR;
-- Transfer Error Acknowledge (O.D.) *** Option ***
-- Flash Config Enable from Ext. Switch
-- Flash CS from DSP
-- ATM Framer CS from DSP
-- Ext Tool CS line 1.
-- Ext Tool CS line 2.
-- T1/E1 Framer CS from DSP.
-- Input from jumper JP1 for DLL bypass when open
: INPUT;
-- Framer CS out to Framer.
-- Enable for Tool Buffers.
-- Enable for Data Bus Buffers to/from ALTERA.
-- Enable for Status Buffer
MSC8101ADS RevB User's Manual
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-- External/Osc clock for EEinit (BCSR3)
-- BCSR SELECT From DSP
-- Debug Enable from Dip-SW (Defines Boot EE0)
-- EE4 from Dip-SW (Defines Boot EE4)
-- EE5 from Dip-SW (Defines Boot EE5)
-- connected to Abort(NMI) pushbutton
(Active LOW)
*** Option ***
C-103