LG 65EF9500 Service Manual page 64

URSA11_DDR_SAMSUNG
IC13001
K4B1G1646G-BCMA
U_MVREFCA_A0
N3 M8
A_DDR3_A[0]
A0 VREFCA
P7
A_DDR3_A[1] A1
P3
A_DDR3_A[2] A2
N2 H1
A_DDR3_A[3]
A3 VREFDQ
P8
A_DDR3_A[4] A4
P2
A_DDR3_A[5] A5
R8 L8 R13016 240
A_DDR3_A[6]
A6 ZQ
R2 1%
A_DDR3_A[7] A7
T8 +1.5V_U_DDR
A_DDR3_A[8] A8
R3 B2
A_DDR3_A[9]
A9 VDD_1
L7 D9
A_DDR3_A[10] A10/AP VDD_2
R7 G7
A_DDR3_A[11] A11 VDD_3
N7 K2
A_DDR3_A[12] A12/BC VDD_4
T3 K8
A_DDR3_A[13] A13 VDD_5
N1
VDD_6
M7 N9
A_DDR3_A[15] NC_5 VDD_7
R1
VDD_8
M2 R9
BA0 VDD_9
A_DDR3_BA[0]
N8
A_DDR3_BA[1] BA1 +1.5V_U_DDR
M3
A_DDR3_MCLK
A_DDR3_BA[2] BA2
C13062 A1
VDDQ_1
J7 A8
0.01uF
CK VDDQ_2
K7 C1
A_DDR3_MCLKZ CK VDDQ_3
K9 C9
A_DDR3_CKE CKE VDDQ_4
D2
VDDQ_5
L2 E9
A_DDR3_CSB1 CS VDDQ_6
K1 F1
A_DDR3_ODT ODT VDDQ_7
J3 H2
A_DDR3_RASZ RAS VDDQ_8
K3 H9
A_DDR3_CASZ CAS VDDQ_9
L3
A_DDR3_WEZ WE
J1
NC_1
T2 J9
A_DDR3_RESET RESET NC_2
L1
NC_3
L9
NC_4
F3 T7
A_DDR3_DQS0 DQSL NC_6 A_DDR3_A[14]
G3
A_DDR3_DQS0B DQSL
C7 A9
A_DDR3_DQS1 DQSU VSS_1
B7 B3
A_DDR3_DQS1B DQSU VSS_2
E1
VSS_3
E7 G8
A_DDR3_DM0 DML VSS_4
D3 J2
A_DDR3_DM1 DMU VSS_5
J8
A_DDR3_DQ[0-15] VSS_6
A_DDR3_DQ[0] E3 M1
DQL0 VSS_7
A_DDR3_DQ[1] F7 M9
DQL1 VSS_8
A_DDR3_DQ[2] F2 P1
DQL2 VSS_9
A_DDR3_DQ[3] F8 P9
DQL3 VSS_10
A_DDR3_DQ[4] H3 T1
DQL4 VSS_11
A_DDR3_DQ[5] H8 T9
DQL5 VSS_12
A_DDR3_DQ[6] G2
DQL6
A_DDR3_DQ[7] H7
DQL7
B1
VSSQ_1
A_DDR3_DQ[8] D7 B9
DQU0 VSSQ_2
A_DDR3_DQ[9] C3 D1
DQU1 VSSQ_3
C8 D8
A_DDR3_DQ[10]
DQU2 VSSQ_4
A_DDR3_DQ[11] C2 E2
DQU3 VSSQ_5
A_DDR3_DQ[12] A7 E8
DQU4 VSSQ_6
A2 F9
A_DDR3_DQ[13]
DQU5 VSSQ_7
A_DDR3_DQ[14] B8 G1
DQU6 VSSQ_8
A_DDR3_DQ[15] A3 G9
DQU7 VSSQ_9
* DDR_VTT
+1.5V_U_DDR
IC13000
AP2303MPTR-G1 [EP]
VIN NC_3
1 8
C13019
10uF
DDR_VTT_URSA
10V GND NC_2
2 7
VREFEN VCNTL
L13000 3 6
CIS21J121
1% 100K
R13001
VOUT NC_1
4 5
C13004 C13009 C13014
10uF 10uF 10uF
10V 10V 10V
+1.5V_U_DDR
C13000 C13005 C13010 C13015 C13022 C13025 C13029
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Close to DDR POWER PIN
+1.5V_U_DDR
C13001 C13006 C13011 C13016 C13023 C13026 C13030 C13033
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Close to DDR POWER PIN
+1.5V_U_DDR
C13003 C13007
C13012 C13017 C13021 C13027
C13031
0.1uF 0.1uF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V
Close to DDR POWER PIN
+1.5V_U_DDR
C13008 C13013 C13018 C13024 C13028 C13032
C13002
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
0.1uF
16V 16V 16V 16V 16V 16V 16V
Close to DDR POWER PIN
15/01/21
Copyright 2015 LG Electronics Inc. All rights reserved.
Only for training and service purposes
DDR_VTT_URSA_1
URSA11_DDR_SAMSUNG
AR13000 AR13001 AR13002 AR13003 AR13004 AR13005 AR13006
56 56 56 56 56 56 56
IC13002
K4B1G1646G-BCMA
N3
A_DDR3_A[0] A0
P7
A_DDR3_A[1] A1
P3
A_DDR3_A[2]
A2
N2
A_DDR3_A[3] A3
P8
A_DDR3_A[4] A4
P2
A_DDR3_A[5]
A5
R8
A_DDR3_A[6] A6
R2
A_DDR3_A[7] A7
T8
A_DDR3_A[8]
A8
R3
A_DDR3_A[9] A9
L7
A_DDR3_A[10] A10/AP
R7
A_DDR3_A[11]
A11
N7
A_DDR3_A[12] A12/BC
T3
A_DDR3_A[13] A13
A_DDR3_A[14]
M7
A_DDR3_A[15] NC_5
M2
A_DDR3_BA[0] BA0
N8
A_DDR3_BA[1] BA1
M3
A_DDR3_BA[2] BA2
J7
A_DDR3_MCLK CK
K7
A_DDR3_MCLKZ CK
K9
A_DDR3_CKE CKE
L2
CS
A_DDR3_CSB2
K1
A_DDR3_ODT ODT
J3
A_DDR3_RASZ RAS
K3
A_DDR3_CASZ CAS
L3
A_DDR3_WEZ WE
T2
A_DDR3_RESET RESET
F3
A_DDR3_DQS2 DQSL
G3
A_DDR3_DQS2B DQSL
C7
A_DDR3_DQS3 DQSU
B7
A_DDR3_DQS3B DQSU
E7
A_DDR3_DM2 DML
D3
A_DDR3_DM3 DMU
A_DDR3_DQ[16-31]
A_DDR3_DQ[16] E3
DQL0
A_DDR3_DQ[17] F7
DQL1
F2
A_DDR3_DQ[18]
DQL2
A_DDR3_DQ[19] F8
DQL3
A_DDR3_DQ[20] H3
DQL4
H8
A_DDR3_DQ[21]
DQL5
A_DDR3_DQ[22] G2
DQL6
A_DDR3_DQ[23] H7
DQL7
A_DDR3_DQ[24] D7
DQU0
A_DDR3_DQ[25] C3
DQU1
A_DDR3_DQ[26] C8
DQU2
A_DDR3_DQ[27] C2
DQU3
A_DDR3_DQ[28] A7
DQU4
A_DDR3_DQ[29] A2
DQU5
A_DDR3_DQ[30] B8
DQU6
A_DDR3_DQ[31] A3
DQU7
DDR PHY VREF
+1.5V_U_DDR +1.5V_U_DDR
U_MVREFCA_A0
+3.3V_NORMAL
R13009
R13012
1K
C13039 1K
L13001
10uF 1% 1%
CIS21J121 10V
R13010 C13055 C13059
R13013
1K
0.1uF 1000pF 1K
1% 1%
Decap removed
DDR_VTT_URSA DDR_VTT_URSA_1
L13002
BLM18PG121SN1D
C13049 C13050 C13051 C13052 C13056
1uF 0.1uF 0.1uF 0.1uF 0.1uF
10V 16V 16V
16V 16V
+1.5V_U_DDR A_DDR3_CKE
C13036
0.1uF R13011
R13004
1K
1K
A_DDR3_RESET
C13034 C13037 C13040 C13042 C13044 C13046 C13048
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V
16V 16V 16V 16V 16V 16V
C13035 C13038 C13041 C13043 C13045 C13047
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V
URSA11_DDR_NANYA
IC13001-*1
U_MVREFCA_A1 NT5CB64M16FP-EK
M8
VREFCA
N3 M8
A0 VREFCA
P7
A1
H1 P3
VREFDQ A2
N2 H1
A3 VREFDQ
P8
A4
L8 R13017 240 P2
ZQ A5
R8 L8
1% +1.5V_U_DDR
A6 ZQ
R2
A7
B2 T8
VDD_1 A8
D9 R3 B2
VDD_2 A9 VDD_1
L7 D9
G7
A10/AP VDD_2
VDD_3
K2 R7 G7
VDD_4 A11 VDD_3
K8 N7 K2
VDD_5 A12/BC VDD_4
T3 K8
N1
NC_6 VDD_5
VDD_6
N9 N1
VDD_7 VDD_6
R1 M7 N9
VDD_8 NC_5 VDD_7
R9 R1
VDD_8
VDD_9
M2 R9
+1.5V_U_DDR
BA0 VDD_9
N8
BA1
A1 M3
BA2
VDDQ_1
A8 A1
VDDQ_2 VDDQ_1
J7 A8
C1
VDDQ_3 CK VDDQ_2
C9 K7 C1
VDDQ_4 CK VDDQ_3
D2 K9 C9
VDDQ_5 CKE VDDQ_4
D2
E9
VDDQ_6 VDDQ_5
F1 L2 E9
VDDQ_7 CS VDDQ_6
H2 K1 F1
VDDQ_8 ODT VDDQ_7
J3 H2
H9
RAS VDDQ_8
VDDQ_9
K3 H9
CAS VDDQ_9
J1 L3
NC_1 WE
J1
J9
NC_1
NC_2
L1 T2 J9
NC_3 RESET NC_2
L9 L1
NC_4 NC_3
L9
T7
A_DDR3_A[14] NC_4
NC_6
F3 T7
DQSL NC_7
G3
DQSL
A9
VSS_1
B3 C7 A9
VSS_2 DQSU VSS_1
E1 B7 B3
VSS_3 DQSU VSS_2
E1
G8
VSS_3
VSS_4
J2 E7 G8
VSS_5 DML VSS_4
J8 D3 J2
VSS_6 DMU VSS_5
J8
M1
VSS_6
VSS_7
M9 E3 M1
VSS_8 DQL0 VSS_7
P1 F7 M9
VSS_9 DQL1 VSS_8
P9 F2 P1
DQL2 VSS_9
VSS_10
T1 F8 P9
VSS_11 DQL3 VSS_10
H3 T1
T9
VSS_12 DQL4 VSS_11
H8 T9
DQL5 VSS_12
G2
DQL6
H7
B1
VSSQ_1 DQL7
B9 B1
VSSQ_2 VSSQ_1
D1 D7 B9
VSSQ_3 DQU0 VSSQ_2
C3 D1
D8
VSSQ_4 DQU1 VSSQ_3
E2 C8 D8
VSSQ_5 DQU2 VSSQ_4
E8 C2 E2
VSSQ_6 DQU3 VSSQ_5
A7 E8
F9
DQU4 VSSQ_6
VSSQ_7
G1 A2 F9
VSSQ_8 DQU5 VSSQ_7
G9 B8 G1
VSSQ_9 DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
U_MVREFCA_A1
C13060 C13061
0.1uF 1000pF
URSA11_DDR_NANYA
IC13002-*1
NT5CB64M16FP-EK
N3 M8
A0 VREFCA
P7
A1
P3
A2
N2 H1
A3 VREFDQ
P8
A4
P2
A5
R8 L8
A6 ZQ
R2
A7
T8
A8
R3 B2
A9 VDD_1
L7 D9
A10/AP VDD_2
R7 G7
A11 VDD_3
N7 K2
A12/BC VDD_4
T3 K8
NC_6 VDD_5
N1
VDD_6
M7 N9
NC_5 VDD_7
R1
VDD_8
M2 R9
BA0 VDD_9
N8
BA1
M3
BA2
A1
VDDQ_1
J7 A8
CK VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4
D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2
RAS VDDQ_8
K3 H9
CAS VDDQ_9
L3
WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3
L9
NC_4
F3 T7
DQSL NC_7
G3
DQSL
C7 A9
DQSU VSS_1
B7 B3
DQSU VSS_2
E1
VSS_3
E7 G8
DML VSS_4
D3 J2
DMU VSS_5
J8
VSS_6
E3 M1
DQL0 VSS_7
F7 M9
DQL1 VSS_8
F2 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
DQL5 VSS_12
G2
DQL6
H7
DQL7
B1
VSSQ_1
D7 B9
DQU0 VSSQ_2
C3 D1
DQU1 VSSQ_3
C8 D8
DQU2 VSSQ_4
C2 E2
DQU3 VSSQ_5
A7 E8
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
For 120Hz Vb1
0.1uF C12832 TXDBN0_L
TXDBN0_L_URSA11
TXDBP0_L_URSA11 0.1uF C12833 TXDBP0_L
TXDBN1_L_URSA11 0.1uF C12834 TXDBN1_L
0.1uF C12835 TXDBP1_L
TXDBP1_L_URSA11
0.1uF C12836 TXDBN2_L
TXDBN2_L_URSA11
0.1uF C12837 TXDBP2_L
TXDBP2_L_URSA11
TXDBN3_L_URSA11 0.1uF C12838 TXDBN3_L
0.1uF C12839 TXDBP3_L
TXDBP3_L_URSA11
0.1uF C12840 TXDBN4_L
TXDBN4_L_URSA11
0.1uF C12841 TXDBP4_L
TXDBP4_L_URSA11
TXDBN5_L_URSA11 0.1uF C12842 TXDBN5_L
TXDBP5_L_URSA11 0.1uF C12843 TXDBP5_L
0.1uF C12844 TXDBN6_L
TXDBN6_L_URSA11
0.1uF C12845 TXDBP6_L
TXDBP6_L_URSA11
TXDBN7_L_URSA11 0.1uF C12846 TXDBN7_L
TXDBP7_L_URSA11 0.1uF C12847 TXDBP7_L
BSD-15Y-LM14A-143_00-HD
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
UF77 ONLY
URSA11_DDR
LGE Internal Use Only