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3.1.2 Serial Wire Debug interface Header definition (J17)
Serial Wire Debug (SWD) is compatible with all ARM processors and any processor using
JTAG for debugging. It provides a debug port for pin limited packages. It replaces the 5-pin
JTAG port with a clock + single bi-directional data pin, SWDIO and SWCLK, providing all the
normal JTAG debug and test functionality.
Standard 10-pin JTAG Debug & Download Interface are shown below in the table:
Pin Number
1
2
3
4
5
6
7
8
9
10
GND = Ground
NC = Not Connected
3.1.3 Serial Wire Debug port for PAN1740 Header definition (J1)
Standard 10-pin JTAG Debug & Download Interface are shown below in the table:
Pin Number
1
2
3
User Manual
Signal
VDD3.3
SWDIO
GND
SWCLK
GND
NC
GND
NC
GND
RESET
Signal
DIO
P1_4/SWCLK
OTP
One time programming selecting pin for PAN1740
Grid-EYE Evaluation Kit
Function
+3.3V
SW debug data signal for ATSAMD21
GND
SW debug clock signal for ATSAMD21
GND
NC
GND
NC
GND
Reset ATSAMD21 MCU
Function
SW debug data signal for PAN1740
SW debug clock signal for PAN1740
10
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