Sharp 27DV-S100 Service Manual page 76

• Block Diagram
IC502 IX1765GE 4M EDO DRAM
Terminal Terminal name
16-19, 22-26 A -A
0 8
14 RAS
28 UCAS
29 LCAS
13 WE
27 OE
2-5, 7-10 DQ -DQ
1
31-34, 36-39
1, 6, 20 V
CC
21, 35, 40 V
SS
11-12, 15, 30 NC
• Block Diagram
OE
WE
UCAS
LCAS
RAS
V
CC
V
SS
A0
A1
A7
A8
DQ
8-14
Output Output
Buffer Buffer
Input
Buffer
Y-DECODER
Y GATING/SENSING
ADDRESS
QUEUE
LATCHES
X-DECODER
ADDRESS
COUNTER
Address inputs.
Row address strobe.
Column address strobe/upper byte control.
Column address strobe/lower byte control.
Write enable.
Output enable.
Data inputs/outputs.
16
+3.3V power supply.
0V ground.
No connection.
RAS clock CAS clock
generator generator
Refresh
counter
Y -Y
0
9
Address buffers
and predecoders
X -X
0 8
DQ
0-7
Input Input
Buffer Buffer
I/O Logic
DATA
QUEUE
ID
REGISTER
Register
CSR
Register
ESRs
Data
Comparator
Program Erase
Voltage Switch
Function
WE clock OE clock
generator generator
Data I/O Bus
Column decoders
Sense amplifiers
I/O
8
512 16
Buffer
Row
Memory
decoders
array
512
77
27DV-S100
27DV-CS10
BYTE#
CE#
OE#
WR#
RP#
RY/BY#
V
PP
V
CC
GND
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16