List Of Figures - Siemens 7SR21 Manual

List of Figures

Figure 1-1 Functional Diagram of 7SR21 Relay ...................................................................................8
Figure 1-2 Connections Diagram for 7SR21 Relay...............................................................................9
Figure 1-3 Functional Diagram of 7SR22 Relay .................................................................................12
Figure 1-4 Connection Diagram for 7SR22 Relay...............................................................................13
Figure 2.5-1 7SR21 with 3 + 8 LEDs in E6 Case...................................................................................15
Figure 2.5-2 7SR22 with 3 + 16 LEDs in E8 Case.................................................................................16
Figure 2.5-3 7SR22 with Function Keys and 3 + 8 LEDs in E8 Case....................................................16
Figure 2.8-1 Binary Input Logic ..............................................................................................................19
Figure 2.9-1 Binary Output Logic ...........................................................................................................20
Figure 3.1-1 Logic Diagram: Directional Overcurrent Element (67).......................................................23
Figure 3.1-2 Logic Diagram: Instantaneous Over-current Element .......................................................24
Figure 3.1-3 Logic Diagram: Time Delayed Overcurrent Element .........................................................26
Figure 3.2-1 Logic Diagram: Voltage Controlled Overcurrent Protection...............................................27
Figure 3.3-1 Logic Diagram: Derived Directional Earth Fault Element ..................................................29
Figure 3.3-2 Logic Diagram: Derived Instantaneous Earth Fault Element ............................................30
Figure 3.3-3 Logic Diagram: Derived Time Delayed Earth Fault Protection..........................................31
Figure 3.4-1 Logic Diagram: Measured Directional Earth Fault Protection ...........................................32
Figure 3.4-2 Logic Diagram: Measured Instantaneous Earth-fault Element..........................................33
Figure 3.4-3 Logic Diagram: Measured Time Delayed Earth Fault Element (51G) ...............................34
Figure 3.5-1 Logic Diagram: SEF Directional Element (67SEF)............................................................35
Figure 3.5-2 Logic Diagram: SEF Instantaneous Element.....................................................................36
Figure 3.5-3 Logic Diagram: SEF Time Delayed Element (51SEF).......................................................37
Figure 3.6-1 Logic Diagram: High Impedance REF (64H) .....................................................................38
Figure 3.7-1 Logic Diagram: Cold Load Settings (51c) ..........................................................................39
Figure 3.8-1 Logic Diagram: Negative Phase Sequence Overcurrent (46NPS)....................................40
Figure 3.9-1 Logic Diagram: Undercurrent Detector (37, 37G & 37SEF) ..............................................41
Figure 3.10-1 Logic Diagram: Thermal Overload Protection (49S)..................................................43
Figure 3.11-1 Logic Diagram: Under/Over Voltage Elements (27/59) .............................................44
Figure 3.12-1 Logic Diagram: NPS Overvoltage Protection (47) .....................................................45
Figure 3.13-1 Logic Diagram: Neutral Overvoltage Element............................................................46
Figure 3.14-1 Logic Diagram: Under/Over Frequency Detector (81) ...............................................47
Figure 4.1-1 Typical Auto Reclose Sequence with 3 Instantaneous and 1 Delayed trip .......................50
Figure 4.7-1 Basic Auto-Reclose Sequence Diagram ...........................................................................55
Figure 4.9-1 Logic Diagram: Circuit Breaker Status...............................................................................57
Figure 4.10-1 Sequence Diagram: Quick Logic PU/DO Timers (Counter Reset Mode Off) ..................59
Figure 5.1-1 Logic Diagram: Circuit Breaker Fail Protection (50BF)......................................................60
Figure 5.2-1 Logic Diagram: VT Supervision Function (60VTS)............................................................62
Figure 5.4-1 Logic Diagram: CT Supervision Function (60CTS-I) - 7SR21 & 7SR22...........................63
Figure 5.5-1 Logic Diagram: CT Supervision Function (60CTS) - 7SR22 ............................................63
Figure 5.6-1 Logic Diagram: Broken Conductor Function (46BC) .........................................................64
Figure 5.7-1 Logic Diagram: Trip Circuit Supervision Feature (74TCS) ................................................64
Figure 5.8-1 Logic Diagram: Harmonic Block Feature (81HBL2) ..........................................................65
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7SR21 & 7SR22 Argus Description of Operation
Chapter 1 Page 4 of 71