Sharp ER-A57R1 Service Manual page 54

Pin No. Symbol
1 VSS
2 RTS
3 RXD
4 RXC
5 TXC
6 TXD
7 IRQ
8 RESET
9 CS
10 RS0
11 RS1
12 R/W
13 E
14 VCC
15 ∼22
D7 – D0
23 RDSR
24 TDSR
25 FD
Ground pin
This pin indicates that send data exists in the TxFIF0. If CR2b7 is set to one, this output is set to Low.
This pin is set to High when a Close flag has been transmitted after a frame is completed, an Abort is
transmitted, CR2b7 is reset in the Mark Idle state (RTS remains at Low if CR2b7 is reset to zero in any
state other than the Mark Idle state), or the RESET input is held at Low.
(Requeset Data Input)
Receiver Data input to accept received data.
(Receiver Data Input)
Receiver Clock input to accept a synchronization signal for the received data input.
(Receiver Clock Input)
Transmitter Clock input, used to synchronize the transmit data output.
When in the Loop mode (including Test mode), the signal at this pin must be in-phase with the RxC.
(Transmitter Clock Input)
TRansmit Data output.
(Transmit Data output)
Interrupt Request output. This pin is set Low if an interrupt occurred and the corresponding Enable bit
is set. It is set High when the cause of the interrupt is removed or the Enable bit is reset.
(Interrupt Request Output)
RESET input. If a Low signal is applied to this pin, the RxReset (CR1b6) and TxReset (CR1b7) are set
to one, which resets the Rx and Tx circuits, respectively. The TxAbort (CR4b5), RTS (CR2b7), Loop
Mode (CR3b5), and Loop on Line/DTR (CR367) are reset to zero.
All initial status conditions are reset. The RTS and LOC/DTR output pins are set to High when the
corresponding control registers are reset, and the TxD output is placed in Mark Idle state.
While the RESET inputs is kept at Low, none of the control register bits mentioned above can be
updated. If the RESET input is set to High, the reset condition continues until CR1b6 and CR1b7 are
reset to zeros by software.
(RESET Input)
Chip Select input. Read/write access to the device is enabled only if this input is Low and the Enable
input is High.
(Chip Select Input)
Register Select inputs. These inputs are used with the R/W input (CR1b0) to address a register within
the device for read/write access.
(Register Select Input)
Read/Write Control input used to indecate tha direction of the data flow.
The Data I/O buffer is placed in the Output mode if this input is High; it is placed in Input mode if this
Low.
(Read/Write Control Input)
Enable Clock input used to time the CS, RS0, RS1, and R/W inputs. Data read/write access to the
device is enabled only if this input is kept high.
This pin is also used for data transfer through the RxFIFO of TxFIFO.
(Enable Clock Input)
This pin accepts a +5V power supply.
(Voltage Source)
Bidirectional data bus used to transfer data with the system. It is a three-state bus except during Read
access.
(Data Bus)
Receive Data Service Request output. This pin reflects the value of ST1b0. A high state of this pin
indicates that the RxFIFO is in request for service.
When the RxFIFO is read, the RDSR outputs is reset to Low. (The RxFIFO here refers to the one
(CR2b1 = 0) or two (CR2b1 = 1) nearest to the data bus.)
When in the Preferred Status mode (CR2b0 = 1) , this pin is kept Low as long as the other status
condition exists.
(Receive Data Service Request Output)
Transmitter Data Service Request output. This pin outputs the value of ST1b6 in any mode other than
the FC mode (CR2b3 = 1). A high state of this pin indicates that the TxFIFO requests service. When
data is written into the TxFIFO, the RDSR is reset to Low. (The TxFIFO here refers to the one (CR2b1
= 0) or two (CR2b1 = 1) nearest to the data bus.)
This pin is kept Low when the RESET pin is at an active Low. CTS pin is High, or CR1b7 is High.
When in the Preferred Status mode (CR2b0 = 1), this pin is also kept High if the Tx-Underrun condition
exists.
(Transmitter Data Service Request Output)
Flag Detect output. This pin remains Low for a one-bit time interval (while Receiver Clock = RxC) after
the last flag bit is detected.
(Flag Detect Output)
Pin name and function
4 ™ 11
Input/
Output
–
Out
In
In
In
Out
Out
In
In
In
In
In
I/O
I/O
Out
Out
Out