Page 1 FUJITSU SEMICONDUCTOR FME-MB96300 rev 14, 2007-12-18 CONTROLLER MANUAL MC-16FX 16-BIT MICROCONTROLLER MB96300 Super series HARDWARE MANUAL...
Page 3 MC-16FX 16-BIT MICROCONTROLLER MB96300 Super series HARDWARE MANUAL FUJITSU LIMITED...
Page 5 MB96300 Super Series Hardware Manual PREFACE ■ Objectives and intended reader Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB96300 Super series has been developed as a general-purpose version of the F MC-16FX series, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC).
Page 6 MB96300 Super Series Hardware Manual CHAPTER 9 "STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT" This chapter explains the functions and operations of the standby mode control circuit and the control of the internal voltage regulator. The regulator control can be used to optimize power consumption, especially in standby modes.
Page 7 MB96300 Super Series Hardware Manual CHAPTER 25 "CLOCK CALIBRATION UNIT" This chapter explains the functions and operation of the Clock Calibration Unit CHAPTER 26 "LCD CONTROLLER/DRIVER" This chapter describes the functions and operations of the LCD Controller/Driver. CHAPTER 27 "STEPPER MOTOR CONTROLLER" This chapter explains the functions and operations of the stepper motor controller.
Page 8 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Page 9: Table Of Contents
MB96300 Super Series Hardware Manual CONTENTS OVERVIEW 7 Features 8 Super series lineup 10 Block Diagram of MB96V300 12 General note on using this document 16 16-bit I/O-Timer Configuration 19 Input Capture Unit source select for LIN-USART 23 Peripheral resource pin relocation 30 CPU 47 Outline of the CPU 48 Hardware Structure 50...
Page 10 MB96300 Super Series Hardware Manual Clock Control Registers 148 Clock Modes 169 Configuration of the PLL 172 Oscillation Stabilization Wait Time 175 Connection of an Oscillator or an External Clock to the Microcontroller 177 CLOCK MODULATOR 179 Overview 180 Register Description 181 Application Note 188 RESETS AND STARTUP 191 Resets 192...
Page 11 MB96300 Super Series Hardware Manual I/O PORTS 349 I/O Ports 350 I/O Port Registers 351 Register usage 362 16-BIT I/O TIMER 363 Outline of 16-bit I/O Timer 364 16-Bit I/O Timer Registers 366 16-bit Free-Running Timer 368 Output Compare Unit 375 Input Capture Unit 388 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 395 Outline of 16-Bit Reload Timer (with Event Count Function) 396...
Page 12 MB96300 Super Series Hardware Manual Configuration of USART 469 USART Pins 474 USART Registers 475 USART Interrupts 496 USART Baud Rates 503 Operation of USART 511 Notes on Using USART 535 400 kHz I2C INTERFACE 541 I2C Interface Overview 542 I2C Interface Registers 544 I2C Interface Operation 567 Programming Flow Charts 570...
Page 13 MB96300 Super Series Hardware Manual Cautions 688 STEPPER MOTOR CONTROLLER 691 Outline of Stepper Motor Controller 692 Stepper Motor Controller Registers 693 PWM Control register (PWCn) 695 PWM Extended Control register (PWECn) 697 PWM1 and PWM2 Compare Registers (PWC1n, PWC2n) 698 PWM1 and PWM2 Selection registers (PWS1n, PWS2n) 701 Operation of Stepper Motor Controller 703 Notes on Using Stepper Motor Controller 706...
Page 14 MB96300 Super Series Hardware Manual Notes on using Flash Memory 881 Flash memory programming example 882 MASK-ROM MEMORY INTERFACE 889 Overview 890 ROM interface registers 891 Read buffers 896 ROM/FLASH SECURITY 897 Overview of the ROM/Flash Security 898 Usage of the ROM/Flash Security 899 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 903 Basic Configuration of Serial Programming Connection 904 Example of connecting a PC for programming the Flash Microcontroller 907...
Page 15: Overview
CHAPTER 1 OVERVIEW The MB96300 Super series is a family member of the MC-16FX micro controllers. It consist of many different series of microcontrollers, which are targetting different applications. Programming between all members of the Super series is common. 1.1 "Features" 1.2 "Super series lineup"...
Page 16: Features
CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Features The feature set of F MC-16FX family’s MB96300 Super series makes it especially well suited for automotive applications.
Page 17 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Features • 16-bit core CPU, 64 MHz internal, 15.6 ns instruction cycle time • 0.18µm CMOS Process Technology • Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes;...
Page 18: Super Series Lineup
CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Super series lineup Table 1.2-1 "MB96300 super series lineup" provides an overview of the MB96300 Super series.
Page 19 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Super series lineup The F MC-16FX MB96300 Super series covers the F MC-16FX series as shown in table 1.2-1. Table 1.2-1 MB96300 super series lineup Series Flash Mask ROM Packages Products Products MB96320 MB96F32x...
Page 20: Block Diagram Of Mb96V300
CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Block Diagram of MB96V300 Figure 1.3-1 shows the block diagram of MB96V300.
Page 21 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Block Diagram of MB96V300...
Page 22 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Figure 1.3-1 Block Diagram of MB96V300 AD00 ... AD15 CKOT0, CKOT1 A00 ... A23 CKOTX0, CKOTX1 WRLX, WRHX X0, X1 X0A, X1A RSTX HAKX MD0...MD2 LBX, UBX CS0 ... CS5 Emulation Memory Patch Clock &...
Page 23 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW Notes: USB is not available for MB96v300. Please refer to the datasheet of your device.
Page 24: General Note On Using This Document
CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual General note on using this document This chapter contains some general notes about this document.
Page 25 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Device dependent resources The derivatives of a Microcontroller series may have different sets of resources (e.g. features, number of channels, interconnections). Details about an individual device can be found in the following documents: •...
Page 26 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Described resources All chapters about resources of the Microcontroller like USART, Reload timers, General purpose ports describe the function of only one channel of this resource. The behavior of all other resources of the same type is the same.
Page 27: 16-Bit I/O-Timer Configuration
MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW 16-bit I/O-Timer Configuration The number of available Free Running timers, Input Capture Units and Output Compare Units differs between different devices. Multiple Input Capture Units and Output Compare Units are connected to one Free Running timer. This chapter describes the relation between these modules.
Page 28 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Connection between Input Capture Units and Free Running Timers Table 1.5-1 Connection between Input Capture Units and Free Running Timers Free Running Input Capture Unit Timer MB96V300 MB9632x MB9633x MB9634x MB9635x MB9636x MB9638x FRT0...
Page 29 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Connection between Output Compare Units and Free Running Timers Table 1.5-2 Connection between Output Compare Units and Free Running Timers Free Output compare unit Running Timer MB96V300 MB9632x MB9633x MB9634x MB9635x MB9636x MB9638x FRT0...
Page 30 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Relation between Timer clear function and OCU, Compare clear and Free running timer Table 1.5-3 Connection between OCU, Compare clear and Free running timer for timer clear Free running Timer is cleared at match with following Note timer compare register...
Page 31: Input Capture Unit Source Select For Lin-Usart
MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW Input Capture Unit source select for LIN-USART The input source for the Input Capture units can be selected between an external pin (INx) and the LIN-USART Sync Field output. This chapter describes how to select the Input capture input and which LIN-USART can be connected to which ICU.
Page 32 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Overview of connection between LIN-USART and ICU Table 1.6-1 Connection between LIN-USARTs and ICUs Free running ICU source LIN-USART Device timer for ICU select bit USART0 ICU0 FRT0 ICE01:ICUS0 MB96V300, MB96(F)32x, MB96(F)33x, MB96(F)34x, MB96(F)36x,...
Page 33 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Input Capture Unit source select The source selection for ICU is done in the Input capture edge registers ICExy. Figure 1.6-1 Input capture edge register ICE01 Initial value X X X 0 X 0 0 0 Address: ICUS1 ICUS0...
Page 34 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Figure 1.6-2 Input capture edge register ICE45 Initial value X X X 0 X 0 0 0 Address: ICUS5 ICUS4 IEI5 IEI4 00004d R/W R/W R/W bit8 IEI4 Input capture valid edge indication bit for ICU4 falling edge detected rising edge detected bit9...
Page 35 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW Figure 1.6-3 Input capture edge register ICE67 Initial value X X X 0 X 0 0 0 Address: ICUS7 ICUS6 IEI7 IEI6 000053 R/W R/W R/W bit8 IEI6 Input capture valid edge indication bit for ICU6 falling edge detected rising edge detected bit9...
Page 36 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Figure 1.6-4 Input capture edge register ICE89 Initial value X X X 0 X 0 0 0 Address: ICUS9 ICUS8 IEI9 IEI8 000515 R/W R/W R/W bit8 IEI8 Input capture valid edge indication bit for ICU8 falling edge detected rising edge detected bit9...
Page 37 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW Figure 1.6-5 Input capture edge register ICE1011 Initial value X X X 0 X 0 0 0 Address: ICUS11 ICUS10 IE11 IEI10 00051b R/W R/W R/W bit8 IEI10 Input capture valid edge indication bit for ICU10 falling edge detected rising edge detected bit9...
Page 38: Peripheral Resource Pin Relocation
CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Peripheral resource pin relocation The input or output pin of some resources can be relocated. The location of these resource pins is deﬁned by the peripheral resource pin relocation registers PRRR[9:0].
Page 39 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Overview of the peripheral resource relocation register Table 1.7-1 Peripheral resource pin relocation register (PRRR0 to PRRR13) Address Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Description Peripheral resource 0004d6 PRRR0 INT7_R INT6_R...
Page 40 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 0 (PRRR0) Figure 1.7-1 Peripheral resource relocation register 0 (PRRR0) Initial value 0 0 0 0 0 0 0 0 Address: INT7_R INT6_R INT5_R INT4_R INT3_R INT2_R INT1_R INT0_R 0004d6 R/W R/W R/W R/W R/W R/W R/W R/W...
Page 41 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 1 (PRRR1) Figure 1.7-2 Peripheral resource relocation register 1 (PRRR1) Initial value 0 0 0 0 0 0 0 0 Address: INT15_R INT14_R INT13_R INT12_R INT11_R INT_10R INT9_R INT8_R 0004d7 R/W R/W R/W R/W R/W R/W R/W R/W...
Page 42 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 2 (PRRR2) Figure 1.7-3 Peripheral resource relocation register 2 (PRRR2) Initial value 0 0 0 0 0 0 0 0 Address: PPG7_R PPG6_R PPG5_R PPG4_R PPG3_R PPG2_R PPG1_R PPG0_R 0004d8 R/W R/W R/W R/W R/W R/W R/W R/W...
Page 43 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 3 (PRRR3) Figure 1.7-4 Peripheral resource relocation register 3 (PRRR3) Initial value 0 0 0 0 0 0 0 0 Address: TOT3_R TIN3_R TOT2_R TIN2_R TOT1_R TIN1_R TOT0_R TIN0_R 0004d9 R/W R/W R/W R/W R/W R/W R/W R/W...
Page 44 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 4 (PRRR4) Figure 1.7-5 Peripheral resource relocation register 4 (PRRR4) Initial value 0 0 0 0 0 0 0 0 Address: IN7_R IN6_R IN5_R IN4_R IN3_R IN2_R IN1_R IN0_R 0004da...
Page 45 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 5 (PRRR5) Figure 1.7-6 Peripheral resource relocation register 5(PRRR5) Initial value 0 0 X X 0 0 0 0 Address: OUT7_R OUT6_R OUT3_R OUT2_R OUT1_R OUT0_R 0004db R/W R/W R/W R/W R/W bit8...
Page 46 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 6 (PRRR6) Figure 1.7-7 Peripheral resource relocation register 6 (PRRR6) Initial value CKOT CKOT1_R SCK2_R SOT2_R SIN2_R FRCK0_R SGA0_R SGO0_R 0 0 0 0 0 0 0 0 Address: X1_R 0004dc...
Page 47 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 7 (PRRR7) Figure 1.7-8 Peripheral resource relocation register 7 (PRRR7) Initial value 0 0 0 0 0 0 0 0 Address: TX2_R RX2_R INT5_R1 INT4_R1 INT3_R1 CS3_R NMI_R ADTG_R 0004dd R/W R/W R/W R/W R/W...
Page 48 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 8 (PRRR8) Figure 1.7-9 Peripheral resource relocation register 8 (PRRR8) Initial value 0 0 0 0 0 0 0 0 Address: SOT9_R SIN9_R SCK8_R1 SOT8_R SIN8_R SCK7_R SOT7_R SIN7_R 0004de R/W R/W R/W R/W R/W R/W R/W R/W...
Page 49 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 9 (PRRR9) Figure 1.7-10 Peripheral resource relocation register 9 (PRRR9) Initial value X X 0 0 0 0 0 0 Address: CKOT0_ROUT10_RFRCK2_R SGA1_R SGO1_R SCK9_R 0004dd R/W R/W R/W R/W R/W R/W R/W R/W bit0 SCK9_R...
Page 50 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral ressource relocation register 10 (PRRR10) Figure 1.7-11 Peripheral resource relocation register 10 (PRRR10) Initial value 0 0 0 0 0 0 0 0 Address: TTG11_RTTG10_R TTG9_R TTG8_R PPG11_R PPG10_R PPG9_R PPG8_R 000660 R/W R/W R/W R/W R/W R/W R/W R/W...
Page 51 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral ressource relocation register 11 (PRRR11) Figure 1.7-12 Peripheral resource relocation register 11 (PRRR11) Initial value 0 0 0 0 0 0 0 0 Address: TTG19_R TTG18_R TTG17_R TTG16_R PPG19_R PPG18_R PPG17_R PPG16_R 000661 R/W R/W R/W R/W R/W R/W R/W R/W...
Page 52 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral ressource relocation register 12 (PRRR12) Figure 1.7-13 Peripheral resource relocation register 12 (PRRR12) Initial value 0 0 0 0 0 0 0 0 Address: CS5_R CS4_R CS2_R CS1_R CS0_R 000662 R/W R/W R/W R/W R/W R/W R/W R/W bit0...
Page 53 MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral ressource relocation register 13 (PRRR13) Figure 1.7-14 Peripheral resource relocation register 13 (PRRR13) Initial value 0 0 0 0 0 0 0 0 Address: 000663 R/W R/W R/W R/W R/W R/W R/W R/W bit0 - bit7 reserved bit...
Page 54 CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual...
Page 55: Cpu
CHAPTER 2 This chapter explains the CPU. 2.1 "Outline of the CPU" 2.2 "Hardware Structure" 2.3 "Memory Space" 2.4 "Special Registers" 2.5 "General-Purpose Registers" 2.6 "Prefix Codes"...
Page 56: Outline Of The Cpu
CHAPTER 2 CPU MB96300 Super Series Hardware Manual Outline of the CPU The F MC-16FX CPU core is a 16-bit CPU designed for applications that require high- speed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F MC-16FX instruction set is designed for controller applications, and is capable of high-speed, highly efﬁcient control processing.
Page 57 MB96300 Super Series Hardware Manual CHAPTER 2 CPU • Instruction set symmetry • Shift instructions...
Page 58: Hardware Structure
CHAPTER 2 CPU MB96300 Super Series Hardware Manual Hardware Structure This section explains the hardware structure of the CPU and the 16FX core. ■ Hardware Structure of the CPU ● CPU Block Diagram Figure 2.2-1 CPU block diagram Instruction Fetch stage F2MC−16FX CPU Queue Decode Address...
Page 59 MB96300 Super Series Hardware Manual CHAPTER 2 CPU • Write back (WB): Writes the operation result to a register or memory location. Figure 2.2-2 Instruction Pipeline Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instructions are not executed out of order. Therefore, if instruction A enters the pipeline ahead of instruction B, instruction A always reaches write back stage before instruction B.
Page 60 CHAPTER 2 CPU MB96300 Super Series Hardware Manual Figure 2.2-3 MCU Device based on the 16FX Core User Ports F2MC−16FX Boot ROM Interrupt Controller (program area) Controller (data area) Timer Serial Clock and Peripheral Mode Control Bus Bridge Peripheral Bus 1 External Bus Peripheral Interface...
Page 61 MB96300 Super Series Hardware Manual CHAPTER 2 CPU ● External Bus Interface The external bus interface is an optional component. Its availability depends on the configuration of the specific device. ● Boot ROM After device initialization by reset, the program counter points to the boot ROM. The CPU starts the execution of the boot ROM program.
Page 62: Memory Space
CHAPTER 2 CPU MB96300 Super Series Hardware Manual Memory Space An F MC-16FX CPU has a 16-Mbyte memory space. 2.3.1 "Memory Areas" 2.3.2 "Linear Addressing Method" 2.3.3 "Bank Addressing Method" 2.3.4 "Multi-byte Data in Memory Space"...
Page 63 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.3.1 Memory Areas All I/O addresses, programs and data are located in the 16-megabyte memory space of the F MC-16FX CPU. The CPU is able to access each resource through an address indicated by the 24-bit address bus.
Page 64 CHAPTER 2 CPU MB96300 Super Series Hardware Manual ■ I/O area The address range of the I/O area is from 00:0000 to 00:00FF . This address range can be used for direct I/ O addressing by specifying the 8 bit address as operand together with the instruction. If an instruction is using the direct I/O addressing method, the register is accessed regardless of the values specified by the direct page register (DPR) or the data bank register (DTB).
Page 65 MB96300 Super Series Hardware Manual CHAPTER 2 CPU ● Mirror area in bank 00 (address: 00:8000 to 00:FFFF This area is used to access the top-most section of 32 kByte ROM by default. The ROM mirror function is variable in size. There are up to 4 segments of 8 kByte each selectable as ROM mirror. The ROM bank to be accessed via bank 00 can be selected in the ROMM register.
Page 66 CHAPTER 2 CPU MB96300 Super Series Hardware Manual 2.3.2 Linear Addressing Method At linear addressing an entire 24-bit address is speciﬁed by an instruction. There are two types of linear addressing: • 24-bit operand speciﬁcation: Directly speciﬁes a 24-bit address using operands. •...
Page 67 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.3.3 Bank Addressing Method In the bank addressing method the eight high-order bits of an address are speciﬁed by an appropriate bank register, and the remaining 16 low-order bits are speciﬁed by an instruction.
Page 68 CHAPTER 2 CPU MB96300 Super Series Hardware Manual instruction. This enables access to the bank space corresponding to the specified prefix code. Table 2.3-2 Bank selection preﬁxes Bank selection preﬁx Selected Space Program space Data space Additional data space Either the system or the user stack space is used, according to the stack ﬂag status upon selection.
Page 69 MB96300 Super Series Hardware Manual CHAPTER 2 CPU bank 00 (000000 to 00FFFF ), and the PC space is allocated in the bank specified by the reset vector. Table 2.3-3 Initialization of bank registers Bank register Initialization by reset Initialization by Boot ROM External vector mode Internal vector mode Byte read from...
Page 70 CHAPTER 2 CPU MB96300 Super Series Hardware Manual 2.3.4 Multi-byte Data in Memory Space Data is written to memory from the low-order address on. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is input immediately after the low-order bits are written, the high-order bits might not be written.
Page 71: Special Registers
MB96300 Super Series Hardware Manual CHAPTER 2 CPU Special Registers The F MC-16FX CPU registers are classiﬁed into two types: special registers and general-purpose registers. This section explains the special registers of the F MC-16FX CPU. The special registers are dedicated internal hardware of the CPU, and they have speciﬁc use deﬁned by the CPU architecture.
Page 72 CHAPTER 2 CPU MB96300 Super Series Hardware Manual ■ Special registers The F MC-16FX CPU has the following special registers: • Accumulator (A=AH:AL): Two 16-bit accumulators (can be used as a single 32-bit accumulator) • User stack pointer (USP): 16-bit user stack pointer •...
Page 73 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.1 Accumulator (A) The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data. ■ Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL).
Page 74 CHAPTER 2 CPU MB96300 Super Series Hardware Manual Figure 2.4-3 Example of AL-AH transfer by means of data preservation MOVW A, @RW1+6 Previous content XXXX 1234 A61540 of the A register A6153E Latest content of the A register 1234 2B52...
Page 75 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.2 User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed. ■...
Page 76 CHAPTER 2 CPU MB96300 Super Series Hardware Manual drawback in stack performance.
Page 77 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.3 Processor Status (PS) The PS register consists of the bits controlling the CPU Operation and indicating the CPU status. ■ Processor status (PS) As shown in Figure 2.4-5“Processor status (PS) structure”, the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM).
Page 78 CHAPTER 2 CPU MB96300 Super Series Hardware Manual ● S: Stack ﬂag: When the S flag is 0, USP is enabled as the stack pointer. When the S flag is 1, SSP is enabled as the stack pointer. The S flag is set by an interrupt reception or a reset. ●...
Page 79 MB96300 Super Series Hardware Manual CHAPTER 2 CPU ■ Interrupt level mask register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the priority of the interrupt is higher than that indicated by the ILM register and the P flag.
Page 80 CHAPTER 2 CPU MB96300 Super Series Hardware Manual Table 2.4-1 Levels indicated by the P ﬂag and interrupt level mask (ILM) register Level P ﬂag ILM value Acceptable interrupt level none Interrupts disabled Level < P1 Interrupts disabled Level < P2 Interrupts disabled Level <...
Page 81 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.4 Program Counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. ■ Program counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU.
Page 82 CHAPTER 2 CPU MB96300 Super Series Hardware Manual 2.4.5 Direct Page Register (DPR) The direct page register (DPR) speciﬁes bits 8 to 15 (addr 8 to addr 15) of the operand address for direct addressing instructions. ■ Direct page register (DPR) DPR specifies bits 8 to 15 of the instruction operands in direct addressing mode as shown in Figure 2.4- 10"Generating a physical address in direct addressing mode".
Page 83 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.6 Bank register (PCB, DTB, ADB, USB, SSB) Each bank register indicates a memory bank where a program space, data space, user stack space or additional data space is allocated ■ Bank Register All bank registers are one byte long.
Page 84: General-Purpose Registers
CHAPTER 2 CPU MB96300 Super Series Hardware Manual General-Purpose Registers The F MC-16FX CPU registers are classiﬁed into two types: special registers and general-purpose registers. This section explains the general-purpose registers (GPRs) of the F2MC-16FX CPU. GPRs can be accessed without addressing, similar to the special registers. The register operations are deﬁned by speciﬁc instructions.
Page 85 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.5.1 Register Bank A register bank consists of eight words. The register bank can be used as general- purpose registers for arithmetic operations. ■ Register bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: •...
Page 86 CHAPTER 2 CPU MB96300 Super Series Hardware Manual In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The status before a reset is maintained. When the power is turned on, the register bank will have an undefined value.
Page 87 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.5.2 Addressing General-Purpose Registers The general-purpose registers of the F MC-16FX use the register bank pointer (RP) to specify the currently used register bank. The register banks can be addressed between 00:0180 and 00:037F in the memory space.
Page 88: Prefix Codes
CHAPTER 2 CPU MB96300 Super Series Hardware Manual Prefix Codes Placing a preﬁx code before an instruction partially changes the operation of that instruction. There are three types of preﬁx codes: • Bank selection preﬁx • Common register bank preﬁx •...
Page 89 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.6.1 Bank Selection Preﬁx Placing a bank selection preﬁx before an instruction enables that instruction to access any speciﬁed memory space, regardless of the addressing method being used. ■ Bank select preﬁx The memory space used for accessing data is determined for each addressing mode.
Page 90 CHAPTER 2 CPU MB96300 Super Series Hardware Manual ● Branch instructions RETI The system stack bank (SSB) is used, regardless of any bank selection prefix is specified. ● String operation instructions FILS FILSW SCEQ SCWEQ MOVS MOVSW The bank register specified by the operand is used, regardless of any bank selection prefix is specified. ●...
Page 91 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.6.2 Common Register Bank Preﬁx (CMR) The common register bank preﬁx (CMR) can be placed before an instruction that accesses a register bank. Then the target register of that instruction is changed to the common register bank.
Page 92 CHAPTER 2 CPU MB96300 Super Series Hardware Manual The specified prefix affects the next instruction.
Page 93 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.6.3 Flag Change Inhibit Preﬁx (NCC) Flag changes associated with the execution of an instruction can be inhibited by placing a ﬂag change inhibit preﬁx code (NCC) before that instruction. ■ Flag change inhibit preﬁx code (NCC) To disable flag changes, use the flag change inhibit prefix code (NCC).
Page 94 CHAPTER 2 CPU MB96300 Super Series Hardware Manual CCR changes according to the instruction specifications regardless of the prefix.
Page 95 MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.6.4 Preﬁx Code Restrictions This section lists the instructions, which reject interrupt requests during execution. If a preﬁx code is placed before such an instruction, the setting of the preﬁx code remains effective until the ﬁrst instruction is executed after this interrupt rejecting instruction.
Page 96 CHAPTER 2 CPU MB96300 Super Series Hardware Manual Figure 2.6-2 Interrupt rejecting instructions and preﬁx codes Interrupt rejecting instruction • • • • ADD A,01 H MOV A, FF H MOV ILM,#imm8 CCR:XXX10XX CCR:XXX10XX CCR does not change with NCC. ■...
Page 97: Interrupts
CHAPTER 3 INTERRUPTS This chapter explains the interrupt functions and operations. 3.1 "Outline of Interrupts" 3.2 "Interrupt Vector" 3.3 "Interrupt Control Registers (ICR)" 3.4 "Non Maskable Interrupt (NMI)" 3.5 "Interrupt Flow" 3.6 "Hardware Interrupts" 3.7 "Software Interrupts" 3.8 "Multiple interrupts" 3.9 "Exceptions"...
Page 98: Outline Of Interrupts
CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Outline of Interrupts The F MC-16FX has interrupt functions that terminate the currently executed program and transfer control to another speciﬁed program when a speciﬁc event occurs. There are four types of interrupt functions: •...
Page 99 MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS • NMI • HW-INT9 (embedded debug support) • DSU break factors (only available on the EVA device) Exception processing is basically the same as interrupt processing. When an exception is detected during instruction execution, exception processing is performed.
Page 100: Interrupt Vector
CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Interrupt Vector Hardware and software interrupts use the same vector table. The execution of interrupt service routines can be triggered by asserting the speciﬁc IRQ line or by executing the INT instruction and specifying the number of the interrupt vector. Interrupt vectors are allocated between addresses as shown in Table 3.2-2 "Interrupt vector table".
Page 101 MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS ● Interrupt Vector Table The interrupt vector table referenced during interrupt processing is assigned to addresses 256*TBR to 256*TBR+3FF in memory. The reset defaults are from FFFC00 to FFFFFF for the location of the vector table.
Page 102 CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Table 3.2-2 Interrupt vector table Interrupt / Vector number Vector address Index of level Hardware IRQ / Interrupt cause register in ICR INT 17 TB+3B8 IL17 Device speciﬁc peripheral. INT 18 TB+3B4 IL18 Device speciﬁc peripheral.
Page 103: Interrupt Control Registers (Icr)
MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Interrupt Control Registers (ICR) For each peripheral resource that has an interrupt function, there is an interrupt control register (ICR). The interrupt control register sets the interrupt level (IL) for the peripheral resource it is assigned to.
Page 104 CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual indexed access: - Use word access to write information to ICR:IX and ICR:IL simultaneously. - At read access, set the index ICR:IX and read the whole ICR register using word access. Check the ICR:IX value to match the intended index to be read for validation of the correct ICR:IL entry.
Page 105: Non Maskable Interrupt (Nmi)
MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Non Maskable Interrupt (NMI) The F2MC-16FX CPU has a non maskable interrupt. The feature of the external NMI pin can be enabled, it’s level can be deﬁned and a ﬂag to quit the NMI request is provided. ■...
Page 106 CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual processing, if an active signal level is detected at the NMI pin (defined by the LEV bit). If EN is set to ’1’, both the LEV and EN bits are locked for writing. Neither the signal level can be changed nor the NMI can be disabled after the NMI feature was enabled once.
Page 107: Interrupt Flow
MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Interrupt Flow Figure 3.5-2 "Interrupt ﬂow" shows the interrupt ﬂow. ■ Interrupt ﬂow The interrupt processing flow is entered at occurrence of hardware interrupts, software interrupts or exceptions. For a detailed interrupt flow chart see Figure 3.5-2 "Interrupt flow". The CPU special registers are saved on the stack before the interrupt is processed (see Figure 3.5-1 "Register saving during interrupt processing").
Page 108 CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Figure 3.5-2 Interrupt ﬂow I, ILM: Interrupt flag and interrupt level mask in CCR/PS of CPU START IF, IE: Internal resource interrupt request flag and enable DER: DMA enable register of the related DMA channel Level configuration of the IRQ channel by ICR/ILR System stack flag in the CCR/PS DISEL: DMA intserrupt select register...
Page 109: Hardware Interrupts
MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Hardware Interrupts In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program deﬁned by the user. ■ Hardware interrupts A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations: •...
Page 110 CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual interrupts, the I flag has to be set and ILM has to be larger than IL. - During interrupt processing, the CPU saves 12 bytes to the memory area indicated by SSB and SSP. Thus the system stack pointer has to be initialized before using interrupts.
Page 111 MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS - If the final transfer count is reached, the DMA completion interrupt is processed by the interrupt controller. 4. The interrupt controller receives the interrupt request. 5. The interrupt controller determines the priority levels of simultaneously requested interrupts. 6.
Page 112: Software Interrupts
CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Software Interrupts In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program deﬁned by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed.
Page 113 MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Figure 3.7-1 Occurrence and release of software interrupt (2b) Register File Stack clear (2c) (2a) Execution Pipeline INT (1) Instruction Queue F2MC−16FX CPU Processing of the RETI Interrupt Service Instruction (4) Routine (3) Instruction (1) 1.
Page 114: Multiple Interrupts
CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Multiple interrupts The F MC-16FX CPU supports multiple interrupts (simultaneous occurring interrupts and nested interrupt processing). ■ Multiple hardware interrupts If an hardware interrupt of a higher priority (lower level value) occurs while another interrupt is being processed, control is transferred to the higher priority interrupt after the currently executing instruction is completed.
Page 115 MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS ■ Interrupt acceptance priority Following table lists all interrupts with conditions for their acceptance.
Page 116 CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Table 3.8-1 Control of interrupt acceptance priority Event INT# Type Level Acceptance condition Action, if accepted Instruction Break Current instruction execution is Save CPU P = 0 (VEIB) ﬁnished, status to ILM = 2 system reserved ILM>2 || P == 1 system stack...
Page 117 MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS System stack flag Privileged mode flag (bit 7 of CCR, PS) Following table defines the naming of the interrupt levels, its corresponding P flag and ILM values. It also lists the interrupt cause, which can request the interrupt level. Table 3.8-2 Interrupt levels Name Category...
Page 118: Exceptions
CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Exceptions The F MC-16FX performs exception processing at occurrence of various software and hardware events. ■ Software exceptions (op-code) Software exceptions are always accepted. Same as software interrupts, software exceptions disable any hardware interrupt acceptance.
Page 119 MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS ● INTE (System reserved, only available with DSU) INTE is used to insert a software break point for the debug system, using the in circuit emulator (ICE). At insertion of a software instruction break, the first byte of the original instruction is replaced by INTE. This instruction branches to the interrupt processing routine indicated by a fixed vector defined by the DSU.
Page 120 CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual (SSP)<-(SSP)-2, ((SSP))<-(PC) (SSP)<-(SSP)-2, ((SSP))<-(PS) (S)<-1, (P)<-0, (ILM)<-6 (PCB)<-Vector #9 address (upper byte) (PC)<-Vector #9 address (lower word) ● NMI provides external hardware exception handling. The privileged mode flag (P flag) is cleared and ILM is set to 4 (enters level P4). This disables all hardware interrupts from peripherals and the HW-INT9.
Page 121 MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS...
Page 122 CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual...
Page 123: Dma
CHAPTER 4 This chapter explains the DMA functions and operations. 4.1 "Overview" 4.2 "DMA Registers" 4.3 "DMA Descriptor" 4.4 "DMA Controller Operation" 4.5 "Examples of DMA transfers"...
Page 124: Overview
CHAPTER 4 DMA MB96300 Super Series Hardware Manual Overview DMA enables automatic data transfer between memory and memory/peripheral resource registers or vice versa without interaction of the CPU. DMA replaces 16LX family’s EI while offering the extended functionality at higher performance. This section describes the DMA functions.
Page 125 MB96300 Super Series Hardware Manual CHAPTER 4 DMA • Automatic data transfer between peripheral resources (I/O) and memory • CPU bus allocation during DMA transfer • Up to 16 DMA transfer channels with fixed priority scheme (the smaller the DMA channel number, the higher the priority of the request).
Page 126 CHAPTER 4 DMA MB96300 Super Series Hardware Manual - I and ILM are used to compare the requested and current interrupt levels and to identify the interrupt enable status. - If the interrupt level is accepted, the CPU handles the interrupt request.
Page 127: Dma Registers
MB96300 Super Series Hardware Manual CHAPTER 4 DMA DMA Registers The DMA controller has three registers (DER, DSR, DSSR, each with one bit per DMA channel) and one register to select the interrupt (DISEL, one byte for each DMA channel). The DMA descriptor is used to set-up the DMA transfer.
Page 128 CHAPTER 4 DMA MB96300 Super Series Hardware Manual Write operations to not available bits/registers have no effect.
Page 129 MB96300 Super Series Hardware Manual CHAPTER 4 DMA 4.2.1 DMA Interrupt Request Select Register (DISEL) Each DMA channel has one Interrupt Request Select Register (DISEL0 ... DISEL15). This register deﬁnes which IRQ number is used to trigger the DMA transfer on this channel. ■...
Page 130 CHAPTER 4 DMA MB96300 Super Series Hardware Manual 4.2.2 DMA Status Register (DSR) This section describes the DMA Status Register (DSR). ■ DMA Status Register (DSR) Figure 4.2-3 DMA Status Register (DSR) conﬁguration Bit No. Address: DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9 DTE8 DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 DSRH, DSRL 0x391, 0x390...
Page 131 MB96300 Super Series Hardware Manual CHAPTER 4 DMA 4.2.3 DMA Stop Status Register (DSSR) This section describes the DMA Stop Status Register (DSSR) ■ DMA Stop Status Register (DSSR) Figure 4.2-4 DMA Stop Status Register (DSSR) conﬁguration Bit No. Address: STP15 STP14 STP13 STP12 STP11 STP10 STP9 STP8 STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 DSSRH, DSSRL...
Page 132 CHAPTER 4 DMA MB96300 Super Series Hardware Manual 4.2.4 DMA Enable Register (DER) This section describes the DMA Enable Register (DER). ■ DMA Enable Register (DER) Figure 4.2-5 DMA Enable Register (DER) conﬁguration Bit No. Address: EN15 EN14 EN13 EN12 EN11 EN10 EN9 DERH, DERL 0x395, 0x394 Read/Write:...
Page 133: Dma Descriptor
MB96300 Super Series Hardware Manual CHAPTER 4 DMA DMA Descriptor For each DMA channel the DMA descriptor consists of 8 bytes. It is used to set-up DMA transfer. ■ Conﬁguration of DMA Descriptors Each DMA channel has its own DMA descriptor of 8 bytes. The DMA descriptors are located from addresses 000100 to 00017F .
Page 134 CHAPTER 4 DMA MB96300 Super Series Hardware Manual Figure 4.3-1 Conﬁguration of the DMA Descriptor Address: Access Initial value: 0x000107 + 8*ch Upper 8 bits of data counter (DCTH) (R/W) 0x000106 + 8*ch Lower 8 bits of data counter (DCTL) (R/W) 0x000105 + 8*ch Upper 8 bits of I/O register address pointer (IOAH)
Page 135 MB96300 Super Series Hardware Manual CHAPTER 4 DMA 4.3.1 Data Count Register (DCT) This section describes the Data Count Register (DCT). ■ Data Count Register (DCT) The Data Count Register (DCT) is a 16-bit register to store the number of bytes to be transferred. After each data transfer, the Data Count Register is decremented by 1 at byte transfer or by 2 at word transfer.
Page 136 CHAPTER 4 DMA MB96300 Super Series Hardware Manual 4.3.2 I/O Register Address Pointer (IOA) This section describes the I/O Register Address Pointer (IOA). ■ I/O Register Address Pointer (IOA) The I/O Register Address Pointer (IOA) is a 16-bit register and indicates the lower addresses (A15 to A0) of the I/O register.
Page 137 MB96300 Super Series Hardware Manual CHAPTER 4 DMA 4.3.3 DMA Control Register (DMACS) This section describes the DMA Control Register (DMACS). ■ DMA Control Register (DMACS) The DMA Control Register (DMACS) is 8-bit long and is used: • to specify, if the Buffer Address Pointer should be incremented or decremented (BPD) •...
Page 138 CHAPTER 4 DMA MB96300 Super Series Hardware Manual Figure 4.3-4 Conﬁguration of DMACS Address: Bit No. 8*ch + 0x103 − − DMACS Read/Write: (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial Value: readable and writable R/W: no access; read returns undefined value, write always 0 to this bit −: [bit 13] BPD: Buffer pointer decrement bit BPD bit...
Page 139 MB96300 Super Series Hardware Manual CHAPTER 4 DMA [bit 9] DIR: Data transfer direction DIR bit Function Transfer from address specified by IOA to address specified by BAP (@IOA -> @BAP). Transfer from address specified by BAP to address specified by IOA (@BAP ->...
Page 140 CHAPTER 4 DMA MB96300 Super Series Hardware Manual 4.3.4 Buffer Address Pointer (BAP) This section describes the Buffer Address Pointer (BAP). ■ Buffer Address Pointer (BAP) The Buffer Address Pointer (BAP) is a 24-bit register and is used to store addresses that will be used for DMA transfer.
Page 141: Dma Controller Operation
MB96300 Super Series Hardware Manual CHAPTER 4 DMA DMA Controller Operation This section describes the DMA controller operation. ■ DMA Controller Operation Figure 4.4-1 "DMAC Operation" shows the DMA controller operation. Figure 4.4-1 DMAC Operation Peripheral function (I/O) I/O register I/O register (5a) DMA controller...
Page 142 CHAPTER 4 DMA MB96300 Super Series Hardware Manual ■ Procedure for using DMAC Figure 4.4-2 Procedure for using DMAC Software processing Hardware processing Interrupt occurence Start DISELx == IRQ number Initialize the system stack Initialize the peripheral function DER:ENx == 1 and DSR:DTEx == 0 Set the interrupt control register STOP request and...
Page 143 MB96300 Super Series Hardware Manual CHAPTER 4 DMA ■ Number of cycles for the data transfer The number of transfer cycles (bus cycles during DMA transfer) is the sum of all single transfers until DCT reaches 0. For reference of the number of cycles for a single DMA transfer, see Table 4.3-2, column "Transfer cycles".
Page 144: Examples Of Dma Transfers
CHAPTER 4 DMA MB96300 Super Series Hardware Manual Examples of DMA transfers This sections describes some of the lesser ordinary DMA transfer types or circumstances. To simplify matters an even address somewhere in memory bank 00 is used as IOA in the following examples. These examples still hold if the addresses of IOA and BAP are exchanged, under the constraint that IOA must refer to memory bank 00 .
Page 145 MB96300 Super Series Hardware Manual CHAPTER 4 DMA Figure 4.5-2 Transferring one word to/from an odd address 01CCAA 00BCDE ■ Word transfer with odd byte count When DCT is set to an odd number of bytes and word transfers are used, the last transfer moves only one byte.
Page 146 CHAPTER 4 DMA MB96300 Super Series Hardware Manual Figure 4.5-4 Transfer of the last byte of a channel set to word transfer and BAP decrement High byte Low byte Transfer 0 Transfer 0 01CCAA 01CCA8 High byte Low byte Transfer n Transfer n 00BCDE ■...
Page 147: Delayed Interrupt
CHAPTER 5 DELAYED INTERRUPT This chapter explains the functions and operations of the delayed interrupt. 5.1 "Outline of Delayed Interrupt Module" 5.2 "Delayed Interrupt Register" 5.3 "Delayed Interrupt Operation"...
Page 148: Outline Of Delayed Interrupt Module
CHAPTER 5 DELAYED INTERRUPT MB96300 Super Series Hardware Manual Outline of Delayed Interrupt Module The Delayed Interrupt source module is used to generate interrupts for task switching. Using this module, interrupts to the F MC-16FX CPU can be requested and canceled by software.
Page 149: Delayed Interrupt Register
MB96300 Super Series Hardware Manual CHAPTER 5 DELAYED INTERRUPT Delayed Interrupt Register DIRR controls request and cancellation of the Delayed Interrupt. Writing "1" to this register issues a delayed interrupt request, and writing "0" cancels the delayed interrupt request. ■ Delayed Interrupt Cause Issuance/Cancellation register (DIRR: Delayed Interrupt Request Register) Figure 5.2-1 Delayed Interrupt Cause/Cancel Register (DIRR) Address:...
Page 150: Delayed Interrupt Operation
CHAPTER 5 DELAYED INTERRUPT MB96300 Super Series Hardware Manual Delayed Interrupt Operation When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the Delayed Interrupt source module is set and an interrupt request is issued to the interrupt controller.
Page 151: Clocks
CHAPTER 6 CLOCKS This chapter describes the clocks used by F MC-16FX family micro controllers. 6.1 Clocks 6.2 Clock Control Registers 6.3 Clock Modes 6.4 Configuration of the PLL 6.5 Oscillation Stabilization Wait Time 6.6 Connection of an Oscillator or an External Clock to the Microcontroller...
Page 152: Clocks
CHAPTER 6 CLOCKS Clocks The F2MC-16FX MCU offers up to 4 different clock sources (RC clock, Main clock, PLL clock and Sub clock). Flexible clock dividers allow an independent setting of the Bus clock (for the internal bus with the CPU and memories) and for the Peripheral clocks frequencies.
Page 153 CHAPTER 6 CLOCKS ■ Block Diagram The following block diagram shows the clock sources, the generation of the internal clocks and the source clock timers of the F2MC-16FX MCU. The different clocks are described below. See also CHAPTER 1 OVERVIEW for a block diagram showing which modules are connected to which clocks. Figure 6.1-1 Block diagram of the clock generation and source clocks timers PLL configuration Clock modulator...
Page 154 CHAPTER 6 CLOCKS ■ Source clocks The following clock signals are the clock sources of the F2MC-16FX MCU. ● RC clock (CLKRC) The RC clock CLKRC is the output clock of the internal RC oscillator. The RC oscillator can generate two different clock frequencies (2MHz and 100kHz nominal, see datasheet) which can be selected with the RCFS (RC Clock Frequency Select) bit of the CKFCR register.
Page 155 CHAPTER 6 CLOCKS clock divider 1 out of the System clock 1 (CLKS1). ● System clock 2 (CLKS2) The System clock 2 (CLKS2) is a second master clock which is never modulated. It feeds the clock divider for the Peripheral Clock 2 (CLKP2) only. Depending on the SC2S[1:0] (System Clock 2 Select) bits of the CKSR register, one of the following 4 clocks can be selected as the System clock 2: CLKRC (RC clock), CLKMC (Main clock), CLKPLL (unmodulated PLL clock) or CLKSC (Sub clock).
Page 156: Clock Control Registers
CHAPTER 6 CLOCKS Clock Control Registers This section lists the clock control registers and describes the function of each register in detail. ■ Clock Control Registers Figure 6.2-1 Clock Control Registers shows an overview of all clock control registers Figure 6.2-1 Clock Control Registers CKSR: Clock Selection Register Address: (000400...
Page 157 CHAPTER 6 CLOCKS 6.2.1 Clock Selection Register (CKSR) The Clock Selection Register (CKSR) is used to control the System Clock selector 1 and 2 and the oscillation circuits. ■ Conﬁguration of the Clock Selection Register (CKSR) Figure 6.2-2 shows the configuration of the Clock Selection Register (CKSR) and Table 6.2-1 describes the function of each bit.
Page 158 CHAPTER 6 CLOCKS Table 6.2-1 Function Description of Each Bit of the Clock Selection Register (CKSR) (1/3) Bit name Function bit 8 - SC1S0 and SC1S1: • These bits control the System Clock 1 Selector for the source of the Bus clock and the bit 9 System Clock 1 Peripheral clock 1 according to the following table:...
Page 159 CHAPTER 6 CLOCKS Table 6.2-1 Function Description of Each Bit of the Clock Selection Register (CKSR) (2/3) Bit name Function bit 12 RCE: • This bit is used to enable/stop the internal RC oscillator. RC Clock Enable • Writing "1" to this bit enables the RC oscillator and writing "0" stops the oscillator. •...
Page 160 CHAPTER 6 CLOCKS Table 6.2-1 Function Description of Each Bit of the Clock Selection Register (CKSR) (3/3) Bit name Function bit 15 SCE: • This bit is used to enable/stop the Sub oscillation circuit. Sub Clock Enable • Writing "1" to this bit enables the Sub oscillator and writing "0" stops the oscillator. •...
Page 161 CHAPTER 6 CLOCKS 6.2.2 Clock Monitor Register (CKMR) The Clock Monitor Register (CKMR) is used to check the current status of the System clocks (Clock mode) and the status of the oscillation circuits. ■ Conﬁguration of the Clock Monitor Register (CKMR) Figure 6.2-3 shows the configuration of the Clock Monitor Register (CKMR) and Table 6.2-2 describes the function of each bit.
Page 162 CHAPTER 6 CLOCKS Table 6.2-2 Function Description of Each Bit of the Clock Monitor Register (CKMR) (1/2) Bit name Function bit 8 - SC1M0 and • These bits indicate which clock is currently used for the System Clock 1 according to bit 9 SC1M1: the following table:...
Page 163 CHAPTER 6 CLOCKS Table 6.2-2 Function Description of Each Bit of the Clock Monitor Register (CKMR) (2/2) Bit name Function bit 13 MCM: • This bit indicates if the main oscillator is ready or not. Main Clock • MCM = "1" means that the main oscillator is ready and can be used. If MCM = "1" Monitor bit although MCE was set to "0", then the Main oscillator has not been disabled because the Main clock or PLL clock is used for System Clock 1 or 2.
Page 164 CHAPTER 6 CLOCKS 6.2.3 Clock Stabilization Select Register (CKSSR) The Clock Stabilization Select Register (CKSSR) is used to select the stabilization times for the oscillation circuits, the PLL and for controlling the feedback resistors of the Main and Sub oscillation circuits. ■...
Page 165 CHAPTER 6 CLOCKS Figure 6.2-4 Conﬁguration of the Clock Stabilization Select Register (CKSSR) Initial value Address: 000402 1 1 1 1 1 1 1 1 MCST2 MCST1 MCST0 SRFBE MRFBE PCST SCST1 SCST0 R/W R/W R/W R/W R/W R/W R/W R/W bit2 bit1 bit0...
Page 166 CHAPTER 6 CLOCKS Table 6.2-3 Function Description of Each Bit of the Clock Stabilization Select Register (CKSSR) (1/2) Bit name Function bit 0 - MCST0 to MCST2: • These bits select the stabilization time for the Main oscillation circuit according to the bit 2 Main Clock following table:...
Page 167 CHAPTER 6 CLOCKS Table 6.2-3 Function Description of Each Bit of the Clock Stabilization Select Register (CKSSR) (2/2) Bit name Function bit 5 PCST: • This bits selects the stabilization time for the PLL clock according to the following PLL Clock table: Stabilization Time bit5...
Page 168 CHAPTER 6 CLOCKS 6.2.4 Clock Frequency Control Register (CKFCR) The Clock Frequency Control Register (CKFCR) is used to control the Peripheral clock dividers (1 and 2), the Bus clock divider and the RC oscillator frequency. ■ Conﬁguration of the Clock Frequency Control Register (CKFCR) Figure 6.2-5 shows the configuration of the Clock Frequency Control Register (CKFCR) and Table 6.2-4 describes the function of each bit.
Page 169 CHAPTER 6 CLOCKS Table 6.2-4 Function Description of Each Bit of the Clock Frequency Control Register (CKFCR) (1/2) Bit name Function bit 0 RCFS: • This bit is used to set the clock frequency of the internal RC oscillator. RC Clock •...
Page 170 CHAPTER 6 CLOCKS Table 6.2-4 Function Description of Each Bit of the Clock Frequency Control Register (CKFCR) (2/2) Bit name Function bit 12 - PC2D0 to PC2D3: • These bits control the clock divider for the Peripheral clock (CLKP2) according to bit 15 Peripheral Clock 2 the following table:...
Page 171 CHAPTER 6 CLOCKS 6.2.5 PLL and clock frequency Control Register (PLLCR) The PLL and clock frequency Control Register (PLLCR) is used to control all functions of the PLL multiplier circuit and to control the Peripheral Clock Divider of CLKP3. ■ Conﬁguration of the PLL and clock domain 3 frequency Control Register (PLLCR) Figure 6.2-6 show the configuration of the PLL and clock domain frequency 3 Control Registers (PLLCR) and Table 6.2-5 describes the function of each bit.
Page 172 CHAPTER 6 CLOCKS Figure 6.2-6 Conﬁguration of the PLL Control Register (PLLCR) Address: Initial value 000406 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 PC3D3 PC3D2 PC3D1 PC3D0 VMS2 VMS1 VMS0 PMS4 PMS3 PMS2 PMS1 PMS0 000407 R/W R/W R/W...
Page 173 CHAPTER 6 CLOCKS Table 6.2-5 Function Description of Each Bit of the PLL Control Register (PLLCR) (1/2) Bit name Function bit 0 - PMS0 to PMS4: • These bits control the PLL clock multiplier factor according to the following table: bit 4 PLL clock bit4...
Page 174 CHAPTER 6 CLOCKS Table 6.2-5 Function Description of Each Bit of the PLL Control Register (PLLCR) (2/2) Bit name Function bit 8- PC3D0 to PC3D3: For devices that do support CLKP3 bit 11 Peripheral Clock 3 • These bits control the clock divider for the Peripheral clock (CLKP3) according to Division select bits the following table: bit11...
Page 175 CHAPTER 6 CLOCKS 6.2.6 Clock Input and LVD Control Register (CILCR) The Clock Input and LVD Control Register (CILCR) is used to control additional functions of the oscillator circuit and the Low Voltage Detection Level. ■ Conﬁguration of the Clock Input and LVD Control Register (CILCR) Figure 6.2-7 shows the configuration of the Clock Input and LVD Control Registers (CILCR) and Table 6.2-6 describes the function of each bit.
Page 176 CHAPTER 6 CLOCKS Table 6.2-6 Function Description of Each Bit of the Clock Input and LVD Control Register (CILCR) Bit name Function bit 8 - LVL0 to LVL3: • These bits control the analog threshold level for the Low Voltage Detector (LVD): bit 11 Low Voltage Detector Level...
Page 177: Clock Modes
CHAPTER 6 CLOCKS Clock Modes Four clock modes are provided: RC clock mode, Main clock mode, PLL clock mode and Sub clock mode. ■ Deﬁnition of clock modes The clock mode of the MCU is defined by the source for the System clock 1 (CLKS1) which is selected by the SC1S[1:0] bits.
Page 178 CHAPTER 6 CLOCKS used for the System clock 2, the watchdog or clock stop detect function. Disabling these clocks also disables the corresponding source clock timers. ■ Clock source switching Clock source switching means changing the clock source for CLKS1 or CLKS2. ●...
Page 179 CHAPTER 6 CLOCKS the corresponding enable bit in the CKSR register to "1". After stabilization of the activated clock, the corresponding Clock monitor bit of the CKMR register is set and indicates the clock as "ready". • The Main clock must be enabled if the PLL clock should be enabled (The setting of PCE has no effect when MCE is set to "0").
Page 180: Configuration Of The Pll
CHAPTER 6 CLOCKS Configuration of the PLL The PLL multiplier circuit is used to generate the PLL clock out of the Main clock. 32 different multiplier values (mul-1 to mul-32) are available. ■ Components of the PLL clock multiplier circuit The following block diagram describes the modules of the PLL.
Page 181 CHAPTER 6 CLOCKS ● "1/n divider" (PLL clock divider) The "1/n divider" is controlled by the PMS[4:0] PLL clock Multiplier Select bits. It defines the frequency multiplication value of the PLL clock multiplier circuit (relation between CLKMC and CLKPLL). Multiplication values from 1 to 32 are available. However the minimum and maximum permitted frequencies for CLKMC, CLKVCO and CLKPLL (->CLKS1/S2) must be adhered.
Page 182 CHAPTER 6 CLOCKS Table 6.4-1 Recommended settings for the PMS[3:0], VMS[2:0] bits (2/2)for CLKMC=4MHz Main Requested Setting for Setting for Oscillation PLL output PMS[4:0] bits VMS[2:0] bits output frequency frequency (n division (m division frequency CLKMC CLKPLL value) value) CLKVCO 4 MHz 88 MHz "10101"...
Page 183: Oscillation Stabilization Wait Time
CHAPTER 6 CLOCKS Oscillation Stabilization Wait Time When the power is turned on, when stop mode is released or when a disabled clock is enabled, an oscillation stabilization wait time is required before the clock can be used. ■ Oscillation Stabilization Wait Interval Ceramic and crystal oscillators which can be connected to the X0/X1 and X0A/X1A pins generally require several ms to stabilize at their natural frequency (oscillation frequency) when oscillation starts.
Page 184 CHAPTER 6 CLOCKS Figure 6.5-1 Operation Immediately after Oscillation Starts Oscillator-activated Oscillation stabilization Clock can be used oscillation time wait interval as System clock X1/X1A Start of oscillation Stable oscillation Clock ready flag set ● RC clock stabilization interval The RC clock stabilization time is fixed to 64 RC clock cycles. However after a Power reset or an External reset (RST falling edge), an additional wait time of 700 RC clock cycle (Power reset) or 700 RC clock cycles (External reset) is applied by the reset extension circuit (see section 8.3 Startup after Power and External reset for more details).
Page 185: Connection Of An Oscillator Or An External Clock To The Microcontroller
Fast Clock Input feature). This feature is activated by setting the CILCR:FCI bit to ’1’ before switching the device to the external Main clock. Fujitsu recommends to always use the Fast Clock Input feature when connecting an external clock to the Main oscillator.
Page 186 CHAPTER 6 CLOCKS Figure 6.6-2 Example of Connecting an External Clock to the Microcontroller MC-16FX MCU X0(X0A) X1(X1A) Open...
Page 187: Clock Modulator
Clock Modulator. The clock modulator is currently being evaluated and should not be used for other purpose than testing. 7.1 "Overview" 7.2 "Register Description" 7.3 "Application Note" THIS FUNCTION IS UNDER EVALUATION AND MAY NOT BE USED. PLEASE CONTACT FUJITSU.
Page 188: Overview
CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual Overview This section describes an overview of the Clock Modulator. ■ Overview The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the spectrum of the clock signal over a wide range of frequencies. The module is fed with an unmodulated reference clock with frequency F0, provided by the PLL circuit.
Page 189: Register Description
MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR Register Description This section lists the clock modulator registers and describes the function of each register in detail. ■ Clock modulator registers Figure 7.2-1 Clock modulator registers CMCR: Clock Modulator Control Register Address: 000418 MOD- MODEN PDX...
Page 190 CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual 7.2.1 Clock Modulator Control Register (CMCR) The Control Register (CMCR) has the following functions: • Set the modulator to power down mode • Modulator enable/disable • Indicates the status of the modulator ■...
Page 191 MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR ■ Clock modulator control register contents Table 7.2-1 Function of each bit of the clock modulator control register (1/2) Bit name Function bit 0 PDX: "0": Power down mode Power down bit "1": Power up •...
Page 192 CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual Table 7.2-1 Function of each bit of the clock modulator control register (2/2) Bit name Function bit 2 MODRUN: "0": MCU is running with unmodulated clock Modulator status "1": MCU is running with modulated clock •...
Page 193 MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR 7.2.2 Clock Modulation Parameter Register (CMPR) The Clock Modulation Parameter Register (CMPR) determines the modulation degree. ■ Clock Modulation parameter register Figure 7.2-3 Clock Modulation parameter register CMPRL: Clock Modulator Parameter Register (lower) Address: 00041A R/W R/W R/W R/W R/W...
Page 194 CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual Frequency of unmodulated input clock (PLL frequency) Period of unmodulated input clock (PLL clock period) resolution: resolution of frequencies in the modulated clock. low (1) to high (7) minimal frequency occurring in the modulated clock maximal frequency occurring in the modulated clock phase skew: The maximal phase shift of the modulated clock relative to the unmodulated...
Page 195 MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR Table 7.2-4 Modulation Parameter recommended settings (2/2) F0 (MHz) resolution (MHz) +/- phase +/- phase CMPR degree skew skew (MHz) min/max [periods] [periods] 12.8 21.3 1.5625 4.0625 04AC 11.63 25.6 3.125 7.4375 04EA 13.47...
Page 196: Application Note
CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual Application Note This chapter describes the startup/stop sequence of the clock modulator and the modulation parameter settings. ■ Recommended startup/stop sequence start Switch modulator from power down to power up mode: Set PDX=1 Switch on PLL Wait PLL lock time (refer to the CKMR:PCM bit).
Page 197 MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR if the EMI measurements does not fulﬁll the requirements, you may either reduce the modulation degree at the same e.g. resolution: 7, degree: 1, CMPR = frequency resolution 0x3F9 (this may improve the reduction in the upper frequency band >...
Page 198 CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual...
Page 199: Resets And Startup
CHAPTER 8 RESETS AND STARTUP This chapter describes the resets and the startup of for the F2MC-16FX family microcontrollers. 8.1 "Resets" 8.2 "Reset, System clock and Stabilization Wait Times" 8.3 "Startup after Power and External reset" 8.4 "Boot ROM program execution and Operation mode and ROM Configuration Block"...
Page 200: Resets
CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Resets If a reset is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared. The CPU then begins with the Boot ROM program execution.
Page 201 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP ● Power reset A power reset is generated when the power is turned on with a power on rise time as specified in the datasheet (power-on reset) or when the low voltage detector detects that the power supply Vcc falls below a certain value as specified in the LVL bits of the CILCR register (low voltage reset).
Page 202 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual The contents of internal RAM and all registers which are not reset (initial value ’X’) is maintained. Note: *1: Except for bytes at addresses 7FFC-7FFF. The contents of the registers in the GPR bank 00 and 01 as well as the 4 above mentioned RAM bytes are undefined after each reset.
Page 203: Reset, System Clock And Stabilization Wait Times
MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Reset, System clock and Stabilization Wait Times The F2MC-16FX family has ﬁve reset causes. The System clocks (CLKS1 and CLKS2) are set to RC clock after each reset. The stabilization wait time depends on the reset cause and the status of the RC oscillator when the reset occurs.
Page 204 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual ● External reset asserted for less than 700 RC clock cycles The External reset extension time is not expired in this case. Hence the execution of the Boot ROM program by the CPU is delayed until the External reset extension time plus the RC clock stabilization time of 64 RC clock cycles is expired.
Page 205: Startup After Power And External Reset
MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Startup after Power and External reset After a Power or External reset event, the MCU waits for the stabilization of the power supply and the RC oscillator. Then the MCU starts executing the Boot ROM program with the RC clock as clock source (RC Run mode).
Page 206 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Figure 8.3-1 Block diagram of reset extension circuit CLKRC Clock Power reset extension counter (10bit) PRST Power-on event Init Low voltage event CLKRC Clock Power-on event External reset extension counter (10bit) Init Low voltage event falling edge detection...
Page 207 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP the Main clock timer is activated 700 RC clock cycles after a RST falling edge or 700 RC clock cycles after clearing a power-on or low voltage event. Thus the Main oscillation stabilization wait time takes place even if RST is still asserted.
Page 208: Boot Rom Program Execution And Operation Mode And Rom Configuration Block
CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Boot ROM program execution and Operation mode and ROM Configuration Block When the reset signal is released, the MCU starts with the execution of the internal Boot ROM program. The Boot ROM program reads the status of the mode pins (MD2-MD0), which deﬁne the operation mode of the MCU.
Page 209 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.4-1 Mode Pin settings Mode pin setting Conﬁguration of Operation mode Boot Vector external bus for Remarks name Source Boot Vector read access Serial Used for serial Flash Communication programming mode Internal Vector...
Page 210 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual The Internal Vector mode is available for all MCU types and the fixed Boot Vector is given by DF0080 ● Serial Communication mode (MD[2:0]="010") This mode allows the reading and writing of any memory address by serial communicated read/write commands.
Page 211 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.4-2 Structure of Main ROM Conﬁguration Block (MRCB) Offset Sub-block Marker Comment MFSB Secure Flash by 99 Reserved MFSUK Unlock key for secured Flash Security and Protection reserved conﬁguration block MFMWPAM Activation of write protection by 292D3A7B MFMWPSM...
Page 212 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual ■ Function description of RCB Markers ● Security and Protection Conﬁguration Block (SPCB) The read security feature prevents the unauthorized read-out of Flash contents and targets all cases other than read access by application in Internal Vector mode.
Page 213 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Figure 8.4-2 Conﬁguration of the UART Scan Deactivation Marker Address: DF0034 : USDM0 (lower word) DF0036 : USDM1 (upper word) USDM0 USDM1 When the content of {USDM1, USDM0} = 292D3A7BH, then no temporary UART scanning is performed. For any other value of {USDM1, USDM0}, the Boot ROM will scan dedicated UART channels for limited time after main reset.
Page 214 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual ■ Flowchart Internal Vector Mode Figure 8.4-4 Boot ROM sequence in Internal Vector Mode Internal Vector Mode not protected (M/S)FMWPAM Main Reset ? set ? write protected Write FMWC USDM set? conﬁguration Scan UART MFSB or...
Page 215 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP ■ Flowchart in External Vector Mode Figure 8.4-5 Boot ROM sequence in External Vector Modes External External External Vector Mode 0 Vector Mode 1 Vector Mode 2 Get conﬁguration Get conﬁguration Get conﬁguration 8bit multiplex 16bit multiplex...
Page 216: Reset Control Registers
CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Reset Control Registers This section lists the Reset Control Registers and describes the function of each register in detail. ■ Reset Control Registers The Reset Controller has two registers, the Reset Configuration Register (RCR) and the Reset Cause and Clock status Register (RCCSR/RCCSRC).
Page 217 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP 8.5.1 Reset Conﬁguration Register (RCR) The Reset Conﬁguration Register (RCR) is used to assert a Software reset, conﬁgure the low voltage reset and detector and to conﬁgure the Clock stop detection circuit. ■...
Page 218 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Figure 8.5-2 Conﬁguration of the Reset Conﬁguration Register (RCR) Address: Initial value 00040C X X 0 0 0 1 1 0 LVDE LVRE SRSTG SCSDI MCSDI CSDRE R/W R/W R/W R/W R/W bit0 SRSTG...
Page 219 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.5-1 Function Description of Each Bit of the Reset Conﬁguration Register (RCR) (2/3) Bit name Function bit 1 LVRE: • This bit controls the Low voltage reset function which is one reset cause of the Power Low Voltage Reset reset.
Page 220 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Table 8.5-1 Function Description of Each Bit of the Reset Conﬁguration Register (RCR) (3/3) Bit name Function bit 5 SCSDI: • This bit controls the measurement interval of the Sub clock stop detection circuit. Sub Clock Stop •...
Page 221 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP 8.5.2 Reset Cause and Clock Status Register (RCCSR/ RCCSRC) The RCCSR/RCCSRC register shows the reset cause and the status of the Main and Sub clock ■ Conﬁguration of the Reset Cause and Clock Status Register (RCCSR/RCCSRC) The Reset Cause and Clock Status Register (RCCSR/RCCSRC) can be accessed at two addresses.
Page 222 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Figure 8.5-3 Conﬁguration of the Reset Cause and Clock Status Register (RCCSR/RCCSRC) Initial value X X X X X X X X Address: SCMF MCMF WRST SRST SCRST MCRST ERST PRST 00040B (RCCSRC) R/C R/C R/C R/C R/C...
Page 223 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.5-2 Function Description of the Bits of the Reset Cause and Clock Status Register (RCCSR) (1/2) Bit name Function bit 8 PRST: • This bit indicates if a Power reset was generated. Power Reset •...
Page 224 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Table 8.5-2 Function Description of the Bits of the Reset Cause and Clock Status Register (RCCSR) (2/2) Bit name Function bit 14 MCMF: • This bit indicates if a missing Main clock was detected. Main Clock •...
Page 225 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP address 00040B . Any bit corresponding to a reset cause that has already been generated is not cleared when another reset is generated (a setting of "1" is retained). After a Power reset, the register should be cleared by reading in order to initialize all bits. Note: If the power is turned on under conditions where power-on reset may not occur (power-on profile as specified in the datasheet not met), the value in RCCSR register is not guaranteed.
Page 226 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual 8.5.3 Clock Input and LVD Control Register (CILCR) The Clock Input and LVD Control Register (CILCR) is used to control additional functions of the oscillator circuit and the Low Voltage Detection Level. ■...
Page 227 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.5-4 Function Description of Each Bit of the Clock Input and LVD Control Register (CILCR) Bit name Function bit 8 - LVL0 to LVL3: • These bits control the analog threshold level for the Low Voltage Detector (LVD): bit 11 Low Voltage Detector Level...
Page 228: Operation Of The Clock Stop Detection Function And Reset
CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Operation of the Clock stop detection function and reset This section describes the operation of the clock stop detection circuit that detects a failure of the external Main or Sub oscillator. ■...
Page 229 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.6-1 Clock stop detection interval Clock Stop Detection Interval RC clock Time for RC clock Time for RC clock Observed Select cycles frequency of frequency of Setting clock 2MHz (min - max) / 100kHz (min - max) (minimum / (minimum...
Page 230 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual ● Activation of the Clock stop detection reset The Clock stop detection reset is enabled by setting the RCR: CSDRE bit to "1". ● Generating a Clock stop detection reset A Clock stop detection reset is generated in the following cases.
Page 231 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP ● Stop mode All oscillators including the RC oscillator are disabled in Stop mode, hence no clock stop detection is possible. If an interrupt is asserted in Stop mode, then the MCU changes to Run mode with the clocks specified in the CKSR register.
Page 232: Operation Of The Low Voltage Reset Function
CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Operation of the low voltage reset function This section describes the operation of the low voltage reset function. ■ Function of the low voltage reset The low voltage reset function is using the low voltage detector that compares the power supply voltage V with an internally generated reference voltage.
Page 233 MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP ● Effect on current consumption The low voltage detector draws a current when it is activated (see datasheet for details). This current flows independent of the selected operation mode. If this is not acceptable when using standby modes, disable the low voltage detector and reset before changing to standby mode.
Page 234 CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual...
Page 235: Standby Mode And Voltage Regulator Control Circuit
CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT This chapter explains the functions and operations of the standby mode control circuit and the control of the internal voltage regulator. The regulator control can be used to optimize power consumption, especially in standby modes. 9.1 "Overview of the CPU Operating Modes"...
Page 236: Overview Of The Cpu Operating Modes
CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Overview of the CPU Operating Modes The F MC-16FX MCU has the following CPU operating modes: • Run mode • Sleep mode • Timer mode • Stop mode Sleep mode, Timer mode and Stop mode are called Standby modes.
Page 237 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Figure 9.1-1 CPU operating mode and current consumption Current consumption Several tens of mA PLL Run mode PLL Sleep mode Main Run mode Main Sleep mode PLL Timer mode RC Run mode RC Sleep mode Main Timer mode...
Page 238 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Figure 9.1-2 Mode change diagram Reset reset release & RC clock ready SC1S=00 & SC1S=01 & SC1S=10 & SC1S=11 & SC1M!=00 SC1M!=01 SC1M!=10 SC1M!=11 RC clock ready Main clock ready PLL clock ready Sub clock ready RC Run...
Page 239 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL peripheral functions. Independent clock dividers for the Bus clock operating the CPU (CLKB) and the Peripheral clock 1 operating most peripheral functions (CLKP1) are fed by the Main clock and allow flexible frequency settings.
Page 240 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series selector. The status of the PLL multiplier circuit, the RC and Sub oscillator depend on the setting of the PCE, RCE and SCE bits when they are not used as System clock 2. ●...
Page 241 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Note: The different Timer modes may have the same behavior if more than one of the PCE, MCE, SCE and RCE bits is set to "1". However, the run mode that the device transits to, upon wakeup from timer mode by interrupt, depends on which of the four timer modes the device was in.
Page 242: Standby Mode Control Register (Smcr)
CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Standby Mode Control Register (SMCR) This register switches to standby mode, controls the pin functions in Timer and Stop mode and sets the voltage regulator to Low Power mode. ■...
Page 243 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Table 9.2-1 Function description of each bit of the standby mode control register (SMCR) Bit name Function bit 0 - SMS0 and SMS1: • These bits request switching to a Standby mode according to the following table: bit 1 Standby Mode Select bit1...
Page 244 ~40µs for switching the regulator back to High Power Mode or Low Power Mode A Note: Do not change this bit, because this function is currently under evaluation by Fujitsu. bit 6 - Reserved • Always write "0" to these bits.
Page 245: Voltage Regulator Control Register (Vrcr)
MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Voltage Regulator Control Register (VRCR) The voltage regulator control register deﬁnes the output voltage of the internal Voltage Regulator in different operation modes ■ Voltage Regulator Control Register (VRCR) Figure 9.3-1 shows the configuration of the Voltage Regulator Control Register (VRCR) and Table 9.3-1 describes the function of each bit.
Page 246 Sub Timer mode) when the Main and RC oscillators are both disabled. It can also be selected with the SMCR:LPMS and LPMSS bits under certain conditions. Note: Do not change these bits, because permitted settings are currently under evaluation by Fujitsu.
Page 247 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Table 9.3-1 Function Description of Each Bit of the Voltage Regulator Control Register (VRCR) (2/2) Bit name Function bit 6 - HPM0 to HPM1: • These bits select the output voltage of the regulator in High Power Mode according to bit 7 High Power Mode the following table:...
Page 248: Standby Modes
CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Standby Modes The standby modes include the Sleep (RC Sleep, Main Sleep, PLL Sleep, Sub Sleep), Timer (RC Timer, Main Timer, PLL Timer, Sub Timer) and Stop modes.
Page 249 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL ■ Operation status during standby mode Table 9.4-1 "Operation status during standby mode" shows the status of the clocks, CPU, Peripherals and external pins for the different standby modes. Table 9.4-1 Operation status during standby mode Condition Main...
Page 250 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series 9.4.1 Sleep mode (RC Sleep, Main Sleep, PLL Sleep, Sub Sleep mode) This mode causes the CPU operating clock (Bus clock CLKB) to stop while other components continue to operate. Transition to Sleep mode is done by writing to the standby mode control register (SMCR).
Page 251 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Note: To make sure instructions following the SMS write instruction are executed after wakeup from Sleep mode (and not before transition to Sleep mode), poll the SMS bits after setting to "01". Branch to the next instruction only when the SMS bits are cleared to "00".
Page 252 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Figure 9.4-1 Release of the Sleep Mode by External Reset RST Pin Sleep mode RC clock Depends on RCE bit Oscillating Main clock Depends on MCE bit Oscillating PLL clock Depends on PCE bit Stopped...
Page 253 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL 9.4.2 Timer Mode (RC Timer, Main Timer, PLL Timer, Sub Timer mode) This mode causes all functions, excluding oscillators, PLL and source clock timers, to stop. Transition to Timer mode is done by writing to the standby mode control register (SMCR).
Page 254 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Note: To make sure instructions following the SMS write instruction are executed after wakeup from Timer mode (and not before transition to Timer mode), poll the SMS bits after setting to "10". Branch to the next instruction only when the SMS bits are cleared to "00".
Page 255 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Figure 9.4-3 Release of the Timer Mode by External Reset RST Pin Timer mode RC clock Depends on RCE bit Oscillating Main clock Depends on MCE bit Oscillating PLL clock Depends on PCE bit...
Page 256 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series 9.4.3 Stop Mode Because this mode causes all oscillators to stop and inactivates all functions, data can be retained by the lowest power consumption. ■ Functions in Stop Mode ●...
Page 257 MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Note: Setting the SMS bits to "11" (Stop mode) is allowed together with changing the clock mode (by writing a new value to the SC1S or SC2S System Clock Select bits of the CKSR register). The new clock setting becomes effective immediately after leaving the Stop mode.
Page 258 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Figure 9.4-5 Release of the Stop Mode by External Reset RST Pin Stop mode RC clock Stopped Oscillating Main clock Stopped Oscillating PLL clock Stopped Stopped Sub clock Stopped Oscillating CPU clock...
Page 259: Mode Change Table And Operation Status
MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Mode Change Table and operation status Table 9.5-1 show the mode change table of the F MC-16FX MCU and Table 9.5-2 shows the operation status in each operating mode. ■...
Page 260 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series ■ Operation status in each operating mode Table 9.5-2 lists the operation status in each operating mode. Table 9.5-2 Operation status in each operating mode RC oscillator Main Clock Clock source for Operation...
Page 261: Usage Notes On Standby Mode
MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Usage Notes on Standby Mode Note the following items when using the standby modes: • Switching to a standby mode and Interrupt • Release of the standby mode by an Interrupt •...
Page 262 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Note: After Stop mode release, the CPU starts operating after stabilization of the System clock 1 selected by the SC1S bit. However another clock can be selected as System clock 2 with a longer stabilization time. If the CPU tries to access a peripheral resource clocked by the Peripheral clock 2, then the CPU will be put into hold state until CLKP2 is stabilized and the access can be completed.
Page 263: Voltage Regulator Operation
MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Voltage Regulator Operation The 16FX MCUs are equipped with an on-chip voltage regulator which generates the power supply for the core logic out of the external power supply. This regulator has different operation modes with programmable output voltage.
Page 264 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series 9.7.1 Changing the Voltage Regulator operation mode The voltage regulator operation modes are automatically controlled by hardware depending on the selected CPU operation mode. However in some modes and under certain conditions, it is permitted to manually change the regulator from High Power mode to Low Power mode for further current saving.
Page 265 Switching to the Low Power mode B with the SMCR:LPMBSS bit Note: Do not change this bit, because this function is under evaluation by Fujitsu. Setting the SMCR:LPMBSS bit to "1" switches the voltage regulator to the Low Power mode B instead of Low Power mode A after the next transition to a Standby mode.
Page 266 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series ■ Permitted conﬁgurations for using the Low Power mode of the voltage regulator The voltage regulator can be switched to the Low Power mode (setting SMCR:LPMS or LMPSS to "1") in the following configurations: Table 9.7-1 Permitted conﬁgurations for using the Low Power mode A Operation...
Page 267 The default output voltage of the regulator in Low Power mode A and B is 1.8V. ● Changing the Core voltage in Low Power mode A Changing the output voltage of the regulator in the Low Power mode A is not approved by Fujitsu. ● Changing the Core voltage in Low Power mode B For applications which require a small current consumption in Stop mode, it is possible to reduce the core voltage to 1.2V by setting the VRCR:LPMB[2:0] bits to "000"...
Page 268 CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series...
Page 269: Source Clock Timers
CHAPTER 10 SOURCE CLOCK TIMERS This chapter explains the functions and operations of the three source clock timers (RC clock timer, Main clock timer and Sub clock timer). 10.1 "Overview" 10.2 "RC Clock Timer" 10.3 "Main Clock Timer" 10.4 "Sub Clock Timer"...
Page 270: Overview
CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.1 Overview The MB96300 Super series offers 3 independent source clock timers (RC clock timer, Main clock timer and Sub clock timer) which can issue interrupts at speciﬁed intervals and which are used to measure the oscillation stabilization time. ■...
Page 271: Rc Clock Timer
MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.2 RC Clock Timer The RC clock timer consists of a 23-bit counter and a control register. The 23-bit counter divides the RC clock CLKRC. The RC clock timer issues interrupts at speciﬁed intervals based on carry signals of the RC clock counter.
Page 272 CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.2.1 RC Clock Timer Control Register (RCTCR) The RC Clock Timer Control Register (RCTCR) is used to control the RC clock timer interval interrupt function and to reset the RC clock timer. ■...
Page 273 MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS Figure 10.2-2 Conﬁguration of the RC Clock Timer Control Register (RCTCR) Address: Initial value 000408 X 0 0 1 0 0 0 0 RCTI2 RCTI1 RCTI0 RCTIE RCTIF RCTR RCTI3 R/W R/W R/W R/W R/W bit3...
Page 274 CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual Table 10.2-1 Function Description of Each Bit of the RC Clock Timer Control Register (RCTCR) Bit name Function bit 0 - RCTI0 to RCTI3: • These bits control the RC clock timer interrupt interval according to the following bit 3 RC Clock Timer table:...
Page 275 MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.2.2 Operations of RC Clock Timer The RC clock timer functions as an interval timer for generating interrupts at speciﬁed intervals. ■ RC clock counter The RC clock counter consists of a 23-bit counter that is clocked with the RC clock CLKRC. When the RC clock is active, the RC clock counter always keeps counting.
Page 276: Main Clock Timer
CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.3 Main Clock Timer The Main clock timer consists of a 23-bit counter and a control register. The 23-bit counter divides the Main clock CLKMC. The Main clock timer issues interrupts at speciﬁed intervals based on carry signals of the Main clock counter.
Page 277 MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.3.1 Main Clock Timer Control Register (MCTCR) The Main Clock Timer Control Register (MCTCR) is used to control the Main clock timer interval interrupt function and to reset the Main clock timer. ■...
Page 278 CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual Figure 10.3-2 Conﬁguration of the Main Clock Timer Control Register (MCTCR) Address: Initial value 000409 X 0 0 1 0 0 0 0 MCTI2 MCTI1 MCTI0 MCTIE MCTIF MCTR MCTI3 R/W R/W R/W R/W R/W bit11...
Page 279 MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS Table 10.3-1 Function Description of Each Bit of the Main Clock Timer Control Register (MCTCR) Bit name Function bit 8 - MCTI0 to MCTI2: • These bits control the Main clock timer interrupt interval according to the following bit 11 Main Clock Timer table:...
Page 280 CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.3.2 Operations of Main Clock Timer The Main clock timer functions as an interval timer for generating interrupts at speciﬁed intervals and as a timer for waiting for the Main oscillation to stabilize. ■...
Page 281: Sub Clock Timer
MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.4 Sub Clock Timer The Sub clock timer consists of a 17-bit counter and a control register. The 17-bit counter divides the Sub clock CLKSC. The Sub clock timer issues interrupts at speciﬁed intervals based on carry signals of the Sub clock counter.
Page 282 CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.4.1 Sub Clock Timer Control Register (SCTCR) The Sub Clock Timer Control Register (SCTCR) is used to control the Sub clock timer interval interrupt function and to reset the Sub clock timer. ■...
Page 283 MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS Figure 10.4-2 Conﬁguration of the Sub Clock Timer Control Register (SCTCR) Address: Initial value 00040A X 0 0 1 X 0 0 0 SCTI2 SCTI1 SCTI0 SCTIE SCTIF SCTR R/W R/W R/W R/W R/W bit2 bit1...
Page 284 CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual Table 10.4-1 Function Description of Each Bit of the Sub Clock Timer Control Register (SCTCR) Bit name Function bit 0 - SCTI0 to SCTI2: • These bits control the Sub clock timer interrupt interval according to the following bit 2 Sub Clock Timer table:...
Page 285 MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.4.2 Operations of Sub Clock Timer The Sub clock timer functions as an interval timer for generating interrupts at speciﬁed intervals and as a timer for waiting for the Sub oscillation to stabilize. ■...
Page 286 CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual...
Page 287: Watchdog Timer And Watchdog Reset
CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET This chapter explains the functions and operations of the Watchdog timer and reset. 11.1 "Outline of Watchdog Timer and Reset" 11.2 "Watchdog Timer Control Registers" 11.3 "Watchdog Timer Operation"...
Page 288: Outline Of Watchdog Timer And Reset
CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual 11.1 Outline of Watchdog Timer and Reset The watchdog circuit consists of a 24-bit watchdog counter, control registers and the watchdog reset controller. The 24-bit watchdog counter uses either the RC clock, the Main clock or the Sub clock as clock source.
Page 289: Watchdog Timer Control Registers
MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET 11.2 Watchdog Timer Control Registers This section lists the Watchdog Timer Control Registers and describes the function of each register in details. ■ Watchdog Timer Control Registers The Watchdog Timer has two control registers, the Watchdog Timer Configuration register (WDTC) and the Watchdog Timer Clear Pattern register (WDTCP).
Page 290 CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual 11.2.1 Watchdog Timer Conﬁguration register (WDTC) The Watchdog Timer Conﬁguration register (WDTC) is used to select the clock source and the watchdog interval and to activate some special functions of the Watchdog Timer. ■...
Page 291 MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET Figure 11.2-2 Conﬁguration of the Watchdog Timer Conﬁguration Register (WDTC) Address: Initial value 00040E X 0 0 0 0 0 0 0 WTI2 WTI1 WTI0 RSTP WTCS1 WTCS0 WTI3 R/W R/W R/W R/W R/W R/W R/W bit3...
Page 292 CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual Table 11.2-1 Function Description of Each Bit of the Watchdog Timer Conﬁguration register (WDTC) (1/2) Bit name Function bit 0 - WTI0 to WTI3: • These bits select the Watchdog Timer Interval according to the following table: bit 3 Watchdog Timer bit3...
Page 293 MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET Table 11.2-1 Function Description of Each Bit of the Watchdog Timer Conﬁguration register (WDTC) (2/2) Bit name Function bit 4 - WTCS0 to • These bits select the clock source for the Watchdog Timer according to the following bit 5 WTCS1: table:...
Page 294 CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual 11.2.2 Watchdog Timer Clear Pattern register (WDTCP) The Watchdog Timer Clear Pattern register (WDTCP) is used to activate the Watchdog reset function and to clear the Watchdog counter. ■...
Page 295: Watchdog Timer Operation
MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET 11.3 Watchdog Timer Operation The Watchdog timer and reset function can be used to detect a hang-up of the user program. If the Watchdog counter is not cleared within the speciﬁed time due to, for example, a program hang-up, the Watchdog timer resets the system.
Page 296 CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual When the RC clock should be used as clock source and the system requires changing the RC clock frequency during operation, then set the WDTC: WTCS[1:0] bits to "00". Be aware that changing the RC clock frequency also changes the Watchdog Timer interval.
Page 297 MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET Writing the same data as currently stored in the WDTCP register has no effect. Writing the complementary data of the current WDTCP contents clears the Watchdog counter and replaces the current value in the WDTCP register.
Page 298 CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual • The RC clock frequency was changed although WDTC:WTCS was set to "01". • Transition to Stop mode was requested although WDTC:RSTP was set to ’1’.
Page 299: External Bus Interface
CHAPTER 12 EXTERNAL BUS INTERFACE This chapter explains the functions and operations of the external bus interface. 12.1 "Outline of External Bus" 12.2 "External bus configuration registers" 12.3 "External Memory Access Control Signal Operation" 12.4 "Notes on using the external bus" 12.5 "External Boot Vector fetch"...
Page 300: Outline Of External Bus
CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.1 Outline of External Bus The External Bus interface of the F MC-16FX MCU provides various access methods and access areas.
Page 301 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE 12.1.1 Features of the External Bus Interface This chapter summarizes the features of the External Bus Interface ■ Features of the External Bus Interface • 16 data lines • Up to 24 address lines (depending on the device) •...
Page 302 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.1.2 Terminology This chapter explains some basic terms of the External Bus Interface. ● Bus mode Bus mode means the mode for controlling the internal ROM operation and external access function. The bus mode depends on the EAE[5:0] and ERE bits of the External Bus Mode register (EBM).
Page 303 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE 12.1.3 External bus areas Up to 6 external bus areas with dedicated Chip select signals can be conﬁgured independently. The 16MB address area can be divided into 6 external address areas with corresponding Chip select signals.
Page 304 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.1.4 Memory Space in Each Bus Mode Figure 12.1-1 "Relationship between Access Areas and Physical Addresses for Each Bus Mode" shows the correspondence between the access areas and physical addresses for each bus mode.
Page 305 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ Memory Space in Each Bus Mode Figure 12.1-1 Relationship between Access Areas and Physical Addresses for Each Bus Mode Single chip Internal ROM, external ROM, external bus external bus ff.ffff ROM/Flash ROM/Flash...
Page 306: External Bus Configuration Registers
CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2 External bus configuration registers The external bus contains various registers to change the external bus conﬁguration for a wide range of external bus protocols: - External Bus Mode register (EBM) - External Bus Clock and Function register (EBCF) - External Bus Address output Enable register [2:0] (EBAE[2:0]) - External Bus Control Signal register (EBCS)
Page 307 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ Overview of External bus conﬁguration registers Figure 12.2-1 External bus conﬁguration registers External Bus Mode register Initial value address: 0006F0 EAE5 EAE4 EAE2 EAE3 EAE1 EAE0 00000000 External Bus Clock and Function register EBCF Initial value address: 0006F1...
Page 308 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.2-2 External bus conﬁguration registers External Area Configuration register 0 (lower byte) EACL0 Initial value address: 0006E0 00000000 External Area Configuration register 0 (upper byte) EACH0 Initial value address: 0006E1 XX000XXX External Area Configuration register 1 (lower byte) EACL1...
Page 309 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.2-3 External bus conﬁguration registers External Area Configuration register 4 (lower byte) EACL4 Initial value address: 0006E8 00000000 External Area Configuration register 4 (upper byte) EACH4 Initial value address: 0006E9 EASZ2 EASZ1 EASZ0 XX000110 External Area Configuration register 5 (lower byte)
Page 310 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.1 External Bus Mode registers (EBM) The External Bus Mode register deﬁnes the bus mode of the external bus interface. For the External Boot Vector fetch, the external bus mode byte is read externally from the address FFFFDF and written to the register directly after reading the Boot Vector.
Page 311 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Bit name Function bit [5:0] EAE[5:0]: • The EAE (External Area Enable) bits are used to activate the External address External area enable areas • ’0’ - the corresponding external address area is disabled. All other settings for this area have no effect.
Page 312 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.2 External Bus Clock and Function register (EBCF) The External Bus Clock and Function register controls the external bus clock, the External Ready and the Hold function: - Hold-function - External Ready function - Clock output enable - Clock active edge - Clock output mode...
Page 313 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ External Bus Clock and Function register Figure 12.2-5 External Bus Clock and Function register (EBCF) Address: Initial value 0006F1 0 0 0 0 0 0 0 0 DIV2 DIV1 DIV0 R/W R/W R/W R/W R/W R/W R/W R/W...
Page 314 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Table 12.2-2 Function description of each bit of the External bus clock and Function register Bit name Function bit[10: 8] DIV[2:0]: • These bits control the clock divider for the external bus clock signal pin External bus clock (ECLK).
Page 315 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Table 12.2-2 Function description of each bit of the External bus clock and Function register Bit name Function bit 12 CKI: • This bit controls the active edge of the external bus clock. External bus clock •...
Page 316 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.3 External Bus Address output Enable registers (EBAE[2:0]) The External Bus Address output Enable registers controls the output function of each address line. ■ External Bus Address output Enable register Figure 12.2-6 External Bus Address output Enable register EBAE[2:0] Address: Initial value...
Page 317 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE All pins used for address outputs must be enabled by the corresponding bit of the EBAE register. This includes shared address/data pins in the multiplexed external bus mode. The address output of all address and address/data pins is active only during an external bus access. The address is not driven in a pause between two external bus accesses.
Page 318 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.4 External Bus Control Signal register (EBCS) This register is used to conﬁgure control signals of the external bus: - Activation of Write strobe, Read strobe and Byte select outputs - Activation of the Address strobe output and selection of the active level ■...
Page 319 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Bit name Function bit 8 LBE: • This bit enables the output of the LB byte select signal. Byte Select LB • ’0’ - output of the LB byte select signal is disabled (I/O port function enabled) output enable •...
Page 320 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.5 External Area Conﬁguration registers (EACH/EACL[5:0]) The External Area Conﬁguration registers are used to conﬁgure the following settings for each external area: - Automatic ready function - Address cycle length - Strobe signal timing - Write strobe function - Little/big endian data format...
Page 321 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.2-8 External Area Conﬁguration register (lower byte) EACL[5:0] Address: 0006E0 Initial value 0006E2 0006E4 0 0 0 0 0 0 0 0 0006E6 0006E8 0006EA R/W R/W R/W R/W R/W R/W R/W R/W bit2 bit1...
Page 322 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Bit name Function bit [2:0] R[2:0]: • These bits enable the automatic ready function and select the number of wait automatic ready cycles for the External area. function bit2 bit1 bit0 Automatic ready function Automatic ready function disabled...
Page 323 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Bit name Function bit 7 This bit selects the data width of the external bus for the corresponding address external bus data area. width • ’0’ - 16-bit data width selected. •...
Page 324 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Table 12.2-3 Endian selection access selected bus sequence on external bus width on width of the little endian (ES = ’0’) big endian (ES = ’1’) internal bus external bus 8-bit 16-bit internal...
Page 325 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.2-9 External Area Conﬁguration register (upper byte) EACH[5:0] Address: 0006E1 0006E3 Initial value 0006E5 X X 0 0 0 1 1 0 EASZ2 EASZ1 EASZ0 0006E7 0006E9 0006EB R/W R/W R/W R/W R/W R/W bit10 bit9...
Page 326 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Bit name Function bit[10:8] EASZ[2:0]: • These bits are used to deﬁne the size of the External area. The setting deﬁnes External Area Size which bits of the corresponding External Area Select register (EAS) are used for the address comparison.
Page 327 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE 12.2.6 External Area Select register (EAS[5:2]) The external bus interface supports two types of External address areas: - Areas with ﬁxed address range (External areas 0 and 1) - Areas with selectable address range (External areas 2 to 5) ■...
Page 328 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 10.0000 in 4 sections. The external area 5 and the corresponding Chip select CS5 is used during external reset vector fetch, except on MB96(F)38x at external Boot Vector fetch in non-multiplexed bus mode, where external area 4 and CS4 are used.
Page 329 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE EAS2= 00 EACH2: EASZ = "110" - not decoded banks: 40...FF - decoded banks: 00...3F 00...0F: no access possible because not selectable for external area 2-5. 10...3F: access possible If an address inside the possible address range of the external bus is accessed but the address is not within the area of an activated external bus area, then the access has no effect (a read access returns ’0’...
Page 330: External Memory Access Control Signal Operation
CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.3 External Memory Access Control Signal Operation This chapter describes the control signals during external bus operations. ■ Multiplexed external bus mode ● All timing charts are shown with following settings •...
Page 331 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ● Timing charts for multiplexed bus modes Figure 12.3-1 Multiplexed 16-bit bus: Word and Byte access for EACL:STS=’0’ and EACL:ACE=’0’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00]...
Page 332 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-2 Multiplexed 16-bit bus: Word and Byte access for EACL:STS=’1’ and EACL:ACE=’0’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...
Page 333 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-3 Multiplexed 16-bit bus: Word and Byte access for EACL:STS=’0’ and EACL:ACE=’1’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...
Page 334 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-4 Multiplexed 16-bit bus: Word and Byte access for EACL:STS=’1’ and EACL:ACE=’1’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...
Page 335 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-5 Multiplexed 8-bit bus: Word and Byte access for EACL:STS=’0’ and EACL:ACE=’0’ ECLK Addr 1 (CS1 area) Addr 1 + 1 Addr 2 (CS2 area) A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 (CS1 area) Addr 1 + 1...
Page 336 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-6 Multiplexed 16-bit bus: One automatic ready wait cycle added (EACL:R[2:0]=’001’, EACL:STS=’0’, EACL:ACE=’0)’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...
Page 337 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ Non-multiplexed external bus mode ● All timing charts are shown with following settings • CSx active level is ’L’: EACHx:CSL=’0’ • all address outputs are enabled: EBAE:A[23:00]=’11...11’ • The inactive level of the external clock is ’0’: EBCF: CKI = ’0’ ●...
Page 338 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual ● Timing charts for non-multiplexed bus mode Figure 12.3-7 Non-multiplexed 16-bit bus: Word and Byte access for EACL:STS=’0’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) Addr 4 (CS1 area) A[23:16] Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area)
Page 339 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-8 Non-multiplexed 16-bit bus: Word and Byte access for EACL:STS=’1’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) Addr 4 (CS1 area) A[23:16] Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) Addr 4 (CS1 area) A[15:00] AD[15:08]...
Page 340 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-9 Non-multiplexed 8-bit bus: Word and Byte access for EACL:STS=’0’ and EACL:ACE=’0’ ECLK Addr 1 (CS1 area) Addr 1 + 1 Addr 2 (CS2 area) Addr 3 (CS1 area) A[23:16] Addr 1 (CS1 area) Addr 1 + 1...
Page 341 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-10 Non-multiplexed 16-bit bus: One automatic ready wait cycle added (EACL:R[2:0]=’001’, EACL:STS=’0’, EACL:ACE=’0)’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[23:16] Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[15:00]...
Page 342 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.3.1 Ready Function Enabling the external ready function (RDY-pin) and/or the automatic wait function enables access to low-speed memory and peripheral circuits. ■ Ready Function The read and write access to an external device can be extended with the ready function. The F MC-16FX MCU offers two possibilities to extend the data cycle of the external access, the automatic ready function and the external ready function.
Page 343 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-11 Multiplexed 16-bit bus: Data cycle extended by external ready function ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...
Page 344 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-12 Non-multiplexed 16-bit bus: Data cycle extended by automatic and external ready function ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[23:16] Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[15:00]...
Page 345 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE 12.3.2 Hold Function The Hold function is used if multiple devices are used to access the same external bus. The Hold function is enabled by setting the HDE-bit in the External Bus Clock and Function register (EBCF) to ’1’.
Page 346 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual corresponding DDR register to "output" and writing the required pin level to the PDR register. The Hold state is left by setting the HRQ-pin back to ’0’. Then the HAK-pin outputs high-level, and all other output pins restore the values which they were driving before the Hold state.
Page 347 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-13 Hold request in multiplexed 16-bit bus mode ECLK Addr 1 (CS1 area) Addr 2 (CS2 area) A[23:16] Addr 1 Addr 3 AD[15:08] Addr 1 Addr 3 AD[07:00] Addr 1 Write Data 1 Addr 3 AD[15:08]...
Page 348: Notes On Using The External Bus
CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.4 Notes on using the external bus The handling of pins for the external bus is the same as for all other resources. This chapter describes how to set up the necessary pin to use the external bus interface. ■...
Page 349 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Table 12.4-1 Recommended state of external bus pins Pin name Status Operation mode 8-bit 16-bit 8-bit 16-bit non-multiplexed non-multiplexed multiplexed multiplexed during external bus used for data used for data access used for address output (if enabled in EBAE0) AD[07:00]...
Page 350 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Table 12.4-1 Recommended state of external bus pins Pin name Status Operation mode 8-bit 16-bit 8-bit 16-bit non-multiplexed non-multiplexed multiplexed multiplexed during external bus used for ALE/AS output (if enabled in EBCS:ASE) access ALE/AS pause between two...
Page 351 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE used for xxx output • The pin can be used as external bus output signal. (if enabled in Exxx) • The output of the external bus function can be enabled/disabled with the corresponding output enable bit in the Exxx register.
Page 352: External Boot Vector Fetch
CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.5 External Boot Vector fetch Devices with external bus interface offer the possibility to read the Boot Vector (User program start address) via the external bus interface. This is possible in three different external bus operation modes depending on the MD[2:0] mode pin setting.
Page 353 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ Procedure of External Boot Vector fetch 1. Internal reset is released. 2. MCU wakes up with RC clock and starts the Boot-ROM Start-up program. 3. Boot-ROM program reads the mode pin setting -> external vector mode detected. 4.
Page 354: Pin Status In Different Mcu States
CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.6 Pin status in different MCU states This chapter describes the status of the external bus pins in the following MCU states: - Reset - Run mode with external bus access - Run mode with internal access - Standby modes - Hold state...
Page 355 MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE the Clock suspend mode is enabled and the ECLK clock divider is active, this is always the inactive level defined by EBCF:CKI.
Page 356 CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual...
Page 357: I/O Ports
CHAPTER 13 I/O PORTS This chapter explains the functions and operations of the I/O ports. 13.1 "I/O Ports" 13.2 "I/O Port Registers" 13.3 "Register usage"...
Page 358: I/O Ports
CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.1 I/O Ports Each pin of the ports can be speciﬁed as input or output using the direction register, if the corresponding peripheral does not use the pin. Before using a pin as input, it must be enabled by setting the Port Input Enable register.
Page 359: I/O Port Registers
MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2 I/O Port Registers Each general purpose port pin GPxx is controlled by nine types of registers. These are: • Port Data Register (PDR00 to PDRnn) • External Pin State Register (EPSR00 to EPSRnn) •...
Page 360 CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.2.1 Port Data Register (PDRnn) Note that R/W for I/O ports differ from R/W for memory in the following points: • Input mode Read: The level at the corresponding pin is read. Write: Data is written to an output latch.
Page 361 MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 1111.1111 (= output) PDR (= last value written to PDR) 0000.0000 0010.0000 (resource output enable) Resource output 0010.0000 current pin value 0010.0000 read by RMW instruction from PDR on 16LX 0010.0000 ->...
Page 362 CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.2.2 External Pin State Register (EPSRnn) With this register the current state of the external pin can be read. ■ External Pin State Register Figure 13.2-3 External Pin State Registers EPSRnn Initial value Access Undeﬁned...
Page 363 MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2.3 Data Direction Register (DDRnn) When a pin is used as a general purpose port, this register switches the corresponding pin to input mode or output mode. ■ Data direction register Figure 13.2-4 Data Direction Registers DDRnn Initial value...
Page 364 CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.2.4 Port Input Enable Register (PIERnn) When a pin is used as general purpose port, the digital input is enabled or disabled with this register. When the digital input is disabled, no transverse current is drawn by the input stage at any input pin potential.
Page 365 MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2.5 Port Input Level Register (PILRnn) and Extended Port Input Level Register (EPILRnn) The digital input level of each pin can be programmed between CMOS Hysteresis, Automotive Hysteresis or TTL level with these two registers. ■...
Page 366 CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual Figure 13.2-7 Digital and analog Input CMOS 0307 Automotive Hysteresis PIER Digital Input CMOS 0208 PILR EPILR 2 Analog Input/ Output...
Page 367 MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2.6 Port Output Drive Register (PODRnn) The output drive option can be programmed with this register. Output drive strength is selectable between normal and reduced current. ■ Port Output Drive Register (PODRnn) Figure 13.2-8 Port Output Drive Register PODRnn Initial value...
Page 368 CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.2.7 Port High Drive Register (PHDR) The high drive option can be enabled or disabled with this register. ■ Port High Drive Register Figure 13.2-9 Port High Drive Registers PHDRnn Initial value Access 00000000 R/W: Readable and writeable...
Page 369 MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2.8 Pull-Up Control Register (PUCR) The Pull-up resistor can be enabled or disabled with this register. ■ Pull-Up Control Register (PUCR) Figure 13.2-10 Pull-Up Control Register PUCRnn Initial value Access 00000000 R/W: Readable and writeable : Undeﬁned Bits PUx (PUCR00 to PUCRnn)
Page 370: Register Usage
CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.3 Register usage This chapter gives a summary about usage of IO registers. ■ Register settings for different port usage Table 13.3-1 Register settings for different port usage Register/ PIER EPSR PILR EPILR PUCR...
Page 371: 16-Bit I/O Timer
CHAPTER 14 16-BIT I/O TIMER This chapter explains the functions and operations of the 16-bit I/O Timer. 14.1 "Outline of 16-bit I/O Timer" 14.2 "16-Bit I/O Timer Registers" 14.3 "16-bit Free-Running Timer" 14.4 "Output Compare Unit" 14.5 "Input Capture Unit"...
Page 372: Outline Of 16-Bit I/O Timer
CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.1 Outline of 16-bit I/O Timer The 16-bit I/O Timer consists of a 16-bit Free-Running Timer and Output Compare Units and Input Capture Units. It is used to generate pulse sequences and to measure the time duration between external events.
Page 373 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER ● The two input channels can operate independently. ● An interrupt can be issued upon a valid edge of an external input signal. The DMA can be activated upon an input capture interrupt. ■...
Page 374: 16-Bit I/O Timer Registers
CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.2 16-Bit I/O Timer Registers The 16-bit I/O timer has the following registers: • 16-bit Free-Running Timer registers • 16-bit Output Compare registers • 16-bit Input Capture registers ■ 16-bit Free-Running Timer registers TCDTn Timer Data Register n TCCSHn...
Page 375 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER • etc. ■ 16-bit Input Capture registers IPCP(2n+0) Capture register 2n+0 IPCP(2n+1) Capture register 2n+1 Control Register (2n+0)/(2n+1) ICS(2n+0)/(2n+1) Capture Edge Register (2n+0)/(2n+1) ICE(2n+0)/(2n+1) Remark: The suffix "n" denotes the number of the Input Capture Unit (0, 1, 2, ...). The register name is composed by the register type name and the suffix.
Page 376: 16-Bit Free-Running Timer
CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.3 16-bit Free-Running Timer The 16-bit Free-Running Timer consists of a 16-bit up counter and a control status register. The count values of this timer are used as the base time for the Output Compare Units and Input Capture Units.
Page 377 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.3.1 Data Register (TCDTn) The Data Register (TCDTn) can read the count value of the 16-bit Free-Running Timer. The counter value is cleared to "0000" upon a reset. The timer value can be set by writing a value to this register.
Page 378 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.3.2 Control Status Register (TCCSLn) The control status register (TCCSLn) sets the operation mode of the 16-bit Free-Running Timer, starts and stops the 16-bit Free-Running Timer, and controls interrupts. ■ Control status register of Free-Running Timer (TCCSLn) Figure 14.3-3 Control status register of Free-Running Timer (TCCSLn) TCCSLn Initial value...
Page 379 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Table 14.3-1 Control status register of Free-Running-Timer (TCCSLn) Bit name Function bit 7 • This bit is the interrupt request ﬂag bit and clear bit • Writing "0": A possible interrupt is cleared. •...
Page 380 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual ■ Control status register of Free-Running Timer (TCCSHn) Figure 14.3-4 Control status register of Free-Running Timer (TCCSHn) TCCSHn ECKE FSEL Initial value 0 1 X X X X X X bit13-8 Undefined bit14...
Page 381 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.3.3 16-bit Free-Running Timer Operation The 16-bit Free-Running Timer starts counting from counter value "0000" after the reset is released. The counter value is used as the base time for the 16-bit Output Compare and 16-bit Input Capture operations.
Page 382 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual ■ Clearing the counter at Compare Clear Register value match Figure 14.3-6 Clearing the Counter when the Compare Clear Register Value matches the 16-bit Free- Running Timer value Counter value FFFF BFFF 7FFF...
Page 383: Output Compare Unit
MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.4 Output Compare Unit The Output Compare Unit (OCU) consists of two 16-bit compare registers, two compare output pins, and one control register. If the value written to the compare register of this module matches the 16-bit free-running timer value, the output level of the pin can be toggled and an interrupt can be issued.
Page 384 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.4.1 Output Compare Register (OCCP(2n) / OCCP(2n+1)) The 16-bit Output Compare registers are compared with the 16-bit Free-Running Timer. Since the initial register values are undeﬁned, set appropriate value before enabling the operation.
Page 385 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.4.2 Control Status Registers of Output Compare (OCS(2n) / OCS(2n+1)) The Control Status Register (OCS(2n) / OCS(2n+1)) sets the operation mode of output compare, starts and stops output compare, controls interrupts, and sets the external output pins.
Page 386 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual • for Output Compare Unit 0: n = 0, hence OCS0 has bits CST0, CST1, ICE0, ICE1, ICP0, ICP1 • for Output Compare Unit 1: n = 1, hence OCS2 has bits CST2, CST3, ICE2, ICE3, ICP2, ICP3 etc.
Page 387 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Table 14.4-1 Output Compare Control Status Register (OCS(2n)) Bit name Function bit 7 ICP(2n+1) • These bits are used as compare match status ﬂags. When the compare register value matches the 16-bit free-run timer value, the bit is set to "1". bit 6 ICP(2n+0) •...
Page 388 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual ■ Output Compare Control Status Register (OCS(2n+1)) Figure 14.4-4 Output Compare Control Status Register (OCS(2n+1)) OCS(2n+1) CMOD1 CMOD0 OTE Initial value 0 X X 0 0 0 0 0 R/W R/W R/W R/W bit 8 OTD(2n+0)
Page 389 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Table 14.4-2 Output Compare Control Status Register (OCS(2n+1)) (2/2) Bit name Function bit 9 OTD(2n+1) These bits are used to change the pin output level when the Output Compare Unit output pin is enabled.
Page 390 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual Figure 14.4-5 Block diagram of output selection (OCU module 1) Compare Control 2 OUT2 CMOD1 CMP0EXT OUT3 CMOD0 Compare Control 3 For OCU module 1, which requires a match with Output Compare Register 0 if CMOD[1:0] = “10 ”...
Page 391 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.4.3 16-bit Output Compare Operation In the 16-bit Output Compare operation, an interrupt request ﬂag can be set and the output level can be toggled when the speciﬁed compare register value matches the 16-bit free-run timer value.
Page 392 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual OUT1 (3): The level is reversed by a match with compare register 0 (2) or with compare register 1 (3). For OUT4, OUT5, OUT6 and OUT7, compare register 4 plays the same role as compare register 0 above. Figure 14.4-7 Sample of a output waveform when CMOD[1:0] = "01 "...
Page 393 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Figure 14.4-8 Output waveform when OCS1:CMOD[1:0] = "01 " and OCS3:CMOD[1:0] = "10 " Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset OCCP0 value BFFF OCCP1 value 7FFF OCCP2 value 3FFF OCCP3 value 5FFF...
Page 394 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual Figure 14.4-9 Output waveform when OCS1:CMOD[1:0] = "11 " and OCS3:CMOD[1:0] = "11 " Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset OCCP0 value BFFF OCCP1 value 7FFF OCCP2 value 3FFF OCCP3 value 5FFF...
Page 395 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER ■ Output compare timing In output compare operation, a compare match signal is generated when the Free-Running Timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued.
Page 396: Input Capture Unit
CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.5 Input Capture Unit The Input Capture Unit (ICU) detects a rising or falling edge or both edges of an external input signal and stores a 16-bit Free-Running Timer value at that time in a register. In addition, the Input Capture Unit can generate an interrupt upon detection of an edge.
Page 397 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.5.1 Input Capture Unit Register Details The Input Capture Unit is conﬁgured by the Control Status Register (ICS(2n)(2n+1)) and the Edge Register (ICE(2n)(2n+1)). The Input Capture Unit has a 16bit data register (IPCPn). This register stores a value from the 16-bit Free-Running Timer when a valid edge of the corresponding external pin input waveform is detected.
Page 398 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual ■ Input Capture Control Status Register (ICS(2n)(2n+1)) Figure 14.5-3 Input Capture Control Status Register (ICS(2n)(2n+1)) ICS(2n)(2n+1) initial value 0 0 0 0 0 0 0 0 ICE ICE EG R/W R/W R/W R/W R/W R/W R/W bit1 bit0...
Page 399 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Table 14.5-2 Input Capture Unit Control Status Register bits Bit name Function bit7 ICP(2n+1): • This bit is used as interrupt request ﬂag for Input Capture Unit n, second Interrupt request ﬂag channel.
Page 400 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual Figure 14.5-4 Input Capture Unit Edge Register (ICE(2n)(2n+1)) ICE(2n)(2n+1) Initial value RES IEI(2n+1)IEI(2n) X X X X X X 0 0 R/W R/W bit8 IEI(2n) Input capture valid edge indication bit for ICU0 falling edge detected rising edge detected bit9...
Page 401 MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.5.2 16-bit Input Capture Operation In 16-bit Input Capture operation, an interrupt can be generated upon detection of the speciﬁed edge, fetching the 16-bit Free-Running Timer value and writing it to the capture data register.
Page 402 CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual Figure 14.5-5 Example of Input Capture fetch timing Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset IN example Capture 0 Undefined 3FFF Capture 1 Undefined 7FFF Capture example Undefined BFFF 3FFF Capture 0...
Page 403: 16-Bit Reload Timer (With Event Count Function)
CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) This chapter explains the functions and operations of the 16-bit Reload Timer (with the Event Count Function). 15.1 "Outline of 16-Bit Reload Timer (with Event Count Function)" 15.2 "16-Bit Reload Timer (with Event Count Function)" 15.3 "Internal Clock and External Event Counter Operations of 16-bit Reload Timer"...
Page 404: Outline Of 16-Bit Reload Timer (With Event Count Function)
CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.1 Outline of 16-Bit Reload Timer (with Event Count Function) The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TINn) and one output pin (TOTn), and control registers. ■...
Page 405 MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT Figure 15.1-1 Block diagram of 16-bit reload timer 16-bit reload register TMISR Reload RELD 16-bit down-counter OUTE detection OUTL GATE INTE CTL. FSEL CSL1 Clock selector CNTE CSL0 Re-trigger Port (TINn)
Page 406: 16-Bit Reload Timer (With Event Count Function)
CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.2 16-Bit Reload Timer (with Event Count Function) The 16-bit Reload Timer has the following registers: • Timer Control Status Register (TMCSRn) • 16-bit Timer Register (TMRn) / 16-bit Reload Register (TMRLRn) ■...
Page 407 MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT 15.2.1 Timer Control Status Register (TMCSRn) The Timer Control Status Register controls the operation mode and interrupts for the 16- bit Reload Timer. ■ Register layout of Timer Control Status Register (TMCSRn) Figure 15.2-2 Register layout of Timer Control Status Register (TMCSRn) TMCSRHn FSEL...
Page 408 CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware Table 15.2-1 Clock sources for CSL0/1 and FSEL bit settings (Continued) FSEL CSL1 CSL0 Clock Source (Time for peripheral clock CLKP1 = 24 MHz) External event count mode External event count mode / 2 [Bits 9, 8, 7] MOD2, MOD1, MOD0 (Operation mode and TINn function) These bits set the operation mode and input pin (TINn) functions.
Page 409 MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT [Bit 6] OUTE (Output enable) If this bit is set to "1", the pin TOTn is used as Reload Timer output. If this bit is set to "0" the timer output TOTn is disabled.
Page 410 CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.2.2 Register Layout of 16-bit Timer Register (TMRn)/16-bit Reload Register (TMRLRn) • TMRn contents Reading this register returns the count value of the 16-bit Reload Timer. The initial value is undeﬁned.
Page 411: Internal Clock And External Event Counter Operations Of 16-Bit Reload Timer
MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT 15.3 Internal Clock and External Event Counter Operations of 16- bit Reload Timer In internal clock mode, the peripheral clock CLKP1 with different divider settings can be selected as the clock source for operating the Reload Timer.
Page 412 CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware Figure 15.3-2 Trigger input operation of 16-bit Reload Timer Count clock Rising edge detected Prescaler clear Counter Reload data XXXX Load 2.5T When used as a gate input, the counter only counts while the active level specified by the MOD0 bit of the control register is input to the TINn pin.
Page 413: Underflow Operation Of 16-Bit Reload Timer
MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT 15.4 Underflow Operation of 16-bit Reload Timer An underﬂow is deﬁned for this timer as the time when the counter value changes from 0000 to FFFF . Therefore, an underﬂow occurs after (reload register setting + 1) counts. ■...
Page 414: Output Pin Functions Of 16-Bit Reload Timer
CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.5 Output Pin Functions of 16-bit Reload Timer In reload mode, the TOTn pin performs toggle output (inverts at each underﬂow). In one- shot mode, the TOTn pin is used as a pulse output that shows the conﬁgured level while the counting is in progress.
Page 415: Counter Operation State
MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT 15.6 Counter Operation State The counter state is determined by the CNTE bit in the control status register and the internal WAIT signal. Available states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE = "1"...
Page 416: Cascading Of 16-Bit Reload Timers
CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.7 Cascading of 16-bit Reload Timers The cascading of multiple adjacent 16-bit Reload Timers allows the user to create its own n * 16-bit-Reload Timer (Example: 3 adjacent Reload Timers available on device). ■...
Page 417 MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT ■ Reload Timer Input Select Register (TMISR) Reload Timer Input Select Register (TMISR) Figure 15.7-2 TMISR TMS5 TMS4 TMS3 TMS2 TMS1 TMS0 Initial value X X 0 0 0 0 0 0 bit0 TMIS0 Reload Timer 0 Input Select...
Page 418 CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware...
Page 419: Programmable Pulse Generator
CHAPTER 16 PROGRAMMABLE PULSE GENERATOR This chapter explains the functions and operations of the Programmable Pulse Generator. 16.1 "Outline of Programmable Pulse Generator" 16.2 "Registers" 16.3 "Operation of Programmable Pulse Generator" 16.4 "Cautions"...
Page 420: Outline Of Programmable Pulse Generator
CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual 16.1 Outline of Programmable Pulse Generator Programmable Pulse Generators (PPGs) are used to obtain one-shot (rectangular wave) output or pulse width modulation (PWM) output. With their software-programmable cycle and duty capability, the PPGs comfortably fit into a broad range of applications. ■...
Page 421 MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR Activation trigger: • Software trigger • Internal trigger • External trigger (TTG pins) Freely configurable Reload Timer as additional prescalar input ■ Simpliﬁed block diagram of Programmable Pulse Generator Figure 16.1-1 Simpliﬁed block diagram of Programmable Pulse Generator Period value Reload Borrow...
Page 422 CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual Figure 16.1-2 Conﬁguration diagram of Programmable Pulse Generator Period value Duty value MDSE PCNn: bit 13 PWM operation PCSR PDUT One shot PGMS OSEL PCNn: bit 9, bit 0 Reload Reload Normal output Inverted output...
Page 423: Registers
MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR 16.2 Registers The programmable pulse generator has the following registers: • PPG Control Status register (PCNn) • General Control register 1 (GCN1g), one per group of 4 PPGs • General Control register 2 (GCN2g), one per group of 4 PPGs •...
Page 424 CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual Figure 16.2-2 PPG Control Status register (PCNn) PCNHn CNTE STGR MDSE RTRG CKS1 CKS0 PGMS Access: R0/W R/W R/W R/W Rx/Wx Initial value: Rewrite during operation: PCNLn EGS1 EGS0 IREN IRQF IRS1 IRS0...
Page 425 MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR Bits 11-10: Counter clock selection CKS1 CKS0 Down Counter Count Clock Selection Clock selected by CKSEL Clock selected by CKSEL divided by 4 Clock selected by CKSEL divided by 16 Clock selected by CKSEL divided by 64 Bit 9: PPG output mask selection PGMS...
Page 426 CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual Counter borrow or the counter equals the duty value. Select the operation in which to generate an interrupt request. Bit 1: PPG output enable Operation Output disabled Output enabled Bit 0: PPG output polarity specification OSEL Operation Normal polarity...
Page 427 MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR PPG0 to PPGn as selected are activated when the edge specified by the Trigger Input Edge Selection bits (PCNn:EGS[1:0]) are detected by the specified activation trigger. ■ General Control Register 2 (GCN2g) The General Control Register 2 (GCN2x) generates internal trigger levels using software for a PPG block of 4 PPGs.
Page 428 CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual Figure 16.2-5 PPG Cycle Setting Register (PCSRn) PCSRHn Access: Initial value: PCSRLn Access: Initial value: W : Write only x : undefined The PPG Period Setting registers come with buffers. Transfers from the buffers to the counter take place automatically upon counter borrow.
Page 429 MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR Figure 16.2-7 PPG Timer Register (PTMRn) PTMRHn Access: Initial value: PTMRLn Access: Initial value: : Read only, write has no effect x : undefined The count of the 16-bit down counter can be read.
Page 430: Operation Of Programmable Pulse Generator
CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual 16.3 Operation of Programmable Pulse Generator The Programmable Pulse generators (PPGs) provide programmable pulse output independently or jointly. The individual modes of operation are described below ■ PWM Operation In PWM operation, variable-duty pulses are generated from the PPG pin. Enable count CNTE Activation trigger...
Page 431 MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR • (11) Counter borrow. • (12) Clear the PPG pin output level (return to normal). • (13) Reload the cycle value. • (14) Reload the duty value. • (15) Steps from (7) to (14) are iterated. •...
Page 432 CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual • (6) Counter down count. • (7) The down counter equals the duty value. • (8) Inverses the PPG pin output level. • (9) Counter down count. • (10) Counter borrow. •...
Page 433: Cautions
MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR 16.4 Cautions This section describes the cautions to be considered while using the programmable pulse generator ■ Cautions • If the Interrupt Request flag (PCN:IRQF) equals “1” and the Interrupt Request flag is set to “0” at the same timing, the setting of the Interrupt Request flag to “1”...
Page 434 CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual PPG stops with its status (count and output level) being latched. If the Timer Operation Enable bit (PCN:CNTE) is subsequently set to “1” to enable the PPG, it restarts from the point of interruption.
Page 435: External Interrupts
CHAPTER 17 EXTERNAL INTERRUPTS This chapter explains the functions and operations of the External Interrupts. 17.1 "Outline of External Interrupts" 17.2 "External Interrupt Registers" 17.3 "Notes on using the External Interrupt functions"...
Page 436: Outline Of External Interrupts
CHAPTER 17 EXTERNAL INTERRUPTS MB96300 Super Series Hardware Manual 17.1 Outline of External Interrupts The External Interrupt detects a signal input to an external interrupt pin and generates an interrupt request. ■ External interrupts For an external interrupt request, four request levels are available: "H", "L", rising edge, and falling edge are available.
Page 437 MB96300 Super Series Hardware Manual CHAPTER 17 EXTERNAL INTERRUPTS ■ External interrupts registers Initial value ENIR0 00000000 ENIR1 EN15 EN14 EN13 EN12 EN11 EN10 00000000 EIRR0 00000000 EIRR1 ER15 ER14 ER13 ER12 ER11 ER10 00000000 ELVR0 00000000 ELVR0 00000000 ELVR1 00000000 LB11 LA11...
Page 438: External Interrupt Registers
CHAPTER 17 EXTERNAL INTERRUPTS MB96300 Super Series Hardware Manual 17.2 External Interrupt Registers The External Interrupt mdule has the following registers: • Interrupt Enable register (ENIRn: External Interrupt Request Enable Register) • Interrupt ﬂag (EIRRn: External Interrupt Request Register) • Request level setting register (ELVRn: External Level Register) ■...
Page 439 MB96300 Super Series Hardware Manual CHAPTER 17 EXTERNAL INTERRUPTS Note: When clearing the interrupt flag, make sure to clear the flag which caused the interrupt alone but not others. ■ Request level setting register (ELVRn: External Interrupt Level Register) Figure 17.2-3 External Interrupt Level Register (ELVRn) ELVR0 Initial value 00000000...
Page 440: Notes On Using The External Interrupt Functions
CHAPTER 17 EXTERNAL INTERRUPTS MB96300 Super Series Hardware Manual 17.3 Notes on using the External Interrupt functions The following points must be considered to use the External Interrupt function. • Conditions on the behavior of external circuit for use of DMA •...
Page 441: A/D Converter
CHAPTER 18 A/D CONVERTER This chapter explains the function and operation of the A/ D converter. 18.1 "Outline of A/D Converter" 18.2 "Registers for A/D Converter" 18.3 "Operation of A/D Converter" 18.4 "Conversion using DMA" 18.5 "Conversion Data Protection Function"...
Page 442: Outline Of A/D Converter
CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.1 Outline of A/D Converter The A/D converter converts analog input voltages to digital values. ■ Outline of A/D converter • Conversion time: 1.9 µs min. per channel (with 24-MHz machine clock) •...
Page 443 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER ■ Block diagram of A/D converter Figure 18.1-1 Block diagram of A/D converter ADSEL AVcc RH/L AVss D/A Converter AN32 Sequential comparison register AN31 Comparator Sample & Hold circuits ADCR Data Register Hold circuit Setting register L Setting register H...
Page 444: Registers For A/D Converter
CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.2 Registers for A/D Converter The A/D converter has the following registers: • Control status register: ADCS • Data register: ADCR • Setting register: ADSR • Extended conﬁguration register: ADECR • Analog input enable register: ADERx...
Page 445 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER ■ Registers for A/D converter Figure 18.2-1 Registers of the A/D Converter A/D control status register ( Upper) Bit No. BUSY INTE PAUS STS1 STS0 STRT ADCSH Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Page 446 CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.2.1 Control status register (ADCS) The control status register (ADCS) controls the A/D converter and indicates its status. Do not rewrite ADCS during A/D conversion. ■ Control Status Register (ADCS) Figure 18.2-2 A/D control status register (ADCS) A/D control status register (Upper) Bit No.
Page 447 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER [bit 14] INT (interrupt) This bit is set when converted data is written to ADCR. When this bit is set with bit5 (INTE) set to “1”, an interrupt request is generated. If DMA is configured and enabled, DMA is activated instead. Writing “1”...
Page 448 CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual In a mode allowing two or more activation causes, A/D conversion is activated by the source that occurs first. When changing the setting of these bits during A/D conversion, the result is immediately reflected. Therefore it is not a recommended practice.
Page 449 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER Note: • The A/D conversion in the continuous or stop mode continues until it is stopped by the BUSY bit. • Write 0 to the BUSY bit to stop the A/D conversion. •...
Page 450 CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.2.2 Data Register (ADCR) The data register (ADCR) is used to store digital value generated as a result of conversion. The register value is rewritten every time the conversion ends. Normally, the last converted value is stored in these register's bits.
Page 451 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER 18.2.3 Setting Register (ADSR) The setting register (ADSR) is used to set the A/D conversion time and the sampling channels and to indicate the current sampling channel. ■ Setting Register (ADSR) Figure 18.2-4 Setting register (ADSR) A/D setting register (Upper) Bit No.
Page 452 CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 1.2µs; For 3.0V Avcc < 4.5V If the driving impedance, R is greater than 1.5 kΩ, the sampling time must be greater than T given by samp the following formula; = (2.25 kΩ + Rext) × 10.7pF × 7; For 4.5V Avcc 5.5V samp...
Page 453 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER Table 18.2-5 Starting Channel Settings (Continued) (2/2) ANS4 ANS3 ANS2 ANS1 ANS0 Starting channel when Starting channel when ADECR:ADSEL = 0 ADECR:ADSEL = 1 AN29* AN61* AN30* AN62* AN31* AN63* * For the highest ADC channel number available on the device, please refer to the corresponding data sheet.
Page 454 CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual Note: • When writing to this register, always use word access. When byte write or read-modify-write is performed for this register, A/D conversion may be started from an unintended channel. • When the same channel is written to the ANE4 to ANE0 bits and to the ANS4 to ANS0 bits, conversion is performed for only 1 channel (single channel conversion).
Page 455 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER 18.2.4 Extended Conﬁguration Register (ADECR) The extended conﬁguration register (ADECR) is used to enable the A/D Converter input channels 32 and higher. It also enables to switch the A/D converters high and low reference voltage between AVRH + AVRL, AVRH + AVSS and AVRH2 + AVSS.
Page 456 CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual Figure 18.2-6 Switching of ADC Reference Voltage (LSEL="0", HSEL="0"). AVCC AVCC AVRH High reference voltage ADECR LSEL=0 HSEL=0 AVRL/AVRH2 Low reference voltage AVSS AVSS Note: This setting is compatible to16LX configuration of A/D converter. It enables to have the low reference voltage of the A/D converter different from AVSS potential.
Page 457 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER Figure 18.2-7 Switching of ADC Reference Voltage (LSEL="0", HSEL="1" or LSEL="1", HSEL="0") AVCC AVCC AVRH High reference voltage ADECR LSEL=0 HSEL=1 LSEL=1 HSEL=0 AVRL/AVRH2 Low reference voltage AVSS AVSS Note: This setting can be used in the case the low reference voltage of the A/D converter is equal to AVSS potential (e.g.
Page 458 CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual Figure 18.2-8 Switching of ADC Reference Voltage (LSEL="1", HSEL="1" AVCC AVCC AVRH High reference voltage ADECR LSEL=1 HSEL=1 AVRL/AVRH2 Low reference voltage AVSS AVSS Note: This setting can be used in the case the low reference voltage of the A/D converter is equal to AVSS potential (e.g.
Page 459 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER 18.2.5 Analog Input Enable Register (ADERx) This register enables the analog input functions for the AD converter ■ Analog input enable register (ADERx) Figure 18.2-9 Analog input enable register (ADERx) ADER0 Bit No.
Page 460: Operation Of A/D Converter
CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.3 Operation of A/D Converter The A/D converter operates using the sequential-comparison converter system; and 10 bits or 8 bits can be selected for the A/D converter's resolution. Since this A/D converter has only one register (10 bits; conversion result data register ADCR) for storing conversion results, this register is rewritten every time conversion is ended.
Page 461: Conversion Using Dma
MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER 18.4 Conversion using DMA Figure 18.4-1 gives an example of ﬂow for the activation of A/D conversion to the transfer of converted data in continous mode. ■ Conversion using DMA Figure 18.4-1 Example of ﬂow for the activation of A/D conversion to the transfer of converted data in continous mode.
Page 462: Conversion Data Protection Function
CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.5 Conversion Data Protection Function The A/D converter has the converted-data protection function, is featured by continuous conversion and securing two or more data using DMA. Only one conversion data register (ADCR) is provided, so when A/D conversion is continuously performed, converted data is stored every time one conversion is ended, destroying the previous data.
Page 463 MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER ■ Example of ﬂow of Conversion Data Protection Function (when DMA is used) Figure 18.5-1 Example of ﬂow of Conversion Data Protection Function (when DMA is used) Set DMA Start continuous A/D conversion First conversion end Store in data register Second conversion end...
Page 464 CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual...
Page 465: Alarm Comparator
CHAPTER 19 ALARM COMPARATOR This chapter explains the functions and operations of the Alarm Comparator. 19.1 "Outline of Alarm Comparator" 19.2 "Alarm Comparator Registers" 19.3 "Alarm Comparator operating modes"...
Page 466: Outline Of Alarm Comparator
CHAPTER 19 ALARM COMPARATOR MB96300 Super Series Hardware Manual 19.1 Outline of Alarm Comparator This chapter provides an overview of the Alarm Comparator (also called Under/Overﬂow voltage Detection), describes the register structure, modes and the operation of the Alarm Comparator ■...
Page 467 MB96300 Super Series Hardware Manual CHAPTER 19 ALARM COMPARATOR ■ Block diagram of Alarm Comparator Figure 19.1-1 Block diagram of Alarm Comparator Analog part Digital part AVCC Interrupt logic ALARMn OUT1 OUT2 VREF INTREF AVSS CLKP1 Note: • The suffix ’n’ denotes the number of the Alarm Comparator module.
Page 468: Alarm Comparator Registers
CHAPTER 19 ALARM COMPARATOR MB96300 Super Series Hardware Manual 19.2 Alarm Comparator Registers The Alarm Comparator has the following two registers: • Alarm Comparator Control/Status register (ACSRn) • Alarm Comparator Extended Control/Status register (AECSRn) ■ Alarm Comparator Control/Status register (ACSRn) Figure 19.2-1 Structure of Alarm Comparator control/status register Bits ACSRn...
Page 469 MB96300 Super Series Hardware Manual CHAPTER 19 ALARM COMPARATOR Analog input voltage < V when AECSRn:INTREF = 0 or EVTL analog input voltage < V when AECSRn:INTREF = 1 IVTL Analog input voltage > V when AECSRn:INTREF = 0 or EVTL analog input voltage >...
Page 470 CHAPTER 19 ALARM COMPARATOR MB96300 Super Series Hardware Manual ■ Alarm Comparator Extended Control/Status Register (AECSRn) Figure 19.2-2 Structure of Alarm Comparator Extended Control/Status register AECSRn Initial value INTREF X X X X X 0 X 0 bit8 INTREF Internal reference voltage select bit Reference voltage derived from AVCC/AVSS Reference voltage derived from internal reference VREF bit9...
Page 471: Alarm Comparator Operating Modes
MB96300 Super Series Hardware Manual CHAPTER 19 ALARM COMPARATOR 19.3 Alarm Comparator operating modes The Alarm Comparator circuit can operate in interrupt or polling mode. The internal interrupt logic will detect each interrupt event independent of setting of the IEN bit. ■...
Page 472 CHAPTER 19 ALARM COMPARATOR MB96300 Super Series Hardware Manual Table 19.3-2 Alarm Comparator operation modes STOP TIMER SLEEP Digital part ACSR:PD Analog part operating run mode operating power down stopped stopped Precaution: The outputs of the Alarm Comparator (analog parts) will remain undefined for at least 3 us after power on and also after reentering the run mode.
Page 473: Usart
CHAPTER 20 USART This chapter explains the functions and operation of the LIN USART. 20.1 "Overview of USART" 20.2 "Configuration of USART" 20.3 "USART Pins" 20.4 "USART Registers" 20.5 "USART Interrupts" 20.6 "USART Baud Rates" 20.7 "Operation of USART" 20.8 "Notes on Using USART"...
Page 474: Overview Of Usart
CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.1 Overview of USART The USART with LIN (Local Interconnect Network) - Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication with external devices. The USART provides bidirectional communication function (normal mode), master-slave communication function (multiprocessor mode in master/slave systems), and special features for LIN-bus systems (working both as master or as slave device).
Page 475 MB96300 Super Series Hardware Manual CHAPTER 20 USART Table 20.1-1 USART functions (2/2) Item Function Synchronous mode Function as Master- or Slave-USART Transceiving pins Direct access possible LIN bus options • Operation as master device • Operation as slave device •...
Page 476 CHAPTER 20 USART MB96300 Super Series Hardware Manual shown in the following table: Table 20.1-3 Mode bit setting Mode Description Asynchronous (normal mode) Asynchronous (multiprocessor mode) Synchronous (normal mode) Asynchronous (LIN mode)
Page 477: Configuration Of Usart
MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.2 Configuration of USART This section provides a short overview on the building blocks of USART. ■ Block diagram of USART USART consists of the following blocks: • Reload Counter • Reception Control Circuit •...
Page 478 CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.2-1 Block diagram of USART AICD PE ORE FRE (OTO, EXT, Peripheral clock REST) transmission clock LBIE Reload Interrupt reception clock Counter Generation TRANSMISSION SCKn circuit CONTROL RECEPTION CIRCUIT CONTROL CIRCUIT Start bit Transmission Detection...
Page 479 MB96300 Super Series Hardware Manual CHAPTER 20 USART bit detection circuit detects start bits from the serial input signal and sends a signal to the reload counter to synchronize it to the falling edge of these start bits. The reception parity counter calculates the parity of the reception data.
Page 480 CHAPTER 20 USART MB96300 Super Series Hardware Manual ● LIN Synch Break Generation Circuit The LIN break generation circuit generates a LIN break of a determined length. ● Bus Idle Detection circuit The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case, the circuit generates the special flag bits TBI and RBI.
Page 481 MB96300 Super Series Hardware Manual CHAPTER 20 USART • Directly accessing SINn and SOTn pins • Specifying continuous clock output operation • Specifying sampling clock edge ● Extended Communication Control Register (ECCRn) This register performs the following functions: • Indicating bus idle state •...
Page 482: Usart Pins
CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.3 USART Pins This section describes the USART pins and provides a pin block diagram. ■ USART pins The USART pins are shared with general purpose ports. Table 20.3-1 "USART pins" lists the pin functions, I/O formats, and settings required to use the USART.
Page 483: Usart Registers
MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4 USART Registers The following ﬁgure shows the USART registers. ■ USART registers Figure 20.4-1 USART registers USART registers bit15 bit8 bit7 bit0 SCRn (Serial Control Register) SMRn (Serial Mode Register) SSRn (Serial Status Register) RDRn/TDRx (RX, TX Data Register) ESCRn (Extended Status/Control Reg.) ECCRn (Extended Comm.
Page 484 CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.4.1 Serial Control Register (SCRn) This register speciﬁes parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error ﬂag, and speciﬁes whether to enable transmission and reception.
Page 485 MB96300 Super Series Hardware Manual CHAPTER 20 USART ■ Serial control register (SCRn) Figure 20.4-2 Conﬁguration of the serial control register (SCRn) SCRn Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W bit8 Transmission enable Disable Transmission Enable Transmission...
Page 486 CHAPTER 20 USART MB96300 Super Series Hardware Manual Table 20.4-1 Functions of each bit of control register (SCRn) Bit name Function bit14 When parity is provided and enabled this bit selects even (0) or odd (1) parity. Parity selection bit bit13 SBL: This bit selects the length of the stop bit of an asynchronous data frame or a...
Page 487 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4.2 Serial mode register (SMRn) This register selects an operation mode and baud rate clock and speciﬁes whether to enable output of serial data and clocks to the corresponding pin.
Page 488 CHAPTER 20 USART MB96300 Super Series Hardware Manual ■ Serial mode register (SMRn) Figure 20.4-3 Conﬁguration of the serial mode register (SMRn) SMRn Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W bit0 Serial data output enable bit of LIN-USART LIN-UART serial data output pin disabled LIN-UART serial data output pin enabled...
Page 489 MB96300 Super Series Hardware Manual CHAPTER 20 USART Table 20.4-2 Bit function of the serial mode register (SMRn) Bit name Function bit5 OTO: This bit sets an external clock directly to the LIN-USART’s serial clock. This function One-to-one external is used for operating mode 2 (synchronous) slave mode operation. clock selection bit bit4 EXT:...
Page 490 CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.4.3 Serial Status Register (SSRn) This register checks the transmission and reception status and error status, it also enables and disables the transmission and receive interrupts.
Page 491 MB96300 Super Series Hardware Manual CHAPTER 20 USART ■ Serial status register (SSRn) Figure 20.4-4 Conﬁguration of the serial status register (SSRn) SSRn Initial value 0 0 0 0 1 0 0 0 R/W R/W bit8 Transmission Interrupt enable Disables Transmission Interrupt Enables Transmission Interrupt bit9 Reception Interrupt enable...
Page 492 CHAPTER 20 USART MB96300 Super Series Hardware Manual Table 20.4-3 Functions of each bit of status register (SSRn) Bit name Function bit14 ORE: • This bit is set to 1 when an overrun error occurs during reception. Overrun error ﬂag bit •...
Page 493 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4.4 Reception and Transmission Data Register (RDRn/TDRn) The reception data register (RDRn) holds the received data. The transmission data register (TDRn) holds the transmission data. Both RDRn and TDRn registers are located at the same address.
Page 494 CHAPTER 20 USART MB96300 Super Series Hardware Manual ● Transmission: When data to be transmitted is written to the transmission data register in transmission enable state, it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output terminal (SOTn pin).
Page 495 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4.5 Extended Status/Control Register (ESCRn) This register provides several LIN functions, direct access to the SINn and SOTn pin and setting for USART synchronous clock mode.
Page 496 CHAPTER 20 USART MB96300 Super Series Hardware Manual ■ Extended status/control register (ESCRn) Figure 20.4-6 Conﬁguration of the extended status/control register (ESCRn) ESCRn Initial value 0 0 0 0 0 1 0 0 R/W R/W R/W R/W R/W R/W bit8 SCES Sampling Clock Edge Selection (Mode 2) Sampling on rising clock edge (normal)
Page 497 MB96300 Super Series Hardware Manual CHAPTER 20 USART Table 20.4-4 Function of each bit of the extended status/control register (ESCRn) Bit name Function bit14 LBD: • This bit goes 1 if a LIN synch break was detected in operating mode 3. Writing a 0 to LIN synch break it clears this bit and the corresponding interrupt, if it is enabled.
Page 498 CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.4.6 Extended Communication Control Register (ECCRn) The extended communication control register provides bus idle recognition interrupt settings, synchronous clock settings, and the LIN break generation.
Page 499 MB96300 Super Series Hardware Manual CHAPTER 20 USART ■ Extended communication control register (ECCRn) Figure 20.4-7 Conﬁguration of the extended communication control register (ECCRn) ECCRn Initial value MS SCDE SSM 0 0 0 0 0 0 X X W R/W R/W bit0 Transmission bus idle TBI *...
Page 500 CHAPTER 20 USART MB96300 Super Series Hardware Manual Table 20.4-6 Function of each bit of the Extended communication control register (ECCRn) Bit name Function bit7 INV: Invert serial • This bit inverts the serial data at SINn and SOTn pin. SCKn is not affected (see data ESCRn: SCES).
Page 501 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4.7 Baud Rate/Reload Counter Register (BGRn) The baud rate/reload counter registers set the division ratio for the serial clock. Also the actual count of the transmission reload counter can be read. ■ Baud rate generator register (BGRn) Figure 20.4-8 Baud rate generator register (BGRn) Initial value 0 0 0 0 0 0 0 0...
Page 502 CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.4.8 Extended Serial Interrupt Register (ESIRn) The extended serial interrupt register contains control bits to change the interrupt handling of the USART for improved interrupt handling and to enable DMA to handle USART data transfers.
Page 503 MB96300 Super Series Hardware Manual CHAPTER 20 USART Table 20.4-7 Function of each bit of the extended serial interrupt register (ESIRn) Bit name Function bit3 TDRE: • This ﬂag has the same function as SSR:TDRE but it is not cleared when data is Transmission Data written to the transmission data register TDR.
Page 504: Usart Interrupts
CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.5 USART Interrupts USART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the Reception Data Register (RDRn), or a reception error occurs. •...
Page 505 MB96300 Super Series Hardware Manual CHAPTER 20 USART ● Receive interrupt If one of the following events occurs in reception mode, the corresponding flag bit of the Serial Status Register (SSRn) and the Extended Serial Interrupt Register (ESIRn) is set to “1”: •...
Page 506 CHAPTER 20 USART MB96300 Super Series Hardware Manual service routine. ● LIN Synchronization Break Interrupt This paragraph is only relevant, if USART operates in mode 3 as a LIN slave. If the bus (serial input) goes “0” (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag bit of the Extended Status/Control Register (ESCRn) is set to “1”.
Page 507 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.5.1 Receive interrupt Generation and Flag Set Timing The following are the receive interrupt causes: completion of reception (SSRn:RDRF) and occurrence of a reception error (SSRn:PE, ORE, or FRE). ■ Receive interrupt generation and ﬂag set timing Generally a receive interrupt is generated, if the received data is complete (when ESIRn:AICD = "0": SSRn:RDRF = "1", when ESIRn:AICD = "1": ESIRn:RDRF = "1") and the receive interrupt Enable (RIE) flag bit of the Serial Status Register (SSRn) was set to “1”.
Page 508 CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.5-2 ORE set timing: Receive data RDRF...
Page 509 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the transmission data is transferred from transmission data register (TDRn) to transmission shift register and started. ■ Transmission interrupt generation and ﬂag set timing A transmission interrupt is generated, when the next data to be sent is ready to be written to the Transmission Data Register (TDRn), i.
Page 510 CHAPTER 20 USART MB96300 Super Series Hardware Manual ■ Transmission interrupt request generation timing If the TDRE flag is set to “1” when a transmission interrupt is enabled (SSRn: TIE=1), transmission interrupt request is generated. Note: A transmission completion interrupt is generated immediately after the transmission interrupt is enabled (TIE=1) because the TDRE bit is set to 1 as its initial value.
Page 511: Usart Baud Rates
MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.6 USART Baud Rates One of the following can be selected for the USART serial clock source: • Dedicated baud rate generator (Reload Counter) • External clock as it is (clock input to the SCKn pin) •...
Page 512 CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.6-1 Baud rate selection circuit (reload counter) REST Start bit falling Reload Value: v edge detected Rxc = 0? Reception Reception Reload Clock 15-bit Reload Counter reset Rxc = v/2? Reload Value: v Peripheral clock CLKP1 Txc = 0?
Page 513 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the baud rate The both 16-bit reload counters are programmed by the baud rate generator registers (BGRn). The following calculation formula should be used to set the desired baud rate: Reload Value: v = [Φ...
Page 514 CHAPTER 20 USART MB96300 Super Series Hardware Manual ■ Suggested division ratios for different peripheral clock CLKP1 frequencies and baud rates The following settings are suggested for different peripheral clock CLKP1 frequencies and baud rates: Table 20.6-1 Suggested baud rates and reload values at different peripheral clock CLKP1 frequencies. 8 MHz 10 MHz 16 MHz...
Page 515 MB96300 Super Series Hardware Manual CHAPTER 20 USART 2) Maximum Synchronous Baud Rate: Peripheral clock CLKP1 frequency divided by 5.
Page 516 CHAPTER 20 USART MB96300 Super Series Hardware Manual ■ Using external clock If the EXT bit of the SMRn register is set, an external clock is selected, which has to be connected to the SCKn pin. The external clock is used in the same way as the peripheral clock CLKP1 to the baud rate reload counter.
Page 517 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.6.2 Restarting the Reload Counter The Reload Counters can be restarted of the following reasons: Transmission and reception reload counter: • Global MCU reset • USART programmable clear (SMRn:UPCL bit) • User programmable restart (SMRn:REST bit) Reception reload counter: •...
Page 518 CHAPTER 20 USART MB96300 Super Series Hardware Manual • Automatic restart In asynchronous USART mode if a falling edge of a start bit is detected the Reception Reload Counter is restarted. This is intended to synchronize the serial input shifter to the incoming serial data stream. ●...
Page 519: Operation Of Usart
MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.7 Operation of USART USART operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in multiprocessor communication.
Page 520 CHAPTER 20 USART MB96300 Super Series Hardware Manual synchronous mode 2. • Select operation mode 1 for the master-slave connection method and use it either for the master or slave system. ■ Synchronization methods In asynchronous operation USART reception clock is automatically synchronized to the falling edge of a received start bit.
Page 521 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) When USART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. ■...
Page 522 CHAPTER 20 USART MB96300 Super Series Hardware Manual ● Transmission operation If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSRn) is “1”, transmission data is allowed to be written to the Transmission Data Register (TDRn). When data is written, the TDRE flag goes “0”.
Page 523 MB96300 Super Series Hardware Manual CHAPTER 20 USART and the P bit specifies even or odd parity in mode 0.
Page 524 CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.7.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer method is used for USART operation mode 2 (normal mode). ■ Operation in synchronous mode (operation mode 2) ● Transfer data format In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the Extended Communication Control Register (ECCRn) is 0.
Page 525 MB96300 Super Series Hardware Manual CHAPTER 20 USART Figure 20.7-3 Transfer data format with clock inversion mark level reception or transmission clock (SCES = 0, CCO = 0): reception or transmission clock (SCES = 1, CCO = 0): mark level data stream (SSM = 1) (here: no parity, 1 stop bit) data frame...
Page 526 CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.7-5 Continuous clock output in mode 2 reception or transmission clock (SCES = 0, CCO = 1): reception or transmission clock (SCES = 1, CCO = 1): data stream (SSM = 1) (here: no parity, 1 stop bit) data frame ●...
Page 527 MB96300 Super Series Hardware Manual CHAPTER 20 USART MS: “0” for master mode (USART generates the serial clock); “1” for slave mode (USART receives serial clock from the master device) Serial control register (SCRn): RXE, TXE: set one or both of these control bits to"1" to begin communication.
Page 528 CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.7.3 Operation with LIN Function (Operation Mode 3) USART can be used either as LIN-Master or LIN-Slave. For this LIN function a special mode is provided. Setting the USART to mode 3 conﬁgures the data format to 8N1-LSB- ﬁrst format.
Page 529 MB96300 Super Series Hardware Manual CHAPTER 20 USART capture module represents 8 times of the baud rate clock cycle. Therefore, baud rate setting value is summarized as follows: without timer overflow : BGRn value = (b-a)/8 with timer overflow : BGRn value = (max + b-a)/8 where max is the timer maximum value at the overflow occurs.
Page 530 CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.7-7 USART behavior as slave in LIN mode Serial clock Serial Input (LIN bus) LBR cleared by CPU Internal Signal Synch break (e. g. 14 Tbit) Synch field LIN Synch Break Detection Interrupt and Flags...
Page 531 MB96300 Super Series Hardware Manual CHAPTER 20 USART ● LIN bus timing Figure 20.7-8 LIN bus timing and USART signals no clock used (calibration frame) old serial clock new (calibrated) serial clock ICU count (SIN) (IRQ0) LBIE Internal Signal to ICU IRQ from RDRF (IRQ0)
Page 532 CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.7.4 Direct Access to Serial Pins USART allows the user to directly access to the transmission pin (SOTn) or the reception pin (SINn). ■ USART direct pin access The USART provides the ability for the software to access directly to serial input or output pin. The software can always monitor the incoming serial data by reading the SIOP bit of the ESCRn.
Page 533 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■...
Page 534 CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.7-10 Connection example of USART mode 2 bidirectional communication Input Output CPU-1 (Master) CPU-2 (Slave) Figure 20.7-11 Example of master-slave communication ﬂowchart (Transmission side) (Reception side) Start Start Operating mode setting Operating mode setting (match the transmission side) (either 0 or 2)
Page 535 MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.7.6 Master-Slave Communication Function (Multiprocessor Mode) USART communication with multiple CPUs connected in master-slave mode is available for both master or slave systems. ■ Master-slave communication function The settings shown in Figure 20.7-12 "Settings for USART operation mode 1" are required to operate USART in multiprocessor mode (operation mode 1).
Page 536 CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.7-13 Connection example of USART master-slave communication SOT1 SIN1 Master CPU Slave CPU #0 Slave CPU #1 ● Function selection Select the operation mode and data transfer mode for master-slave communication as shown in Table 20.7-3 "Selection of the master-slave communication function".
Page 537 MB96300 Super Series Hardware Manual CHAPTER 20 USART Figure 20.7-14 Master-slave communication ﬂowchart (Master CPU) (Slave CPU) Start Start Set operation mode 1 Set operation mode 1 Set SIN pin as the Set SIN pin as the serial data input pin. serial data input pin.
Page 538 CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.7.7 LIN Communication Function USART communication with LIN devices is available for both LIN master or LIN slave systems. ■ LIN-master-slave communication function The settings shown in the figure below are required to operate USART in LIN communication mode (operation mode 3).
Page 539 MB96300 Super Series Hardware Manual CHAPTER 20 USART Figure 20.7-16 Connection example of a small LIN-Bus system LIN bus Single-Wire- Single-Wire- LIN-Slave LIN-Master Transceiver Transceiver...
Page 540 CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.7.8 Sample Flowcharts for USART in LIN communication (Operation Mode 3) This section contains sample ﬂowcharts for USART in LIN communication.
Page 541 MB96300 Super Series Hardware Manual CHAPTER 20 USART ■ USART as master device Figure 20.7-17 USART LIN master ﬂow chart START Initial setting : Set operation mode 3 Serial data output enabled Baudrate setting Synch break length setting TXE=1, TIE=0 RXE=0, RIE=1 Send Message? No (transmission)
Page 542 CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.7-18 USART LIN slave ﬂow chart START Initial setting : Set operation mode 3 Serial data output enabled Baudrate setting Synch break length setting TXE=1, TIE=0 RXE=0, RIE=1 Connection with UART and ICU Reception prohibited ICU interrupt enabled Synch break interrupt enabled...
Page 543: Notes On Using Usart
MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.8 Notes on Using USART Notes on using USART are given below. ■ Notes on using USART ● Enabling operations In USART, the control register (SCRn) has TXE (transmission) and RXE (reception) operation enable bits. Both, transmission and reception operations, must be enabled before the communication starts because they have been disabled as the default value (initial value).
Page 544 CHAPTER 20 USART MB96300 Super Series Hardware Manual the synch break can not be correctly checked against the minimum requirement of the LIN specification (13 master bit time and 11 slave bit time). ● Bus idle function The Bus Idle Function cannot be used in synchronous slave mode mode 2. ●...
Page 545 MB96300 Super Series Hardware Manual CHAPTER 20 USART Figure 20.8-1 Baud Rate Detection Using the Input Capture Units Pin IN4 ICU4 LIN-UART4 PFR[4] & EPFR[4] LSYN Free-Run TIMER4 Pin IN5 ICU5 LIN-UART5 PFR[5] & EPFR[5] LSYN If the PFR bit equals ‘1’ and the EPFR bits equals ‘0’, the ICU is connected to its corresponding input pin IN. If the PFR bit equals ‘1’...
Page 546 CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.8-3 Data Stream Synchronization Note: In case a framing error occurred (stop bit: SINn = "0") and next start bit (SINn = "0") follows immediately, this start bit is recognized regardless of no falling edge before. This is used to remain UART synchronized to the data stream and to determine bus always dominant errors (See Figure 20.8-4 "USART Dominant Bus Behaviour"...
Page 547 MB96300 Super Series Hardware Manual CHAPTER 20 USART Figure 20.8-4 USART Dominant Bus Behaviour...
Page 548 CHAPTER 20 USART MB96300 Super Series Hardware Manual...
Page 549: 400 Khz I2C Interface
CHAPTER 21 400 kHz I C INTERFACE This section describes the functions and operation of the fast I C interface. 21.1 "I2C Interface Overview" 21.2 "I2C Interface Registers" 21.3 "I2C Interface Operation" 21.4 "Programming Flow Charts"...
Page 550: I2C Interface Overview
CHAPTER 21 400 kHz I C INTERFACE 21.1 C Interface Overview The I C interface is a serial I/O port supporting the Inter IC bus, operating as a master/ slave device on the I C bus. ■ Features • Master/slave transmitting and receiving functions •...
Page 551 CHAPTER 21 400 kHz I C INTERFACE Figure 21.1-1 Block diagram ICCR C enable ICCR Clock Divider 1 2 3 4 5 ... 32 Clock Selector Sync Clock Divider 2 (by 12) Shift Clock Generator SCL Duty Cycle Generator IBSR Bus busy Repeated start Bus Observer...
Page 552: I2C Interface Registers
CHAPTER 21 400 kHz I C INTERFACE 21.2 C Interface Registers This section describes the function of the I C interface registers in detail.
Page 553 CHAPTER 21 400 kHz I C INTERFACE ■ I C Interface registers Figure 21.2-1 I C Interface registers Bus Control Register (IBCRn) IBCRn BER BEIE SCC MSS ACK GCAA INTE Initial value 0 0 0 0 0 0 0 0 R/W R/W W R/W R/W R/W Bus Status Register (IBSRn)
Page 554 CHAPTER 21 400 kHz I C INTERFACE Seven bit slave address MasK register (ISMKn) ISMKn SM6 SM5 SM4 SM3 SM2 SM1SM0 ENSB Initial value 0 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W Data Register (IDARn) IDARn D7 D6 D5 D4 D3 D2 D1 D0...
Page 555 CHAPTER 21 400 kHz I C INTERFACE 21.2.1 Bus Status Register (IBSRn) The bus status register (IBSRn) has the following functions: • Bus busy detection • Repeated start condition detection • Arbitration loss detection • Acknowledge detection • Data transfer direction indication •...
Page 556 CHAPTER 21 400 kHz I C INTERFACE Figure 21.2-2 Conﬁguration of the bus status register (IBSRn) IBSRn TRX AAS Initial value 0 0 0 0 0 0 0 0 bit 0 Address data transfer bit Incoming data is not address (or bus not in use) Incoming data is address bit 1 General Call Address bit...
Page 557 CHAPTER 21 400 kHz I C INTERFACE Table 21.2-1 Function of each bit of the bus status register (IBSRn) (2/3) Bit name Function bit 5 This bit indicates an arbitration loss. Arbitration loss "0": No arbitration loss detected. "1": Arbitration loss occurred during master sending. This bit is cleared by writing "0"...
Page 558 CHAPTER 21 400 kHz I C INTERFACE Table 21.2-1 Function of each bit of the bus status register (IBSRn) (3/3) Bit name Function bit 0 ADT: This bit indicates the detection of an address data transfer. Address data "0": Incoming data is not address data (or bus is not in use). transfer bit "1": Incoming data is address data.
Page 559 CHAPTER 21 400 kHz I C INTERFACE 21.2.2 Bus Control Register (IBCRn) The Bus Control Register (IBCRn) has the following functions: • Interrupt enabling ﬂags • Interrupt generation ﬂag • Bus error detection ﬂag • Repeated start condition generation • Master / slave mode selection •...
Page 560 CHAPTER 21 400 kHz I C INTERFACE Figure 21.2-3 Conﬁguration of the bus control register (IBCRn) IBCRn BER BEIE SCC MSS ACK GCAA INTE Initial value 0 0 0 0 0 0 0 0 R/W R/W W R/W R/W R/W bit 8 Interrupt bit see table on next page for details...
Page 561 CHAPTER 21 400 kHz I C INTERFACE Table 21.2-2 Function of each bit of the bus control register (IBCRn) (1/2) Bit name Function bit 15 BER: This bit is the bus error interrupt ﬂag. It is set by the hardware and cleared by the user. Bus error bit It always reads "1"...
Page 562 CHAPTER 21 400 kHz I C INTERFACE Table 21.2-2 Function of each bit of the bus control register (IBCRn) (2/2) Bit name Function bit 11 ACK: This bit enables the acknowledge generation on data byte reception. It only can be Acknowledge bit changed by the user.
Page 563 MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE and “0” to the MSS bit, the MSS bit clearing takes priority. A stop condition is generated and the interface enters slave mode. If specific conditions are met, the AL (arbitration lost) bit does not set the INT (interrupt) bit.
Page 564 CHAPTER 21 400 kHz I2C INTERFACE MB96300 Super Series Hardware Manual Figure 21.2-5 Diagram of timing at which an interrupt upon detection of "AL bit = 1" does not occur Stop Condition INT bit interruption is not generated Start Condition in 9th clock.
Page 565 MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE Master mode setting Setting “1” to MSS bit in bus control register (IBCR) Wait for the time for three-bit data transmission at the I2C transfer frequency set in the clock control register (ICCR).* BB bit =0 and AL bit = 1 Setting EN bit to “0”...
Page 566 CHAPTER 21 400 kHz I2C INTERFACE MB96300 Super Series Hardware Manual 21.2.3 Ten Bit Slave Address Register (ITBAn) The Ten Bit Slave Address Register (ITBAn) designates the ten bit slave address. ■ Ten Bit Slave Address Register (ITBAn) Write access to this register is only possible if the interface is disabled (EN="0" in ICCR). Figure 21.2-7 Conﬁguration of the Ten Bit Slave Address Register (IBTAn) ITBAHn TA9 TA8...
Page 567 MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE 21.2.4 Ten Bit Slave Address Mask Register (ITMKn) The Ten Bit Slave Address Mask Register (ITMKn) contains the ten bit slave address mask and the ten bit slave address enable bit. ■...
Page 568 CHAPTER 21 400 kHz I2C INTERFACE MB96300 Super Series Hardware Manual Table 21.2-4 Function of each bit of the ten bit address mask register (ITMKn) Bit name Function bit 9 to 0 TM9 to TM0: This register is used to mask the ten bit slave address of the interface. Write access to Ten bit slave these bits is only possible if the interface is disabled (EN="0"...
Page 569 MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE 21.2.5 Seven Bit Slave Address Register (ISBAn) The Seven Bit Slave Address Register (ISBAn) contains the seven bit slave address. ■ Seven Bit Slave Address Register (ISBAn) Write access to this register is only possible if the interface is disabled (EN="0" in ICCR). Figure 21.2-9 Conﬁguration of the Seven Bit Slave Address Register (ISBAn) ISBAn SA6 SA5 SA4 SA3 SA2 SA1 SA0...
Page 570 CHAPTER 21 400 kHz I2C INTERFACE MB96300 Super Series Hardware Manual 21.2.6 Seven Bit Slave Address Mask Register (ISMKn) The Seven Bit Slave Address Mask Register (ISMKn) contains the seven bit slave address mask and the seven bit slave address enable bit. ■...
Page 571 MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE 21.2.7 Data Register (IDARn) The Data Register for the 400 kHz I C Interface (IDARn) is used to send and receive data by the CPU. ■ Data Register (IDARn) Figure 21.2-11 Conﬁguration of the Data Register (IDARn) IDARn D7 D6 D5 D4 D3 D2...
Page 572 CHAPTER 21 400 kHz I2C INTERFACE MB96300 Super Series Hardware Manual 21.2.8 Clock Control Register (ICCRn) The Clock Control Register (ICCRn) has the following functions: • Enable test mode • Enable IO pad noise ﬁlters • Enable I C interface operation •...
Page 573 MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE ■ Clock Control Register (ICCRn) contents Table 21.2-8 Function of each bit of the Clock Control Register (ICCRn) Bit name Function bit 15 Undeﬁned This bit always returns "0" during reading. bit 14 NSF: This bit enables the noise ﬁlters built into the SDA and SCL IO pads.
Page 574 CHAPTER 21 400 kHz I2C INTERFACE MB96300 Super Series Hardware Manual ■ Clock prescaler settings The calculation formula for CS0 to CS4 is determined as follows: φ φ Bitrate = n>0 : Peripheral clock CLKP1, Noise ﬁlter disabled n*12 + 16 φ...
Page 575: I2C Interface Operation
MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE 21.3 C Interface Operation The I C bus executes communication using two bi-directional bus lines, the serial data line (SDA) and serial clock line (SCL). The I C interface has two open-drain I/O pins (SDA/ SCL) corresponding to these lines, enabling wired logic applications.
Page 576 CHAPTER 21 400 kHz I2C INTERFACE MB96300 Super Series Hardware Manual Since there are separate registers for the ten and seven bit address and their bit masks, it is possible to make the interface acknowledge on both addresses by setting the ENSB (in ISMK) and ENTB (in ITMK) bits. The received slave address length (seven or ten bit) may be determined by reading the RAL bit in the ITMK register (this bit is valid if the AAS bit is set only).
Page 577 MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE the master, the TRX bit is set to "0" and the device goes to receiving mode. This enables the master to generate a stop condition as soon as the slave has released the SCL line. In master mode, acknowledgement by the slave can be checked by reading the LRB bit in the IBSR register.
Page 578: Programming Flow Charts
CHAPTER 21 400 kHz I2C INTERFACE MB96300 Super Series Hardware Manual 21.4 Programming Flow Charts Each programming ﬂow charts for the 400 kHz I C interface is shown below.
Page 579 MB96300 Super Series Hardware Manual CHAPTER 21 400 kHz I2C INTERFACE ■ Programming ﬂow charts Figure 21.4-1 Example of slave addressing and sending data Addressing a 7 bit slave Sending data Start Start Address slave for write Clear BER bit (if set); Enable Interface EN:=1;...
Page 580 CHAPTER 21 400 kHz I2C INTERFACE MB96300 Super Series Hardware Manual Figure 21.4-2 Example of receiving data Start Address slave for read Clear ACK bit in IBCR if it’s the last byte to read from slave; INT := 0 INT=1? Bus error BER=1? reenable IF...
Page 581: Can Controller
CHAPTER 22 CAN CONTROLLER This chapter explains the functions and operations of the CAN controller. 22.1 "Overview" 22.2 "Functional Description" 22.3 "Register Description" 22.4 "CAN Device Related Registers" 22.5 "CAN Protocol Related Registers" 22.6 "Message Interface Register Sets" 22.7 "Message Object in the Message Memory" 22.8 "Message Handler Registers"...
Page 582: Overview
CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.1 Overview The CAN performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the physical layer additional transceiver hardware is required.
Page 583: Functional Description
MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.2 Functional Description This chapter provides an overview of the CAN module’s operating modes and how to use them. ■ Software Initialisation The software initialization is started by setting the bit INIT in the CAN Control Register CTRLRLn, either by software or by a hardware reset, or by going Bus_Off.
Page 584 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual transmission of a message may be requested autonomously by the reception of a remote frame with a matching identifier. ■ Disabled Automatic Retransmission According to the CAN Specification (see ISO11898, 6.3.3 Recovery Management), the CAN provides means for automatic retransmission of frames that have lost arbitration or that have been disturbed by errors during transmission.
Page 585 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER Figure 22.2-1 CAN Core in Silent Mode ■ Loop Back Mode The CAN Core can be set in Loop Back Mode by programming the Test Register TESTRn bit LBACK to one. In Loop Back Mode, the CAN Core treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) into a Receive Buffer.
Page 586 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual Figure 22.2-3 CAN Core in Loop Back combined with Silent Mode ■ Basic Mode The CAN Core can be set in Basic Mode by programming the Test Register TESTRn bit BASIC to "1". In this mode the CAN module runs without the Message RAM.
Page 587: Register Description
MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.3 Register Description This section lists the CAN registers and describes the function of each register in detail. ■ Programmer’s Model The CAN module allocates an address space of 256 bytes (64 words). The CAN registers can be accessed from the CPU in byte and word.
Page 588 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual Table 22.3-1 CAN Register Summary Offset Byte Register Word Register Description Initial value Name Name CANn base address + 0xC BRPERLn BRPERn CAN n - BRP Extension XXXX0000 register CANn base address + 0xD BRPERHn CAN n - BRP Extension XXXXXXXX...
Page 589 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER Table 22.3-1 CAN Register Summary Offset Byte Register Word Register Description Initial value Name Name CANn base address + 0x22 IF1DTB1Ln IF1DTB1n CAN n - IF1 Data B1 00000000 CANn base address + 0x23 IF1DTB1Hn CAN n - IF1 Data B1 00000000...
Page 590 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual Table 22.3-1 CAN Register Summary Offset Byte Register Word Register Description Initial value Name Name CANn base address + 0x50 IF2DTA2Ln IF2DTA2n CAN n - IF2 Data A2 00000000 CANn base address + 0x51 IF2DTA2Hn CAN n - IF2 Data A2 00000000...
Page 591 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER Table 22.3-1 CAN Register Summary Offset Byte Register Word Register Description Initial value Name Name CANn base address + 0xB2 MSGVAL2Ln MSGVAL2n CAN n - Message Valid 00000000 Register CANn base address + 0xB3 MSGVAL2Hn CAN n - Message Valid 00000000...
Page 592: Can Device Related Registers
CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.4 CAN Device Related Registers These registers are related to the device which hosts the CANbus controller.
Page 593 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.4.1 CAN Output Enable Register (COERn) The CAN Output Enable Register (COERn) controls whether the device pins is used as CANbus controller’s TX pin or not. ■ CAN Output Enable Register (COERn) Figure 22.4-1 Conﬁguration of the CAN Output Enable Register (COERn) ⇐...
Page 594: Can Protocol Related Registers
CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.5 CAN Protocol Related Registers These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes and the conﬁguration of the CAN bit timing and provide status information.
Page 595 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.5.1 CAN Control Register (CTRLRn) The CAN Control Register (CTRLRn) controls the basic operation modes of the CAN controller. ■ CAN Control Register (CTRLRn) Figure 22.5-1 Conﬁguration of the CAN Control Register (CTRLRn) ⇐...
Page 596 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual are transmitted, the TXRQST and NEWDAT bits will be reset and, if enabled by TXIE, INTPND will be set. [bit4] reserved bit Always write "0". Read value is not deﬁned. Read-Modify-Write is not affected. [bit3] Error Interrupt Enable Disabled - No Error Status Interrupt will be generated.
Page 597 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.5.2 Status Register (STATRn) The Status Register (STATRn) shows the status of the CAN controller. ■ Status Register (STATRn) Figure 22.5-2 Conﬁguration of the Status Register (STATRn) ⇐ Bit no. Status Register high byte STATRHn Address : Base + 0x03 Read/write ⇒...
Page 598 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. [bit2 - bit0] Last Error Code (Type of the last error to occur on the CAN bus) No Error More than 5 equal bits in a sequence have occurred in a part of a received message Stuff Error...
Page 599 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.5.3 Error Counter (ERRCNTn) The Error Counter Register (ERRCNTn) contains the Receive and Transmit Error Counters REC and TEC. ■ Error Counter (ERRCNTn) Figure 22.5-3 Conﬁguration of the Error Counter (ERRCNTn) ⇐...
Page 600 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.5.4 Bit Timing Register (BTRn) The Bit Timing Register (BTRn) enables controlling of the CAN bus controller bit timing. ■ Bit Timing Register (BTRn) Figure 22.5-4 Conﬁguration of the Bit Timing Register (BTRn) ⇐...
Page 601 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER are set.
Page 602 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.5.5 Test Register (TESTRn) The Test Register (TESTRn) offers functionality to test the CAN bus system. ■ Test Register (TESTRn) Figure 22.5-5 Conﬁguration of the Test Register (TESTRn) ⇐ Bit no. Test Register high byte TESTRHn Address : Base + 0x0B...
Page 603 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER [bit2] BASIC Basic Mode Basic Mode disabled. IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. [bit1-bit0] Reserved Bits Always write "0". Read value is not deﬁned. Read-Modify-Write is not affected. Note: Write access to the Test Register is enabled by setting bit TEST in the CAN Control Register CTRLRn.
Page 604 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.5.6 BRP Extension Register (BRPERn) The BRP Extension Register (BRPERn) contains an extension for the baud rate generator prescaler. ■ BRP Extension Register (BRPERn) Figure 22.5-6 Conﬁguration of the BRP Extension Register (BRPERn) ⇐...
Page 605: Message Interface Register Sets
MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.6 Message Interface Register Sets To avoid access conﬂicts between the CPU and the CAN bus controller in accessing the Message RAM, there are two sets of Interface Registers which are used to control the CPU access to the Message RAM.
Page 606 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.6.1 IFx Command Request Registers (IFxCREQn) A message transfer is started as soon as the CPU has written the message number to the Command Request Register (IFxCREQn). With this write operation the CPU is notiﬁed that a transfer is in progress.
Page 607 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER Message Number (for 128 message buffer CANs, please refer to the data sheet for the number of message buffers [bit7-bit0] MSGN of the device.) 0x00 Not a valid Message Number, interpreted as 0x80. 0x01-0x80 Valid Message Number, the Message Object in the Message RAM is selected for data transfer.
Page 608 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.6.2 IFx Command Mask Register (IFxCMSKn) The control bits of the IFx Command Mask Register (IFxCMSKn) specify the transfer direction and select which of the IFx Message Buffer Registers are source or target of the data transfer.
Page 609 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER Transfer Control Bits to Message Object. [bit3] Clear Interrupt Pending Bit When writing to a Message Object, this bit is ignored. [bit2] TXREQ Access Transmission Request Bit TXRQST bit unchanged set TXRQST bit [bit1] DATAA Access Data Bytes 0-3...
Page 610 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual [bit0] DATAB Access Data Bytes 4-7 Data Bytes 4-7 unchanged. Transfer Data Bytes 4-7 to IFx Message Buffer Register. Note: A read access to a Message Object can be combined with the reset of the control bits INTPND and NEWDAT.
Page 611 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.6.3 IFx Mask Registers (IFxMSK1n, IFxMSK2n) The bits of the Message Buffer registers mirror the Message Objects in the Message RAM. The bits of the IFx Mask Registers (IFxMSK1n, IFxMSK2n) specify which parts of the message arbitration registers (IFxARB1n, IFxARB2n) are evaluated.
Page 612 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.6.4 IFx Arbitration Registers (IFxARB1n, IFxARB2n) The bits of the Message Buffer registers mirror the Message Objects in the Message RAM. In case of transmission, the bits of the message arbitration registers (IFxARB1n, IFxARB2n) specify the ID of the message.
Page 613 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.6.5 IFx Message Control Register (IFxMCTRn) The bits of the Message Buffer registers mirror the Message Objects in the Message RAM. The bits of the Message Control Register (IFxMCTRn) contain status information and control bits.
Page 614 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.6.6 IFx Data A and Data B Registers (IFxDTA1n, IFxDTA2n, IFxDTB1n, IFxDTB2n) The data bytes of CAN messages are stored in the IFx Message Buffer Registers. ■ IFx Data A and Data B Registers (IFxDTAn, IFxDTBn) In a CAN Data Frame, Data(0) is the first, Data(7) is the last byte to be transmitted or received.
Page 615: Message Object In The Message Memory
MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.7 Message Object in the Message Memory There are 32 Message Objects (up to 128 depending on the implementation) in the Message RAM. To avoid conﬂicts between CPU access to the Message RAM and CAN message reception and transmission, the CPU cannot directly access the Message Objects, these accesses are handled via the IFx Interface Registers.
Page 616 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual MSK28-0 Identiﬁer Mask The corresponding bit in the identiﬁer of the message object cannot inhibit the match in the acceptance ﬁltering. The corresponding identiﬁer bit is used for acceptance ﬁltering. Extended Identiﬁer The 11-bit (“standard”) Identiﬁer will be used for this Message Object.
Page 617 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER Note: This bit is used to concatenate two ore more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer) this bit must always be set to 1. For details on the concatenation of Message Objects see section "Configuration of a FIFO Buffer", on page 624.
Page 618 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual Depending on the exact time when TXRQST was set to 0, the message may not be transmitted immediately after setting TXRQST = "1", but after any of the following events: 1. there is activity ongoing on the CANbus 2.
Page 619: Message Handler Registers
MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.8 Message Handler Registers All Message Handler registers are read-only. Their contents (TXRQST, NEWDAT, INTPND, and MSGVAL bits of each Message Object and the Interrupt Identiﬁer) is status information provided by the Message Handler FSM.
Page 620 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.8.1 Interrupt Register (INTRn) The Interrupt Register (INTRn) points to the pending interrupt of highest priority. ■ Interrupt Register (INTRn) Figure 22.8-1 Conﬁguration of the Interrupt Register (INTRn) ⇐ Bit no. Interrupt Register high byte INTRH Address : Base + 0x08...
Page 621 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.8.2 Transmission Request Registers (TREQR1n, TREQR2n) The Transmission Request Registers (TREQR1n, TREQR2n) control the transmission of message objects. ■ Transmission Request Registers (TREQR1n, TREQR2n) Figure 22.8-2 Transmission Request Registers (TREQR1n, TREQR2n) ⇐...
Page 622 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual immediately after setting TXRQST = "1", but after any of the following events: 1. there is activity ongoing on the CANbus 2. a transmission request is issued on another message object 3.
Page 623 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.8.3 New Data Registers (NEWDT1n, NEWDT2n) The New Data Registers (NEWDT1n, NEWDT2n) indicate per message buffer that new data has been received. ■ New Data Registers (NEWDT1n, NEWDT2n) Figure 22.8-3 Conﬁguration of the New Data Registers (NEWDT1n, NEWDT2n) ⇐...
Page 624 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual If more than 32 message buffers are implemented, the following table gives an overview about the additional flags: Table 22.8-2 Additional ﬂags when more than 32 message buffers exist addr+0 addr+1 addr+2 addr+3 NEWDT 4 &...
Page 625 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.8.4 Interrupt Pending Registers (INTPND1n, INTPND2n) The Interrupt Pending Registers (INTPND1n, INTPND2n) indicate whether a message object caused an interrupt or not. ■ Interrupt Pending Registers (INTPND1n, INTPND2n) Figure 22.8-4 Conﬁguration of Interrupt Pending Registers (INTPND1n, INTPND2n) ⇐...
Page 626 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual If more than 32 message buffers are implemented, the following table gives an overview about the additional flags: Table 22.8-3 Additional ﬂags when more than 32 message buffers exist addr+0 addr+1 addr+2 addr+3 INTPND 4 &...
Page 627 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER 22.8.5 Message Valid Registers (MSGVAL1n, MSGVAL2n) The Message Valid Registers (MSGVAL1n, MSGVAL2n) show the validity status for each message object. ■ Message Valid Registers (MSGVAL1n, MSGVAL2n) Figure 22.8-5 Conﬁguration of Message Valid Registers (MSGVAL1n, MSGVAL2n) ⇐...
Page 628: Can Application
CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual 22.9 CAN Application This section describes how to use the CAN module in the application ■ Management of Message Objects The configuration of the Message Objects in the Message RAM will (with the exception of the bits MSGVAL, NEWDAT, INTPND, and TXRQST) not be affected by resetting the chip.
Page 629 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER Figure 22.9-1 Data Transfer between IFx Registers and Message RAM After the partial write of a Message Object, the Message Buffer Registers that are not selected in the Command Mask Register will be set to the actual contents of the selected Message Object. After the partial read of a Message Object, the Message Buffer Registers that are not selected in the Command Mask Register will be left unchanged.
Page 630 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual scanning of the Message RAM for a matching valid Message Object. To scan the Message RAM for a matching Message Object, the Acceptance Filtering unit is loaded with the arbitration bits from the CAN Core shift register. Then the arbitration and mask fields (including MSGVAL, UMASK, NEWDAT, and EOB) of Message Object 1 are loaded into the Acceptance Filtering unit and compared with the arbitration field from the shift register.
Page 631 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER Figure 22.9-2 Initialisation of a Transmit Object MSGVAL DATA MASK NEWDAT MSGLST RXIE TXIE INTPND RMTEN TXRQST appl. appl. appl. appl. appl. The Arbitration Registers (ID28-0 and XTD bit) are given by the application. They define the identifier and type of the outgoing message.
Page 632 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual appl. appl. appl. appl. The Arbitration Registers (ID28-0 and XTD bit) are given by the application. They define the identifier and type of accepted received messages. If an 11-bit Identifier (“Standard Frame”) is used, it is programmed to ID28 - ID18, ID17 - ID0 can then be disregarded.
Page 633 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER values of these bits in the Message Control Register always reflect the status before resetting the bits. To assure the correct function of a FIFO Buffer, the CPU should read out the Message Objects starting at the FIFO Object with the lowest message number.
Page 634 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual Figure 22.9-4 CPU Handling of a FIFO Buffer START Message Interrupt Read Interrupt Pointer case Interrupt Pointer 0x8000h else 0x0000h Status Change Interrupt Handling MessageNum = Interrupt Pointer Write MessageNum to IFx Command Request (Read Message to IFx Registers, Reset NewDat = 0, Reset IntPnd = 0)
Page 635 MB96300 Super Series Hardware Manual CHAPTER 22 CAN CONTROLLER ■ Handling of Interrupts If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it.
Page 636 CHAPTER 22 CAN CONTROLLER MB96300 Super Series Hardware Manual The Synchronisation Segment Sync_Seg is that part of the bit time where edges of the CAN bus level are expected to occur; the distance between an edge that occurs outside of Sync_Seg and the Sync_Seg is called the phase error of that edge.
Page 637: Clock Output Function
CHAPTER 23 CLOCK OUTPUT FUNCTION This chapter describes the functions and operations of the clock output function. 23.1 "Overview of the Clock Output Function" 23.2 "Clock Output Configuration and Activation Registers" 23.3 "Operation of the Clock Output Function"...
Page 638: Overview Of The Clock Output Function
CHAPTER 23 CLOCK OUTPUT FUNCTION MB96300 Super Series Hardware Manual 23.1 Overview of the Clock Output Function The clock output function can be used to output up to two internal clocks to the four clock output pins CKOT0/CKOTX0 and CKOT1/CKOTX1 (one non-inverted and one inverted output pin for each clock).
Page 639: Clock Output Configuration And Activation Registers
MB96300 Super Series Hardware Manual CHAPTER 23 CLOCK OUTPUT FUNCTION 23.2 Clock Output Configuration and Activation Registers The Clock Output Conﬁguration Register (COCR) selects the output clock and controls the clock divider. The COCR0 register controls the CKOT0/CKOTX0 output clock and the COCR1 register controls the CKOT1/CKOTX1 output clock.
Page 640 CHAPTER 23 CLOCK OUTPUT FUNCTION MB96300 Super Series Hardware Manual ■ Clock Output Conﬁguration Register (COCR) Figure 23.2-1 Clock Output Conﬁguration Register (COCR) 15/7 14/6 13/5 12/4 11/3 10/2 Address: Initial value COCR1: 000417 X 0 0 0 0 0 0 0 DIV2 DIV1 DIV0...
Page 641 MB96300 Super Series Hardware Manual CHAPTER 23 CLOCK OUTPUT FUNCTION Table 23.2-1 Function Description of Each Bit of the Clock Output Conﬁguration Register (COCR0/1) Bit name Function bit 0 - SEL0 to SEL3: • These bits select which clock is output to the CKOT0/1 pins according to the bit 3 / Clock Select bits following table:...
Page 642 CHAPTER 23 CLOCK OUTPUT FUNCTION MB96300 Super Series Hardware Manual ■ Clock Output Activation Register (COAR) Figure 23.2-2 Clock Output Activation Register (COAR) Address: Initial value COAR: 000415 0 0 0 0 0 0 0 0 RUNM1 RUNC1 CKOXE1 CKOE1 RUNM0 RUNC0 CKOXE0...
Page 643 MB96300 Super Series Hardware Manual CHAPTER 23 CLOCK OUTPUT FUNCTION Table 23.2-2 Function Description of Each Bit of the Clock Output Activation Register (COAR) (1/2) Bit name Function bit 8 CKOE0 • This bit controls the resource output enable of the direct clock output function. Clock Output •...
Page 644 CHAPTER 23 CLOCK OUTPUT FUNCTION MB96300 Super Series Hardware Manual Table 23.2-2 Function Description of Each Bit of the Clock Output Activation Register (COAR) (2/2) Bit name Function bit 14 RUNC1 • This bit controls the synchronous start/stop function of the CKOT1/CKOTX1 clock Clock Run Control outputs.
Page 645: Operation Of The Clock Output Function
MB96300 Super Series Hardware Manual CHAPTER 23 CLOCK OUTPUT FUNCTION 23.3 Operation of the Clock Output Function The clock output function can be used to output two independent clocks at the CKOT0/ CKOTX0 and CKOT1/CKOTX1 output pins. The clocks can be activated and deactivated synchronously.
Page 646 CHAPTER 23 CLOCK OUTPUT FUNCTION MB96300 Super Series Hardware Manual...
Page 647: Real Time Clock
CHAPTER 24 REAL TIME CLOCK This chapter explains the functions and operations of the Real Time Clock. 24.1 "Outline of Real Time Clock" 24.2 "Real Time Clock Registers" 24.3 "Operation" 24.4 "Cautions"...
Page 648: Outline Of Real Time Clock
CHAPTER 24 REAL TIME CLOCK MB96300 Super Series Hardware Manual 24.1 Outline of Real Time Clock The Real Time Clock consists of the Timer Control register, Sub-second register, Second/ Minute/Hour registers, 1/2 clock divider, 21-bit prescaler and Second/Minute/Hour counters. The oscillation frequency of the MCU is assumed to be at 4MHz or 5MHz for the aimed operation of the Real Timer Clock.
Page 649 MB96300 Super Series Hardware Manual CHAPTER 24 REAL TIME CLOCK ■ Block diagram of Real Time Clock Figure 24.1-1 Block diagram of Real Time Clock Sub-Second Registers Reload Counter 21 Bit Oscillation Second Minute Hour Down Counter clock Update Second Minute Hour ■...
Page 650: Real Time Clock Registers
CHAPTER 24 REAL TIME CLOCK MB96300 Super Series Hardware Manual 24.2 Real Time Clock Registers The Real Time Clock has the following seven registers: • Timer Control Register (WTCR) • Timer Control Extended Register (WTCER) • Clock Select Register (WTCKSR) •...
Page 651 MB96300 Super Series Hardware Manual CHAPTER 24 REAL TIME CLOCK ■ Real Time Clock registers Figure 24.2-1 Real Time Clock registers Timer control register INTE3 INT3 INTE2 INT2 INTE1 INT1 INTE0 INT0 UPDT OE WTCR Reserved Reserved Reserved R/W R/W R/W R/W Initial value: Timer control extended register...
Page 652 CHAPTER 24 REAL TIME CLOCK MB96300 Super Series Hardware Manual 24.2.1 Timer Control Registers The timer control registers start and stop the Real Time Clock, control interrupts, and set the external output pins. ■ Timer Control Register (WTCR) Figure 24.2-2 Timer Control Register (WTCR) Timer Control Register INTE3 INT3 INTE2 INT2 INTE1 INT1 INTE0 INT0 UPDT OE...
Page 653 MB96300 Super Series Hardware Manual CHAPTER 24 REAL TIME CLOCK bit11: Enable interrupt requests at 1-minute intervals When the minute counter overflows, this flag is set to “1”. INTE1 Operation No interrupt requests Generate interrupt requests at 1-minute intervals. bit10: 1-minute interrupt request flag INT1 Operation Read...
Page 654 CHAPTER 24 REAL TIME CLOCK MB96300 Super Series Hardware Manual bit1: Output Enable Status/Operation The WOT external pin can be used as a general purpose I/O or for another peripheral block. The WOT external pin serves as the output for the 21-bit down counter. bit0: Start Operation The Real-time Clock module stops to operate, and the 21 bit down counter and the hour/...
Page 655 MB96300 Super Series Hardware Manual CHAPTER 24 REAL TIME CLOCK bit1: Enable interrupt requests at half-second (500ms) intervals When the 21-bit counter overflows, this flag is set to “1”. INTE4 Operation No interrupt requests Generate interrupt requests at half-second (500 ms) intervals. bit0: half-second (500ms) interrupt request flag INT4 Status...
Page 656 CHAPTER 24 REAL TIME CLOCK MB96300 Super Series Hardware Manual 24.2.2 Sub-Second Register The Sub-Second Register stores a reload value for the 21-bit counter that divides the oscillation clock. The reload value is usually set so that the 21-bit counter will output exactly within a half second cycle.
Page 657 MB96300 Super Series Hardware Manual CHAPTER 24 REAL TIME CLOCK 24.2.3 Second/Minute/Hour Registers (WTSR, WTMR, WTHR) The Second/Minute/Hour registers store the time information. It is a binary representation of the second, minute and hour. Reading these registers simply returns the counter values. These registers are write accessible however, the written data is loaded in the counters after the UPDT bit is set to "1".
Page 658 CHAPTER 24 REAL TIME CLOCK MB96300 Super Series Hardware Manual registers. Since there are three byte-registers, make sure the obtained values from the registers are consistent. For example, obtained value of "1 hour, 59 minute, 59 second" could be "1 hour, 59 minute, 59 second" or "1 hour, 0 minute, 0 second"...
Page 659: Operation
MB96300 Super Series Hardware Manual CHAPTER 24 REAL TIME CLOCK 24.3 Operation This section describes the Real Time Clock operation.
Page 660 CHAPTER 24 REAL TIME CLOCK MB96300 Super Series Hardware Manual ■ Real Time Clock operation Figure 24.3-1 Real Time Clock operation (19) (19) reload value 21 bit down counter 0000 h 0000 h (20) (20) Clear (10) (10) Half Second Second (10) (10)
Page 661 MB96300 Super Series Hardware Manual CHAPTER 24 REAL TIME CLOCK (4) The software writes the appropriate values to the sub-second registers, WTBRL0/WTBRH0/WTBR1. (5) The interrupt request bits (INT0, INT1, INT2, INT3 and INT4) are initialized, and the interrupt request enable bits (INTE0, INTE1, INTE2, INT3 and INTE4) are set to “interrupts enabled”. (6) The start bit (ST) is set to “1”.
Page 662: Cautions
CHAPTER 24 REAL TIME CLOCK MB96300 Super Series Hardware Manual 24.4 Cautions This section describes the cautions to be considered while using the Real Time Clock ■ Cautions • Setting the interrupt request flags (WTCR:INT0, WTCR:INT1, WTCR:INT2, WTCR:INT4 and WTCER:INT4) to “1” due to overflow, and writing “0” to that bit have occurred at the same time, the flag is set to “1”...
Page 663 MB96300 Super Series Hardware Manual CHAPTER 24 REAL TIME CLOCK used to read time (HH/MM/SS). • In order for the Real Time Clock module to function properly, the frequency of the subclock (CLKSC) or the RC-clock (CLKRC) must be much lower than that of the peripheral clock (CLKP1). If not, correct values cannot be read from WTHR/WTMR/WTSR.
Page 664 CHAPTER 24 REAL TIME CLOCK MB96300 Super Series Hardware Manual...
Page 665: Clock Calibration Unit
CHAPTER 25 CLOCK CALIBRATION UNIT This chapter explains the functions and operation of the Clock Calibration Unit 25.1 "Outline" 25.2 "Register Description" 25.3 "Application Notes"...
Page 666: Outline
CHAPTER 25 CLOCK CALIBRATION UNIT MB96300 Super Series Hardware Manual 25.1 Outline The Clock Calibration Module provides possibilities to calibrate the sub oscillator clock or the RC oscillator clock with respect to the main oscillator clock. This chapter gives an overview of the Clock Calibration Unit, describes the registers and provides some application notes.
Page 667 MB96300 Super Series Hardware Manual CHAPTER 25 CLOCK CALIBRATION UNIT ■ Block Diagram Figure 25.1-1 Block Diagram CLKMCG = CLKMC | ~STRT | (READY & ~RUNS); CLKMCG CLKMC gate STRT READY RUNS CLKSC gate CLKRC STRT CLKPG CLKP1 gate Duration Timer (CLKSC/CLKRC) TRD Calibration Timer (CLKMC) CLKSRCG RSLEEPB...
Page 668 CHAPTER 25 CLOCK CALIBRATION UNIT MB96300 Super Series Hardware Manual ■ Timing Figure 25.1-2 Timing of the measurement process CLKSC (32kHz) STRT (CLKP1) STRTS (32 kHz) (32 kHz) RUNS (4 MHz) 32 kHz counter (16 bit) CUTD CUTD-1 CUTD 4 MHz counter (24 bit) old CUTR new CUTR READY...
Page 669: Register Description
MB96300 Super Series Hardware Manual CHAPTER 25 CLOCK CALIBRATION UNIT 25.2 Register Description This section lists the registers of the calibration unit and describes the function of each register in detail. ■ Clock Calibration Unit registers Register CUCR [R/W] CUTD [R/W] ---0--00 -------- 00000000 10000000 CUTR1 [R]...
Page 670 CHAPTER 25 CLOCK CALIBRATION UNIT MB96300 Super Series Hardware Manual new calibration. Otherwise the end of the calibration process is only signalized by the STRT bit (the INT flag stays 1 also during calibration). BIT[2]: CKSEL - Input clock select use CLKSC (default) use CLKRC The RC-clock frequency depends on the setting of CKSCR:RCFS bit (RC-Oscillator frequency select).
Page 671 MB96300 Super Series Hardware Manual CHAPTER 25 CLOCK CALIBRATION UNIT If CUTD is initialized with 0x0000 an underflow will occur and the measurement will take (0xFFFF + 1) * CLKSC/CLKRC In order to achieve a measurement duration of 1 second at a 32kHz oscillation, the CUTD register has to be loaded with 0x8000 = 32768 dec.
Page 672 CHAPTER 25 CLOCK CALIBRATION UNIT MB96300 Super Series Hardware Manual After INT has changed from 0 to 1 / STRT has changed from 1 to 0, the value of CUTR is valid. ⇐ Bit no. Calibration Timer Register2 low byte CUTR2L TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Read/write ⇒...
Page 673: Application Notes
MB96300 Super Series Hardware Manual CHAPTER 25 CLOCK CALIBRATION UNIT 25.3 Application Notes This section lists application notes concerning accuracy of the calibration, power dissipation and measurement duration. ■ 32 kHz The setting of the Duration Timer Data Register can be calculated in the following way. If the duration of 1 second is desired for the calibration, 8000Hex = 32768Dec should be set in the Duration Timer Data Register and it represents 32,768 pulses of the 32.768kHz oscillation clock.
Page 674 CHAPTER 25 CLOCK CALIBRATION UNIT MB96300 Super Series Hardware Manual way: 0.25us (Clock cycle time) / 1 second (duration)=0.25 ppm. In general: Accuracy = (Clock cycle time of Calibration Timer) / (Duration of calibration) ■ Power Dissipation Suppose the current consumption I in run mode is 20 times the consumption I in RTC mode (I 20 x I...
Page 675: Lcd Controller/Driver
CHAPTER 26 LCD CONTROLLER/DRIVER This chapter describes the functions and operations of the LCD Controller/Driver. 26.1 "Configuration of LCD Controller/Driver" 26.2 "LCD Controller Registers" 26.3 "LCD Enable Registers (LCDER, LCDVER)" 26.4 "LCD Controller/Driver Display RAM" 26.5 "Operation of LCD Controller/Driver" 26.6 "Cautions"...
Page 676: Configuration Of Lcd Controller/Driver
CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual 26.1 Configuration of LCD Controller/Driver The LCD Controller/Driver consists of the blocks listed below. Functionally, it consists of the controller section, which generates a segment signal and common signal based on display RAM data, and the driver section, which drives the LCD.
Page 677 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER ■ Conﬁguration Diagram Figure 26.1-1 Conﬁguration Diagram LCD Controller COMEN0 LCDCMR: bit 0...3 LCR: bit7 COMEN3 FP1,0 FP1,0 COM output disabled (other peripheral LCR0: bit1,0 Peripheral clock Sub/RC clock function or general purpose input/output) MS1,0 LCR: bit3,2 COM output enabled CLKP...
Page 678 CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual ■ Register List Figure 26.1-2 Register List bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 CSS LCEN VSEL LECR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 CKSEL LCDCMR bit7 bit6 bit5 bit4 bit3...
Page 679 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER 26.1.1 LCD Controller/Driver’s divide resistors The LCD drive voltage is generated either by external voltage divide resistors or internal voltage divide resistors. The brightness can be controlled by connecting a variable resister between the V V3 pins.
Page 680 CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual Figure 26.1-4 Using internal divide resistors and an external resistor for dimming: V[3]=1 LCDVER:V[0:3] V3/SEGa V[3]=1 SEGa V2/SEGb V[2]=0 SEGb V[1]=0 V1/SEGc SEGc V[0]=0 V0/SEGd SEGd LCR:VSEL = 1 LCR:MS[1:0] <> 00 N-ch LCD operation enabled LCDER:SEG[a:d]...
Page 681 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER deactivating LCD controller can be shut off by connecting external divide resistors to the V0 pin on the Vss side. To shut off the current, use the display mode select bit (LCR:MS[1:0] = “00”).
Page 682: Lcd Controller Registers
CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual 26.2 LCD Controller Registers This section describes the registers related to the conﬁguration of LCD Controller/Driver. ■ LCD Control register (LCR) Figure 26.2-1 "Bit configuration of LCD Control Register (LCR)" shows the bit configuration of the registers related to the LCD Controller/Driver.
Page 683 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER of the corresponding LCDER register bits is ignored. When internal divide resistors are selected the external voltage pins can not be connected. The setting of LCDVER:V[0:3] is ignored bit4 BK: Select blanking Enable LCD display Disable (blank) LCD display bit3-2: Select a display mode...
Page 684 CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual Figure 26.2-2 Bit conﬁguration of LCD Common Pin Switching register (LCDCMR) LCDCMR (LCD Common Pin Switching Register) initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0XXX0000 DTCH COMEN3 COMEN2 COMEN1 COMEN0 (R/W) (R/W) (R/W) (R/W) (R/W) R/W read and write permission...
Page 685 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER bit0 CKSEL: Clock selection bit use Sub clock CLKSC use RC-Clock CLKRC If Sub clock or RC-clock shall be used as LCD clock, the LCR:CSS bit must be set. Devices with sub clock: If the Clock setting shall be changed, the clock which is currently selected must be active for at lease 3 cycles if it was enabled at any time before.
Page 686: Lcd Enable Registers (Lcder, Lcdver)
CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual 26.3 LCD Enable Registers (LCDER, LCDVER) This section describes the LCD enable registers...
Page 687 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER ■ LCD Segment Enable Registers LCDER and Voltage Line Enable Register LCDVER Figure 26.3-1 Bit conﬁguration of LCD Segment Enable and Reference Voltage Enable registers LCDER1/0 LCD SEG enable register 1/0 Initial value 00000000 00000000 SEG13 SEG12...
Page 688 CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual Remark: When an internal divide resistor x is activated by LCDVER:Vx = 1, the setting in the LCD enable register LCDERy:SEGz of the segment sharing the pin of Vx is ignored and the segment is disabled.
Page 689: Lcd Controller/Driver Display Ram
MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER 26.4 LCD Controller/Driver Display RAM The display RAM is a 36 x 8 bit display memory area used to generate a segment output signal. ■ Memory area (VRAM) for setting display data •...
Page 690: Operation Of Lcd Controller/Driver
CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual 26.5 Operation of LCD Controller/Driver This chapter describes step by step how to use the LCD Controller/Driver ■ LCD Controller/Driver (LCDC) Operation • Set values to the display data memory (VRAM) in advance. •...
Page 691 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER Figure 26.5-1 Output Waveform (1/2 duty cycle) COM0 output COM1 output COM2 output COM3 output SEG 2n output SEG 2n+1 output LCD cell corresponding to SEG 2n, COM0 output LCD cell corresponding to SEG 2n, COM1 output LCD cell corresponding to SEG 2n+1, COM0 output LCD cell corresponding to SEG 2n+1, COM1 output...
Page 692 CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual ■ Output waveform during LCD controller/driver operation (1/3 duty cycle) In the 1/3 duty cycle output mode, COM0, COM1 and COM2 outputs are used for LCD display. COM3 output is not used Example of 1/3 Bias Output Waveform LCD cells with the maximum voltage difference between common and segment outputs are lit.
Page 693 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER Figure 26.5-2 Output Waveform (1/3 duty cycle) COM0 output COM1 output COM2 output COM3 output SEG 2n output SEG 2n+1 output LCD cell corresponding to SEG 2n, COM0 output LCD cell corresponding to SEG 2n, COM1 output LCD cell corresponding to SEG 2n, COM2 output LCD cell corresponding to SEG 2n+1, COM0 output LCD cell corresponding to SEG 2n+1, COM1 output...
Page 694 CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual ■ Output waveform during LCD controller/driver operation (1/4 duty cycle) In the 1/4 duty cycle output mode, COM0, COM1, COM2, and COM3 outputs are all used for LCD display Example of 1/3 Bias Output Waveform LCD cells with the maximum voltage difference between common and segment outputs are lit.
Page 695 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER Figure 26.5-3 Output Waveform (1/4 duty cycle) CO M 0 o ut p u t CO M 1 o ut p u t CO M 2 o ut p u t CO M 3 o u tp u t S E G 2n o ut p ut S E G 2 n +1 ou t p ut...
Page 696: Cautions
CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual 26.6 Cautions Cautions covering the usage of LCD controller/driver • Switching the frame period generation clocks: - Frame period generation clocks (LCR:CSS) can be switched even during LCD display. - However, switching may cause some screen flicker. To avoid such flicker, be sure to set the blanking select bit (LCR:BK) to “1”...
Page 697 MB96300 Super Series Hardware Manual CHAPTER 26 LCD CONTROLLER/DRIVER Table 26.6-2 LCD operation in MCU Timer modes Operation for MS[1:0] ≠ "00" LCEN CKSEL clock clock CLKSC CLKRC running running LCD display is deactivated. Do not use this setting! DC voltage is applied to the LCD panel.
Page 698 CHAPTER 26 LCD CONTROLLER/DRIVER MB96300 Super Series Hardware Manual...
Page 699: Stepper Motor Controller
CHAPTER 27 STEPPER MOTOR CONTROLLER This chapter explains the functions and operations of the stepper motor controller. 27.1 "Outline of Stepper Motor Controller" 27.2 "Stepper Motor Controller Registers" 27.3 "PWM Control register (PWCn)" 27.4 "PWM Extended Control register (PWECn)" 27.5 "PWM1 and PWM2 Compare Registers (PWC1n, PWC2n)" 27.6 "PWM1 and PWM2 Selection registers (PWS1n, PWS2n)"...
Page 700: Outline Of Stepper Motor Controller
CHAPTER 27 STEPPER MOTOR CONTROLLER MB96300 Super Series Hardware Manual 27.1 Outline of Stepper Motor Controller The Stepper Motor Controller consists of PWM pulse generators, motor drivers and selector logic circuits. ■ Outline The four motor drivers have a high-output driving capability, and two motor coils can be connected directly to four pins.
Page 701: Stepper Motor Controller Registers
MB96300 Super Series Hardware Manual CHAPTER 27 STEPPER MOTOR CONTROLLER 27.2 Stepper Motor Controller Registers There are seven registers for the Stepper Motor Controller: PWM Control Register PWM Extended Control Register PWM1 Compare Register PWM2 Compare Register PWM1 Selection Register PWM2 Selection Register...
Page 702 CHAPTER 27 STEPPER MOTOR CONTROLLER MB96300 Super Series Hardware Manual ■ Stepper Motor Controller registers Figure 27.2-1 Overview of the Stepper Motor Controller registers PWM Control register (PWCx) Initial value: 0 0 0 0 0 0 - - R/W R/W R/W R/W R/W Initial value: x x x x x x 0 0 R/W R/W...
Page 703: Pwm Control Register (Pwcn)
MB96300 Super Series Hardware Manual CHAPTER 27 STEPPER MOTOR CONTROLLER 27.3 PWM Control register (PWCn) The PWM Control register (PWCn) starts and stops the Stepper Motor Controller, controls interrupts, and sets the external output pins. ■ PWM Control register (PWCn) Figure 27.3-1 PWM Control Register (PWCn) PWM Control register (PWCx) Initial value:...
Page 704 CHAPTER 27 STEPPER MOTOR CONTROLLER MB96300 Super Series Hardware Manual [bit 2] SC: 8/10 bits switching bit When "1" is set to the SC bit, the PWM pulse generator operates at 10 bits. When "0" is set to the SC bit, the PWM pulse generator operates at 8 bits.
Page 705: Pwm Extended Control Register (Pwecn)
MB96300 Super Series Hardware Manual CHAPTER 27 STEPPER MOTOR CONTROLLER 27.4 PWM Extended Control register (PWECn) The PWM Extended Control register (PWECn) enables the PWM output. ■ PWM Extended Control register (PWECn) Figure 27.4-1 PWM Extended Control register (PWECn) PWM Extended Control register (PWECx) Initial value: x x x x x x 0 0 R/W R/W...
Page 706: Pwm1 And Pwm2 Compare Registers (Pwc1N, Pwc2N)
CHAPTER 27 STEPPER MOTOR CONTROLLER MB96300 Super Series Hardware Manual 27.5 PWM1 and PWM2 Compare Registers (PWC1n, PWC2n) The value of the two 8 (10) bits compare register of PWM1 and PWM2 (PWC1n, PWC2n) determine the width of the PWM pulse. The stored "00 (000 )"...
Page 707 MB96300 Super Series Hardware Manual CHAPTER 27 STEPPER MOTOR CONTROLLER Figure 27.5-2 Relationship between the Compare Register setting value and PWM pulse width Register value One PWM cycle 256 (1024) input cycles (200 128 (512) input cycle (3FF 255 (1023) input cycle...
Page 708 CHAPTER 27 STEPPER MOTOR CONTROLLER MB96300 Super Series Hardware Manual Figure 27.5-3 Load timing of PWM compare register value [Automatic clear of BS bit] Load the values of the registers and PWM 1 cycle reflected in the output signal. PWM pulse PWM pulse generator 3FFh 000h...
Page 709: Pwm1 And Pwm2 Selection Registers (Pws1N, Pws2N)
MB96300 Super Series Hardware Manual CHAPTER 27 STEPPER MOTOR CONTROLLER 27.6 PWM1 and PWM2 Selection registers (PWS1n, PWS2n) The PWM1 and PWM2 Selection registers (PWS1n, PWS2n) determine whether to set the output of the external pin of the Stepper Motor Controller to "0", "1", PWM pulse or high impedance.
Page 710 CHAPTER 27 STEPPER MOTOR CONTROLLER MB96300 Super Series Hardware Manual [bit 6] BS: Rewrite bit The BS bit makes the setting for the PWM output match another setting. Until the BS bit is set, changes made to the two Compare registers and two Selection registers are not reflected in the output signal. When "1"...
Page 711: Operation Of Stepper Motor Controller
MB96300 Super Series Hardware Manual CHAPTER 27 STEPPER MOTOR CONTROLLER 27.7 Operation of Stepper Motor Controller Description of the Stepper Motor Controller operation. ■ Setting Operation of Stepper Motor Controller Figure 27.7-1 Setting of Stepper Motor Controller PWM1 H width (compare value) is set. PWM2 H width (compare value) is set.
Page 712 CHAPTER 27 STEPPER MOTOR CONTROLLER MB96300 Super Series Hardware Manual ■ Operation of PWM-pulse generator When the counter is started (PWC: CE = 1), the counter starts incrementing from 00 on the selected count clock rising. The PWM output pulse wave remains "H" until the value of the counter matches the value set to PWM compare register, and then changes to and remains "L"...
Page 713 MB96300 Super Series Hardware Manual CHAPTER 27 STEPPER MOTOR CONTROLLER ■ Selection of motor drive signals Motor drive signals that are output to each pin related to the Stepper Motor Controller can be selected among four types of signals for each pin by setting the PWM selection register. Table 27.7-1 "Motor drive signals selection and PWM Selection registers 1 and 2 setting"...
Page 714: Notes On Using Stepper Motor Controller
CHAPTER 27 STEPPER MOTOR CONTROLLER MB96300 Super Series Hardware Manual 27.8 Notes on Using Stepper Motor Controller The cautions when using the Stepper Motor Controller are described below. ■ Cautions when Changing the PWM Setting PWM Compare register 1 (PWC1x), PWM Compare register 2 (PWC2x), PWM Selection register 1 (PWS1x), and PWM Selection register 2 (PWS2x) can always be accessed.
Page 715: Sound Generator
CHAPTER 28 SOUND GENERATOR This chapter explains the functions and operations of the sound generator. 28.1 "Outline of Sound Generator" 28.2 "Sound Generator Registers"...
Page 716: Outline Of Sound Generator
CHAPTER 28 SOUND GENERATOR MB96300 Super Series Hardware Manual 28.1 Outline of Sound Generator The Sound Generator consists of the Sound Control Register, Frequency Data Register, Amplitude Data Register, Decrement Grade Register, Tone Count Register, PWM Pulse Generator, Frequency Counter, Decrement Counter and Tone Pulse Counter. ■...
Page 717: Sound Generator Registers
MB96300 Super Series Hardware Manual CHAPTER 28 SOUND GENERATOR 28.2 Sound Generator Registers The Sound Generator has the following registers: • Sound Control Register (SGCRn) • Frequency Data Register (SGFRn) • Amplitude Data Register (SGARn) • Decrement Grade Register (SGDRn) •...
Page 718 CHAPTER 28 SOUND GENERATOR MB96300 Super Series Hardware Manual 28.2.1 Sound Generator Control Register (SGCRn) The Sound Control Register (SGCR) controls the operation status of the Sound Generator by controlling interrupts and setting the external output pins. ■ Sound Generator Control Register (SGCRHn) Figure 28.2-2 Conﬁguration of the Sound Generator Control Register (SGCRHn) SGCRHn Initial value...
Page 719 MB96300 Super Series Hardware Manual CHAPTER 28 SOUND GENERATOR Table 28.2-1 Function of each bit of the Sound Generator Control Register (SGCRHn) Name Function bit 10 FSEL: PWM This bit switches the count value of the PWM counter between 256 and 384. Stop counter switching operation when switching the count value.
Page 720 CHAPTER 28 SOUND GENERATOR MB96300 Super Series Hardware Manual ■ Sound Generator Control Register (SGCRLn) Figure 28.2-3 Conﬁguration of the Sound Generator Control Register (SGCRLn) SGCRL TONE OE2 OE1 INTE Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W bit 0...
Page 721 MB96300 Super Series Hardware Manual CHAPTER 28 SOUND GENERATOR ■ Sound Generator Control Register (SGCRLn) contents Table 28.2-2 Function of each bit of the Sound Generator Control Register (SGCRLn) Name Function bit7, 6 S1, S0: These bits specify the clock input signal for the Sound Generator. Operation clock select bits Clock input...
Page 722 CHAPTER 28 SOUND GENERATOR MB96300 Super Series Hardware Manual 28.2.2 Amplitude Data Register (SGARn) The Amplitude Data Register (SGARn) stores the reload value for the PWM pulse generator. The register value represents the amplitude of the sound. The register value is reloaded into the PWM pulse generator at falling edge of tone signal.
Page 723 MB96300 Super Series Hardware Manual CHAPTER 28 SOUND GENERATOR Figure 28.2-5 Relationship between SGARn value and PWM Pulse (FSEL=0) One PWM cycle 384 input clock cycles Register value One input clock cycle 3 input clock cycles 381 input clock cycles 383 input clock cycles 384 input clock cycles Note:...
Page 724 CHAPTER 28 SOUND GENERATOR MB96300 Super Series Hardware Manual 28.2.3 Frequency Data Register (SGFRn) The Frequency Data Register (SGFRn) stores the reload value for the Frequency counter. The stored value represents the frequency of the sound (or the tone signal from the toggle ﬂip-ﬂop).
Page 725 MB96300 Super Series Hardware Manual CHAPTER 28 SOUND GENERATOR 28.2.4 Tone Count Register (SGTRn) The Tone Count Register (SGTRn) stores the reload value for the Tone Pulse counter. The Tone Pulse counter accumulates the number of tone pulses (or number of decrement operations) and when it reaches the reload value it sets the INT bit, reducing the frequency of interrupts by the number of programmed tones.
Page 726 CHAPTER 28 SOUND GENERATOR MB96300 Super Series Hardware Manual 28.2.5 Decrement Grade Register (SGDRn) The Decrement Grade Register (SGDRn) stores the reload value for the Decrement counter. It automatically decrements the reload value of the Amplitude Data register to reduce the frequency of interrupts. The register value is reloaded into the counter at Decrement counter underﬂow and falling edge of tone signal.
Page 727: Usb Function
CHAPTER 29 USB FUNCTION This chapter describes the functions and operations of the USB Function. 29.1 USB Function Overview 29.2 USB Function Block Diagram 29.3 USB Function Registers Description 29.4 USB Function Operation...
Page 728: Usb Function Overview
CHAPTER 29 USB FUNCTION 29.1 USB Function Overview The USB function is an interface that supports the USB (Universal Serial Bus) 2.0 communication protocol. Only FULL speed transfer (12 Mbps) is supported. ■ Features of USB Function • FULL speed (12 Mbps) is supported. (conform to USB 2.0 Full Speed) •...
Page 729: Usb Function Block Diagram
CHAPTER 29 USB FUNCTION 29.2 USB Function Block Diagram Description of the USB Function. ■ Block Diagram of USB Function Figure 29.2-1 Block Diagram of USB Function Endpoint 0 In Buffer Internal Data bus Endpoint 0 Out Buffer Endpoint 1 Interrupt Buffer Endpoint 2...
Page 730: Usb Function Registers Description
CHAPTER 29 USB FUNCTION 29.3 USB Function Registers Description Description of the USB function registers. ■ Register List of the USB function Table 29.3-1 Register List UDCC (R/W) EP0C (R/W) EP1C (R/W) EP2C (R/W) EP3C (R/W) EP4C (R/W) EP5C (R/W) TMSP UDCIE UDCS...
Page 731 CHAPTER 29 USB FUNCTION Table 29.3-2 Registers of USB function RESUM HCON USTP Reserved Reserved RFBK UDC control register (UDCC) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PKS0 EP0 control register (EP0C) Reserved Reserved STAL Reserved PKS 1 EP1 control register (EP1C) EPEN TYPE...
Page 732 CHAPTER 29 USB FUNCTION Table 29.3-2 Registers of USB function SUSP BRST WKUP SETP CONF UDC status register (UDCS) Reserved Reserved SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE UDC interruption permission register (UDCIE) EP0I status register (EP0IS) BFINI DRQIIE DRQI Reserved SIZE EP0O status register (EP0OS) BFINI...
Page 733 CHAPTER 29 USB FUNCTION Table 29.3-2 Registers of USB function BFDT EP0 data register (EP6BT) BFDT BFDT EP 1 data register (EP1DT) BFDT BFDT EP 2 data register (EP2DT) BFDT BFDT EP 3 data register (EP3DT) BFDT BFDT EP 4 data register (EP4DT) BFDT BFDT EP 5 data register (EP5DT)
Page 734 CHAPTER 29 USB FUNCTION 29.3.1 UDC Control Register (UDCC) UDC control register (UDCC) controls the UDC core circuit.
Page 735 CHAPTER 29 USB FUNCTION ■ UDC Control Register (UDCC) Figure 29.3-1 UDC Control Register (UDCC) Initial Value: 10100000 RESUM HCON USTP Reserved Reserved RFBK bit0 Power supply control bit Bus powered device Self powered device bit1 Data toggle mode bit (Rate feedback mode) Data toggle mode disable Data toggle mode enable bit2 &...
Page 736 CHAPTER 29 USB FUNCTION The following describes the function of each bit in the UDC control register (UDCC). Bit names Function Bit7 • Reset the whole USB function only. • Apply a reset to the USB Function with the RST bit when connecting a cable to the HOST PC.
Page 737 CHAPTER 29 USB FUNCTION To deselect the stop mode, reset SUSP and USTP bits to "0".
Page 738 CHAPTER 29 USB FUNCTION 29.3.2 EP0 Control Register (EP0C) EP0 control register (EP0C) controls concerning endpoint 0. ■ EP0 Control Register (EP0C) Figure 29.3-2 EP0 Control Register (EP0C) Initial Value: 10100000 Reserved PKS0 PKS0 PKS0 PKS0 PKS0 PKS0 PKS0 bit0 to 6 PKS0 PKS0 bits Initial value...
Page 739 CHAPTER 29 USB FUNCTION Bit names Function Bit11-10 Reserved • Do not use Bit9 STAL • Setting the STAL bit can put EndPoint0 in STALL status (STALL response). • The STALL response is continued to the host while the STAL bit is set.
Page 740 CHAPTER 29 USB FUNCTION 29.3.3 EP1 to EP5 Control Register (EP1C to EP5C) EP1 to EP5 control register (EP1C to EP5C) are used to control the operation of endpoints 1 to 5.
Page 741 CHAPTER 29 USB FUNCTION ■ EP1 to EP5 Control Register (EP1C to EP5C) Figure 29.3-3 EP1 Control Register (EP1C) Initial Value: 00000000 PKS1 PKS1 PKS1 PKS1 PKS1 PKS1 PKS1 PKS1 bit0 to 6 PKS1 PKS1 bits Initial value value Packet size value Initial Value: 01100001 EPEN...
Page 742 CHAPTER 29 USB FUNCTION Figure 29.3-4 EP2 to EP5 Control register (EP2C to EP5C) Initial Value: n= 2..5 01000000 Reserved PKSn PKSn PKSn PKSn PKSn PKSn PKSn bit0 to 6 PKSn PKSn bits Initial value value Packet size value bit7 Reserved Reserved Always write "0"...
Page 743 CHAPTER 29 USB FUNCTION Note: EP1 to EP5 control registers (EP1C to EP5C) must always be set, except DMAE, NULE, and STAL bits, when both UDCC:RST bit and EP[0..5]S:BFINI are 1. Those registers must not be overwrite while the USB is operating. Below a description of the function of each bit in the EP1 to EP5 control register (EP1C to EP5C).
Page 744 CHAPTER 29 USB FUNCTION Bit names Function Bit0-8 • This bit specifies the maximum number transfer per packet. The following table shows the maximum packet number to be transfered that can be specified for each endpoint: Endpoint Max number of transfer Possible values 256 bytes 001h to 100h...
Page 745 CHAPTER 29 USB FUNCTION 29.3.4 Time Stamp Register (TMSP) The time stamp register (TMSP) displays a frame number when an SOF packet is received. ■ Time Stamp register (TMSP) Figure 29.3-5 Time Stamp register (TMSP) Initial Value: 00000000 TMSP TMSP TMSP TMSP TMSP...
Page 746 CHAPTER 29 USB FUNCTION 29.3.5 UDC Status register (UDCS) The UDC status register (UDCS) informs on USB communication status. Each bit, except SETP, is a ﬂag triggering (if enabled) interrupts to the CPU. ■ UDC Status register (UDCS) Figure 29.3-6 UDC Status register Initial Value: xx000000 Undef...
Page 747 CHAPTER 29 USB FUNCTION Bit names Function Bit5 SUSP • This flag indicates that the USB function is in suspend mode. SUSP triggers an interrupt. • Writing "1" is ignored. • Clear by writing "0". "1" is read at the read modification write. Bit4 •...
Page 748 CHAPTER 29 USB FUNCTION 29.3.6 UDC Interruption Enable Register (UDCIE) The UDC Interrupt Enable register (UDCIE) is a register that enables each ﬂag in the UDC status register to trigger an interrupt except for CONFN. ■ UDC Interrupt Enable register (UDCIE) Figure 29.3-7 UDC Interrupt Enable Register (UDCIE) Initial Value: 00000000...
Page 749 CHAPTER 29 USB FUNCTION Bit names Function Bit15-14 Reserved • Do not use Bit13 SUSPIE • enable interrupt caused by SUSP flag. Bit12 SOFIE • enable interrupt caused by SOF flag. Bit11 BRSTIE • enable interrupt caused by BRST flag. Bit10 WKUPIE •...
Page 750 CHAPTER 29 USB FUNCTION 29.3.7 EP0I Status Register (EP0IS) The EP0I status register (EP0IS) displays status of IN direction transfer of the endpoint0. ■ EP0I Status Register (EP0IS) Figure 29.3-8 EP0I Status register (EP0IS) Initial Value: xxxxxxxx Undef Undef Undef Undef Undef Undef...
Page 751 CHAPTER 29 USB FUNCTION Bit names Function Bit15 BIFNI • This bit Initializes the transmission buffer. • The BFINI bit is automatically set when the RST flag in the UDC control register (UDCC) is set to 0. • When the reset operation has been performed with the RST bit, clear the RST bit before clearing the BFINI bit.
Page 752 CHAPTER 29 USB FUNCTION 29.3.8 EP0O Status Register (EP0OS) The EP0O status register (EP0OS) displays status of OUT direction transfer of the endpoint0.
Page 753 CHAPTER 29 USB FUNCTION ■ EP0O Status Register (EP0OS) Figure 29.3-9 EP0O Status Register (EP0OS) Initial Value: 0xxxxxxx Reserved SIZE SIZE SIZE SIZE SIZE SIZE SIZE BIFNI Reset: 0xxxxxxx bit0 to 6 SIZE SIZE bits Initial value value Packet size value bit7 Reserved Reserved...
Page 754 CHAPTER 29 USB FUNCTION Bit names Function Bit15 BIFNI • This bit Initializes the transmission buffer. • The BFINI bit is automatically set when the RST flag in the UDC control register (UDCC) is set to 0. • When the reset operation has been performed with the RST bit, clear the RST bit before clearing the BFINI bit.
Page 755 CHAPTER 29 USB FUNCTION 29.3.9 EP1 to EP5 Status Register (EP1S to EP5S) The EP1 to EP5 status registers (EP1S to EP5S) display status of endpoint1 to endpoint5.
Page 756 CHAPTER 29 USB FUNCTION ■ EP1 to EP5 Status Register (EP1S to EP5S) Figure 29.3-10 EP1 Status Register (EP1S) Initial Value: xxxxxxxx SIZE SIZE SIZE SIZE SIZE SIZE SIZE SIZE BIFNI Reset: xxxxxxxx bit0 to 7 SIZE SIZE bits Initial value value Packet size value Initial Value:...
Page 757 CHAPTER 29 USB FUNCTION Figure 29.3-11 EP2 to EP5 Status Register (EPS2 to EPS5) Initial Value: 0xxxxxxx Reserved SIZE SIZE SIZE SIZE SIZE SIZE SIZE BIFNI Reset: 0xxxxxxx bit0 to 6 SIZE SIZE bits Initial value value Packet size value bit7 Reserved Reserved...
Page 758 CHAPTER 29 USB FUNCTION The function of each bit in the EP1 to EP5 status register (EP1S to EP5S) is described in the following. Bit names Function Bit15 BIFNI • This bit initializes the transmission/reception buffer. • The BFINI bit is automatically set when the RST flag in the UDC control register (UDCC) is set to 0.
Page 759 CHAPTER 29 USB FUNCTION Bit names Function Bit9 • This bit indicates that the number of transfered data packet successfully received by the HOST is less than the maximum packet number value set in EPnC:PKS (including 0 byte) • The SPK bit trigger an interrupt. •...
Page 760 CHAPTER 29 USB FUNCTION 29.3.10 EP0 to EP5 Data Register (EP0DT to EP5DT) The EP0 to EP5 Data registers (EP0DT to EP5DT) are access registers used to read or write into the transmission/receive buffer for transfer data related to endpoint0 to endpoint5.
Page 761: Usb Function Operation
CHAPTER 29 USB FUNCTION 29.4 USB Function Operation This chapter describes the basics of the USB function. ■ USB Function operation The USB function performs a both way packet transfer with a host controller that supports the USB protocol. A host PC and its devices are connected and configured by the enumeration process. Then, communications based on various types of transfers using device drivers are performed.
Page 762 CHAPTER 29 USB FUNCTION Figure 29.4-1 Example of Connecting for USB Cable Terminal Direction Overview of operation USB bus connection Host Device Operation is not started until the host detects detection pull-up on the USB bus. Host Device Data of descriptor is returned to the host. Acquiring descriptor information Host...
Page 763 CHAPTER 29 USB FUNCTION ● Getting descriptor The USB device receives a request from the HOST PC and sends data to the HOST PC. In more detail, communications are performed in the following three stages: Figure 29.4-2 Communication Stages → →...
Page 764 CHAPTER 29 USB FUNCTION 29.4.1 Detecting Connection and Disconnection This section describes how to detect connection to and disconnection from the USB host. ■ USB connection example Connection to and disconnection from the USB host can be detected by connecting an external interrupt pin to the VBUS pin on the USB connector and connecting a pull-down resistor.
Page 765 CHAPTER 29 USB FUNCTION occurs, VBUS stabilization time must elapse before proceeding further. 3. The external interrupt must be temporarily disabled. The interrupt must be set to detect "L" level inputs to the external interrupt pin, and the external interrupt must be clear and enabled again. 4.
Page 766 CHAPTER 29 USB FUNCTION 29.4.2 Description of the USB function operation This section describes the basic operations and effects on USB registers. The processing of ﬁrmware tasks triggered via CPU interrupts are described. ■ Read Command USB function operation For GetDescripter, SynchFrame, and the class vender command Figure 29.4-6 Read Command USB function operation Setup stage Data stage...
Page 767 CHAPTER 29 USB FUNCTION after the DRQO is set, this routine checks that the number of received data is 0, and clears the interrupt cause DRQO and returns to continue with the preparation of the next setup stage. ■ Write Command USB function operation For GetDescripter and the class vendor command Figure 29.4-7 Write Command USB function operation Setup stage...
Page 768 CHAPTER 29 USB FUNCTION 29.4.3 Suspend Mode Function A USB device must have bus power supply conﬁguration with a power consumption less than 500µA in SUSPEND mode. This section describes the USB device procedure to enter SUSPEND mode and then STOP mode. ■...
Page 769 CHAPTER 29 USB FUNCTION 29.4.4 Wake-up Function To change a USB device from SUSPEND mode to WAKE UP mode, the USB protocol provides 2 different options: Remote wake-up from device Wake-up from host PC and Remote Wake-up Figure 29.4-9 Remote Wake-up Operation Suspend state 20ms Host PC...
Page 770 CHAPTER 29 USB FUNCTION 29.4.5 DMA Transfer Function Data transfers between USB function buffers and internal RAM is possible. There are two different DMA transfer modes: Packet Transfer mode and Data Number Automatic Transfer mode. ■ Packet Transfer Mode The packet transfer mode performs transfer by setting the number of data per packet to be transfered by the DMA and clearing the interrupt cause when the transfer is complete.
Page 771 CHAPTER 29 USB FUNCTION ● IN direction (host PC → device) forwarding Figure 29.4-12 IN Packet Forwarding IN packet IN packet Host PC Device DRQ flag * Device DATA0 DATA1 DRQ flag * CPU clear Host PC CPU clear DMAE DRQIE DER(Enx) DMA sending buffer write...
Page 772 CHAPTER 29 USB FUNCTION ● OUT direction (host PC → device) forwarding Figure 29.4-13 OUT Direction (Host PC → Device) Forwarding OUT packet Last OUT packet Host PC → DATA0 OUT DATA1 Device DRQ flag * DRQ flag * Device Automatic CPU clear →...
Page 773 CHAPTER 29 USB FUNCTION Figure 29.4-14 IN Direction (Device → Host PC) Forwarding Data Last Data Host PC → Device DRQ flag * DRQ flag * Device DATA0 DATA1 Automatic CPU clear → Host PC clear DMAE DRQIE DATA0 DATA1 DER(Enx) Write PKS part of Write the rest of...
Page 774 CHAPTER 29 USB FUNCTION 29.4.6 NULL Transfer Function It is possible to automatically transfer 0-byte data packet to inform the HOST of the termination of a buffer transfer mode. This function is only available for IN transfer direction. ■ NULL Transfer Mode This mode is activated if the following conditions are met: The automatic buffer transfer mode must be set (DMAE=1).
Page 775: Usb Mini-Host
CHAPTER 30 USB Mini-host This chapter describes the functions and operations of USB Mini-host. 30.1 USB Mini-host features 30.2 Differences with USB host 30.3 USB Mini-host Block Diagram 30.4 USB Mini-host Registers 30.5 USB Mini-host operation 30.6 Token Flow Chart...
Page 776: Usb Mini-Host Features
CHAPTER 30 USB Mini-host 30.1 USB Mini-host features USB Mini-host provides minimum host functionalities required. It enables data to be transferred to and from a device without PC intervention. ■ USB Mini-host features USB Mini-host has the following features: • Automatic detection of Full Speed forwarding •...
Page 777: Differences With Usb Host
CHAPTER 30 USB Mini-host 30.2 Differences with USB host Description of the differences between the standard USB host and USB Mini-host. ■ USB host versus USB Mini-host Host Mini-host ❍ Support Hub ❍ ❍ Transfer Bulk transfer ❍ ❍ Control transfer ❍...
Page 778: Usb Mini-Host Block Diagram
CHAPTER 30 USB Mini-host 30.3 USB Mini-host Block Diagram Block diagram of USB Mini-host. ■ Block Diagram of USB Mini-host Figure 30.3-1 Block Diagram of USB Mini-host Selector Receive control unit Buffer CPU I/F UDC I/F TXENL Transmit control unit USB bus reset Host receive HTXENL...
Page 779: Usb Mini-Host Registers
CHAPTER 30 USB Mini-host 30.4 USB Mini-host Registers This chapter describes all the registers of the USB Mini-host function. ■ Register of USB Mini-host Table 30.4-1 Registers of USB Mini-host RWKIRE URIRE CMPIRE CNNIRE DIRE SOFIRE URST HOST HCTN0 Reserved HCTN1 SOFSTEP CANCEL...
Page 780 CHAPTER 30 USB Mini-host Table 30.4-1 Registers of USB Mini-host Reserved FRAME1 HFRAME HTOKEN...
Page 781 CHAPTER 30 USB Mini-host 30.4.1 Host Control Registers 0,1 (HCNT0/HCNT1) Host control registers 0, 1 (HCNT0/HCNT1) specify the USB operation mode and the interrupt settings.
Page 782 CHAPTER 30 USB Mini-host ■ Host Control Registers 0, 1 (HCNT0/HCNT1) Figure 30.4-1 Host Control Register (HCTN0) Initial Value: 00000000 RWKIRE URIRE CMPIRE CNNIRE DIRE SOFIRE URST HOST bit0 HOST HOST Mode bit USB function is in device mode USB function is in Mini-host mode bit1 URST USB Reset bit...
Page 783 CHAPTER 30 USB Mini-host Figure 30.4-2 Host Control Register (HCTN1) Initial Value: 00000000 Reserved Reserved Reserved Reserved Reserved SOFSTEP CANCEL RETRY bit8 RETRY Retry function bit No retry Retry is on going bit9 CANCEL Cancel token bit The token is not cancelled Token is cancelled bit10 SOF interrupt trigger bit...
Page 784 CHAPTER 30 USB Mini-host Bit names Function Bit7 RWKIRE • This bit enables a resume wake up interrupt to be triggered when the Mini-host function is ready again after a resume operation is completed. • In host mode, HSTATE:SUSP bit must be set to enter suspend status.
Page 785 CHAPTER 30 USB Mini-host 30.4.2 Host Interrupt Register (HIRQ) The host interrupt register (HIRQ) displays all the interrupt request ﬂags.
Page 786 CHAPTER 30 USB Mini-host ■ Host Interrupt Register (HIRQ) Figure 30.4-3 Bit Conﬁguration of Host Interrupt Register (HIRQ) Initial Value: 00000000 TCAN Reserved RWKIRQ URIRQ CMPIRQ CNNIRQ DIRQ SOFIRQ bit0 SOFIRQ SOF Interrupt Request No SOF interrupt requested SOF interrupt requested bit1 DIRQ Disconnection Interrupt Request...
Page 787 CHAPTER 30 USB Mini-host Bit names Function Bit6 Reserved • Do not use. Bit5 RWKIRQ • This flag indicates the completion of the resume operation that triggers an interrupt if HCNT0:RWKIRE bit is set. • Clear by writing 0. • Writing "1" preserves the current state. •...
Page 788 CHAPTER 30 USB Mini-host 30.4.3 Host Error Status Register (HERR) The host error status register (HERR) indicates what type of error has occured in case of data transfer failure.
Page 789 CHAPTER 30 USB Mini-host ■ Host Error Status Register (HERR) Figure 30.4-4 Bit Description of the Host Error Status Register (HERR) Initial Value: 00000011 LSTSOF RERR TOUT TGERR STUFF bit8 to 9 Handshake Status bit10 STUFF Stuffing Error bit No stuffing error Stuffing error detected bit11 TGERR...
Page 790 CHAPTER 30 USB Mini-host Bit names Function Bit14 RERR • This bit indicates that the number of packet received has exceeded a maximum value. • When the error occurence sets the TOUT bit to "1". • Please do "0" in the writing to clear "1". •...
Page 791 CHAPTER 30 USB Mini-host 30.4.4 Host State Status Register (HSTATE) The Host State Status Register (HSTATE) indicates the status of the USB circuit.
Page 792 CHAPTER 30 USB Mini-host ■ Host State Status Register (HSTATE) Figure 30.4-5 Bit Configuration of the Host State Status Register (HSTATE) Initial Value: xx010010 Reserved Reserved ALIVE CLKSEL SOFBUSY SUSP TMODE CSTAT bit0 CSTAT Connection status bit Device is disconnected Device is connected bit1 TMODE...
Page 793 CHAPTER 30 USB Mini-host Bit names Function Bit4 CLKSEL • This bit selects the operating clock of the USB. • This bit can only be modified while UDCC:RST bit is set to "1" and the host mode is enabled. Bit3 SOFBUSY •...
Page 794 CHAPTER 30 USB Mini-host 30.4.5 SOF Interruption FRAME Comparison Register (HFCOMP) The SOF interrupt FRAME comparison register (HFCOMP) is used to set data that is compared with the lower 8 bits of FRAME Number register for SOF token interrupt. ■ SOF Interruption FRAME Comparison Register (HFCOMP) Figure 30.4-6 Bit Configuration of SOF Interruption FRAME Comparison Register (HFCOMP) Initial Value: 00000000...
Page 795 CHAPTER 30 USB Mini-host 30.4.6 Retry Timer Setting Register (HRTIMER) The retry timer setting register (HRTIMER) is used to set a retry time period for a token.
Page 796 CHAPTER 30 USB Mini-host ■ Retry Timer Setting Register (HRTIMER) Figure 30.4-7 Bit Configuration of Retry Timer Setting Register (HRTIMER) Initial Value: 00000000 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 bit0 to 7 Retry Timer Setting Register RTIMER0 Initial Value: 00000000 RTIMER1 RTIMER1...
Page 797 CHAPTER 30 USB Mini-host 30.4.7 Host Address Register (HADR) The host address register (HADR) is a register used for an address ﬁeld when a token is sent. ■ Host Address Register (HADR) Figure 30.4-8 Bit Configuration of Host address Register (HADR) Initial Value: 00000000 Resreved...
Page 798 CHAPTER 30 USB Mini-host 30.4.8 EOF Setting Register (HEOF) The EOF setting register (HEOF) deﬁnes a time period for which a token is inhibited before the execution of the SOF token. ■ EOF Setting Register (HEOF) Figure 30.4-9 Bit Configuration of EOF Setting Register (HEOF) Initial Value: 00000000 EOF0...
Page 799 CHAPTER 30 USB Mini-host Bit names Function Bit13-0 EOF 0/1 • The EOF registers hold a time period during which the execution of a token is inhibited before the execution of SOF. If the value stored in the SOF timer turns out to be lower than value stored in the HEOF register (as a result of comparing both), for any of an IN, OUT or SETUP token execution requests made, they will be run only after the...
Page 800 CHAPTER 30 USB Mini-host 30.4.9 FRAME Setting Register (HFRAME) The FRAME setting register (HFRAME) holds the FRAME Number when handling SOF tokens. ■ FRAME Setting Register (HFRAME) Figure 30.4-10 Bit Configuration of FRAME Setting Register (HFRAME) Initial Value: 00000000 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 bit0 to 7 Frame Number Register HFRAME...
Page 801 CHAPTER 30 USB Mini-host 30.4.10 Host Token Endpoint Register (HTOKEN) The host token endpoint register (HTOKEN) is a register that sets a toggle, endpoint, and token. ■ Host Token Endpoint Register (HTOKEN) Figure 30.4-11 Bit Configuration of Host Token Endpoint Register (HTOKEN) Initial Value: 00000000 TGGL...
Page 802 CHAPTER 30 USB Mini-host Bit names Function Bit6-4 TKNEN • These bits send a token corresponding to the setting. Once the operation is completed, the value is "000", and the HIRQ:CMPIRQ bit is set to "1" (HCNT0:CMPIRE bit must also set for an interrupt to be generated). •...
Page 803: Usb Mini-Host Operation
CHAPTER 30 USB Mini-host 30.5 USB Mini-host operation Summary of the USB Mini-host operation. ● Device connection The software detects that the external USB device is connected. ● USB bus reset USB bus is reset. ● Token packet Three kinds of token can be selected in host mode. ●...
Page 804 CHAPTER 30 USB Mini-host 30.5.1 Device Connection Operation of the external USB device connection detection. ■ Setting of Mini-host function The HCNT0:HOST bit must be set to "1" to turn the USB function as a host. ■ Disconnection status, connection status of an external USB device When the external USB device is disconnected, both Mini-host pins, D+ and D-, are "L"...
Page 805 CHAPTER 30 USB Mini-host HCNT0:HOST bit.
Page 806 CHAPTER 30 USB Mini-host 30.5.2 USB Bus Reset Description of the USB Bus reset operation. ■ USB Bus Reset When the HCNT0:URST bit is set to "1" in the host mode, it sends out SE0 for not less than 10 ms and resets the USB bus.
Page 807 CHAPTER 30 USB Mini-host 30.5.3 Token Packet This chapter describes the token packet. ■ Setting of Token Packet For the IN, OUT or SETUP token, the destination address is set in the host address register (HADR), and the maximum transferable number of bytes in one packet is set in the EP1C:PKS bits (or the EP2C based on the token to be executed).
Page 808 CHAPTER 30 USB Mini-host • Disconnection of the device (For "0" the HSTATE:CSTAT bit). To switch from host mode to device mode, it is mandatory to check that HSTATE:SOFBUSY bit is effectively "0" after clearing it. If you want to set back the HSTATE:SOFBUSY bit to "1" again, you need to run an SOF token once again.
Page 809 CHAPTER 30 USB Mini-host 30.5.4 Data Packet This chapter describes the Data Packet processing procedure. ■ Data Packet If a data packet is transmitted after a packet token has been sent, a toggle data will be transmitted based on the HTOKEN:TGGL bit, as well as the buffer data, the CRC16 data, and EOP is sent. In case a data packet transmission, the transmitted HTOKEN:TGGL bit and the received toggle data are compared, and, if they match, the received data is written to the endpoint corresonding to EP1C:DIR bit value, and the CRC16 is checked for an error later on.
Page 810 CHAPTER 30 USB Mini-host 30.5.5 Handshake Packet Transmitter and receiver are informed of their own status via handshake packet. ■ Handshake Packet The receiver transmits one of ACK, NAK, and STALL in an handshake packet to inform the data transmitter whether it can receive data properly or not. When the USB circuit receives a handshake packet, it sets the HERR:HS bit.
Page 811 CHAPTER 30 USB Mini-host 30.5.6 Retry Function This function enables the transfer error handling by retry. ■ Retry Function The retry function is enabled (i.e. HCNT1:RETRY is set to "1"), when NAK or an error such as CRC error occurs, the function will continue to retry the transfer during a time period set in the retry timer register (HRTIMER).
Page 812 CHAPTER 30 USB Mini-host 30.5.7 SOF Interrupt This chapter describes the SOF interrupt processing. ■ SOF Interrupt Once the HCNT0:SOFIRE bit is set, setting then HIRQ:SOFIRQ bit to "1" will trigger an interrupt when a SOF starts according to HCNT1:SOFSTEP and the SOF interrupt FRAME comparison register (HFCOMP) settings.
Page 813 CHAPTER 30 USB Mini-host Figure 30.5-7 Example of Token Cancel Operation when HCNT1:CANCEL bit is "1". IN TOKEN write EOF area execution SOFIRQ bit of HIRQ TKNEN bit of HTOKEN (000 (010 (000 CMPIRQ bit of HIRQ "0" Figure 30.5-8 Example of Token Cancel Operation when HCNT1:CANCEL bit is "0". IN TOKEN write IN TOKEN EOF area...
Page 814 CHAPTER 30 USB Mini-host 30.5.8 Error Status This chapter describes the various error types that the USB Mini-host can detect. ■ Error Status ● Stufﬁng error If 6 bits are continously equal to "1", one "0" bit must be inserted somewhere in the sequence. In other words, if 7 bits in a row are equal to "1", the HERR:STUFF bit is set signaling thus a stuffing error.
Page 815 CHAPTER 30 USB Mini-host 30.5.9 Packet End This chapter describes the Packet End process. ■ Packet End Timing When one packet terminates in USB Mini-host, an interrupt is triggered by the HIRQ:CMPIRQ bit (if the interrupt is enabled by setting HCNT0:CMPIRE). The interrupt is generated in the following timing: •...
Page 816 CHAPTER 30 USB Mini-host 30.5.10 Suspend Resume USB Mini-host supports suspend and resume operations. ■ Suspend Operation To enter the suspend mode, the HSTATE:SUSP bit must be set, the USB bus must be set in a high impedance state and circuit blocks where clock is not necessary must be stopped. The USB Mini-host can not set the USB circuit to suspend status or stop clock supplied to the circuit when the USB bus is being reset or the HSTATE:SOFBUSY is "1"...
Page 817 CHAPTER 30 USB Mini-host Figure 30.5-12 Resume Operation by Device (Full Speed Mode) (2) The simple host pins D+ and D- are detected to be K State. Discovers that Mini-HOST pin D + and Mini-HOST pin D - become K State. Pin D+ for Mini-HOST Pin D-...
Page 818 CHAPTER 30 USB Mini-host Figure 30.5-14 Resume Operation by Device Connection (4) The device is detected being connected. Connect Pin D+ for Mini-HOST Pin D- for Mini-HOST RWKIRQ bit of HIRQ (RWKIRE="1") HIRQ bit2 Interrupt (DIRE="1") occurs CSTAT bit of HSTATE 2.5µs or more : Drive by resistances of pull-up and pull-down...
Page 819 CHAPTER 30 USB Mini-host 30.5.11 Device disconnection This chapter describes the device disconnection detection. ■ Device disconnection Once both Mini-host pins D+ and D- become "L", the disconnection timer starts, and sets the HSTATE:CSTAT bit to "0" when both pins detect "L" for 2.5 ms or longer, which determines the device disconnection.
Page 820: Token Flow Chart
CHAPTER 30 USB Mini-host 30.6 Token Flow Chart The ﬂow chart of each USB Mini-host token. ■ IN, OUT, SETUP Token Figure 30.6-1 Flow Chart at IN, OUT, SETUP Token IN,OUT, SETUP TOKEN HADR change? HADR change IN TOKEN EP1 DIR=1? EP1 DIR=1? EP2C PKS change?
Page 821 CHAPTER 30 USB Mini-host ■ SOF Token Figure 30.6-2 Flow Chart of SOF Token SOF TOKEN HFRAME change? HFRAME change HEOF change? HEOF change TOKEN execution (Setting TGGL and ENDPT is disregarded.) CMPIRQ of HIRQ=1?
Page 822 CHAPTER 30 USB Mini-host...
Page 823: Memory Patch Function
CHAPTER 31 MEMORY PATCH FUNCTION This chapter explains the memory patch function and how the data patch or a debug function can be realised with that. 31.1 "Outline of the Memory Patch Function" 31.2 "Registers of the Memory Patch Function" 31.3 "Operation of the Memory Patch Function"...
Page 824: Outline Of The Memory Patch Function
CHAPTER 31 MEMORY PATCH FUNCTION MB96300 Super Series Hardware Manual 31.1 Outline of the Memory Patch Function The Memory Patch Function can detect addresses for code fetch or data access on the 16FX core bus. If the address matches the value set in a patch function address register, the code or data read is replaced with the value given by the according data patch register or an hardware interrupt is asserted.
Page 825 MB96300 Super Series Hardware Manual CHAPTER 31 MEMORY PATCH FUNCTION ■ Structure of the Memory Patch Function Figure 31.1-1 Block diagram of the Memory Patch Function address and control Address F2MC−16FX and Type Core Patch Address Match Detection PFA0 address match Patch Address/Mask PFA1...
Page 826: Registers Of The Memory Patch Function
CHAPTER 31 MEMORY PATCH FUNCTION MB96300 Super Series Hardware Manual 31.2 Registers of the Memory Patch Function The Memory Patch Function has following registers: • Patch function address registers (PFA0 to PFA7) • Patch function data registers (PFD0 to PFD7) •...
Page 827 MB96300 Super Series Hardware Manual CHAPTER 31 MEMORY PATCH FUNCTION the patch function address registers PFAx, the patch function data registers PFDx and the patch function control/status register PFCSx. ■ Patch function data register (PFD0 to PFD7) Figure 31.2-2 Patch function data registers (PFD0 to PFD7) byte+1 byte+0 Access...
Page 828 CHAPTER 31 MEMORY PATCH FUNCTION MB96300 Super Series Hardware Manual ■ Patch function control/status register (PFCS0 to PFCS3) Figure 31.2-3 Patch function control/status register (PFCS0/1/2/3) Address: Initial value 0000 PFCS0 0003B0 READWRITE BYTE WORDCODE PE1 PE0 DATA CPU DMA Access: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
Page 829 MB96300 Super Series Hardware Manual CHAPTER 31 MEMORY PATCH FUNCTION Table 31.2-1 Function of each bit of the PFCS0 (MPF channel 0 and 1) Name Function bit 13 BYTE This bit controls, if byte accesses are considered for the address match detection. •...
Page 830 CHAPTER 31 MEMORY PATCH FUNCTION MB96300 Super Series Hardware Manual Table 31.2-1 Function of each bit of the PFCS0 (MPF channel 0 and 1) Name Function bit 6 The address range bit AR controls the range option of the MPF channel 0. •...
Page 831 MB96300 Super Series Hardware Manual CHAPTER 31 MEMORY PATCH FUNCTION Table 31.2-1 Function of each bit of the PFCS0 (MPF channel 0 and 1) Name Function bit 2 This is an enable bit for the interrupt ﬂag I0. It controls the hardware interrupt generation of MPF channel 0.
Page 832 CHAPTER 31 MEMORY PATCH FUNCTION MB96300 Super Series Hardware Manual Table 31.2-2 lists the correspondence between the patch function address registers PFAx, the patch function data registers PFDx and the patch function control/status register PFCSx. Table 31.2-2 Correspondence between PFAx, PFDx and PFCSx Patch address (PFA) Patch data...
Page 833 MB96300 Super Series Hardware Manual CHAPTER 31 MEMORY PATCH FUNCTION The PFCSx:IEx and PFCSx:PEx configuration bits select the main operation of the MPF channel. Table 31.2-3 Channel Operation deﬁnition by the IE and PE bits in PFCS Operation Off. No interrupt and no data patch enabled. However, an address match is recorded in the I-ﬂag, when one of the enabled access types (PFCS[15:8]) and the given address (PFA, PFCS:AR, PFCS:AM) are matching.
Page 834 CHAPTER 31 MEMORY PATCH FUNCTION MB96300 Super Series Hardware Manual ■ EDSU extension register (EDSU) Figure 31.2-4 EDSU extension register (EDSU) Initial value Address: 0X0X000X TIE TINT SEL1 SEL0 RIE RINT EDSU 0003AF Access: R/W R R/W R/W R/W R R/W : Readable and writable : Read only To avoid the implementation of the debug services directly in the kernel of the application, external event...
Page 835 MB96300 Super Series Hardware Manual CHAPTER 31 MEMORY PATCH FUNCTION Table 31.2-4 Function of each bit of the EDSU register Name Function bit 13 This bit enables INT9 for the transmit interrupt of the selected communication device. • Writing ’0’ - The INT9 generation on transmit IRQ is disabled. •...
Page 836 CHAPTER 31 MEMORY PATCH FUNCTION MB96300 Super Series Hardware Manual ■ EDSU extension register 2 (EDSU2) Figure 31.2-5 EDSU extension register 2 (EDSU2) Initial value Address: 0003AD 00 00 TSEL RSEL EDSU2 0003AC Access: R/W : Readable and writable The EDSU extension register 2 (EDSU2) controls the extended break interrupt selection to trigger an INT9 exception.
Page 837: Operation Of The Memory Patch Function
MB96300 Super Series Hardware Manual CHAPTER 31 MEMORY PATCH FUNCTION 31.3 Operation of the Memory Patch Function This section describes the usage of the Memory Patch Function for different application purposes. ■ Memory Patch Function This is a data replacement function bound to an address match. It can be used to insert a software interrupt/ break point, branch instruction or to patch the code or data words directly.
Page 838 CHAPTER 31 MEMORY PATCH FUNCTION MB96300 Super Series Hardware Manual • Program the address into PFAx (byte access, hence address bit 0 is significant) • Program the access types to be detected in the PFCSx. At least one item out of each group of preferences need to be selected: Direction {READ|WRITE}, Size {BYTE|WORD}, Purpose {CODE|DATA}, Master {CPU|DMA}.
Page 839: Rom/Ram Mirroring Module
CHAPTER 32 ROM/RAM MIRRORING MODULE This chapter explains the ROM mirroring module. 32.1 "Outline of ROM Mirroring Module" 32.2 "ROM Mirroring Register (ROMM)"...
Page 840: Outline Of Rom Mirroring Module
CHAPTER 32 ROM/RAM MIRRORING MODULE MB96300 Super Series Hardware Manual 32.1 Outline of ROM Mirroring Module The ROM-Mirroring module maps the logical address (e.g. CPU address) of bank 00 to a physical address in a selected ROM bank. The mirrored ROM size is conﬁgurable. Unused ROM-Mirror area is used for mirroring RAM from bank 01.
Page 841: Rom Mirroring Register (Romm)
MB96300 Super Series Hardware Manual CHAPTER 32 ROM/RAM MIRRORING MODULE 32.2 ROM Mirroring Register (ROMM) The ROM Mirroring register (ROMM) conﬁgures all functions of the ROM mirroring module: - the mirrored ROM bank - the size of the mirrored ROM - the ROM mirror enable ■...
Page 842 CHAPTER 32 ROM/RAM MIRRORING MODULE MB96300 Super Series Hardware Manual Table 32.2-1 Description of ROMM Bit Name Function bit [7:4] BS[3:0]: These bits select the mirrored ROM-bank. BS[3:0] correspond to bit [3:0] of the bank selection memory bank address. bits ROMM:BS[3:0] mirrored Memory bank 1111...
Page 843 MB96300 Super Series Hardware Manual CHAPTER 32 ROM/RAM MIRRORING MODULE Table 32.2-2 description of Mirror size select bits MS[1:0] mirrored selected ROM/RAM-area ROM/RAM-mirrored to ROM/RAM- for mirroring area Size (physical address) (logical address) Fx.8000 - Fx.FFFF 00.8000 - 00.FFFF no RAM-Mirroring no RAM-Mirroring Note: Do not write the ROM mirroring register (ROMM) when code is executed from addresses inside the mirrored...
Page 844 CHAPTER 32 ROM/RAM MIRRORING MODULE MB96300 Super Series Hardware Manual...
Page 845: Flash Memory
CHAPTER 33 FLASH MEMORY This chapter explains the functions and operation of the ﬂash memory. 33.1 Overview of the Flash Memory 33.2 Block Diagram of the Flash Memory and Sector Configuration of the Flash Memory 33.3 Write/Erase Modes 33.4 Flash Memory Control Registers 33.5 Starting the Flash Memory Automatic Algorithm 33.6 Confirming the Automatic Algorithm Execution State 33.7 Detailed Explanation of Writing to and Erasing Flash Memory...
Page 846: Overview Of The Flash Memory
CHAPTER 33 FLASH MEMORY 33.1 Overview of the Flash Memory Up to two ﬂash memories are available on F2MC-16FX Flash MCU products. The "main" ﬂash memory is mapped in the CPU memory map to the banks DF to FF. Small sectors are located in bank DF. Depending on the size of the main ﬂash memory, large sectors are located starting at bank E0 or higher up to bank FF.
Page 847 CHAPTER 33 FLASH MEMORY When the "satellite" flash memory is available, it is possible to erase/write the "satellite" Flash while reading code and/or data from the "main" flash memory or vice versa. Hence, there is no need to copy data or code to RAM.
Page 848: Block Diagram Of The Flash Memory And Sector Configuration Of The Flash Memory
CHAPTER 33 FLASH MEMORY 33.2 Block Diagram of the Flash Memory and Sector Configuration of the Flash Memory Figure 33.2-1 Block diagram of the ﬂash memory shows a block diagram of the ﬂash memory and the ﬂash memory interface circuit. Figure 33.2-2 Sector conﬁguration of the ﬂash memory shows the sector conﬁguration of the ﬂash memory.
Page 849 CHAPTER 33 FLASH MEMORY Figure 33.2-2 Sector conﬁguration of the ﬂash memory Alternative mode Flash memory Sector number CPU address mode address - size FF:FFFFh 3F:FFFFh fixed position (top sector Main Flash) SA39 - 64K FF:0000h 3F:0000h FE:FFFFh 3E:FFFFh SA38 - 64K FE:0000h 3E:0000h FD:FFFFh...
Page 850 CHAPTER 33 FLASH MEMORY Figure 33.2-3 Sector conﬁguration of the ﬂash memory for different memory sizes Alternative mode Flash memory Main Flash size Main Flash size CPU address mode address 96kByte 160kByte FF:FFFFh 3F:FFFFh SA39 - 64K SA39 - 64K FF:0000h 3F:0000h FE:FFFFh...
Page 851: Write/Erase Modes
CHAPTER 33 FLASH MEMORY 33.3 Write/Erase Modes The ﬂash memory can be accessed in two different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus.
Page 852: Flash Memory Control Registers
CHAPTER 33 FLASH MEMORY 33.4 Flash Memory Control Registers This chapter describes the control/status registers which are needed to control the ﬂash memory erase/write process and to conﬁgure read access timing. ■ Flash Memory Control Registers The "main" flash memory is controlled by the following registers: •...
Page 853 CHAPTER 33 FLASH MEMORY 33.4.1 Flash Memory Control Status Register (MFMCS, SFMCS) The ﬂash memory control status register (MFMCS for "main" ﬂash memory, SFMCS for "satellite" ﬂash memory), together with the ﬂash memory interface circuit, is used to write data to and erase data from the ﬂash memory.
Page 854 CHAPTER 33 FLASH MEMORY ■ Flash Memory Control Status register (MFMCS, SFMCS) Figure 33.4-1 Conﬁguration of the Flash Memory Control Status register (MFMCS, SFMCS) Address: 0003F1 (MFMCS for "main" flash memory) 0003F5 (SFMCS for "satellite" flash memory) Initial value X 0 1 1 0 0 0 X RD19V DRBE CRBE INTE RDYINT RDY R/W R/W R/W R/W...
Page 855 CHAPTER 33 FLASH MEMORY Table 33.4-1 Function of each bit of the Flash Memory Control Status register (MFMCS/SFMCS) Bit names Function bit 0 RDY: This bit shows the status of the (sampled) Flash RDY output. Flash RDY Writing to this bit has no effect. status A read value of ’0’...
Page 856 CHAPTER 33 FLASH MEMORY Table 33.4-1 Function of each bit of the Flash Memory Control Status register (MFMCS/SFMCS) Bit names Function bit 6 RD19V: 1.9V • This bit must be set according to the conﬁguration of the voltage regulator operation (1.8V or 1.9V core voltage, please refer to CHAPTER 9 STANDBY MODE mode select AND VOLTAGE REGULATOR CONTROL CIRCUIT).
Page 857 CHAPTER 33 FLASH MEMORY 33.4.2 Flash Memory Timing Conﬁguration register (MFMTC, SFMTC) The Flash Memory Timing Conﬁguration register (MFMTC, SFMTC) is used to conﬁgure the access mode and the number of wait states of the ﬂash memory. Table 33.4-4 shows recommended settings.
Page 858 CHAPTER 33 FLASH MEMORY ■ Flash Memory Timing Conﬁguration register low byte (MFMTCL, SFMTCL) Figure 33.4-2 Conﬁguration of the Flash Memory Timing Conﬁguration register (MFMTCL, SFMTCL) Address: 0003F2 ("Main" Flash) 0003F6 ("Satellite" Flash) Initial value X 0 1 1 1 0 0 1 WEXL CLKBW ADS SYNC FAWC2 FAWC1 FAWC0...
Page 859 CHAPTER 33 FLASH MEMORY Table 33.4-2 Bit name Function bit 0 - bit 2 FAWC0 to • These bits deﬁne how many CPU wait cycles (CLKB cycles) are added at any FAWC2: read and write access to the Flash. Flash Access •...
Page 860 CHAPTER 33 FLASH MEMORY ■ Flash Memory Timing Conﬁguration register high byte (MFMTCH, SFMTCH) Figure 33.4-3 Conﬁguration of the Flash Memory Timing Conﬁguration register (MFMTCH, SFMTCH) Address: 0003F3 ("Main" Flash) 0003F7 ("Satellite" Flash) Initial value ATD- ATD- ATD- 0 0 0 0 0 0 1 0 EQL2 EQL1 EQL0 ATDL1 ATDL0 EQD1...
Page 861 CHAPTER 33 FLASH MEMORY Table 33.4-3 Bit name Function bit 9 - bit 10 ATDL0 to • These bits deﬁne the length of the ATDIN pulse according to the table in ATDL1: Figure 33.4-3 Conﬁguration of the Flash Memory Timing Conﬁguration ATDIN length register (MFMTCH, SFMTCH).
Page 862 CHAPTER 33 FLASH MEMORY ■ Recommended Flash Timing Settings Table 33.4-4 shows recommended Flash Memory Timing configurations. The maximum operating frequency of different timing configurations depends on the core supply voltage. Please refer to CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT for a description how to program the core supply voltage.
Page 863 CHAPTER 33 FLASH MEMORY Flash timing which is valid for both, the old and the new clock setting. The settings 6F3Dh/6F3Fh can be used for any clock transition. When using the modulated clock CLKMOD as clock source for CLKS1, make sure that the maximum and minimum values of the CLKMOD frequency are within the permitted range for the CLKS1 frequency.
Page 864 CHAPTER 33 FLASH MEMORY 33.4.3 Flash Memory Write Control registers 0-5 (FMWC0- FMWC5) Flash Memory Write Control registers (FMWC0-FMWC5) control the erase/write permission of each sector of the ﬂash memory. ■ Flash Memory Write Control registers (FMWC0-FMWC5)
Page 865 CHAPTER 33 FLASH MEMORY Figure 33.4-4 Conﬁguration of the Flash Memory Write Control registers (FMWC0-FMWC5) Address: 0003F8 : FMWC0 (reserved for "Satellite" Flash) 0003F9 : FMWC1 (reserved for "Main" Flash) 0003FA : FMWC2 (reserved for "Main" Flash) 0003FB : FMWC3 (reserved for "Main" Flash) 0003FC : FMWC4 (reserved for "Main"...
Page 866: Starting The Flash Memory Automatic Algorithm
CHAPTER 33 FLASH MEMORY 33.5 Starting the Flash Memory Automatic Algorithm Four types of commands are available for starting the ﬂash memory automatic algorithm: Read/Reset, Write and Chip Erase and Sector Erase. Control of suspend and restart is enabled for sector erase. ■...
Page 867 CHAPTER 33 FLASH MEMORY • SA: Sector address. See section 33.2 Block Diagram of the Flash Memory and Sector Configuration of the Flash Memory. • RD: Read data • PD: Write data. Only word data can be specified. *1: Both of the two types of Read/Reset commands can reset the flash memory to read mode except on suspended erase operation.
Page 868: Confirming The Automatic Algorithm Execution State
CHAPTER 33 FLASH MEMORY 33.6 Confirming the Automatic Algorithm Execution State Because the write/erase ﬂow of the ﬂash memory is controlled using the automatic algorithm, the ﬂash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables conﬁrmation of the operating state of the built-in ﬂash memory using the following hardware sequences.
Page 869 CHAPTER 33 FLASH MEMORY Table 33.6-2 Hardware sequence ﬂag functions State State Write --> Write completed (write DQ7 --> Toggle --> 0 --> 0 --> 1 --> change for address speciﬁed) DATA:7 DATA:6 DATA:5 DATA:3 DATA:2 normal Toggle --> Toggle --> operation Chip/sector erase -->...
Page 870 CHAPTER 33 FLASH MEMORY 33.6.1 Data Polling Flag (DQ7) The data polling ﬂag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated ■ Data polling ﬂag (DQ7) Table 33.6-3 Data polling flag state transitions (state change for normal operation) and Table 33.6-4 Data polling flag state transitions (state change for abnormal operation)"Data polling flag state transitions (state change for abnormal operation)"...
Page 871 CHAPTER 33 FLASH MEMORY being erased. Note: When the automatic algorithm is being started, read-access to the specified address is ignored. Since termination of the data polling flag (DQ7) can be accepted for a data read and other bits output, data read after the automatic algorithm has terminated should be performed after read-access has confirmed that data polling has terminated.
Page 872 CHAPTER 33 FLASH MEMORY 33.6.2 Toggle Bit Flag (DQ6) Like the data polling ﬂag, the toggle bit ﬂag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. ■ Toggle bit ﬂag (DQ6) Table 33.6-5 Toggle bit flag state transitions (state change for normal operation) and Table 33.6-6 Toggle bit flag state transitions (state change for abnormal operation) list the state transitions of the toggle bit flag.
Page 873 CHAPTER 33 FLASH MEMORY 33.6.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded ﬂag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the ﬂash memory. ■ Timing limit exceeded ﬂag (DQ5) Table 33.6-7 Timing limit exceeded flag state transitions (state change for normal operation) and Table 33.6-8 Timing limit exceeded bit flag state transitions (state change for abnormal operation) list the state transitions of the timing limit exceeded flag.
Page 874 CHAPTER 33 FLASH MEMORY 33.6.4 Sector Erase Timer Flag (DQ3) The sector erase timer ﬂag (DQ3) is used to post whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started. ■...
Page 875 CHAPTER 33 FLASH MEMORY ● Read access during sector erase Read-access during execution of sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. If this address does not belong to the sector being erased, the flash memory outputs bit 3 (DATA:3) of the corresponding memory value.
Page 876 CHAPTER 33 FLASH MEMORY 33.6.5 Toggle Bit-2 Flag (DQ2) The toggle bit-2 ﬂag (DQ2) is a ﬂag that uses the toggle bit function to indicate that the sector is in the erase-suspended state. ■ Toggle bit-2 ﬂag (DQ2) Table 33.6-11 Toggle bit-2 flag state transitions (state change for normal operation) and Table 33.6-12 Toggle bit-2 flag state transitions (state change for abnormal operation) list the state transitions of the toggle bit flag.
Page 877 CHAPTER 33 FLASH MEMORY ● While a sector erase operation is suspended If successive reads are executed while a sector erase operation is suspended, and if the address indicates the sector to be erased, the DQ2 flag toggles. If the address indicates the sector is not to be erased, the flash memory outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address.
Page 878: Detailed Explanation Of Writing To And Erasing Flash Memory
CHAPTER 33 FLASH MEMORY 33.7 Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of ﬂash memory Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a command that starts the automatic algorithm is issued. ■...
Page 879 CHAPTER 33 FLASH MEMORY 33.7.1 Setting The Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the ﬂash memory to the read/reset state. ■ Setting the ﬂash memory to the read/reset state The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 33.5-1 Command sequence table in Section 33.5 Starting the Flash Memory Automatic Algorithm) continuously to the target sector in the flash memory.
Page 880 CHAPTER 33 FLASH MEMORY 33.7.2 Writing Data This section describes the procedure for issuing the Write command to write data to the ﬂash memory. ■ Writing data to the ﬂash memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 33.5-1 Command sequence table in Section 33.5 Starting the Flash Memory Automatic Algorithm) continuously to the target sector in the flash memory.
Page 881 CHAPTER 33 FLASH MEMORY Figure 33.7-1 Example of the ﬂash memory write procedure Start writing (M/S)FMCS:WE (bit 3) Enable flash memory write Write command sequence (1) sssAAA <-- XXAA (2) sss554 <-- XX55 (3) sssAAA <-- XXA0 (4) Write address <-- Write data Read internal address Next address Data...
Page 882 CHAPTER 33 FLASH MEMORY 33.7.3 Erasing All Data (Erasing Chips) This section describes the procedure for issuing the Chip Erase command to erase all data in the ﬂash memory. ■ Erasing all data in the ﬂash memory (erasing chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 33.5-1 Command sequence table in Section 33.5 Starting the Flash Memory Automatic Algorithm) continuously to the target sector in the flash memory.
Page 883 CHAPTER 33 FLASH MEMORY 33.7.4 Erasing Optional Data (Erasing Sectors) This section describes the procedure for issuing the Sector Erase command to erase optional data (erase sector) in the ﬂash memory. Individual sectors can be erased. Multiple sectors can also be speciﬁed at one time. ■...
Page 884 CHAPTER 33 FLASH MEMORY Figure 33.7-2 Example of the ﬂash memory sector erase procedure Start erasing (M/S)FMCS:WE (bit 3) Enable flash memory erase Erase command sequence (1) sssAAA <-- XXAA (2) sss554 <-- XX55 (3) sssAAA <-- XX80 (4) sssAAA <-- XXAA (5) sss554 <-- XX55 Sector erase timer (DQ3) (6) Enter code to erase sector...
Page 885 CHAPTER 33 FLASH MEMORY 33.7.5 Suspending Sector Erase This section describes the procedure for issuing the Sector Erase Suspend command to suspend erasing of ﬂash memory sectors. Data can be read from sectors that are not being erased. ■ Suspending erasing of ﬂash memory sectors Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend command in the command sequence table (see Table 33.5-1 Command sequence table in Section 33.5 Starting the Flash Memory Automatic Algorithm) continuously to the target sector in the flash memory.
Page 886 CHAPTER 33 FLASH MEMORY 33.7.6 Restarting Sector Erase This section describes the procedure for issuing the Sector Erase Restart command to restart suspended erasing of ﬂash memory sectors. ■ Restarting erasing of ﬂash memory sectors Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase Restart command in the command sequence table (see Table 33.5-1 Command sequence table in Section 33.5 Starting the Flash Memory Automatic Algorithm) continuously to the target sector in the flash memory.
Page 887 CHAPTER 33 FLASH MEMORY 33.7.7 Protecting sectors from being erased/written to This section describes the procedure to protect sectors from being unintentionally erased or written to. ■ Activating the write protection by user program Individual sectors of the flash memory can be protected from being erased or written to by programming the Flash Memory Write Control registers.
Page 888 CHAPTER 33 FLASH MEMORY Figure 33.7-4 Conﬁguration of the Flash Write Protection Sector Markers (MFWPSM0 -MFWPSM5, SFWPSM0) Address: DE0020 : SFWPSM0 (reserved for "Satellite" Flash) DF0020 : MFWPSM0 (reserved for "Main" Flash) DF0021 : MFWPSM1 (reserved for "Main" Flash) DF0022 : MFWPSM2 (reserved for "Main"...
Page 889: Notes On Using Flash Memory
CHAPTER 33 FLASH MEMORY 33.8 Notes on using Flash Memory This section contains notes on using ﬂash memory. ■ Notes on using ﬂash memory ● Compatibility to MBM29LV200TC Please review the MBM29LV200TC data sheet in conjunction with this document. ● Input of a hardware reset (RST) A hardware reset during writing causes the data being written to be undefined.
Page 890: Flash Memory Programming Example
■ Programming example Flash memory sample program: ;==================================================================== ; THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES. (C) FUJITSU MICROELECTRONICS EUROPE 1998-2007 ;==================================================================== ;...
Page 891 CHAPTER 33 FLASH MEMORY CKSSR.EQU0x0402; Clock stabilization control CKMR.EQU 0x0403; Clock stabilization status CKFCR.EQU0x0404; Clock frequency control PLLCR.EQU0x0406; PLL settings ; RAM RAMSTART .EQU0x4000; Start address of RAM code ; FLASH SA1.EQU0x00DF2000; SA1 data sector SA1_554.EQU0x00DF2554; Flash sequence address 1 SA1_AAA.EQU0x00DF2AAA;...
Page 892 CHAPTER 33 FLASH MEMORY MOVPDR00, A; status flag to port 00 MOVWRW6, A; save status flag CALLP(RAMSTART + 4); write Data MOVWA, RW6; restore status flag ORWA MOVPDR00, A; show result LOOP:BRA LOOP; endless loop ;====== FLASH ERASE/WRITE RAM CODE ================================ ;...
Page 893 CHAPTER 33 FLASH MEMORY MOVLRL0, A MOVA, #0xAA; *0xDF2AAA = 0xAA MOVW@RL0, A MOVLA,#SA1_554 MOVLRL0, A MOVA, #0x55; *0xDF2554 = 0x55 MOVW@RL0, A MOVLA,#SA1 MOVLRL0, A MOVA, #0x30; *0xDF2000 = 0x30 MOVW@RL0, A ; Wait for sector erase start E_DQ3:MOVWA, @RL0+0; read sector state MOVNA, #DQ3 ANDWA MOVNA, #DQ3...
Page 894 CHAPTER 33 FLASH MEMORY POPWA MOVMFMCS, A MOVWA, RW2; status flag in A RAMEND:RETP ;====== FLASH WRITE ============================================= ; writes 0xAA55 to start of sector SA1 (0xDF2000) ; input: none ; output (in A): POK0 = successfully written POK1 = successfully written with "pre-time-out" PERR = time out error WRITE:MOVA, MFMCS;...
Page 895 CHAPTER 33 FLASH MEMORY ANDWA, #DQ7 CMPWA, RW5 BNZW_1 MOVWA, #POK0; successful written MOVWRW2, A W_1:MOVWA, @RL0+0; read Flash state ANDWA, #DQ5; time out? CWBNEA, #DQ5, W_2 MOVWA, @RL0+0; read Flash state MOVWRW4, #0xAA55 ; dummy data ANDWA, #DQ7; data polling MOVWRW5, A MOVWA, RW4 ANDWA, #DQ7...
Page 896 CHAPTER 33 FLASH MEMORY...
Page 897: Mask-Rom Memory Interface
CHAPTER 34 MASK-ROM MEMORY INTERFACE This chapter explains the functions and operation of the rom memory interface. 34.1 Overview 34.2 ROM interface registers 34.3 Read buffers...
Page 898: Overview
CHAPTER 34 MASK-ROM MEMORY INTERFACE 34.1 Overview This chapter describes the main features of the ROM interface. This interface is compatible with the Flash memory interface. ■ Main features The ROM interface supports the following features: • Configuration of the ROM interface is compatible with the Flash interface. •...
Page 899: Rom Interface Registers
CHAPTER 34 MASK-ROM MEMORY INTERFACE 34.2 ROM interface registers This chapter describes the ROM interface registers. It includes 3 conﬁguration registers: the ROM security MFMSEC, the ROM Control Status register MFMCS and the ROM Timing Conﬁguration register (MFMTC0). ■ ROM control/status register (MFMCS) In the description below, the bit described in grey do exist in the ROM interface and indicate thus the compatibility with the Flash interface.
Page 900 CHAPTER 34 MASK-ROM MEMORY INTERFACE Figure 34.2-1 ROM control/status register Address: 0003F1 0003F5 Initial value 0 0 1 1 0 0 0 1 RDYI RD19V DRBE CRBE INTE RDYINT R/W R/W R/W R/W R/W R/W bit 8 ROM RDY status ROM is ready bit9 RDYINT...
Page 901 CHAPTER 34 MASK-ROM MEMORY INTERFACE Table 34.2-1 ROM Control/Status register (MFMCS) Bit name Function bit 9 - • Only available for compatibility with Flash interface but without func- bit 11 tionallity. Any values can be writen here. bit 12 CRBE •...
Page 902 CHAPTER 34 MASK-ROM MEMORY INTERFACE Figure 34.2-2 ROM timing conﬁguration register 0 (MFMTC0) Address: 0003F2 Initial value 0 0 1 1 1 0 0 1 SSE WEXL CLKBW ADS SYNC FAWC2 FAWC1 FAWC0 R/W R/W R/W R/W R/W R/W R/W R/W bit2 bit1 bit0...
Page 903 CHAPTER 34 MASK-ROM MEMORY INTERFACE Figure 34.2-3 ROM timing conﬁguration register 1 (MFMTC1) Address: 0003F3 Initial value ATD- ATD- ATD- 0 0 0 0 0 0 1 0 EQL2 EQL1 EQL0 ATDL1 ATDL0 EQD1 EQD0 INIT R/W R/W R/W R/W R/W R/W R/W R/W bit8 ATDINIT...
Page 904: Read Buffers
CHAPTER 34 MASK-ROM MEMORY INTERFACE 34.3 Read buffers Two independent read buffers are implemented: the ﬁrst one for Code fetch, the second one for Data fetch. ■ Read buffer features • Code fetch read buffer is enabled with MFMCS:CRBE=1. Data fetch read buffer is enabled with MFMCS:DRBE=1.
Page 905: Rom/Flash Security
CHAPTER 35 ROM/FLASH SECURITY This chapter explains the functions and operation of the ROM/Flash security. 35.1 "Overview of the ROM/Flash Security" 35.2 "Usage of the ROM/Flash Security"...
Page 906: Overview Of The Rom/Flash Security
CHAPTER 35 ROM/FLASH SECURITY MB96300 Super Series Hardware Manual 35.1 Overview of the ROM/Flash Security The ROM/Flash security is a feature to prevent that the content of the ROM/Flash memory is read-out in a way not intended in the application. ■...
Page 907: Usage Of The Rom/Flash Security
MB96300 Super Series Hardware Manual CHAPTER 35 ROM/FLASH SECURITY 35.2 Usage of the ROM/Flash Security This section describes how the ROM/Flash Security is enabled and disabled and how the content of the ROM/Flash memory is protected against unintented read-out. ■ Flash security registers Figure 35.2-1 Conﬁguration of the ROM/Flash security byte Address: DE0000...
Page 908 CHAPTER 35 ROM/FLASH SECURITY MB96300 Super Series Hardware Manual ■ ROM security register Figure 35.2-2 ROM security register Initial value 00000000 FMSEC7 FMSEC6 FMSEC5 FMSEC4 FMSEC3 FMSEC2 FMSEC1 FMSEC0 Address R/W R/W R/W R/W R/W R/W R/W R/W 0003F0 Table 35.2-2 ROM security register FMSEC Bit name Function bit 0 -...
Page 909 MB96300 Super Series Hardware Manual CHAPTER 35 ROM/FLASH SECURITY ■ Unlocking the ROM/Flash security Figure 35.2-3 Conﬁguration of the ROM/Flash security unlock key Address: DE0002 ...DE0011H : SFSUK0 ... SFSUK15 (for "Satellite" Flash) DF0002 ...DF0011H : MFSUK0 ... MFSUK15 (for "Main" Flash) SFSUK0 SFSUK15 MFSUK0...
Page 910 CHAPTER 35 ROM/FLASH SECURITY MB96300 Super Series Hardware Manual On flash memory devices, the ROM/Flash security can be disabled as follows: • When starting in internal vector mode (MD[2:0] = 011 ), the application program can disable the Flash security by - changing the value of the Flash/ROM security byte to a value different to 99 by writing to this Flash memory location.
Page 911: Examples Of Serial Programming Connection
CHAPTER 36 EXAMPLES OF SERIAL PROGRAMMING CONNECTION This chapter describes how to connect the MCU for in- circuit serial programming of the Flash memory. 36.1 "Basic Configuration of Serial Programming Connection" 36.2 "Example of connecting a PC for programming the Flash Microcontroller"...
Page 912: Basic Configuration Of Serial Programming Connection
In a minimal system, the MB96300 Super series Flash micrcocontroller is connected via the USART in asynchronous mode to the RS-232 port of the PC. Figure 36.1-1 Connection between PC serial port to Fujitsu MB96300 Super series ﬂash microcontrollers RS-232 port of PC...
Page 913 MB96300 Super Series Hardware Manual CHAPTER 36 EXAMPLES OF SERIAL PROGRAMMING CONNECTION Table 36.1-1 Pins used for Fujitsu serial onboard programming Function Additional information MD2, MD1 Mode pins Controls the operation mode of the MCU. For details, please refer to chapter 8.4 "Boot ROM program execution and Operation mode...
Page 914 CHAPTER 36 EXAMPLES OF SERIAL PROGRAMMING CONNECTIONMB96300 Super Series Hardware Manual ■ Serial data baud rate The MCU determines automatically the serial data baud rate as adjusted in the programming tool or PC running programming software.
Page 915: Example Of Connecting A Pc For Programming The Flash Microcontroller
MB96300 Super Series Hardware Manual CHAPTER 36 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 36.2 Example of connecting a PC for programming the Flash Microcontroller Figure 36.2-1 shows an example of the minimum connection to a PC to program the ﬂash microcontroller. ■...
Page 916: Example Of Connecting A Programming Tool For Programming The Flash Microcontroller
CHAPTER 36 EXAMPLES OF SERIAL PROGRAMMING CONNECTIONMB96300 Super Series Hardware Manual 36.3 Example of connecting a programming tool for programming the Flash Microcontroller Figure 36.3-1 is an example of connecting a programming tool to program the ﬂash microcontroller. ■ Example of connecting a programming tool to program the ﬂash microcontroller For high speed programming a device programmer must be connected as shown in the example below.
Page 917 APPENDIX The appendixes provide I/O maps, instructions, and other information. APPENDIX A "I/O Map of MB96V300" APPENDIX B "Instructions" APPENDIX C "Timing Diagrams in Flash Memory Mode"...
Page 918 APPENDIX MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 This appendix lists the addresses to be assigned to the registers in the peripheral blocks.
Page 919 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 ■ I/O maps of MB96V300 Table A-1 I/O map of MB96V300 (1/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000000H P00 - I/O Port Port Data Register PDR00 000001H P01 - I/O Port Port Data Register...
Page 920 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (2/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000022H FRT0 - Control status register of free-running timer TCCSL0 TCCS0 000023H FRT0 - Control status register of free-running timer TCCSH0 000024H FRT1 - Data register of free-running timer...
Page 921 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (3/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000040H ICU0/ICU1 - Control Status Register ICS01 000041H ICU0/ICU1 - Edge register ICE01 000042H ICU0 - Capture Register IPCPL0...
Page 922 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (4/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 00005DH EXTINT1 - External Interrupt Interrupt request EIRR1 Register 00005EH EXTINT1 - External Interrupt Level Select ELVRL1 ELVR1 00005FH EXTINT1 - External Interrupt Level Select ELVRH1...
Page 923 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (5/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000071H RLT6 - Timer Control Status Register High (dedic. TMCSRH6 RLT for PPG) 000072H RLT6 - Reload Register Low (dedic.
Page 924 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (6/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 00008AH PPG2 - Period setting register PCSR2 00008BH PPG2 - Period setting register 00008CH PPG2 - Duty cycle register PDUT2 00008DH PPG2 - Duty cycle register...
Page 925 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (7/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0000A8H PPG5 - Duty cycle register PDUT5 0000A9H PPG5 - Duty cycle register 0000AAH PPG5 - Control status register PCNL5...
Page 926 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (8/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0000C5H USART0 - Ext. Status Register ESCR0 0000C6H USART0 - Baud Rate Generator Register Low BGRL0 BGR0 0000C7H USART0 - Baud Rate Generator Register High BGRH0 0000C8H...
Page 927 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (9/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0000E3H USART3 - Ext. Status Register ESCR3 0000E4H USART3 - Baud Rate Generator Register Low BGRL3 BGR3 0000E5H...
Page 928 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (10/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000119H DMA3 - Buffer address pointer middle byte BAPM3 00011AH DMA3 - Buffer address pointer high byte BAPH3 00011BH DMA3 - DMA control register DMACS3...
Page 929 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (11/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000137H DMA6 - Data counter high byte DCTH6 000138H DMA7 - Buffer address pointer low byte BAPL7 000139H DMA7 - Buffer address pointer middle byte...
Page 930 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (12/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000155H DMA10 - I/O register address pointer high byte IOAH10 000156H DMA10 - Data counter low byte DCTL10 DCT10 000157H DMA10 - Data counter high byte...
Page 931 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (13/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000173H DMA14 - DMA control register DMACS14 000174H DMA14 - I/O register address pointer low byte IOAL14 IOA14 000175H...
Page 932 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (14/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000390H DMA7-DMA0 - status register DSRL 000391H DMA15-DMA8 - status register DSRH 000392H DMA7-DMA0 - stop status register DSSRL DSSR 000393H...
Page 933 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (15/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0003BEH Memory Patch function - Patch address 2 low PFAL2 0003BFH Memory Patch function - Patch address 2 middle PFAM2 0003C0H Memory Patch function - Patch address 2 high...
Page 934 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (16/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0003DCH Memory Patch function - Patch data 6 PFDL6 PFD6 0003DDH Memory Patch function - Patch data 6 PFDH6 0003DEH Memory Patch function - Patch data 7...
Page 935 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (17/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 00040BH Reset cause and clock status register with clear RCCSRC function 00040CH Reset conﬁguration register 00040DH Reset cause and clock status register RCCSR...
Page 936 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (18/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000442H P18- I/O Port Data Direction Register DDR18 000443H P19 - I/O Port Data Direction Register DDR19 000444H P00 - I/O Port Port Input Enable Register PIER00 000445H...
Page 937 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (19/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000460H P08 - I/O Port Port Input Level Register PILR08 000461H P09 - I/O Port Port Input Level Register PILR09 000462H P10 - I/O Port Port Input Level Register...
Page 938 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (20/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 00047EH P18 - I/O Port Port Output Drive Register EPILR18 00047FH P19 - I/O Port Port Output Drive Register EPILR19 000480H P00 - I/O Port Port Output Drive Register...
Page 939 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (21/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0004ABH P03 - I/O Port Pull-Up resistor Control Register PUCR03 0004ACH P04 - I/O Port Pull-Up resistor Control Register PUCR04 0004ADH P05 - I/O Port Pull-Up resistor Control Register...
Page 940 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (22/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0004C9H P13 - I/O Port External Pin State Register EPSR13 0004CAH P14 - I/O Port External Pin State Register EPSR14 0004CBH P15 - I/O Port External Pin State Register...
Page 941 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (23/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0004E8H RTC - Timer Control Register L WTCRL WTCR 0004E9H RTC - Timer Control Register H WTCRH 0004EAH CAL - Calibration unit Control register...
Page 942 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (24/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000508H OCU8 - Output Compare Control Status OCS8 000509H OCU9 - Output Compare Control Status OCS9 00050AH OCU8 - Compare Register OCCP8 00050BH OCU8 - Compare Register...
Page 943 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (25/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000525H USART4 - Ext. Status Register ESCR4 000526H USART4 - Baud Rate Generator Register Low BGRL4 BGR4 000527H...
Page 944 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (26/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000543H USART7 - Ext. Status Com. Register ESCR7 000544H USART7 - Baud Rate Generator Register BGRL7 BGR7 000545H USART7 - Baud Rate Generator Register BGRH7 000546H...
Page 945 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (27/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000566H PPG6 - Period setting register PCSR6 000567H PPG6 - Period setting register 000568H PPG6 - Duty cycle register PDUT6...
Page 946 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (28/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000584H PPG9 - Duty cycle register PDUT9 000585H PPG9 - Duty cycle register 000586H PPG9 - Control status register PCNL9 PCN9 000587H...
Page 947 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (29/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0005A2H PPG12 - Control status register PCNL12 PCN12 0005A3H PPG12 - Control status register PCNH12 0005A4H PPG13 - Timer register...
Page 948 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (30/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0005C0H PPG16 - Timer register PTMR16 0005C1H PPG16 - Timer register 0005C2H PPG16 - Period setting register PCSR16 0005C3H PPG16 - Period setting register 0005C4H...
Page 949 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (31/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0005DEH PPG19 - Control status register PCNL19 PCN19 0005DFH PPG19 - Control status register PCNH19 0005E0H SMC0 - PWM control register...
Page 950 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (32/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000602H SMC3 - PWM control register PWM 2 PWC23 000603H SMC3 - PWM control register PWM 2 000604H SMC3 - PWM Select register PWS13 000605H...
Page 951 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (33/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000627H LCD - Extended Control Register LECR 000628H LCD - Common pin switching register LCDCMR 000629H LCD - Control Register...
Page 952 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (34/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000645H LCD - Data register for Segment VRAM27 000646H LCD - Data register for Segment VRAM28 000647H LCD - Data register for Segment VRAM29 000648H LCD - Data register for Segment 61-60...
Page 953 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (35/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0006B3H USB - EP0 Control Register High EP0CH0 0006B4H USB - EP1 Control Register Low EP1CL0 EP1C0 0006B5H...
Page 954 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (36/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0006D1H USB - EP0 Data register High EP0DTH0 0006D2H USB - EP1 Data register Low EP1DTL0 EP1DT0 0006D3H USB - EP1 Data register High EP1DTH0 0006D4H...
Page 955 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (37/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 0006F3H External bus Address output enable register 1 EBAE1 0006F4H External bus Address output enable register 2 EBAE2 0006F5H External bus Control signal register...
Page 956 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (38/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 00071DH CAN0 - IF1 Message Control Register IF1MCTRH0 00071EH CAN0 - IF1 Data A1 IF1DTA1L0 IF1DTA10 00071FH CAN0 - IF1 Data A1 IF1DTA1H0 000720H CAN0 - IF1 Data A2...
Page 957 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (39/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000755H CAN0 - IF2 Data B2 IF2DTB2H0 000780H CAN0 - Transmission Request Register TREQR1L0 TREQR10 000781H...
Page 958 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (40/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000800H CAN1 - Control register CTRLRL1 CTRLR1 000801H CAN1 - Control register (reserved) CTRLRH1 000802H CAN1 - Status register STATRL1 STATR1 000803H...
Page 959 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (41/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000820H CAN1 - IF1 Data A2 IF1DTA2L1 IF1DTA21 000821H CAN1 - IF1 Data A2 IF1DTA2H1 000822H CAN1 - IF1 Data B1...
Page 960 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (42/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000882H CAN1 - Transmission Request Register TREQR2L1 TREQR21 000883H CAN1 - Transmission Request Register TREQR2H1 000890H CAN1 - New Data Register NEWDT1L1 NEWDT11 000891H...
Page 961 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (43/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000911H CAN2 - IF1 Command request register IF1CREQH2 000912H CAN2 - IF1 Command Mask register IF1CMSKL2 IF1CMSK2 000913H...
Page 962 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (44/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000949H CAN2 - IF2 Arbitration register IF2ARB1H2 00094AH CAN2 - IF2 Arbitration register IF2ARB2L2 IF2ARB22 00094BH CAN2 - IF2 Arbitration register IF2ARB2H2 00094CH CAN2 - IF2 Message Control Register...
Page 963 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (45/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000A00H CAN3 - Control register CTRLRL3 CTRLR3 000A01H CAN3 - Control register (reserved) CTRLRH3 000A02H CAN3 - Status register...
Page 964 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (46/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000A20H CAN3 - IF1 Data A2 IF1DTA2L3 IF1DTA23 000A21H CAN3 - IF1 Data A2 IF1DTA2H3 000A22H CAN3 - IF1 Data B1 IF1DTB1L3 IF1DTB13 000A23H...
Page 965 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (47/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000A82H CAN3 - Transmission Request Register TREQR2L3 TREQR23 000A83H CAN3 - Transmission Request Register TREQR2H3 000A90H CAN3 - New Data Register...
Page 966 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (48/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000B11H CAN4 - IF1 Command request register IF1CREQH4 000B12H CAN4 - IF1 Command Mask register IF1CMSKL4 IF1CMSK4 000B13H CAN4 - IF1 Command Mask register (reserved) IF1CMSKH4 000B14H...
Page 967 MB96300 Super Series Hardware Manual APPENDIX A I/O Map of MB96V300 Table A-1 I/O map of MB96V300 (49/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000B49H CAN4 - IF2 Arbitration register IF2ARB1H4 000B4AH CAN4 - IF2 Arbitration register IF2ARB2L4 IF2ARB24 000B4BH...
Page 968 APPENDIX MB96300 Super Series Hardware Manual Table A-1 I/O map of MB96V300 (50/50) Address Register Abbreviation Abbreviation Access 8-bit access 16-bit access 000C00H External bus area (16-bit address up to 000FFFH) EXTBUS1 001000H External bus area (Remaining RAM AREA) EXTBUS1 001000H External bus area (Remaining RAM AREA) EXTBUS1...
Page 969 MB96300 Super Series Hardware Manual APPENDIX B Instructions APPENDIX B Instructions Appendix B describes the instructions used by the F MC-16FX. B.1 "Instruction Types" B.2 "Addressing" B.3 "Direct Addressing" B.4 "Indirect Addressing" B.5 "Execution Cycle Count" B.6 "Effective address field" B.7 "How to Read the Instruction List"...
Page 970 APPENDIX MB96300 Super Series Hardware Manual Instruction Types The F MC-16FX supports 351 types of instructions. Addressing is enabled by using an effective address ﬁeld of each instruction or using the instruction code itself. ■ Instruction types The F MC-16FX supports the following 351 types of instructions: •...
Page 971 MB96300 Super Series Hardware Manual APPENDIX B Instructions Addressing With the F MC-16FX, the address format is determined by the instruction effective address ﬁeld or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
Page 972 APPENDIX MB96300 Super Series Hardware Manual ■ Effective address ﬁeld Table B.2-1 "Effective address field" lists the address formats specified by the effective address field. Table B.2-1 Effective address ﬁeld Code Representation Address format Default bank (RL0) Register direct: Individual parts correspond to (RL1) the byte, word, and long word types in order None...
Page 973 MB96300 Super Series Hardware Manual APPENDIX B Instructions Direct Addressing An operand value, register, or address is speciﬁed explicitly in direct addressing mode. ■ Direct addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of immediate addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution 2 2 3 3 4 4 5 5...
Page 974 APPENDIX MB96300 Super Series Hardware Manual Figure B.3-2 Example of register direct addressing (This instruction transfers the eight low-order bits of A to the general-purpose MOV R0, A register R0.) Before execution 0 7 1 6 2 5 3 4 Memory space After execution 0 7 1 6 2 5 6 4...
Page 975 MB96300 Super Series Hardware Manual APPENDIX B Instructions ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of direct branch addressing (addr24) (This instruction causes an unconditional branch by direct branch 24-bit JMPP 333B20H...
Page 976 APPENDIX MB96300 Super Series Hardware Manual ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB).
Page 977 MB96300 Super Series Hardware Manual APPENDIX B Instructions ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
Page 978 APPENDIX MB96300 Super Series Hardware Manual ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of vector addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector...
Page 979 MB96300 Super Series Hardware Manual APPENDIX B Instructions Indirect Addressing In indirect addressing mode, an address is speciﬁed indirectly by the address data of an operand. ■ Indirect addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
Page 980 APPENDIX MB96300 Super Series Hardware Manual Figure B.4-2 Example of register indirect addressing with post increment (@RWj+ j = 0 to 3) (This instruction reads data by register indirect addressing with post MOVW A, @RW1+ increment and stores it in A.) Before execution 0 7 1 6 2 5 3 4...
Page 981 MB96300 Super Series Hardware Manual APPENDIX B Instructions ● Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): •...
Page 982 APPENDIX MB96300 Super Series Hardware Manual ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank.
Page 983 MB96300 Super Series Hardware Manual APPENDIX B Instructions Figure B.4-9 Example of register list (rlist) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) 3 4 F A 3 4 F E Memory space Memory space...
Page 984 APPENDIX MB96300 Super Series Hardware Manual ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB).
Page 985 MB96300 Super Series Hardware Manual APPENDIX B Instructions ● Indirect speciﬁcation branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of indirect speciﬁcation branch addressing (@eam) (This instruction causes an unconditional branch by register indirect addressing.) JMP @RW0 Before execution 3 C 2 0...
Page 986 APPENDIX MB96300 Super Series Hardware Manual Execution Cycle Count The execution cycle count for 16FX is TBD and will be shown here in a future version of the hardware manual.
Page 987 MB96300 Super Series Hardware Manual APPENDIX B Instructions Effective address field Table B.6-1 "Effective address ﬁeld" shows the effective address ﬁeld. ■ Effective Address Field Table B.6-1 Effective address ﬁeld Byte count of extended address part Code Representation Address format (*1) (RL0) Register direct: Individual parts correspond to...
Page 988 APPENDIX MB96300 Super Series Hardware Manual How to Read the Instruction List Table B.7-1 "Description of items in the instruction list" describes the items used in the MC-16FX Instruction List, and Table B.7-2 "Explanation on symbols in the instruction List" describes the symbols used in the same list. ■...
Page 989 MB96300 Super Series Hardware Manual APPENDIX B Instructions Table B.7-1 Description of items in the instruction list (Continued) Item Description Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note:...
Page 990 APPENDIX MB96300 Super Series Hardware Manual Table B.7-2 Explanation on symbols in the instruction List (Continued) Symbol Explanation addr24 Physical direct addressing ad24 0-15 Bits 0 to 15 of addr24 ad24 16-23 Bits 16 to 23 of addr24 I/O area (000000H to 0000FFH) #imm4 4-bit immediate data #imm8...
Page 991 MB96300 Super Series Hardware Manual APPENDIX B Instructions MC-16FX Instruction List Table B.8-1 "41 Transfer instructions (byte)" to Table B.8-18 "10 String instructions" list the instructions used by the F MC-16FX. ■ F MC-16FX instruction list Table B.8-1 41 Transfer instructions (byte) Mnemonic Operation MOV A,dir...
Page 992 APPENDIX MB96300 Super Series Hardware Manual Table B.8-2 38 Transfer instructions (word / long word) Mnemonic Operation MOVW A,dir word (A) <-- (dir) MOVW A,addr16 word (A) <-- (addr16) MOVW A,SP word (A) <-- (SP) MOVW A,RWi word (A) <-- (RWi) MOVW A,ear word (A) <-- (ear) MOVW A,eam...
Page 993 MB96300 Super Series Hardware Manual APPENDIX B Instructions Table B.8-3 42 Addition/subtraction instructions (byte, word, long word) Mnemonic Operation A,#imm8 byte (A) <-- (A) + imm8 A,dir byte (A) <-- (A) + (dir) A,ear byte (A) <-- (A) + (ear) A,eam byte (A) <-- (A) + (eam) ear,A...
Page 994 APPENDIX MB96300 Super Series Hardware Manual Table B.8-4 12 Increment/decrement instructions (byte, word, long word) Mnemonic Operation byte (ear) <-- (ear) + 1 byte (eam) <-- (eam) + 1 byte (ear) <-- (ear) - 1 byte (eam) <-- (eam) - 1 INCW word (ear) <-- (ear) + 1 INCW...
Page 995 MB96300 Super Series Hardware Manual APPENDIX B Instructions Table B.8-6 11 Unsigned multiplication/division instructions (word, long word) Mnemonic Operation DIVU word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) DIVU A,ear word (A) / byte (ear) quotient -->...
Page 996 APPENDIX MB96300 Super Series Hardware Manual Table B.8-7 11 Signed multiplication/division instructions (word, long word) Mnemonic Operation word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) A,ear word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) A,eam word (A) / byte (eam) quotient -->...
Page 997 MB96300 Super Series Hardware Manual APPENDIX B Instructions Table B.8-8 39 Logic 1 instructions (byte, word) Mnemonic Operation A,#imm8 byte (A) <-- (A) and imm8 A,ear byte (A) <-- (A) and (ear) A,eam byte (A) <-- (A) and (eam) ear,A byte (ear) <-- (ear) and (A) eam,A byte (eam) <-- (eam) and (A)
Page 998 APPENDIX MB96300 Super Series Hardware Manual Table B.8-9 6 Logic 2 instructions (long word) Mnemonic Operation ANDL A,ear long (A) <-- (A) and (ear) ANDL A,eam long (A) <-- (A) and (eam) A,ear long (A) <-- (A) or (ear) A,eam long (A) <-- (A) or (eam) XORL A,ear...
Page 999 MB96300 Super Series Hardware Manual APPENDIX B Instructions Table B.8-12 18 Shift instructions (byte, word, long word) Mnemonic Operation RORC byte (A) <-- With right rotation carry ROLC byte (A) <-- With left rotation carry RORC byte (ear) <-- With right rotation carry RORC byte (eam) <-- With right rotation carry ROLC...
Page 1000 APPENDIX MB96300 Super Series Hardware Manual Table B.8-13 31 Branch 1 instructions Mnemonic Operation BZ/BEQ Branch on (Z) = 1 BNZ/BNE Branch on (Z) = 0 BC/BLO Branch on (C) = 1 BNC/BHS Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0...
Page 1001 MB96300 Super Series Hardware Manual APPENDIX B Instructions Table B.8-14 19 Branch 2 instructions Mnemonic Operation S T N Z V C R CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 CWBNE A,#imm16,rel Branch on word (A) not equal to imm16 CBNE ear,#imm8,rel Branch on byte (ear) not equal to imm8...
Page 1002 APPENDIX MB96300 Super Series Hardware Manual Table B.8-15 28 Other control instructions (byte, word, long word) Mnemonic Operation PUSHW word (SP) <-- (SP) - 2, ((SP)) <-- (A) PUSHW word (SP) <-- (SP) - 2, ((SP)) <-- (AH) PUSHW word (SP) <-- (SP) - 2, ((SP)) <-- (PS) PUSHW rlst (SP) <-- (SP) - 2n, ((SP)) <-- (rlst)

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