Epson S1D13505 Technical Manual

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S1D13505 Embedded RAMDAC LCD/CRT Controller

S1D13505

TECHNICAL MANUAL

Document Number: X23A-Q-001-12

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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Page 1 S1D13505 Embedded RAMDAC LCD/CRT Controller S1D13505 TECHNICAL MANUAL Document Number: X23A-Q-001-12 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 2 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 TECHNICAL MANUAL X23A-Q-001-12 Issue Date: 01/04/18...
Page 3: Customer Support Information
Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 S1D13505 X23A-Q-001-12...
Page 4 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 TECHNICAL MANUAL X23A-Q-001-12 Issue Date: 01/04/18...
Page 5 S1D13505 EMBEDDED RAMDAC LCD/CRT CONTROLLER DESCRIPTION The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.
Page 6: System Block Diagram
S1D13505 SYSTEM BLOCK DIAGRAM Data and Control Signals CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS • S1D13505 Technical • Linux Console Driver Manual • S5U13505 Evaluation Boards • Windows CE Display Driver • CPU Independent Software • VXWorks Tornado...
Page 7 S1D13505 Embedded RAMDAC LCD/CRT Controller Hardware Functional Specification Document Number: X23A-A-001-14 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 8 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Hardware Functional Specification X23A-A-001-14 Issue Date: 01/02/02...
Page 9: Table Of Contents
D.C. Characteristics ........38 Hardware Functional Specification Issue Date: 01/02/02 Table of Contents Page 3 S1D13505 X23A-A-001-14...
Page 10 MIPS/ISA Interface Timing ........54 7.1.8 Philips Interface Timing (e.g. PR31500/PR31700) ..... . .56 7.1.9 Toshiba Interface Timing (e.g.
Page 11 ......137 ......141 Page 5 S1D13505 X23A-A-001-14...
Page 12 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Hardware Functional Specification X23A-A-001-14 Issue Date: 01/02/02...
Page 13 Philips Timing........
Page 14 S1D13505 Addressing ........
Page 15 Philips Timing ........
Page 16 Mechanical Drawing QFP15 ........148 S1D13505...
Page 17: Introduction
The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.
Page 18: Features
• 8/16-bit SH-4 bus interface. • 8/16-bit SH-3 bus interface. • 8/16-bit interface to 8/16/32-bit MC68000 microprocessors/microcontrollers. • 8/16-bit interface to 8/16/32-bit MC68030 microprocessors/microcontrollers. • Philips PR31500/PR31700 (MIPS). • Toshiba TX3912 (MIPS) • 16-bit Power PC (MPC821) microprocessor. • 16-bit Epson E0C33 microprocessor.
Page 19: Display Support
• Memory clock can be input clock or (input clock/2), providing flexibility to use CPU bus clock as input. • Pixel clock can be the memory clock, (memory clock/2), (memory clock/3) or (memory clock/4). Hardware Functional Specification Issue Date: 01/02/02 Page 13 S1D13505 X23A-A-001-14...
Page 20: Miscellaneous
Output that can be used to control the LCD backlight. Power-on polarity is selected by an MD configuration pin. • Operating voltages from 2.7 volts to 5.5 volts are supported • 128-pin QFP15 surface mount package S1D13505 X23A-A-001-14 Epson Research and Development Vancouver Design Center...
Page 21: Typical System Implementation Diagrams
4/8/16-bit FPSHIFT FPSHIFT FPFRAME FPFRAME Display FPLINE FPLINE DRDY LCDPWR RED,GREEN,BLUE HRTC Display VRTC IREF IREF FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT Display FPFRAME FPFRAME FPLINE FPLINE DRDY LCDPWR RED,GREEN,BLUE HRTC Display VRTC IREF IREF X23A-A-001-14 Page 15 S1D13505...
Page 22: Figure 3-3: Typical System Diagram (Mc68K Bus 1, 16-Bit 68000)
Figure 3-3: Typical System Diagram (MC68K Bus 1, 16-Bit 68000) MC68030 A[31:21] Decoder FC0, FC1 Decoder A[20:0] D[31:16] R/W# SIZ1 SIZ0 DSACK1# BCLK RESET# Figure 3-4: Typical System Diagram (MC68K Bus 2, 32-Bit 68030) S1D13505 X23A-A-001-14 Oscillator Power Management M/R# FPDAT[15:8] AB[20:1] DB[15:0] S1D13505F00A AB0# WE1# RED,GREEN,BLUE RD/WR# WAIT#...
Page 23: Figure 3-5: Typical System Diagram (Generic Bus)
4/8/16-bit FPSHIFT FPSHIFT Display FPFRAME FPFRAME FPLINE FPLINE DRDY LCDPWR RED,GREEN,BLUE HRTC Display VRTC IREF IREF FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT FPFRAME FPFRAME Display FPLINE FPLINE DRDY LCDPWR RED,GREEN,BLUE HRTC Display VRTC IREF IREF X23A-A-001-14 Page 17 S1D13505...
Page 24: Figure 3-7: Typical System Diagram (Philips Pr31500/Pr31700 Bus)
Page 18 Philips PR31500 /PR31700 A[12:0] D[31:16] /CARDREG /CARDIORD /CARDIOWR /CARDxCSH /CARDxCSL /CARDxWAIT DCLKOUT RESET# Figure 3-7: Typical System Diagram (Philips PR31500/PR31700 Bus) Toshiba TX3912 A[12:0] D[23:16] D[31:24] CARDREG* CARDIORD* CARDIOWR* CARDxCSH* CARDxCSL* CARDxWAIT* DCLKOUT RESET# Figure 3-8: Typical System Diagram (Toshiba TX3912 Bus)
Page 25: Figure 3-9: Typical System Diagram (Power Pc Bus)
4/8/16-bit FPSHIFT FPSHIFT Display FPFRAME FPFRAME FPLINE FPLINE DRDY LCDPWR RED,GREEN,BLUE HRTC Display VRTC IREF IREF FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT FPFRAME FPFRAME Display FPLINE FPLINE DRDY LCDPWR RED,GREEN,BLUE HRTC Display VRTC IREF IREF X23A-A-001-14 Page 19 S1D13505...
Page 26: Internal Description
4.2.3 CPU R/W The CPU R/W block synchronizes the CPU requests for display buffer access. If SwivelView is enabled, the data is rotated in this block. S1D13505 X23A-A-001-14 16-bit FPM/EDO-DRAM Memory...
Page 27: Memory Controller
The DAC is the Digital to Analog converter for analog CRT support. 4.2.11 Power Save The Power Save block contains the power save mode circuitry. 4.2.12 Clocks The Clocks module is the source of all clocks in the chip. Hardware Functional Specification Issue Date: 01/02/02 Page 21 S1D13505 X23A-A-001-14...
Page 28: Pins
AB12 AB11 AB10 128-pin QFP15 surface mount package S1D13505 X23A-A-001-14 82 81 80 79 78 77 76 S1D13505 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32...
Page 29: Pin Description
• For MC68K Bus 2, this pin inputs system address bit 0 (A0). • For Generic Bus, this pin inputs system address bit 0 (A0). • For MIPS/ISA Bus, this pin inputs system address bit 0 (SA0). • For Philips PR31500/31700 Bus, this pin inputs system address bit 0 (A0). Hi-Z •...
Page 30: Vancouver Design Center
RESET# Cell State • For Philips PR31500/31700 Bus, these pins are connected to V • For Toshiba TX3912 Bus, these pins are connected to V • For PowerPC Bus, these pins input the system address bits 15 through 18 (A[15:18]).
Page 31: Vancouver Design Center
• For MIPS/ISA Bus, this pin inputs the system byte high enable signal (SBHE#). CS/TS Hi-Z • For Philips PR31500/31700 Bus, this pin inputs the odd byte access enable signal (/CARDxCSH). • For Toshiba TX3912 Bus, this pin inputs the odd byte access enable signal (CARDxCSH*).
Page 32: Vancouver Design Center
This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#). The S1D13505 needs this signal for early decode of the bus cycle. • For MC68K Bus 1, this pin inputs the read write signal (R/W#).
Page 33: Vancouver Design Center
• For Generic Bus, this pin inputs the read command for the lower data byte (RD0#). • For MIPS/ISA Bus, this pin inputs the memory read signal (MEMR#). • For Philips PR31500/31700 Bus, this pin inputs the memory read Hi-Z command (/RD).
Page 34: Vancouver Design Center
Hi-Z (IOCHRDY); MD5 must be pulled low during reset by the internal pull- down resistor. • For Philips PR31500/31700 Bus, this pin outputs the wait state signal (/CARDxWAIT); MD5 must be pulled low during reset by the internal pull-down resistor.
Page 35: Memory Interface
Configuration Options. Internal pull-down resistors (typical values of 100K at 5V/3.3V respectively) pull the reset states to 0. External pull-up resistors can be used to pull the reset states to 1. See Memory Interface Timing for detailed functionality. Page 29 Description S1D13505 X23A-A-001-14...
Page 36: Vancouver Design Center
Pin Name Type Pin # 58, 60, 62, MA[8:0] 64, 66, 67, 65, 63, 61 MA10 MA11 S1D13505 X23A-A-001-14 Table 5-2: Memory Interface Pin Descriptions (Continued) RESET# Cell State Multiplexed memory address - see Memory Interface Timing for 0utput functionality.
Page 37: Lcd Interface
Analog output for CRT color Red Analog output for CRT color Green Analog output for CRT color Blue Current reference for DAC - see Analog Pins. This pin must be left unconnected if the DAC is not needed. Page 31 Description Description S1D13505 X23A-A-001-14...
Page 38: Miscellaneous
• When MD9 = 0 at rising edge of RESET#, this pin is an Hi-Z if MD[9]=0 active-low Schmitt input used to put the S1D13505 into High if Hardware Suspend mode - see Section 15, “Power Save CS/TS1 MD[10:9]=01 Modes”...
Page 39: Summary Of Configuration Options
011 = Generic 100 = Reserved 101 = MIPS/ISA 110 = PowerPC 111 = PC Card (when MD11 = 1 Philips PR31500/PR31700 or Toshiba TX3912 Bus) Little Endian WAIT# is active high (1 = insert wait state) Memory Address/GPIO configuration: 00 = symmetrical 256K 16 DRAM.
Page 40: Multiple Function Pin Mapping
R/W# WE0# WE0# WE0# WAIT# WAIT# DTACK# DSACK1# RESET# RESET# RESET# RESET# Note The bus signal A0 is not used by the S1D13505 internally. S1D13505 X23A-A-001-14 Table 5-6: CPU Interface Pin Mapping Philips MC68K Generic MIPS/ISA PR31500 Bus 2 /PR31700...
Page 41: Table 5-7: Memory Interface Pin Mapping
Epson Research and Development Vancouver Design Center S1D13505 Sym 256Kx16 Pin Names 2-CAS# 2-WE# MD[15:0] MA[8:0] GPIO3 MA10 MA11 UCAS# UCAS# UWE# LCAS# LCAS# CAS# LWE# RAS# Note All GPIO pins default to input on reset and unless programmed otherwise, should be connected...
Page 42: Table 5-8: Lcd Interface Pin Mapping
Page 36 Monochrome Passive Panel S1D13505 Single Dual Names 4-bit 8-bit 8-bit FPFRAME FPLINE FPSHIFT DRDY FPDAT0 driven 0 FPDAT1 driven 0 FPDAT2 driven 0 FPDAT3 driven 0 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0...
Page 43: Crt Interface
DAC V = 3.3V 1.5k 4.6 mA 2N2222 DAC V DAC V DAC V To CRT DAC V Figure 5-3: External Circuitry for CRT Interface DAC V = 2.7V to 5.5V 4.6 mA LM334 1N457 DAC V Page 37 S1D13505 X23A-A-001-14...
Page 44: C. Characteristics
Output Voltage Storage Temperature Solder Temperature/Time Symbol Parameter Supply Voltage Input Voltage Operating Temperature S1D13505 X23A-A-001-14 Table 6-1: Absolute Maximum Ratings - 0.3 to 6.0 - 0.3 to 6.0 - 0.3 to V + 0.5 - 0.3 to V + 0.5 -65 to 150 260 for 10 sec.
Page 45: Table 6-3: Electrical Characteristics For Vdd = 5.0V Typical
-8mA (Type2) -12mA (Type3) VDD = min 4mA (Type1), 8mA (Type2) 12mA (Type3) CMOS level, V = max CMOS level, V = min CMOS Schmitt, = 5.0V CMOS Schmitt, = 5.0V CMOS Schmitt, = 5.0V Page 39 Units S1D13505 X23A-A-001-14...
Page 46: Table 6-4: Electrical Characteristics For Vdd = 3.3V Typical
Low Level Input Voltage High Level Input Voltage Low Level Input Voltage Hysteresis Voltage Pull Down Resistance Input Pin Capacitance Output Pin Capacitance Bi-Directional Pin Capacitance S1D13505 X23A-A-001-14 Condition Quiescent Conditions VDD = min -2mA (Type1), - 0.3 -4mA (Type2)
Page 47: Table 6-5: Electrical Characteristics For Vdd = 3.0V Typical
-3.5mA (Type2) -5mA (Type3) VDD = min 1.8mA (Type1), 3.5mA (Type2) 5mA (Type3) CMOS level, V = max CMOS level, V = min CMOS Schmitt, = 3.0V CMOS Schmitt, = 3.0V CMOS Schmitt, = 3.0V Page 41 Units S1D13505 X23A-A-001-14...
Page 48: C. Characteristics
D[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001-14 = 3.0V ± 10% and V = 5.0V ± 10% for all inputs must be 5 nsec (10% ~ 90%)
Page 49: Table 7-1: Sh-4 Timing
Vancouver Design Center Note The SH-4 Wait State Control Register for the area in which the S1D13505 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK).
Page 50: Interface Timing
The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. Note The SH-3 Wait State Control Register for the area in which the S1D13505 resides must be set to a non-zero value. S1D13505...
Page 51: Table 7-2: Sh-3 Timing
Rising edge RD# to D[15:0] tri-state (read cycle) If the S1D13505 host interface is disabled, the timing for WAIT# driven is relative to the fall- ing edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later.
Page 52: Mc68K Bus 1 Interface Timing (E.g. Mc68000)
DTACK# D[15:0](write) D[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001-14 Figure 7-3: MC68000 Timing Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02...
Page 53: Table 7-3: Mc68000 Timing
If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of UDS#, LDS# or the first positive edge of CLK after A[20:1], M/R# becomes valid, whichever one is later.
Page 54: Mc68K Bus 2 Interface Timing (E.g. Mc68030)
DSACK1# D[31:16](write) D[31:16](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001-14 Figure 7-4: MC68030 Timing Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02...
Page 55: Table 7-4: Mc68030 Timing
AS# high setup to CLK If the S1D13505 host interface is disabled, the timing for DSACK1# driven high is relative to the falling edge of CS#, AS# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later.
Page 56: Pc Card Interface Timing
-WAIT D[15:0](write) D[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001-14 Figure 7-5: PC Card Timing Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02...
Page 57: Table 7-5: Pc Card Timing
Rising edge of -OE to D[15:0] tri-state (read cycle) If the S1D13505 host interface is disabled, the timing for -WAIT driven low is relative to the falling edge of -OE, -WE or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later.
Page 58: Generic Interface Timing
WAIT# D[15:0](write) D[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001-14 Figure 7-6: Generic Timing Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02...
Page 59: Table 7-6: Generic Timing
Rising edge of RD0#,RD1# to D[15:0] tri-state (read cycle) If the S1D13505 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of RD0#, RD1#, WE0#, WE1# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later.
Page 60: Mips/Isa Interface Timing
IOCHRDY SD[15:0](write) SD[15:0](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001-14 Figure 7-7: MIPS/ISA Timing Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02...
Page 61: Table 7-7: Mips/Isa Timing
SD[15:0] setup to rising edge IOCHRDY# (read cycle) Rising edge of MEMR# toSD[15:0] tri-state (read cycle) If the S1D13505 host interface is disabled, the timing for IOCHRDY driven low is relative to the falling edge of MEMR#, MEMW# or the first positive edge of BUSCLK after LatchA20, SA[19:0], M/R# becomes valid, whichever one is later.
Page 62: Philips Interface Timing (E.g. Pr31500/Pr31700)
Page 56 7.1.8 Philips Interface Timing (e.g. PR31500/PR31700) DCLKOUT ADDR[12:0] -CARDREG -CARDxCSH -CARDxCSL -CARDIORD -CARDIOWR -WE -RD -CARDxWAIT D[31:16](write) D[31:16](read) S1D13505 X23A-A-001-14 Figure 7-8: Philips Timing Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02...
Page 63: Table 7-8: Philips Timing
DCLKOUT after ADDR[12:0] becomes valid, whichever one is later. If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] be- comes valid, whichever one is later.
Page 64: Toshiba Interface Timing (E.g. Tx3912)
Page 58 7.1.9 Toshiba Interface Timing (e.g. TX3912) DCLKOUT ADDR[12:0] CARDREG* CARDxCSH* CARDxCSL* CARDIORD* CARDIOWR* WE* RD* CARDxWAIT* D[31:16](write) D[31:16](read) S1D13505 X23A-A-001-14 Figure 7-10: Toshiba Timing Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 01/02/02...
Page 65: Table 7-10: Toshiba Timing
DCLKOUT after ADDR[12:0] becomes valid, whichever one is later. If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] be- comes valid, whichever one is later.
Page 66: Power Pc Interface Timing (E.g. Mpc8Xx, Mc68040, Coldfire)
TSIZ[0:1], M/R# D[0:15](write) D[0:15](read) Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. S1D13505 X23A-A-001-14 Figure 7-12: Power PC Timing Epson Research and Development Vancouver Design Center t15 t16 Hardware Functional Specification...
Page 67: Table 7-12: Power Pc Timing
CLKOUT to D[0:15] driven (read cycle) D[0:15] valid to TA# falling edge (read cycle) CLKOUT to D[0:15] tri-state (read cycle) Hardware Functional Specification Issue Date: 01/02/02 Table 7-12: Power PC Timing Parameter Page 61 3.0V 5.0V Units 19.7 S1D13505 X23A-A-001-14...
Page 68: Clock Input Requirements
Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) Note When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2). S1D13505 X23A-A-001-14 Figure 7-13: Clock Input Requirement Parameter...
Page 69: Memory Interface Timing
Vancouver Design Center 7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read/Write/Read-Write Timing Memory Clock RAS# CAS# WE# (read) MD (read) WE#(write) MD(write) Hardware Functional Specification Issue Date: 01/02/02 t11 t10 t11 t20 t21 Figure 7-14: EDO-DRAM Read/Write Timing S1D13505 X23A-A-001-14 Page 63...
Page 70: Table 7-15: Edo-Dram Read/Write/Read-Write Timing
Row address hold time (REG[22h] bits 3-2 = 00 or Row address hold time (REG[22h] bits 3-2 = 01) Column address setup time Column address hold time S1D13505 X23A-A-001-14 t10 t11 Figure 7-15: EDO-DRAM Read-Write Timing Table 7-15: EDO-DRAM Read/Write/Read-Write Timing 1.45 t1 - 3...
Page 71: Vancouver Design Center
2.45 t1 - 3 0.45 t1- 3 0.45 t1 - 3 0.45 t1 - 3 0.45 t1 - 3 1.45 t1- 3 t1- 5 0.45 t1 0.45t1 + 21 1 t1 - 3 t1- 5 X23A-A-001-14 Page 65 Units S1D13505...
Page 72: Edo-Dram Cas Before Ras Refresh Timing
RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2 = 10) CAS# pulse width CAS# setup time (REG[22h] bits 3-2 = 00 or 10) CAS# setup time (REG[22h] bits 3-2 = 01) S1D13505 X23A-A-001-14 Clock RAS# CAS# Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing...
Page 73: Vancouver Design Center
2.45 t1 - 3 3 t1 - 3 3.45 t1 - 3 1.45 t1 - 3 2 t1 - 3 2.45 t1 - 3 0.45 t1 - 3 1 t1 - 3 1.45 t1 - 3 Page 67 Units S1D13505 X23A-A-001-14...
Page 74: Edo-Dram Self-Refresh Timing
CAS# setup time (REG[22h] bits 3-2 = 00 or 10) CAS# setup time (REG[22h] bits 3-2 = 01) CAS# precharge time (REG[22h] bits 3-2 = 00) CAS# precharge time (REG[22h] bits 3-2 = 01 or 10) S1D13505 X23A-A-001-14 Stopped for Restarted for...
Page 75: Fpm-Dram Read/Write/Read-Write Timing
Epson Research and Development Vancouver Design Center 7.3.4 FPM-DRAM Read/Write/Read-Write Timing Memory Clock RAS# CAS# WE#(read) MD(read) WE#(write) MD(write) Hardware Functional Specification Issue Date: 01/02/02 t11 t10 t11 t18 t19 Figure 7-18: FPM-DRAM Read/Write Timing Page 69 S1D13505 X23A-A-001-14...
Page 76: Table 7-18: Fpm-Dram Read/Write/Read-Write Timing
RAS# hold time Row address setup time (REG[22h] bits 3-2 = 00) Row address setup time (REG[22h] bits 3-2 = 01) Row address setup time (REG[22h] bits 3-2 = 10) S1D13505 X23A-A-001-14 t10 t11 Figure 7-19: FPM-DRAM Read-Write Timing Table 7-18: FPM-DRAM Read/Write/Read-Write Timing...
Page 77: Vancouver Design Center
0.45 t1 - 3 0.45 t1 - 3 0.45 t1 - 3 t1 - 3 4 t1 - 3 3 t1 - 3 3 t1 - 3 2 t1 - 3 t1- 5 0.45 t1 0.45t1 + 21 X23A-A-001-14 Page 71 Units S1D13505...
Page 78: Fpm-Dram Cas Before Ras Refresh Timing
CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits 3-2 = 00) CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits 3-2 = 01 or 10) S1D13505 X23A-A-001-14 Table 7-19: FPM-DRAM CAS Before RAS Refresh Timing 2.45 t1 - 3 1.45 t1 - 3...
Page 79: Fpm-Dram Self-Refresh Timing
Stopped for suspend mode Figure 7-21: FPM-DRAM Self-Refresh Timing Table 7-20: FPM-DRAM CBR Self-Refresh Timing Parameter Restarted for active mode 2.45 t1 - 1 1.45 t1 - 1 2 t1 1 t1 0.45 t1 - 2 X23A-A-001-14 Page 73 Units S1D13505...
Page 80: Power Sequencing
FPDATA, DRDY active FPLINE, FPSHIFT, FPDATA, DRDY active to LCDPWR, on and FPFRAME active CLKI active to SUSPEND# inactive Note Where T S1D13505 X23A-A-001-14 Table 7-21: LCD Panel Power Off/ Power On Parameter is the period of FPFRAME and T FPFRAME...
Page 81: Power Save Status
Note It is recommended that memory access not be performed after a Power Save Mode has been initiated. Hardware Functional Specification Issue Date: 01/02/02 not allowed Parameter Page 75 allowed Units Frames MCLK MCLK S1D13505 X23A-A-001-14...
Page 82: Display Interface
VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1...
Page 83: Table 7-23: 4-Bit Single Monochrome Passive Lcd Panel A.c. Timing
= [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts Hardware Functional Specification Issue Date: 01/02/02 Parameter note 2 Ts (note 1) note 3 note 4 note 5 t10 + t11 note 6 X23A-A-001-14 Page 77 Units S1D13505...
Page 84: 8-Bit Single Monochrome Passive Lcd Panel Timing
Example timing for a 640x480 panel Figure 7-26: 8-Bit Single Monochrome Passive LCD Panel Timing = Vertical Display Period VNDP = Vertical Non-Display Period = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 1-10...
Page 85: Table 7-24: 8-Bit Single Monochrome Passive Lcd Panel A.c. Timing
= [((REG[05h] bits [4:0]) + 1)*8 - 25] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts Hardware Functional Specification Issue Date: 01/02/02 note 2 note 3 note 5 t10 + t11 note 6 Page 79 Units Ts (note 1) note 4 S1D13505 X23A-A-001-14...
Page 86: 4-Bit Single Color Passive Lcd Panel Timing
Example timing for a 640x480 panel Figure 7-28: 4-Bit Single Color Passive LCD Panel Timing = Vertical Display Period VNDP = Vertical Non-Display Period = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 1-G2...
Page 87: Table 7-25: 4-Bit Single Color Passive Lcd Panel A.c. Timing
= [((REG[05h] bits [4:0]) + 1)*8 - 19] Ts Hardware Functional Specification Issue Date: 01/02/02 Parameter note 2 Ts (note 1) note 3 note 4 note 5 t10 + t11 note 6 0.45 0.45 0.45 0.45 X23A-A-001-14 Page 81 Units S1D13505...
Page 88: 8-Bit Single Color Passive Lcd Panel Timing (Format 1)
Example timing for a 640x480 panel Figure 7-30: 8-Bit Single Color Passive LCD Panel Timing (Format 1) = Vertical Display Period VNDP = Vertical Non-Display Period = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 1-R1...
Page 89: Table 7-26: 8-Bit Single Color Passive Lcd Panel A.c. Timing (Format 1)
= [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts Hardware Functional Specification Issue Date: 01/02/02 Parameter note 2 Ts (note 1) note 3 note 4 note 5 t9 + t10 note 6 note 7 X23A-A-001-14 Page 83 Units S1D13505...
Page 90: 8-Bit Single Color Passive Lcd Panel Timing (Format 2)
Example timing for a 640x480 panel Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2) = Vertical Display Period VNDP = Vertical Non-Display Period = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 1-B3...
Page 91: Table 7-27: 8-Bit Single Color Passive Lcd Panel A.c. Timing (Format 2)
= [((REG[05h] bits [4:0]) + 1)*8 - 28] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 19] Ts Hardware Functional Specification Issue Date: 01/02/02 Parameter note 2 Ts (note 1) note 3 note 4 note 5 note 6 t14 + 2 X23A-A-001-14 Page 85 Units S1D13505...
Page 92: 16-Bit Single Color Passive Lcd Panel Timing
Example timing for a 640x480 panel Figure 7-34: 16-Bit Single Color Passive LCD Panel Timing = Vertical Display Period VNDP = Vertical Non-Display Period = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 1-R1...
Page 93: Table 7-28: 16-Bit Single Color Passive Lcd Panel A.c. Timing
= [(REG[05h] bits [4:0]) + 1)*8 - 27] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts Hardware Functional Specification Issue Date: 01/02/02 Parameter note 2 Ts (note 1) note 3 note 4 note 5 note 6 t14 + 3 X23A-A-001-14 Page 87 Units S1D13505...
Page 94: 8-Bit Dual Monochrome Passive Lcd Panel Timing
Figure 7-36: 8-Bit Dual Monochrome Passive LCD Panel Timing = Vertical Display Period VNDP = Vertical Non-Display Period = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480...
Page 95: Table 7-29: 8-Bit Dual Monochrome Passive Lcd Panel A.c. Timing
= [((REG[05h] bits [4:0]) + 1)*8 - 19] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 10] Ts Hardware Functional Specification Issue Date: 01/02/02 Parameter Units note 2 Ts (note 1) note 3 note 4 note 5 note 6 t14 + 2 X23A-A-001-14 Page 89 S1D13505...
Page 96: 8-Bit Dual Color Passive Lcd Panel Timing
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel = Vertical Display Period VNDP = Vertical Non-Display Period = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 1-G2 1-R 1...
Page 97: Table 7-30: 8-Bit Dual Color Passive Lcd Panel A.c. Timing
= [((REG[05h] bits [4:0]) + 1)*8 - 11] Ts Hardware Functional Specification Issue Date: 01/02/02 Parameter note 2 Ts (note 1) note 3 note 4 note 5 note 6 t14 + t11 0.45 0.45 0.45 0.45 X23A-A-001-14 Page 91 Units S1D13505...
Page 98: 16-Bit Dual Color Passive Lcd Panel Timing
Figure 7-40: 16-Bit Dual Color Passive LCD Panel Timing = Vertical Display Period VNDP = Vertical Non-Display Period = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480...
Page 99: Table 7-31: 16-Bit Dual Color Passive Lcd Panel A.c. Timing
= [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 11] Ts Hardware Functional Specification Issue Date: 01/02/02 Parameter Units note 2 Ts (note 1) note 3 note 4 note 5 note 6 t14 + 2 S1D13505 X23A-A-001-14 Page 93...
Page 100: 16-Bit Tft/D-Tfd Panel Timing
Example Timing for 640x480 panel = Vertical Display Period VNDP = Vertical Non-Display Period = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13505 X23A-A-001-14 VNDP LINE1 HNDP Figure 7-42: 16-Bit TFT/D-TFD Panel Timing = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1...
Page 101: Figure 7-43: Tft/D-Tfd A.c. Timing
Epson Research and Development Vancouver Design Center FPFRAME FPLINE FPLINE DRDY FPSHIFT R[5:1] G[5:0] B[5:1] Note: DRDY is used to indicate the first pixel Hardware Functional Specification Issue Date: 01/02/02 Figure 7-43: TFT/D-TFD A.C. Timing X23A-A-001-14 Page 95 S1D13505...
Page 102: Table 7-32: Tft/D-Tfd A.c. Timing
= [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])*8)+1] Ts = [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])+1)*8 - 2] Ts 10. t17 = [((REG[05h] bits [4:0])+1)*8 - ((REG[06h] bits [4:0])+1)*8 + 2] S1D13505 X23A-A-001-14 Table 7-32: TFT/D-TFD A.C. Timing Parameter 0.45 0.45 0.45...
Page 103: Crt Timing
Figure 7-44: CRT Timing = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = HNDP + HNDP = ((REG[05h] bits [4:0]) + 1)*8Ts Page 97 LINE480 HNDP 1-640 S1D13505 X23A-A-001-14...
Page 104: Figure 7-45: Crt A.c. Timing
VRTC falling edge to FPLINE falling edge phase difference = [((REG[09h] bits 1:0, REG[08h] bits 7:0)+1) + ((REG[0Ah] bits 6:0)+1)] lines = [((REG[0Ch] bits 2:0)+1)] lines = [((REG[06h] bits 4:0)+1)*8] Ts S1D13505 X23A-A-001-14 Figure 7-45: CRT A.C. Timing Parameter Epson Research and Development...
Page 105: Registers
8 Registers 8.1 Register Mapping The S1D13505 registers are memory mapped. The system addresses the registers through the CS#, M/R#, and AB[5:0] input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001.
Page 106: Memory Configuration Registers
Frame Buffer is disabled (REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive (Reg[27h] bits 7-6 = 00). This condition also occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset. For further programming information, see S1D13505 Programming Notes and Examples, document number X23A-G-003-xx.
Page 107: Panel/Monitor Configuration Registers
TFT/D-TFD Panel Data Width Width Size 4-bit 8-bit 16-bit Reserved MOD Rate Bit MOD Rate Bit MOD Rate Bit Page 101 TFT/ Passive Dual/Single LCD Panel Panel Select Select Size 9-bit 12-bit 16-bit Reserved MOD Rate Bit MOD Rate Bit S1D13505 X23A-A-001-14...
Page 108: Vancouver Design Center
The recommended minimum value which should be programmed into this register is 3 (32 pixels). The maximum value which can be programmed into this register is 1Fh, which gives a horizontal non-display period of 256 pixels. Note This register must be programmed such that REG[05h] S1D13505 X23A-A-001-14 Horizontal Horizontal Display Width Display Width...
Page 109: Table 8-4: Fpline Polarity Selection
(REG[06h] + 1) + (REG[07h] bits [3:0] +1) Page 103 HRTC/ HRTC/ FPLINE Start FPLINE Start Position Bit 1 Position Bit 0 HRTC/ HRTC/ FPLINE Pulse FPLINE Pulse Width Bit 1 Width Bit 0 active low active high S1D13505 X23A-A-001-14...
Page 110: Vancouver Design Center
Vertical Non-Display Period Bits [5:0] These bits specify the vertical non-display period. Vertical non-display period (lines) = Vertical Non-Display Period Bits [5:0] + 1 Note This register must be programmed such that REG[0Ah] S1D13505 X23A-A-001-14 Vertical Vertical Vertical Display Display...
Page 111: Table 8-5: Fpframe Polarity Selection
(REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1) Page 105 VRTC/ VRTC/ FPFRAME FPFRAME Start Position Start Position Bit 1 Bit 0 VRTC/ VRTC/ FPFRAME FPFRAME Pulse Width Pulse Width Bit 1 Bit 0 TFT/D-TFD FPFRAME Polarity active low active high S1D13505 X23A-A-001-14...
Page 112: Display Configuration Registers
Simultaneous Display, the Half Frame Buffer Disable, REG[1Bh] bit 0, must be set to 1. This results in a lower contrast on the LCD panel, which may require adjustment. 2. The Line doubling option is not supported with dual panel. S1D13505 X23A-A-001-14 Bit-per-pixel...
Page 113: Table 8-7: Bit-Per-Pixel Selection
8 bpp 15 bpp 16 bpp Reserved Screen 1 Line Screen 1 Line Screen 1 Line Compare Bit 2 Compare Bit 1 Compare Bit 0 Screen 1 Line Screen 1 Line Compare Bit 9 Compare Bit 8 X23A-A-001-14 Page 107 S1D13505...
Page 114: Vancouver Design Center
A combination of this register and the Pixel Panning register (REG[18h]) can be used to uniquely identify the start (top left) pixel within the Screen 2 image stored in the display buffer. See “Display Configuration” for details. S1D13505 X23A-A-001-14 Start Address...
Page 115: Table 8-8: Pixel Panning Selection
Address Offset Bit 1 Offset Bit 0 Memory Memory Address Address Offset Bit 9 Offset Bit 8 Screen 1 Screen 1 Pixel Panning Pixel Panning Bit 1 Bit 0 Bits [3:0] Bits [2:0] Bits [1:0] Bit 0 none S1D13505 X23A-A-001-14...
Page 116: Clock Configuration Register
When this bit = 0, the chip is either powered up, in transition of powering up, or in transition of powering down. See Section 15 Power Save Modes for details. S1D13505 X23A-A-001-14 MCLK Divide...
Page 117: Miscellaneous Registers
(see REG[31h]). For details on Frame Rate calculation see Section 14.2, “Frame Rate Calcu- lation” on page 141. Hardware Functional Specification Issue Date: 01/02/02 Table 8-10: Suspend Refresh Selection DRAM Refresh Type CAS-before-RAS (CBR) refresh Self-Refresh Page 111 No Refresh Half Frame Buffer Disable S1D13505 X23A-A-001-14...
Page 118: Table 8-11: Ma/Gpio Pin Functionality
1 GPIO1 Pin IO Configuration When this bit = 1, the GPIO1 pin is configured as an output pin. When this bit = 0 (default), the GPIO1 pin is configured as an input pin. S1D13505 X23A-A-001-14 MD[4] Status MD[3] Status...
Page 119: Vancouver Design Center
GPO output is set to the inverse of the reset state. For information on the reset state of this pin see “Miscellaneous Interface Pin Descriptions“ on page 32 and “Summary of Power On/Reset Options“ on page 33. Hardware Functional Specification Issue Date: 01/02/02 GPIO3 Pin GPIO2 Pin IO Status IO Status Page 113 GPIO1 Pin IO Status S1D13505 X23A-A-001-14...
Page 120: Table 8-12: Minimum Memory Timing Selection
(REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive (Reg[27h] bits 7-6 = 00). This condition also occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset. For further programming information, see S1D13505 Programming Notes and Examples, docu- ment number X23A-G-003-xx.
Page 121: Table 8-13: Ras#-To-Cas# Delay Timing Select
FPM and N = 1 or 2 if FPM and N = 1.5 = 1 or 2 = 1.5 = 1 or 2 = 1.5 RAS#-to-CAS# Delay (t . These bits specify the number = 1 or 2 X23A-A-001-14 Page 115 S1D13505...
Page 122: Table 8-14: Ras Precharge Timing Select
When this bit = 0 the display FIFO is enabled. Note For further performance increase in dual panel mode disable the half frame buffer (see section 8.2.7) and disable the cursor (see section 8.2.9). S1D13505 X23A-A-001-14 Table 8-14: RAS Precharge Timing Select Reserved...
Page 123: Look-Up Table Registers
7-0 LUT Address Bits [7:0] These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13505 has three 256-posi- tion, 4-bit wide LUTs, one for each of red, green, and blue – refer to “Look-Up Table Architecture”...
Page 124: Ink/Cursor Registers
Position Bit 6 Position Bit 5 Cursor X Position Register 1 REG[29h] Reserved REG[29] bit 7 Reserved This bit must be set to 0. S1D13505 X23A-A-001-14 LUT Data Bit 0 Cursor High Threshold Bit 3 Table 8-17: Ink/Cursor Selection REG[27h]...
Page 125: Vancouver Design Center
Cursor Y Position Bit 1 Position Bit 0 Cursor Y Cursor Y Position Bit 9 Position Bit 8 Cursor Color Cursor Color 0 Bit 1 0 Bit 0 Cursor Color Cursor Color 0 Bit 9 0 Bit 8 S1D13505 X23A-A-001-14...
Page 126: Table 8-18: Ink/Cursor Start Address Encoding
The Ink/Cursor image is stored contiguously. The address offset from the starting word of line n to the starting word of line n+1 is calculated as follows: Ink Address Offset (words) = REG[04h] + 1 Cursor Address Offset (words) = 8 S1D13505 X23A-A-001-14 Cursor Color Cursor Color...
Page 127: Table 8-19: Recommended Alternate Frm Scheme
Bit 4 Bit 3 Table 8-19: Recommended Alternate FRM Scheme Panel Mode Single Passive Alternate Alternate Alternate Bit 2 Bit 1 Bit 0 Register Value 0000 0000 or 1111 1111 0000 0000 or 1111 1010 1111 1111 X23A-A-001-14 Page 121 S1D13505...
Page 128: Display Buffer
Half-Frame Buffer Image Buffer Ink/Cursor Buffer Half-Frame Buffer S1D13505 X23A-A-001-14 Table 9-1: S1D13505 Addressing M/R# Register access: • REG[00h] is addressed when AB[5:0] = 0 • REG[01h] is addressed when AB[5:0] = 1 • REG[n] is addressed when AB[5:0] = n...
Page 129: Image Buffer
6D400h to 7FFFFh. In a 2M byte display buffer, the half-frame buffer resides from 1ED400h to 1FFFFFh. Hardware Functional Specification Issue Date: 01/02/02 = 4 for color panel = 1 for monochrome panel Page 123 S1D13505 X23A-A-001-14...
Page 130: Display Configuration
Byte 1 Byte 2 Host Address 8 bpp: Byte 0 Byte 1 Byte 2 Host Address Figure 10-1: 1/2/4/8 Bit-per-pixel Format Memory Organization S1D13505 X23A-A-001-14 bit 7 bit 0 Display Memory bit 7 bit 0 Display Memory bit 7 bit 0...
Page 131: Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization
Hardware Functional Specification Issue Date: 01/02/02 5-5-5 RGB bit 7 bit 0 Display Memory 5-6-5 RGB bit 7 bit 0 Display Memory represent the red, green, and blue color components. Page 125 = (R Panel Display = (R Panel Display S1D13505 X23A-A-001-14...
Page 132: Image Manipulation
Screen 2 Image Buffer (REG[12h], REG[11h], REG[10h]) REG[18h] bits [3:0] Screen 1 (REG[15h], REG[14h], REG[13h]) REG[18h] bits [7:4] Screen 2 (REG[17h], REG[16h]) S1D13505 X23A-A-001-14 Display Line 0 Line 1 Screen 1 Line (REG[0Fh], REG[0Eh]) Screen 2 ((REG[04h]+1)*8) pixels Figure 10-3: Image Manipulation...
Page 133: Look-Up Table Architecture
Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path 2 Bit-per-pixel Monochrome Mode Green Look-Up Table 256x4 2 bit-per-pixel data from Image Buffer Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path Hardware Functional Specification Issue Date: 01/02/02 4-bit Grey Data 4-bit Grey Data Page 127 S1D13505 X23A-A-001-14...
Page 134: Figure 11-3: 4 Bit-Per-Pixel Monochrome Mode Data Output Path
Page 128 4 Bit-per-pixel Monochrome Mode Green Look-Up Table 256x4 4 bit-per-pixel data from Image Buffer Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path S1D13505 X23A-A-001-14 Epson Research and Development 0000 0001 0010 0011 0100 0101 0110 4-bit Grey Data...
Page 135: Color Modes
Green Look-Up Table 256x4 Blue Look-Up Table 256x4 1 bit-per-pixel data from Image Buffer Figure 11-4: 1 Bit-per-pixel Color Mode Data Output Path Hardware Functional Specification Issue Date: 01/02/02 4-bit Red Data 4-bit Green Data 4-bit Blue Data Page 129 S1D13505 X23A-A-001-14...
Page 136: Figure 11-5: 2 Bit-Per-Pixel Color Mode Data Output Path
Red Look-Up Table 256x4 Green Look-Up Table 256x4 Blue Look-Up Table 256x4 2 bit-per-pixel data from Image Buffer Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path S1D13505 X23A-A-001-14 Epson Research and Development 4-bit Red Data 4-bit Green Data 4-bit Blue Data...
Page 137 0010 0011 0100 0101 0110 4-bit Green Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 4-bit Blue Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 Page 131 S1D13505 X23A-A-001-14...
Page 138: Figure 11-6: 4 Bit-Per-Pixel Color Mode Data Output Path
Figure 11-7: 8 Bit-per-pixel Color Mode Data Output Path 15/16 Bit-per-pixel Color Modes The LUT is bypassed and the color data is directly mapped for this color mode – See “Display Configuration” on page 124. S1D13505 X23A-A-001-14 Epson Research and Development 0000 0000...
Page 139: Ink/Cursor Architecture
• position an Ink buffer between the image and half-frame buffers; • position a Cursor buffer between the image and half-frame buffers; • select from a multiple of Cursor buffers. = (A Panel Display S1D13505 X23A-A-001-14 Page 133...
Page 140: Ink/Cursor Image Manipulation
Note There is no means to set a negative cursor position. If a cursor must be set to a negative position, this must be dealt with through software. S1D13505 X23A-A-001-14 ), selects the color for pixel n as follows: Table 12-2: Ink/Cursor Color Select...
Page 141: Swivelview
The display is refreshed in the following sense: C–A–D–B. The application image is written to the S1D13505 in the following sense: A–B–C–D. The S1D13505 rotates and stores the application image in the following sense: C–A–D–B, the same sense as display refresh.
Page 142: Image Manipulation In Swivelview
• Increment/decrement Display Start Address register in 8 bpp mode: scroll down/up by 2 lines. • Increment/decrement Display Start Address register in 16 bpp mode: scroll down/up by 1 line. • Increment/decrement Pixel Panning register in 8 bpp or 16 bpp mode: scroll down/up by 1 line. S1D13505 X23A-A-001-14 Epson Research and Development...
Page 143: Physical Memory Requirement
The following table summarizes the DRAM size requirement for SwivelView using different panel sizes and display modes. Note that DRAM size for the S1D13505 is limited to either 512K byte or 2M byte. The calculation is based on the minimum required image buffer size. The calculated minimum display buffer size is based on the image buffer and the half-frame buffer only;...
Page 144: Limitations
• Hardware cursor and ink layer images are not rotated – software rotation must be used. Swivel- View must be turned off when the programmer is accessing the sprite or the ink layer. • Split screen images appear side-by-side, i.e. the portrait display is split vertically. • Pixel panning works vertically. S1D13505 X23A-A-001-14 Display Half-Frame...
Page 145: Clocking
MCLK/2 MCLK/2 Page 139 8 bpp 16 bpp MCLK/2 MCLK/3 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/2 MCLK/3 MCLK/2 MCLK/3 MCLK/2 MCLK/3 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/3 MCLK/3 MCLK/2 MCLK/3 MCLK/3 MCLK/4 MCLK/3 MCLK/3 MCLK/2 MCLK/3 S1D13505 X23A-A-001-14...
Page 146: Table 14-2: Maximum Pclk Frequency With Fpm-Dram
• Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. • Dual Color with Half Frame Buffer Enabled. • Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable. S1D13505 X23A-A-001-14 Epson Research and Development Maximum PCLK allowed 1 bpp...
Page 147: Frame Rate Calculation
= ((REG[04h] bits [6:0]) + 1) * 8Ts = ((REG[05h] bits [4:0]) + 1) * 8Ts = given in table below = PCLK Maximum Maximum Frame Minimum Pixel Rate (Hz) Panel Clock HNDP(T Panel (MHz) 13.3 13.3 X23A-A-001-14 Page 141 S1D13505...
Page 148 800x600 @ 16 bpp requires 2M bytes of display buffer for all display types. 800x600 @ 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame buffer is enabled. S1D13505 X23A-A-001-14 Color Depth...
Page 149: Bandwidth Calculation
= 4MCLKs. Memory access Number of MCLKs Half Frame Buffer, color Display @ 1 bpp Display @ 2 bpp Display @ 4 bpp Display @ 8 bpp Display @ 16 bpp is set to 4MCLKs and the S1D13505 X23A-A-001-14 Page 143...
Page 150: Table 14-5: Total # Mclks Taken For Display Refresh
Percentage of non display period for dual panel = (680*242 - 640*240)/680*242) = 6.6% Average Bandwidth = Percentage of non display period * Bandwidth during non display period + (1- Percentage of non display period) * Bandwidth during display period S1D13505 X23A-A-001-14 Table 14-5: Total # MCLKs taken for Display refresh Display...
Page 151: Table 14-6: Theoretical Maximum Bandwidth M Byte/Sec, Cursor/Ink Disabled
6.67 6.27 13.3 6.67 6.67 6.67 16.5 5.17 4.21 16.5 5.24 4.49 16.5 Page 145 8 bpp 16 bpp 6.36 1.79 6.27 0.41 6.67 6.67 6.67 3.94 6.67 6.67 6.27 6.67 6.67 5.24 1.47 5.17 0.34 3.25 5.17 S1D13505 X23A-A-001-14...
Page 152 MCLK = 25MHz Enabled. • Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. • Dual Color Panel with Half Frame Buffer Enabled. S1D13505 X23A-A-001-14 Epson Research and Development Vancouver Design Center Max. Pixel Maximum Bandwidth (M byte/sec)
Page 153: Power Save Modes
Epson Research and Development Vancouver Design Center 15 Power Save Modes Three power save modes are incorporated into the S1D13505 to meet the important need for power reduction in the hand-held device market. Function Display Active? Register Access Possible? Memory Access Possible?
Page 154: Mechanical Data
Page 148 16 Mechanical Data 128-pin QFP15 surface mount package S1D13505 X23A-A-001-14 16.0 ± 0.4 14.0 ± 0.1 Index 0.16 ± 0.1 0.5 ± 0.2 Figure 16-1: Mechanical Drawing QFP15 Epson Research and Development Vancouver Design Center Unit: mm 0~10°...
Page 155: Programming Notes And Examples
S1D13505 Embedded RAMDAC LCD/CRT Controller Programming Notes and Examples Document Number: X23A-G-003-07 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 156 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Programming Notes and Examples X23A-G-003-07 Issue Date: 01/02/05...
Page 157 ......38 ......40 Page 3 S1D13505 X23A-G-003-07...
Page 158 Introduction To SwivelView ......47 S1D13505 SwivelView ......47 Registers .
Page 159 12.1 Introduction ....... 84 12.1.1 Sample code using the S1D13505 HAL API ..... 84 12.1.2 Sample code without using the S1D13505 HAL API .
Page 160 Page 6 Epson Research and Development Vancouver Design Center S1D13505 Programming Notes and Examples X23A-G-003-07 Issue Date: 01/02/05...
Page 161 Vancouver Design Center Table 2-1: S1D13505 Initialization Sequence ......12 Table 4-1: Look-Up Table Configurations ......21 Table 4-2: Recommended LUT Values for 1 Bpp Color Mode .
Page 162 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Programming Notes and Examples X23A-G-003-07 Issue Date: 01/02/05...
Page 163 Figure 11-1: Components needed to build 13505 HAL application ....78 Programming Notes and Examples Issue Date: 01/02/05 List of Figures Page 9 S1D13505 X23A-G-003-07...
Page 164 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Programming Notes and Examples X23A-G-003-07 Issue Date: 01/02/05...
Page 165: Introduction
Vancouver Design Center 1 Introduction This guide describes how to program the S1D13505 Embedded RAMDAC LCD/CRT Controller. The guide presents the basic concepts of the LCD/CRT controller and provides methods to directly program the registers. It explains some of the advanced techniques used and the special features of the S1D13505.
Page 166: Initialization
2 Initialization This section describes how to initialize the S1D13505. Sample code for performing initialization of the S1D13505 is provided in the file init13505.c which is available on the internet at http://www.eea.epson.com. S1D13505 initialization can be broken into three steps. First, enable the S1D13505 controller (if necessary identify the specific controller).
Page 167 Epson Research and Development Vancouver Design Center Table 2-1: S1D13505 Initialization Sequence (Continued) Register Value [06] 0000 0000 FPLINE start position - only required for CRT or TFT/D-TFD [07] 0000 0000 FPLINE polarity set to active high [08] 1110 1111...
Page 168 Page 14 Table 2-1: S1D13505 Initialization Sequence (Continued) Register Value [24] 0000 0000 [26] 0000 0000 [27] 0000 0000 [28] 0000 0000 [29] 0000 0000 The remaining register control operation of the LUT and [2A] 0000 0000 hardware cursor/ink layer. During the chip initialization none of these registers needs to be set.
Page 169: Miscellaneous
Alternate FRM Register (REG[31h]) with the recommended value of FFh may produce more visually appealing output. For further information on the half frame buffer and the Alternate FRM Register see the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. Programming Notes and Examples Issue Date: 01/02/05...
Page 170: Memory Models
3.1 Display Buffer Location The S1D13505 supports either a 512k byte or 2M byte display buffer. The display buffer is memory mapped and can be accessed directly by software. The memory location allocated to the S1D13505 display buffer varies with each individual hardware platform, and is determined by the OEM.
Page 171: Memory Organization For Two Bit-Per-Pixel (4 Colors/Gray Shades)
Pixel 0 Pixel 1 Pixel 1 Bit 0 Bit 3 Bit 2 Page 17 Bit 1 Bit 0 Pixel 3 Pixel 3 Bit 1 Bit 0 Bit 1 Bit 0 Pixel 1 Pixel 1 Bit 1 Bit 0 S1D13505 X23A-G-003-07...
Page 172: Memory Organization For Eight Bit-Per-Pixel (256 Colors/16 Gray Shades)
At this color depth the read-modify-write cycles of the lessor pixel depths are eliminated. Each byte indexes into one of the 256 positions of the Look-Up Table. The S1D13505 LUT supports four bits per primary color, therefore this translates into 4096 possible colors when color mode is selected.
Page 173: Memory Organization For Sixteen Bit-Per-Pixel (65536 Colors/16 Gray Shades)
Figure 3-6: Pixel Storage for 16 Bpp (65536 Colors/16 Gray Shades) in Two Bytes of Display Buffer In 16 bit-per-pixel mode the S1D13505 is capable of generating 65536 colors. The 65536 color pixel is divided into three parts: five bits for red, six bits for green, and five bits for blue.
Page 174: Look-Up Table (Lut)
LUT. Refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx for more detail. The S1D13505 Look-Up Table is used for both the CRT and panel interface and consists of 256 indexed red/green/blue entries. Each entry is 4 bits wide. Two registers, at offsets 24h and 26h, control access to the LUT.
Page 175: Look-Up Table Organization
This intensity can range in value between 0 and 0Fh. • The S1D13505 Look-Up Table is linear; increasing the LUT entry number results in a lighter color or gray shade. For example, a LUT entry of 0Fh into the red LUT entry will result in a bright red output while a LUT entry of 5 would result in a dull red.
Page 176 The selection of which entries are used is automatic. 1 bpp color When the S1D13505 is configured for 1 bpp color mode, the LUT is limited to the first two entries. The two LUT entries can be any two RGB values but are typically set to black-and- white.
Page 177 Vancouver Design Center 4 bpp color When the S1D13505 is configured for 4 bpp color mode the first 16 entries in the LUT are used. Each byte in the display buffer contains two adjacent pixels. The upper and lower nibbles of the byte are used as indices into the LUT.
Page 178 VGA RAMDAC and the S1D13505 LUT. (i.e. VGA levels 0 - 3 map to LUT level 0, VGA levels 4 - 7 map to LUT level 1...). Additionally, the significant bits of the color tables are located at different offsets within their respective bytes.
Page 179 The Look-Up Table is bypassed at this color depth, hence programming the LUT is not necessary. 16 bpp color The Look-Up Table is bypassed at this color depth, hence programming the LUT is not necessary. Programming Notes and Examples Issue Date: 01/02/05 Index Index S1D13505 X23A-G-003-07 Page 25...
Page 180 In 2 bpp gray shade mode the first four green elements are used to provide values to the panel. The remaining indices are unused. Table 4-7: Suggested Values for 2 Bpp Gray Shade Index S1D13505 X23A-G-003-07 Address Green = Required to match CRT to panel...
Page 181 Four bits of green resolves to 16 colors. Now however, each pixel requires two bytes. Programming Notes and Examples Issue Date: 01/02/05 Index Green Blue Required to match CRT to panel Unused entries Page 27 S1D13505 X23A-G-003-07...
Page 182 As with 8 bpp there are limitations to the colors which can be displayed. In this mode the four most significant bits of green are used to set the absolute intensity of the image. Four bits of green resolves to 16 colors. Now however, each pixel requires two bytes. S1D13505 X23A-G-003-07 Epson Research and Development...
Page 183: Advanced Techniques
In addition to the calculated limit the virtual vertical size is limited by the size and location of the half frame buffer and the ink/cursor if present. Programming Notes and Examples Issue Date: 01/02/05 Page 29 or 2048 words. S1D13505 X23A-G-003-07...
Page 184: Registers
To maintain a constant virtual width as color depth changes, the memory address offset must also change. At 1 bpp each word contains 16 pixels, at 16 bpp each word contains one pixel. The formula to determine the value for these registers is: offset = pixels_per_line / pixels_per_word S1D13505 X23A-G-003-07 320x240 Viewport 640x480 “Virtual”...
Page 185: Examples
“virtual” image. After determining the amount of memory used by each line, do a calculation to see if there is enough memory to support the desired number of lines. 1. Initialize the S1D13505 registers for a 320x240 panel. (See Introduction on page 11). 2. Determine the offset register value.
Page 186: Registers
At color depths less than 15 bpp a second register, the pixel pan register, is required for smooth pixel level panning. Internally, the S1D13505 latches different signals at different times. Due to this internal sequence, there is an order in which the start address and pixel pan registers should be accessed during scrolling operations to provide the smoothest scrolling.
Page 187: Examples
Table 5-2: Active Pixel Pan Bits Color Depth (bpp) Pixel Pan bits used bits [3:0] bits [2:0] bits [1:0] bit 0 15/16 Screen 1 Screen 1 Screen 1 Pixel Pan Bit Pixel Pan Bit Pixel Pan Bit Page 33 S1D13505 X23A-G-003-07...
Page 188 2. Increment the start address by the number of words per virtual line. start_address = start_address + words 3. Separate the start address value into three bytes. Write the LSB to register [10h] and the MSB to register [12h]. S1D13505 X23A-G-003-07 320x240 single panel LCD. Epson Research and Development...
Page 189: Split Screen
The Split Screen feature of the S1D13505 allows a programmer to setup a display for such an application. The figure below illustrates setting a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239.
Page 190 1 (i.e. screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located several thousand bytes into the display buffer). While not particularly useful, it is possible to set screen 1 and screen 2 to the same address. S1D13505 X23A-G-003-07 Start Addr...
Page 191: Examples
Write the screen 2 start address registers [15h], [14h] and [13h] with the values 00h, 4Bh and 00h respectively. Programming Notes and Examples Issue Date: 01/02/05 is located immediately after image 1 in the display buffer. Assume a 640x480 display and a color depth of 1 bpp. Page 37 S1D13505 X23A-G-003-07...
Page 192: Lcd Power Sequencing And Power Save Modes
Bit 1 Bit 0 The LCD Enable bit triggers all automatic power sequencing. Setting the LCD Enable bit to 1 causes the S1D13505 to enable the LCD display. The following sequence of events occurs: 1. Confirms the LCD power is disabled.
Page 193: Lcd Power Disable
If your situation requires using the LCD Power Disable bit, see Section 6.1.2, “LCD Power Disable” on page 39 for the correct procedure. The LCD Enable bit (REG[0Dh] bit 0) should be set to 1 to allow the S1D13505 to power-on the LCD using the automatic LCD Power Sequencing.
Page 194: Software Power Save
- This changes the display resolution to minimum (32x1). 3. Set REG[1Ah] bit 0 to 0 - Enables power save mode. 4. Wait delay time (based on new frame rate, see S1D13505 Hardware Functional Spec- ification, document number X23A-A-001-xx) - at this time any clocks can be disabled.
Page 195: Registers
The Power Save Status bit is a read-only status bit which indicates the power-save state of the S1D13505. When this bit returns a 1, the panel is powered-off and the memory is in a suspend memory refresh mode. When this bit returns a 0, the S1D13505 is either powered- on, in transition of powering-on, or in transition of powering-off.
Page 196: Hardware Power Save
Page 42 6.3 Hardware Power Save The S1D13505 supports a hardware suspend power save mode. This mode is not program- mable by software. It is controlled directly by the S1D13505 SUSPEND# pin. While hardware suspend is enabled the following conditions apply.
Page 197: Hardware Cursor/Ink Layer
7 Hardware Cursor/Ink Layer 7.1 Introduction The S1D13505 provides hardware support for a cursor or an ink layer. These features are mutually exclusive and therefore only one or the other may be active at any given time. A hardware cursor improves video throughput in graphical operating systems by off- loading much of the work typically assigned to software.
Page 198: Registers
When ink mode is selected these registers should be set to zero. Cursor X Position bits 9-0 determine the horizontal location of the cursor. With 10 bits of resolution the horizontal cursor range is 1024 pixels. S1D13505 X23A-G-003-07 Cursor High Threshold...
Page 199 Cursor Color 0 bit 9 0 bit 8 Cursor Color Cursor Color 1 bit 1 1 bit 0 Cursor Color Cursor Color 1 bit 9 1 bit 8 Ink/Cursor Ink/Cursor Start Address Start Address bit 1 bit 0 S1D13505 X23A-G-003-07...
Page 200: Limitations
No Top/Left Clipping on Hardware Cursor The S1D13505 does not clip the hardware cursor on the top or left edges of the display. For cursor shapes where the hot spot is not the upper left corner of the image (the hourglass for instance), the cursor image will have to be modified to clip the cursor shape.
Page 201: Swivelview
S1D13x0x products, however, the S1D13505 does not support 180° or 270° rotation. 8.2 S1D13505 SwivelView The S1D13505 provides hardware support for SwivelView in 8, 15 and 16 bpp modes. Enabling SwivelView carries several conditions: • The (virtual) display offset must be set to 1024 pixels.
Page 202: Limitations
SwivelView must be turned off when the programmer is accessing the Hardware Cursor or the Ink Layer. • Split screen images appear side-by-side, i.e. when SwivelView is enabled the screen is split vertically. • Pixel panning works vertically. S1D13505 X23A-G-003-07 Bit-Per-Pixel Bit-Per-Pixel Bit-Per-Pixel...
Page 203: Examples
3. Write the start address during the display enabled portion of the frame. a) loop waiting for vertical non-display (b7 of register [0Ah] high). do register = ReadRegister(0Ah) Programming Notes and Examples Issue Date: 01/02/05 by 4 pixels. while (80h != (register & 80h)); Page 49 S1D13505 X23A-G-003-07...
Page 204 Write the new pixel panning value. register = ReadRegister(18h); register &= F0h; register |= (PixelPan & 0Fh); WriteRegister(18h, register); S1D13505 X23A-G-003-07 while (80h == (register & 80h)); while (80h == (register & 80h)); while (80h != (register & 80h));...
Page 205: Crt Considerations
Vancouver Design Center 9 CRT Considerations 9.1 Introduction The S1D13505 is capable of driving either an LCD panel, or a CRT display, or both simul- taneously. As display devices, panels tend to be lax in their horizontal and vertical timing require- ments.
Page 206: Identifying The S1D13505
Page 52 10 Identifying the S1D13505 The S1D13505 can only be identified once the host interface has been enabled. The steps to identify the S1D13505 are: 1. If using an ISA evaluation board in a PC follow steps a. and b.
Page 207: Hardware Abstraction Layer (Hal)
13505CFG.EXE allows quick customization of a program for a new target display or environment. Using the HAL keeps sample code simpler, although some programmers may find the HAL functions to be limited in their scope, and may wish to program the S1D13505 without using the HAL. 11.2 Contents of the HAL_STRUCT The HAL_STRUCT below is contained in the file “hal.h”...
Page 208: Using The Hal Library
Page 54 Within the Regs array in the structure are all the registers defined in the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. Using the 13505CFG.EXE utility you can adjust the content of the registers contained in HAL_STRUCT to allow for different LCD panel timing values and other default settings used by the HAL.
Page 209 Initialize virtual screen mode setting x and y sizes seVirtMove pan/scroll the virtual screen surface(s) seSetReg Write a Byte value to the specified S1D13505 register seSetWordReg Write a Word value to the specified S1D13505 register seSetDwordReg Write a Dword value to the specified S1D13505 register...
Page 210: Initialization
Description Ink Layer: Power Save: This function registers the S1D13505 device parameters with the HAL library. The device parameters include address range, register values, desired frame rate, etc., and are stored in the HAL_STRUCT structure pointed to by lpHalInfo. Additionally this routine allocates system memory as address space for accessing registers and the display buffer.
Page 211 - operation completed with no problems This routine sets the S1D13505 registers for operation using the default settings. Initialization of the S1D13505 is a two step process consisting of initializing the HAL (seInitHal) and initializing the S1D13505 registers (seSetInit). Unlike the HAL the registers do not necessarily require initialization at program startup and may be initialized as needed (e.g.
Page 212: General Hal Support
Parameters: S1D13505 X23A-G-003-07 This routine sets the S1D13505 registers according to the values contained in the HAL_STRUCT register section. Setting all the registers means that timing, display surface dimensions, and all other aspects of chip operation are set with this call, including loading default values into the color Look-Up Tables (LUTs).
Page 213 Return Value: ERR_OK int seGetMemSize(int DevID, DWORD * pSize) Description: Programming Notes and Examples Issue Date: 01/02/05 For the S1D13505 the return values are currently: ID_S1D13505_REV0 ID_UNKNOWN Other HAL libraries will return their respective controller IDs upon detection of their controller.
Page 214 DevID, UINT * pBytes) Description: Parameters: Return Value: ERR_OK - operation completed with no problems int seGetScreenSize(int DevID, UINT * Width, UINT * Height) Description: S1D13505 X23A-G-003-07 DevID - registered device ID pSize - pointer to a DWORD to receive the size...
Page 215 Return value: ERR_OK int seSelectBusWidth(int DevID, int Width) Description: Parameters: Return Value: ERR_OK Note This call applies to the S1D13505 ISA evaluation cards only. int seGetHostBusWidth(int DevID, int * Width) Description: Parameters: Return Value: ERR_OK int seDisplayEnable(int DevID, BYTE State)
Page 216: Advanced Hal Functions
This function was originally intended for non-PC platforms. Because information on how to access the timers was not always immediately available, we use the frame rate for timing calculations. The S1D13505 registers must be initialized for this function to work correctly.
Page 217 The smallest screen 1 can be set to is one line. This is due to the way the register values are used internally on the S1D13505. Setting the line compare register to zero results in one line of screen 1 being displayed followed by screen 2.
Page 218: Register / Memory Access
Return Value: ERR_OK Note seVirtInit() must be called before calling seVirtMove(). 11.5.3 Register / Memory Access The Register/Memory Access functions provide access to the S1D13505 registers and display buffer through the HAL. int seSetReg(int DevID, int Index, BYTE Value) Description:...
Page 219 - operation completed with no problems This routine writes one or more bytes to the display buffer at the offset specified by Offset. If a count greater than one is specified all bytes will have the same value. Page 65 S1D13505 X23A-G-003-07...
Page 220 Note If offset + (count*4) > memory size, this function will limit the writes to the end of memory. int seReadDisplayByte(int DevID, DWORD Offset, BYTE *pByte) Description: S1D13505 X23A-G-003-07 DevID - registered device ID Offset - offset from start of the display buffer...
Page 221: Color Manipulation
A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue. The color information is stored in the four most significant bits of each byte. DevID - registered device ID pLut - pointer to an array of BYTE lut[16][3] lut[x][0] == RED component Page 67 S1D13505 X23A-G-003-07...
Page 222 DevID, int index, BYTE *pEntry) Description: Parameters: Return Value: ERR_OK int seSetBitsPerPixel(int DevID, UINT BitsPerPixel) Description: S1D13505 X23A-G-003-07 lut[x][1] == GREEN component ut[x][2] == BLUE component Count - the number of LUT entries to write. - operation completed with no problems This routine reads one or more LUT entries and puts the result in the byte array pointed to by pLUT.
Page 223: Drawing
2) factors such as input clock and memory speed will affect the ability to set some color depths. If the requested color depth cannot be set this call will fail This function reads the S1D13505 registers to determine the current color depth and returns the result in pBitsPerPixel. DevID...
Page 224 Description: Parameters: Return Value: ERR_OK int seDrawEllipse(int DevID, long xc, long yc, long xr, long yr, DWORD Color, BOOL SolidFill) S1D13505 X23A-G-003-07 DevID - Registered device ID - horizontal coordinate of the pixel (starting from 0) - vertical coordinate of the pixel (starting from 0) pColor - at 1, 2, 4, and 8 bpp pColor points to an index into the LUT.
Page 225: Hardware Cursor
- unused - operation completed with no problems. Prepares the hardware cursor for use. This consists of determining a location in display buffer for the cursor, setting cursor memory to the transparent color and enabling the cursor. Page 71 S1D13505 X23A-G-003-07...
Page 226 DevID, long x, long y) Description: Parameters: Return Value: ERR_OK int seSetCursorColor(int DevID, int Index, DWORD Color) Description: S1D13505 X23A-G-003-07 When this call returns the cursor is enabled, the cursor image is transparent and ready to be drawn. DevID - a registered device ID...
Page 227 If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel result will be an inversion of the underlying screen color. If 'SolidFill' is specified the interior of the rectangle will be filled with 'Color', otherwise the rectangle is only outlined in 'Color'. Page 73 S1D13505 X23A-G-003-07...
Page 228 Return Value: ERR_OK int seDrawCursorCircle(int DevID, long x, long y, long Radius, DWORD Color, BOOL SolidFill) Description: Parameters: Return Value: ERR_OK S1D13505 X23A-G-003-07 DevID - a registered device ID (x1,y1) - upper left corner of the rectangle (in pixels) (x2,y2)
Page 229: Ink Layer
The functions in this section support the hardware ink layer. Overall these functions are nearly identical to the hardware cursor routines. In fact the same S1D13505 hardware is used for both features which means that only the cursor or the ink layer can be active at any given time.The difference between the hardware cursor and the ink layer is that in cursor...
Page 230 DevID, long x1, long y1, long x2, long y2, DWORD Color, BOOL SolidFill) Description: S1D13505 X23A-G-003-07 Sets the color of the specified ink/cursor index to 'Color'. The user definable hardware cursor colors are sixteen bit 5-6-5 RGB colors.
Page 231 - circle radius (in pixels) Color - a two bit (0 to 3) value to draw the circle with SolidFill - flag to fill the interior of the circle (currently not used) - operation completed with no problems Page 77 S1D13505 X23A-G-003-07...
Page 232: Power Save
- operation completed with no problems Causes the S1D13505 to enter/leave hardware suspend mode. This option in only supported on S1D13505B0B ISA evaluation boards. When hardware suspend mode is engaged the display is disabled and display buffer is inaccessible and the registers and LUT are inaccessible.
Page 233: Building The Libse Library For Sh3 Target Example
The following examples assume that you have a copy of the complete source code for the S1D13505 utilities, including the nmake makefiles, as well as a copy of the GNU Compiler v2.7-96q3a for Hitachi SH3.
Page 234: Building The Hal Library For The Target Example
Hal version %s\n", p1); ** Register the device with the HAL ** NOTE: HalInfo is an instance of HAL_STRUCT and is defined ** in Appcfg.h if (seRegisterDevice(&HalInfo, &DevId) != ERR_OK) S1D13505 X23A-G-003-07 {0, 0, 0}, {0xF0, 0, 0}, {0, 0, 0xF0}...
Page 235 /* Set the LUT to values appropriate to Black, Red, case 2: case 4: case 8: seSetLut(DevId, (BYTE *)&RedBlue- color_red color_blue = 2; break; default: /* 15 or 16 bpp */ color_red Page 81 = 1; = RED16BPP; S1D13505 X23A-G-003-07...
Page 236 0, GREEN16BPP); seSetCursorColor(DevId, 1, BLUE16BPP); seDrawCursorRect(DevId, 0, 0, 63, 63, 1, FALSE); seDrawCursorRect(DevId, 1, 1, 62, 62, 0, TRUE); seCursorOn(DevId); S1D13505 X23A-G-003-07 color_blue = BLUE16BPP; break; printf("\r\nERROR: Unable to draw line\r\n"); return -1; printf("\r\nERROR: Unable to draw box\r\n");...
Page 237 Epson Research and Development Vancouver Design Center ** Delay for 2 seconds seDelay(DevId, (DWORD)2); seMoveCursor(DevId, width-1-63, 0); return 0; Programming Notes and Examples Issue Date: 01/02/05 Move the cursor Page 83 S1D13505 X23A-G-003-07...
Page 238: Vancouver Design Center
12 Sample Code 12.1 Introduction There are two included examples of programming the S1D13505 color graphics controller. First is a demonstration using the HAL library and the second without. These code samples are for example purposes only. Lastly, are three header files that may make some of the structures used clearer.
Page 239 ** will use that location from here on. Programming Notes and Examples Issue Date: 01/02/05 case ERR_OK: break; case HAL_DEVICE_ERR: printf("\nERROR: Too many devices exit(1); default: printf("\nERROR: Could not regis- exit(1); printf("\nERROR: Did not detect SED1355."); exit(1); printf("\nERROR: Could not initialize device."); exit(1); Page 85 S1D13505 X23A-G-003-07...
Page 240: Sample Code Without Using The S1D13505 Hal Api
** the cursor to 101,101. seDrawCursorRect(Device, 0, 0, 63, 63, 1, FALSE); seMoveCursor(Device, 101, 101); exit(0); 12.1.2 Sample code without using the S1D13505 HAL API **=========================================================================== INIT1355.C - sample code demonstrating the initialization of the SED1355. Beta release 2.0 The code in this example will perform initialization to the following specification: - 640 x 480 dual 16-bit color passive panel.
Page 241 0x00, 0xA0, 0xF0, 0x00, 0xB0, 0xF0, 0x00, 0xE0, 0xF0, 0x00, 0xF0, 0xF0, 0x00, 0xF0, 0xD0, 0x00, 0xF0, 0xC0, 0x00, 0xF0, 0x90, 0x00, 0xF0, 0x80, 0x00, 0xF0, 0x50, 0x00, 0xF0, 0x40, 0x00, 0xF0, 0x10, 0x00, 0xF0, 0x00, Page 87 S1D13505 X23A-G-003-07...
Page 242 0x50, 0x50, 0xF0, 0x80, 0x80, 0xF0, 0x90, 0x90, 0xF0, 0xC0, 0xC0, 0xF0, 0xD0, 0xD0, 0xF0, ** REGISTER_OFFSET points to the starting address of the SED1355 registers S1D13505 X23A-G-003-07 Epson Research and Development 0x20, 0xF0, 0x00, 0x30, 0xF0, 0x00, 0x60, 0xF0, 0x00,...
Page 243 ** Register 1: Memory Configuration - 4 ms refresh, EDO *(pRegs + 0x01) = 0x30; Programming Notes and Examples Issue Date: 01/02/05 ((unsigned char *) 0x14000000) ((unsigned char *) 0x4000000) 0x200000 /* 0000 0000 */ /* 1000 0000 */ /* 0011 0000 */ Page 89 S1D13505 X23A-G-003-07...
Page 244 ** Registers 8-9: Vertical Display Height (VDP) - 480 lines. 480/2 - 1 = 239t = 0xEF *(pRegs + 0x08) = 0xEF; *(pRegs + 0x09) = 0x00; S1D13505 X23A-G-003-07 /* 0010 0100 */ /* 0010 0110 */ /* 0000 0000 */...
Page 245 /* 0000 0000 */ /* 0000 0000 */ /* 0000 0000 */ /* 0000 0000 */ /* 0000 0000 */ /* 0000 0000 */ /* 0100 0000 */ /* 0000 0001 */ /* 0000 0000 */ Page 91 S1D13505 X23A-G-003-07...
Page 246 (rgb = 0; rgb < 3; rgb++) *(pRegs + 0x26) = *pLUT; pLUT++; ** Register 27: Ink/Cursor Control - disable ink/cursor *(pRegs + 0x27) = 0x00; S1D13505 X23A-G-003-07 Epson Research and Development /* 0000 0001 */ /* 0000 0000 */...
Page 247 /* 0000 0000 */ /* 0000 0000 */ /* 0001 1111 */ /* 0000 0000 */ /* 1110 0000 */ /* 0000 0111 */ /* 0000 0000 */ /* 0000 0000 */ /* 0000 1101 */ Page 93 S1D13505 X23A-G-003-07...
Page 248 *(pRegs + 0x2F) = 0xFF; ** Draw a hollow rectangle around the cursor. pTmp = pCursor; for (lpCnt = 0; lpCnt < 16; lpCnt++) *pTmp = 0x55; pTmp++; S1D13505 X23A-G-003-07 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/05...
Page 249: Header Files
The following header files are included as they help to explain some of the structures used when programming the S1D13505. The following header file defines the structure used to store the configuration information contained in all utilities using the S1D13505 HAL API. /********************************************************************************/ 1355 HAL INF (do not remove) HAL_STRUCT Information generated by 1355CFG.EXE...
Page 250 25175, /* ClkI (kHz) 8000, /* BusClk (kHz) 0xE00000, /* Register Address */ 0xC00000, /* Display Address */ /* Panel Frame Rate (Hz) */ /* CRT Frame Rate (Hz) */ S1D13505 X23A-G-003-07 0x00, 0x4F, 0x03, 0x00, 0x00, 0x00, 0x0D, 0xFF,...
Page 251 /* Ras Access Charge time in ns */ /* RAS Access Charge time in ns */ /* Host CPU bus width in bits */ The following header file defines the S1D13505 HAL registers. /*=========================================================================== HAL_REGS.H Created 1998, Epson Research & Development Vancouver Design Center.
Page 252 #define REG_ALTERNATE_FRM ** WARNING!!! MAX_REG must be the last available register!!! #define MAX_REG #endif __HAL_REGS_H__ */ The following header file defines the structures used in the S1D13505 HAL API. **=========================================================================== ** HAL.H **--------------------------------------------------------------------------- Created 1998, Epson Research & Development Vancouver Design Center.
Page 253 #define MAKEWORD(lo, hi) ((WORD)(((WORD)(lo)) | (((WORD)(hi)) << 8)) ) #endif #ifndef MAKELONG #define MAKELONG(lo, hi) ((long)(((WORD)(lo)) | (((DWORD)((WORD)(hi))) << 16))) #endif #ifndef TRUE Programming Notes and Examples Issue Date: 01/02/05 // Disable the 'single line comment' warning. Page 99 S1D13505 X23A-G-003-07...
Page 254 #define DPFL(exp) printf(#exp " = %x\n", exp) #else #define DPF(exp) ((void)0) #define DPF1(exp) ((void)0) #define DPFL(exp) ((void)0) #endif /*-------------------------------------------------------------------------*/ enum S1D13505 X23A-G-003-07 " #exp2 "=%d\n", exp1, exp2) Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/05...
Page 255 #define MIN_NON_DISP_X #define MAX_NON_DISP_X #define MIN_NON_DISP_Y #define MAX_NON_DISP_Y /******************************************* Programming Notes and Examples Issue Date: 01/02/05 /* No error, call was successful. */ /* General purpose failure. /* */ /* Function was called with invalid parameter. */ Page 101 S1D13505 X23A-G-003-07...
Page 256 /******************************************* * Definitions for sePowerSaveMode() *******************************************/ #define PWR_CBR_REFRESH #define PWR_SELF_REFRESH #define PWR_NO_REFRESH /*************************************************************************/ enum DISP_MODE_LCD = 0, DISP_MODE_CRT, DISP_MODE_SIMULTANEOUS, S1D13505 X23A-G-003-07 0x00 0x01 0x02 0x00 0x01 0x02 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/05...
Page 257 /* Memory speed in ns */ /* Ras to Cas Delay in ns */ /* Ras Precharge time in ns */ /* Ras Access Charge time in ns */ /* Host CPU bus width in bits */ FUNCTION PROTO-TYPES TRUE Page 103 S1D13505 X23A-G-003-07...
Page 258 DWORD addr, BYTE val, DWORD count ); int seWriteDisplayWords( int seReserved1, DWORD addr, WORD val, DWORD count ); int seWriteDisplayDwords( int seReserved1, DWORD addr, DWORD val, DWORD count ); /*------------------------------- Drawing ---------------------------------*/ S1D13505 Programming Notes and Examples X23A-G-003-07 Issue Date: 01/02/05...
Page 259 DWORD color, BOOL SolidFill ); /*------------------------------ Color ------------------------------------*/ int seSetLut( int seReserved1, BYTE *pLut, int count ); int seGetLut( int seReserved1, BYTE *pLut, int count ); Programming Notes and Examples Issue Date: 01/02/05 Page 105 S1D13505 X23A-G-003-07...
Page 260 *fmt, ... ); int sePutChar( int seReserved1, int ch ); int seGetChar( void ); /*--------------------------- XLIB Support --------------------------------*/ int seGetLinearDispAddr(int seReserved1, DWORD *pDispLogicalAddr); int InitLinear(int seReserved1); #endif /* _HAL_H_ */ S1D13505 Programming Notes and Examples X23A-G-003-07 Issue Date: 01/02/05...
Page 261: Appendix A Supported Panel Values
7-0 set vertical display height bits 9-8 set vertical non-display period set 8 bpp and LCD enable set MCLK and PCLK divide disable half frame buffer set Look-Up Table address to 0 load Look-Up Table X23A-G-003-07 Page 107 S1D13505...
Page 262 REG[03h] REG[04h] REG[05h] REG[06h] REG[07h] REG[08h] REG[09h] REG[0Ah] REG[0Bh] REG[0Ch] REG[0Dh] REG[19h] REG[1Bh] REG[24h] REG[26h] S1D13505 X23A-G-003-07 Mono 8-Bit Color 8-Bit Color 16-Bit 640X480@60Hz 640X480@60Hz 640X480@60Hz 0001 0010 0001 0110 0010 0110 0000 0000 0000 0000 0000 0000 0100 1111...
Page 263 IO Status Notes 1 These bits are used to identify the S1D13505. For the S1D13505 the product code should be 3. The host interface must be enabled before reading this register (set REG[1B] b7=0). 2 N/A bits should be written 0.
Page 264 S1D13505F00A Register Summary 3 DRAM Refresh Rate Select DRAM Refresh Example Refresh Example period for CLKI Frequency Rate Select Bits Rate for CLKI = 256 refresh cycles at Divisor [2:0] 33MHz CLKI = 33MHz 520 kHz 0.5 ms 260 kHz 1 ms 130 kHz 2 ms...
Page 265 S1D13505 Embedded RAMDAC LCD/CRT Controller 13505CFG Configuration Program Document Number: X23A-B-001-04 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 266 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505CFG Configuration Program X23A-B-001-04 Issue Date: 01/03/29...
Page 267 13505CFG ..........5 S1D13505 Supported Evaluation Platforms ..... . 5 Installation .
Page 268 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505CFG Configuration Program X23A-B-001-04 Issue Date: 01/03/29...
Page 269: 13505Cfg
13505CFG is an interactive Windows® 9x/ME/NT/2000 program that calculates register values for a user defined S1D13505 configuration. The configuration information can be used to directly alter the operating characteristics of the S1D13505 utilities or any program built with the Hardware Abstraction Layer (HAL) library. Alternatively, the configuration information can be saved in a variety of text file formats for use in other applications.
Page 270: Installation
Page 6 Installation Create a directory for 13505cfg.exe and the S1D13505 utilities. Copy the files 13505cfg.exe and panels.def to that directory. Panels.def contains configuration infor- mation for a number of panels and must reside in the same directory as 13505cfg.exe.
Page 271: 13505Cfg Configuration Tabs
13505CFG provides a series of tabs which can be selected at the top of the main window. Each tab allows the configuration of a specific aspect of S1D13505 operation. The tabs are labeled “General”, “Preference”, “Memory”, “Clocks”, “Panel”, “CRT”, and “Registers”.
Page 272 Page 8 Register Address Display Buffer Address S1D13505 X23A-B-001-04 Epson Research and Development The physical address of the start of register decode space (in hexadecimal). This field is automatically set according to the Decode Address unless the “User-Defined” decode address is selected.
Page 273: Preferences Tab
The selections “None” and “Panel” are always available. The S1D13505 SwivelView feature is capable of rotating the image displayed on an LCD panel 90° in a clockwise direction. This sets the initial orientation of the panel.
Page 274: Memory Tab
DRAM manufacturer’s specification unless otherwise noted. Selects the access time of the DRAM. The S1D13505 evaluation boards use 50ns DRAM. Selects the memory type, either Extended Data Out (EDO) or Fast Page Mode (FPM). The S1D13505 evaluation boards use EDO DRAM.
Page 275 If this option is selected, the memory contents are lost during power save. Selects the amount of DRAM available for the display buffer. The S1D13505 evaluation boards have 2M bytes of DRAM installed. Page 11 S1D13505 X23A-B-001-04...
Page 276: Clocks Tab
The Clocks tab is intended to simplify the selection of input clock frequencies and the source of internal clocking signals. For further information regarding clocking and clock sources, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. In automatic mode the values are calculated based on either the LCD or CRT tab settings.
Page 277 Epson Research and Development Vancouver Design Center The S1D13505 may use as many as three input clocks or as few as one. The more clocks used the greater the flexibility of choice in display type and memory speed. CLKI BUSCLK...
Page 278 Divide Timing MCLK Source Divide Timing S1D13505 X23A-B-001-04 Epson Research and Development These settings select the signal source and input clock divisor for the CRT pixel clock (CRT PCLK). The CRT PCLK source is CLKI. Specifies the divide ratio of CLKI to derive the CRT PCLK.
Page 279: Panel Tab
Panel Data Width Panel Type EL Support Panel Dimensions HRTC/FPLINE The S1D13505 supports many panel types. This tab allows configuration of most panel settings such as panel dimensions, type and timings. Panel Type EL Support 13505CFG Configuration Program Issue Date: 01/03/29...
Page 280 Selects color STN panel format 2. This option is specif- ically for configuring 8-bit color STN panels. See the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx, for description of format 1 / format 2 data formats. Most new panels use the format 2 data format.
Page 281 Higher frame rates correspond to smaller horizontal and vertical non-display values, or higher frequencies. Select the desired Pixel Clock (in MHz) from the drop- down list. The range of frequencies displayed is dependent on settings selected on the Clocks tab. Page 17 S1D13505 X23A-B-001-04...
Page 282 Epson Research and Development These settings allow fine tuning the TFT line pulse parameters and are only available when the selected panel type is TFT. Refer to S1D13505 Hardware Functional Specification, document number X23A-A- 001-xx for a complete description of the FPLINE pulse settings.
Page 283: Crt/Tv Tab
(height) of the images. If both displays are the same resolution, select “Normal”. Otherwise, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx for information on selecting the best option.
Page 284: Registers Tab
Page 20 Registers Tab The Registers tab allows viewing and direct editing the S1D13505 register values. Scroll up and down the list of registers and view their configured value. Individual register settings may be changed by double-clicking on the register in the listing. Manual changes to the registers are not checked for errors, so caution is warranted when directly editing these values.
Page 285: 13505Cfg Menus
This may be used to quickly arrive at a starting point for register configuration. The only requirement is that the file being opened must contain a valid S1D13505 HAL library information block. 13505CFG supports a variety of executable file formats. Select the file type(s) 13505CFG should display in the Files of Type drop-down list and then select the filename from the list and click on the Open button.
Page 286: Save
Note When “Save As” is selected then an exact duplicate of the file as opened by the “Open” option is created containing the new configuration information. S1D13505 X23A-B-001-04 Epson Research and Development Vancouver Design Center...
Page 287: Configure Multiple
ISA, MPC and IDP based programs at the same time for a new panel type, the physical addresses for each are retained. This feature is primarily intended for the test lab where multiple hardware configurations exist and are being tested. 13505CFG Configuration Program Issue Date: 01/03/29 Page 23 S1D13505 X23A-B-001-04...
Page 288: Export
“Preview” button starts Notepad with a copy of the configuration file about to be saved. When the C Header File for S1D13505 WinCE Drivers option is selected as the export type, additional options are available and can be selected by clicking on the Options button.
Page 289: Enable Tooltips
This “Help” menu item is actually a hotlink to the Epson Research and Development website. Selecting “Help” then “ERD on the Web” starts the default web browser and points it to the ERD product web site. The latest software, drivers, and documentation for the S1D13505 is available at this website. About 13505CFG Selecting the “About 13505CFG”...
Page 290 Page 26 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505CFG Configuration Program X23A-B-001-04 Issue Date: 01/03/29...
Page 291 S1D13505 Embedded RAMDAC LCD/CRT Controller 13505SHOW Demonstration Program Document Number: X23A-B-002-05 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 292 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505SHOW Demonstration Program X23A-B-002-05 Issue Date: 01/02/02...
Page 293 Vancouver Design Center 13505SHOW 13505SHOW is designed to demonstrate and test some of the S1D13505 display capabilities. The program can cycle through all the color depths and display a pattern showing all available colors, or the user can specify a color depth and display configuration.
Page 294 13505SHOW Examples The 13505SHOW demonstration program is designed to both demonstrate and test some of the features of the S1D13505. Some examples follow showing how to use the program in both instances. Using 13505SHOW For Demonstration To show color patterns which must be manually stepped through all bit-per-pixel modes, type the following: The program will display 16 bit-per-pixel mode.
Page 295 16 bit-per-pixel screen. To exit the program after using “/read”, press ESC and wait for a couple of seconds (the keystroke is checked after reading a full screen). 13505SHOW Demonstration Program Issue Date: 01/02/02 13505SHOW b=[mode] 13505SHOW /p 13505SHOW /s 13505SHOW b=8 /g 13505SHOW b=16 /read Page 5 S1D13505 X23A-B-002-05...
Page 296 “Color” from the “Panel” dialog box if you want the CRT to show color. • For simultaneous display, select both “/lcd” and “/crt”. • If the “b=” option is not used, 13505SHOW will cycle through all available bit-per-pixel modes. S1D13505 X23A-B-002-05 Epson Research and Development...
Page 297 13505CFG configuration program. ERROR: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly.
Page 298 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505SHOW Demonstration Program X23A-B-002-05 Issue Date: 01/02/02...
Page 299 S1D13505 Embedded RAMDAC LCD/CRT Controller 13505SPLT Display Utility Document Number: X23A-B-003-03 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 300 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505SPLT Display Utility X23A-B-003-03 Issue Date: 01/02/02...
Page 301 Epson Research and Development Vancouver Design Center 13505SPLT 13505SPLT demonstrates S1D13505 split screen capability by showing two different areas of display memory on the screen simultaneously. Screen 1 shows horizontal bars and Screen 2 shows vertical bars. Screen 1 memory is located at the start of the display buffer. Screen 2 memory is located immedi- ately after Screen 1 in the display buffer.
Page 302 Press <ESC> to exit the program. Comments • When using a PC with the S5U13505 evaluation board, the PC must not have more than 12M bytes of system memory. S1D13505 X23A-B-003-03 enables manual split screen operation no argument enables automatic split screen operation...
Page 303 Program Messages ERROR: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Too many devices registered.
Page 304 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505SPLT Display Utility X23A-B-003-03 Issue Date: 01/02/02...
Page 305 S1D13505 Embedded RAMDAC LCD/CRT Controller 13505VIRT Display Utility Document Number: X23A-B-004-04 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 306 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505VIRT Display Utility X23A-B-004-04 Issue Date: 01/02/02...
Page 307 Vancouver Design Center 13505VIRT 13505VIRT demonstrates the virtual display capability of the S1D13505. A virtual display is where the image to be displayed is larger than the physical display device (CRT or LCD). 13505VIRT uses panning and scrolling to allow the display device to show a “window” into the entire image.
Page 308 Embedded platform: execute 13505virt and at the prompt, type the command line argument. Where: The following keyboard commands are for navigation within the program. Manual mode: Automatic and Manual modes: S1D13505 X23A-B-004-04 panning and scrolling is performed manually no argument for manual mode, specifies the width of the virtual...
Page 309 Program Messages ERROR: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Too many devices registered.
Page 310 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505VIRT Display Utility X23A-B-004-04 Issue Date: 01/02/02...
Page 311 S1D13505 Embedded RAMDAC LCD/CRT Controller 13505PLAY Diagnostic Utility Document Number: X23A-B-005-04 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 312 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13550 13505PLAY Diagnostic Utility X23A-B-005-04 Issue Date: 01/02/02...
Page 313 Vancouver Design Center 13505PLAY 13505PLAY is a diagnostic utility which allows the user to read/write to all the S1D13505 Registers, Look-Up Tables and Display Buffer. 13505PLAY is similar to the DOS DEBUG program; commands are received from the standard input device, and output is sent to the standard output device (console for Intel, terminal for embedded platforms).
Page 314 Page 4 Usage PC platform: at the prompt, type 13505play [/?]. Embedded platform: execute 13505play and at the prompt, type the command line argument. Where: /? displays program version information. The following commands are valid within the 13505PLAY program. b 8|16 f[w] addr1 addr2 data .
Page 315 Epson Research and Development Vancouver Design Center p 1|0 r[w] addr [count] w[w] addr data . . . x[w] index [data] 13505PLAY Example Type "13505PLAY" to start the program. Type "?" for help. Type "i" to initialize the registers. Type "xa" to display the contents of the registers. Type "x 5"...
Page 316 “results.” Example: Create an ASCII text file that contains the commands i, xa, and q. ; This file initializes the S1D13505 and reads the registers. ; Note: after a semicolon (;), all characters on a line are ignored.
Page 317 Program Messages WARNING: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Failed to change to ?? mode.
Page 318 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13550 13505PLAY Diagnostic Utility X23A-B-005-04 Issue Date: 01/02/02...
Page 319 S1D13505 Embedded RAMDAC LCD/CRT Controller 13505BMP Demonstration Program Document Number: X23A-B-006-04 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 320 Page 0 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505BMP Demonstration Program X23A-B-006-04 Issue Date: 01/02/02...
Page 321 Vancouver Design Center 13505BMP 13505BMP is a demonstration utility used to show the S1D13505 display capabilities by rendering bitmap images on the display. The program will display any bitmap in Windows BMP file format and then exit. 13505BMP also loads images to demonstrate the hardware cursor and ink layer.
Page 322 Image Color white black any other color S1D13505 X23A-B-006-04 /mouse use mouse to move hardware cursor (press ESC to exit program) /noclear don’t clear display buffer memory...
Page 323 • Prior to selecting the “/mouse” option, a valid mouse driver must be loaded. • If x and y coordinates are not specified for the Hardware Cursor, the Hardware Cursor will be displayed starting in the top left corner (position x=0,y=0). 13505BMP Demonstration Program Issue Date: 01/02/02 Page 3 S1D13505 X23A-B-006-04...
Page 324 13505CFG configuration program. ERROR: Did not detect S1D13505. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Insufficient memory for ?? bit-per-pixel.
Page 325 The Ink Layer BMP image must always have a color depth of four bit-per-pixel. ERROR: Could not change to ?? bit-per-pixel. The HAL library detected that the requested color depth (bit-per-pixel) will violate the S1D13505 hardware specification for clocks. To reprogram the clocks, run 13505CFG and select the desired color depth (bit-per-pixel).
Page 326 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505BMP Demonstration Program X23A-B-006-04 Issue Date: 01/02/02...
Page 327 S1D13505 Embedded RAMDAC LCD/CRT Controller 13505PWR Software Suspend Power Sequencing Utility Document Number: X23A-B-007-03 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 328 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 13505PWR Software Suspend Power Sequencing Utility X23A-B-007-03 Issue Date: 01/02/02...
Page 329 Vancouver Design Center 13505PWR 13505PWR is a diagnostic utility used to test some of the power save capabilities of the S1D13505. 13505PWR enables or disables the software suspend mode, hardware suspend mode, and the LCD, allowing testing of the power sequencing in each mode.
Page 330 To disable hardware suspend mode, type the following: 13505PWR /hardware /disable To enable the LCD, type the following: 13505PWR /lcd /enable To disable the LCD, type the following: 13505PWR /lcd /disable S1D13505 X23A-B-007-03 /hardware | /lcd] [/enable selects software suspend /software selects hardware suspend (PC only)
Page 331 Program Messages ERROR: Did not detect S1D13505. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Unknown command line argument.
Page 332 There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505F00A device. A S1D13505 device was not found at the configured addresses. Check the configuration address using the 13505CFG configuration program. S1D13505...
Page 333 S1D13505 Embedded RAMDAC LCD/CRT Controller Windows® CE 2.x Display Drivers Document Number: X23A-E-001-06 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 334 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Windows® CE 2.x Display Drivers X23A-E-001-06 Issue Date: 01/05/25...
Page 335 Vancouver Design Center WINDOWS® CE 2.x DISPLAY DRIVERS The Windows CE display driver is designed to support the S1D13505 Embedded RAMDAC LCD/CRT Controller running under the Microsoft Windows CE 2.x operating system. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no rotation), and 8 and 16 bit-per-pixel SwivelView™...
Page 336 Click on “Shortcut” and replace the string “DEMO1” under the entry “Target” with “DEMO7”. Click on “OK” to finish. 5. Create a sub-directory named S1D13505 under x:\wince\platform\cepc\drivers\dis- play. 6. Copy the source code to the S1D13505 subdirectory. S1D13505 X23A-E-001-06 Epson Research and Development Vancouver Design Center 2.0.
Page 337 Epson Research and Development Vancouver Design Center 7. Edit the file x:\wince\platform\cepc\drivers\display\dirs and add S1D13505 into the list of directories. 8. Edit the file PLATFORM.BIB (located in x:\wince\platform\cepc\files) to set the de- fault display driver to the file EPSON.DLL (EPSON.DLL will be created during the build in step 13).
Page 338 640x480 LCD panel with a color depth of 8 bpp in SwivelView 0° (landscape) mode: ; Default for EPSON Display Driver ; 640x480 at 8 bits/pixel, LCD display, no rotation ; Useful Hex Values ; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0 [HKEY_LOCAL_MACHINE\Drivers\Display\S1D13505] "Width"=dword:280 "Height"=dword:1E0 "Bpp"=dword:8 “ActiveDisp”=dword:1 “Rotation”=dword:0 11.
Page 339 6. Make an S1D13505 directory under x:\wince\platform\cepc\drivers\display, and copy the S1D13505 driver source code into x:\wince\platform\cepc\drivers\dis- play\S1D13505. 7. Edit the file x:\wince\platform\cepc\drivers\display\dirs and add S1D13505 into the list of directories. 8. Edit the file x:\wince\platform\cepc\files\platform.bib and make the following two changes: a.
Page 340 13505CFG, refer to the 13505CFG Configuration Program User Manual, document number X23A-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13505 WinCE Drivers”. Save the new configuration as MODE0.H in x:\wince\platform\cepc\drivers\display\S1D13505, replacing the original configura- tion file.
Page 341 --”Build Epson for x86”. 13. Type BLDDEMO <ENTER> at the command prompt of the “Build Epson for x86” window to generate a Windows CE image file (NK.BIN). Windows® CE 2.x Display Drivers Issue Date: 01/05/25 Page 9 S1D13505 X23A-E-001-06...
Page 342 Edit CONFIG.SYS on the hard drive to contain only the following line: c. Edit AUTOEXEC.BAT on the hard drive to contain the following lines: d. Copy NK.BIN and HIMEM.SYS to c:\. e. Boot the system. S1D13505 X23A-E-001-06 device=a:\himem.sys mode com1:9600,n,8,1 loadcepc /B:9600 /C:1 c:\nk.bin...
Page 343 Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13505 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.
Page 344 To select which display mode the display driver should use upon boot, add the following lines to your PLATFORM.REG file: [HKEY_LOCAL_MACHINE\Drivers\Display\S1D13505] “Width”=dword:280 “Height”=dword:1E0 “Bpp”=dword:8 “Rotation”=dword:0...
Page 345 • At this time, the drivers have been tested on the x86 CPUs and have been run with version 2.0 of the ETK, Platform Builder v2.1x. Windows® CE 2.x Display Drivers Issue Date: 01/05/25 Page 13 S1D13505 X23A-E-001-06...
Page 346 Page 14 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Windows® CE 2.x Display Drivers X23A-E-001-06 Issue Date: 01/05/25...
Page 347 S1D13505 Embedded RAMDAC LCD/CRT Controller Wind River WindML v2.0 Display Drivers Document Number: X23A-E-002-03 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 348 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Wind River WindML v2.0 Display Drivers X23A-E-002-03 Issue Date: 01/04/06...
Page 349 The source code is written for portability and contains functionality for most features of the S1D13505. Source code modification is required to provide a smaller, more efficient driver for mass production (e.g. CRT support may be removed for products not requiring a CRT).
Page 350 The configuration program 13505CFG can be used to build a new mode0.h file. If building for 8 bpp, place the new mode0.h file in the directory “x:\13505\8bpp\File”. If building for 16 bpp, place the new mode0.h file in “x:\13505\16bpp\File”. S1D13505 X23A-E-002-03 mkboot a: bootrom_uncmp Epson Research and Development Vancouver Design Center Wind River WindML v2.0 Display Drivers...
Page 351 From a command prompt change to the directory “x:\Tornado\host\x86-win32\bin” and run the batch file torvars.bat. Next, change to the directory “x:\Tornado\tar- get\src\ugl” and type the command: 7. Open the S1D13505 workspace. From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and select the file “x:\13505\8bpp\13505.wsp” (or “x:\13505\16bpp\13505.wsp”).
Page 352 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Wind River WindML v2.0 Display Drivers X23A-E-002-03 Issue Date: 01/04/06...
Page 353 S1D13505 Embedded RAMDAC LCD/CRT Controller Wind River UGL v1.2 Display Drivers Document Number: X23A-E-003-02 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 354 Page 2 S1D13505 X23A-E-003-02 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Wind River UGL v1.2 Display Drivers Issue Date: 01/02/05...
Page 355 Wind River’s UGL v1.2. The drivers provide support for both 8 and 16 bit-per-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13505. Source code modification is required to provide a smaller, more efficient driver for mass production.
Page 356 13505CFG can be used to build a new mode0.h file. If building for 8 bpp, place the new mode0.h file in “x:\13505\8bpp\File”. If building for 16 bpp, place the new mode0.h file in “x:\13505\16bpp\File”. S1D13505 X23A-E-003-02 mkboot a: bootrom_uncmp...
Page 357 Mode0.h should be created using the configuration utility 13505CFG. For more infor- mation on 13505CFG, see the 13505CFG Configuration Program User Manual, docu- ment number X23A-B-001-xx available at www.erd.epson.com. 6. Open the S1D13505 workspace. From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and select the file “x:\13505\8bpp\13505.wsp” (or “x:\13505\16bpp\13505.wsp”).
Page 358 Page 6 S1D13505 X23A-E-003-02 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Wind River UGL v1.2 Display Drivers Issue Date: 01/02/05...
Page 359 S1D13505 Embedded RAMDAC LCD/CRT Controller Windows® CE 3.x Display Drivers Document Number: X23A-E-006-01 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 360 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Windows® CE 3.x Display Drivers X23A-E-006-01 Issue Date: 01/05/17...
Page 361 Vancouver Design Center WINDOWS® CE 3.x DISPLAY DRIVERS The Windows CE 3.x display driver is designed to support the S1D13505 Embedded RAMDAC LCD/CRT Controller running the Microsoft Windows CE operating system, version 3.0. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no rotation), and 8 and 16 bit-per-pixel SwivelView™...
Page 362 Click the OK button. 6. Add the environment variable CEPC_DDI_S1D13X0X. a. From the Platform menu, select “Settings”. b. Select the “Environment” tab. c. In the Variable box, type “CEPC_DDI_S1D13X0X”. S1D13505 X23A-E-006-01 Epson Research and Development Vancouver Design Center Windows® CE 3.x Display Drivers...
Page 363 Click the Set button. Click the OK button. 7. Create a new directory S1D13505, under x:\wince300\platform\cepc\drivers\display, and copy the S1D13505 driver source code into this new directory. 8. Add the S1D13505 driver component. a. From the Platform menu, select “Insert | User Component”.
Page 364 X23A-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13505 WinCE Drivers”. Save the new configuration as MODE0.H in the \wince300\platform\cepc\drivers\display, replacing the original configuration file. 12. From the Platform window, click on ParameterView Tab. Show the tree for MY- PLATFORM Parameters by clicking on the ‘+’...
Page 365 CEPC_DDI_S1D13X0X=1 4. Generate the build environment by calling cepath.bat. 5. Create a new folder called S1D13505 under x:\wince300\platform\cepc\drivers\dis- play, and copy the S1D13505 driver source code into x:\wince300\platform\cepc\driv- ers\display\S1D13505. 6. Edit the file x:\wince300\platform\cepc\drivers\display\dirs and add S1D13505 into the list of directories.
Page 366 X23A-B-001-xx, available at www.erd.epson.com After selecting the desired configuration, export the file as a “C Header File for S1D13505 WinCE Drivers”. Save the new configuration as MODE0.H in the \wince300\platform\cepc\drivers\display, replacing the original configuration file. 9. Edit the file PLATFORM.REG to match the screen resolution, color depth, and rota- tion information in MODE.H.
Page 367 10. Delete all the files in the x:\wince300\release directory and delete the file x:\wince300\platform\cepc\*.bif 11. Type BLDDEMO <ENTER> at the command prompt to generate a Windows CE image file. The file generated will be x:\wince300\release\nk.bin. Windows® CE 3.x Display Drivers Issue Date: 01/05/17 Page 9 S1D13505 X23A-E-006-01...
Page 368 Edit CONFIG.SYS on the hard drive to contain only the following line: c. Edit AUTOEXEC.BAT on the hard drive to contain the following lines: d. Copy NK.BIN and HIMEM.SYS to c:\. e. Boot the system. S1D13505 X23A-E-006-01 device=a:\himem.sys mode com1:9600,n,8,1 loadcepc /B:9600 /C:1 c:\nk.bin...
Page 369 Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13505 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.
Page 370 To select which display mode the display driver should use upon boot, add the following lines to your PLATFORM.REG file: [HKEY_LOCAL_MACHINE\Drivers\Display\S1D13505] “Width”=dword:280 “Height”=dword:1E0 “Bpp”=dword:8 “Rotation”=dword:0...
Page 371 OEM must also configure the display driver to never use off-screen memory. • Ensure that display memory never loses power. Windows® CE 3.x Display Drivers Issue Date: 01/05/17 Page 13 S1D13505 X23A-E-006-01...
Page 372 To enable or disable the use of off-screen memory, edit the file: x:\wince300\platform\cepc\driv- ers\display\S1D13505\sources. In SOURCES, there is a line which, when uncom- mented, will instruct Windows CE to use off-screen display memory (if sufficient...
Page 373 Windows CE is shut down. If dis- play memory is kept powered up (set the S1D13505 in powersave mode), then the dis- play data will be maintained and this step can be skipped.
Page 374 • At this time, the drivers have been tested on the x86 CPUs and have been built with Plat- form Builder v3.00. S1D13505 X23A-E-006-01 Epson Research and Development Vancouver Design Center Windows®...
Page 375 S1D13505 Embedded RAMDAC LCD/CRT Controller SDU1355B0C Rev. 1.0 ISA Bus Evaluation Board User Manual Document Number: X23A-G-004-05 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 376 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X23A-G-004-05 Issue Date: 01/02/05...
Page 377 ......14 ....15 Page 3 S1D13505 X23A-G-004-05...
Page 378 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X23A-G-004-05 Issue Date: 01/02/05...
Page 379: List Of Figures
S1D13505B00C Schematic Diagram (4 of 4) ..........22 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual Issue Date: 01/02/05 List of Tables List of Figures Page 5 S1D13505 X23A-G-004-05...
Page 380 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X23A-G-004-05 Issue Date: 01/02/05...
Page 381: Introduction
Implemented using the S1D13505 Embedded RAMDAC LCD/CRT Controller, the S5U13505B00C is designed for the ISA bus environment. It also provides CPU/Bus interface connectors for non-ISA bus support. For more information regarding the S1D13505, refer to the S1D13505 Hardware Functional Speci- fication, document number X23A-A-001-xx. 1.1 Features •...
Page 382: Installation And Configuration
Page 8 2 Installation and Configuration The S1D13505 has 16 configuration inputs MD[15:0] which are read on the rising edge of RESET#. Inputs MD[5:1] are fully configurable on this evaluation board for different host bus selections; one eight-position DIP switch is provided for this purpose. All remaining configuration inputs are hard- wired.
Page 383: Lcd Interface Pin Mapping
Epson Research and Development Vancouver Design Center 3 LCD Interface Pin Mapping S1D13505 Connector Pin Names Pin No. 9-bit FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPSHIFT DRDY FPLINE FPFRAME 2-26...
Page 384: Cpu/Bus Interface Connector Pinouts
Connector Pin No. S1D13505 X23A-G-004-05 Table 4-1: CPU/BUS Connector (H1) Pinout Comments Connected to DB0 of the S1D13505 Connected to DB1 of the S1D13505 Connected to DB2 of the S1D13505 Connected to DB3 of the S1D13505 Ground Ground Connected to DB4 of the S1D13505...
Page 385 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual Issue Date: 01/02/05 Table 4-2: CPU/BUS Connector (H2) Pinout Comments Connected to AB0 of the S1D13505 Connected to AB1 of the S1D13505 Connected to AB2 of the S1D13505 Connected to AB3 of the S1D13505...
Page 386: Host Bus Interface Pin Mapping
Page 12 5 Host Bus Interface Pin Mapping S1D13505 SH-3 SH-4 Pin Names AB20 AB[16:13] A[19:13] A[19:13] AB[12:1] A[12:1] A[12:1] DB[15:0] D[15:0] D[15:0] WE1# WE1# WE1# M/R# BUSCLK CKIO CKIO RD/WR# RD/WR# RD/WR# WE0# WE0# WE0# WAIT# WAIT# RESET# RESET#...
Page 387: Technical Description
F80000h in order to enable a 16-bit ISA environment. This must be done prior to initializing the S1D13505. Failure to do so will result in the S1D13505 being configured as a 16-bit device (de- fault, power-up), with the ISA Bus interface (supported through the PAL (U4)) configured for an 8-bit interface.
Page 388 Voltage lines are provided on the header strips. • For the ISA bus, a 22V10 PAL (U4, socketed) is currently used to provide the S1D13505 CS# (pin 4), M/R# (pin 5) and other decode logic signals. This functionality must now be provided externally.
Page 389: Dram Support
Refer to Table 3-1 “LCD Signal Connector (J6)” on page 9 for connection information. 6.7 Color Passive LCD Panel Support The S1D13505 directly supports 4, 8 and 16-bit, dual and single, color passive LCD panels. All the necessary signals are provided on the 40-pin ribbon cable header J6. The interface signals on the cable are alternated with grounds to reduce crosstalk and noise.
Page 390: Color Tft/D-Tfd Lcd Panel Support
When supporting an 18-bit TFT/D-TFD panel, the S1D13505 can display 64K of a possible 256K colors. A maximum 16 of the possible 18 bits of LCD data are available from the S1D13505. Refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx for details.
Page 391: Cpu/Bus Interface Header Strips
Vancouver Design Center 6.13 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of the S1D13505 are connected to the header strips H1 and H2 for easy interface to a CPU, or bus other than ISA. Refer to Table 4-1 “CPU/BUS Connector (H1) Pinout” on page 10 and Table 4-2 “CPU/BUS Connector (H2) Pinout”...
Page 392: Parts List
C12,C13,C18,C25,C27,C28,C29 C9,C30 C14,C19 C15,C16,C17 C21,C22,C23,C24 D1,D2,D3 JP1,JP2 L1,L2,L3,L4,L5,L7 Q1,Q3” R1,R2,R21,R26,R30,R31,R32,R33,R 34,R35 R5,R6,R7 R11,R12,R13,R14,R15,R16,R17,R18, R19,R20 R28,R27 S1D13505 X23A-G-004-05 Part Value 0.1uF 0.01uF 1uF 6V 47uF 6V 4.7uF 50V 56uF 35V 4.7uF 16V BAV99 H1,H2 HEADER 17X2 HEADER 3 VGA connector AT CON-A...
Page 393 Designation U7,U8,U9 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual Issue Date: 01/02/05 Part Value MT4C1M16E5DJS-5 PAL22V10-15 RD-0412 EPN001 74AHC244 LT1117CM-3.3 Page 19 Description 50ns self-refresh EDO DRAM Xentek RD-0412 Xentek EPN001 “5V to 3.3V regulator, 800mA” S1D13505 X23A-G-004-05...
Page 394: Schematic Diagrams
Page 20 8 Schematic Diagrams S1D13505 X23A-G-004-05 Figure 1: S1D13505B00C Schematic Diagram (1 of 4) S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual Epson Research and Development Vancouver Design Center Issue Date: 01/02/05...
Page 395 Epson Research and Development Vancouver Design Center S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual Issue Date: 01/02/05 DC_OUT VOUT_ADJ REMOTE DC_IN Figure 2: S1D13505B00C Schematic Diagram (2 of 4) Page 21 DC_OUT DC_OUT VOUT_ADJ DC_IN DC_IN S1D13505 X23A-G-004-05...
Page 396 Page 22 Epson Research and Development Vancouver Design Center Figure 3: S1D13505B00C Schematic Diagram (3 of 4) S1D13505 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X23A-G-004-05 Issue Date: 01/02/05...
Page 397 Epson Research and Development Vancouver Design Center S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual Issue Date: 01/02/05 Figure 4: S1D13505B00C Schematic Diagram (4 of 4) Page 23 S1D13505 X23A-G-004-05...
Page 398 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual X23A-G-004-05 Issue Date: 01/02/05...
Page 399 S5U13505-D9000 Evaluation Board User Manual Document Number: X23A-G-002-04 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 400 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13505-D9000 Evaluation Board User Manual X23A-G-002-04 Issue Date: 01/02/05...
Page 401 Features ..........8 S1D13505 Embedded RAMDAC LCD/CRT Controller ....8 2.1.1...
Page 402 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13505-D9000 Evaluation Board User Manual X23A-G-002-04 Issue Date: 01/02/05...
Page 403 Epson Research and Development Vancouver Design Center Table 2-1: LCD Connector Pinout ........10 Table 2-2: Touchscreen Header (TS1) Pinout .
Page 404 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13505-D9000 Evaluation Board User Manual X23A-G-002-04 Issue Date: 01/02/05...
Page 405: Introduction
S5U13505-D9000 Evaluation Board is used to provide a color LCD/CRT solution for the Windows CE environment. Reference S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. D9000 Development System, Hardware User Manual - Hitachi. Evaluation Board User Manual Issue Date: 01/02/05...
Page 406: Features
RAMDAC allowing simultaneous display of both the CRT and LCD displays. In this design, the S1D13505 has a 3.3V supply voltage for both logic and the embedded RAMDAC. For complete details on register functionality and programming, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx, and the S1D13505 Programming Notes and Examples, document number X23A-G-003-xx.
Page 407: Lcd Display Support
Epson Research and Development Vancouver Design Center 2.1.2 LCD Display Support The S1D13505 provides a wide range of flexibility for display type and resolution. Display types include: • 4/8-bit monochrome passive. • 4/8/16-bit color passive. • 9/12/18-bit Active matrix TFT/D-TFD.
Page 408 Page 10 Pin # S1D13505F00A Pin Names 9-bit FPDAT[0] FPDAT[1] FPDAT[2] FPDAT[3] FPDAT[4] FPDAT[5] FPDAT[6] FPDAT[7] FPDAT[8] FPDAT[9] FPDAT[10] FPDAT[11] FPDAT[12] FPDAT[13] FPDAT[14] FPDAT[15] FPSHIFT 35 or 38 DRDY FPLINE FPFRAME 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26 LCDBACK# LCDVCC...
Page 409: Touchscreen Support
"Platform II Audio/Touch" peripheral board. Pinout assignment is described in the table below. 2.1.4 CRT Support The S1D13505 has an embedded RAMDAC and provides complete one-chip CRT support. Refer to the Programmer’s Notes and Examples, document number X23A-G-003-xx, for programming details.
Page 410 Page 12 LCDPWR is an output signal which follows a pre-defined power-up/power-down sequence designed to protect the LCD panel from damage caused by the power supply being enabled in the absence of control signals. Determine the panel’s specific power requirements and set the potentiometer accordingly before connecting the panel.
Page 411: D9000 Specifics
Evaluation Board User Manual Issue Date: 01/02/05 Table 3-1: Connectors Pinout for Channel A7 Channel A7 S1D13505 Signal Pin # SmXY BCLK Page 13 FPGA Signal S1D13505 Signal dc5v DC5V dc3v DC3V dc3v...
Page 412 S5U13505-D9000 X23A-G-002-04 Channel A7 S1D13505 Signal Pin # Epson Research and Development Vancouver Design Center FPGA Signal S1D13505 Signal chA7p34 chA7p33 chA7p32 chA7p31 Evaluation Board User Manual Issue Date: 01/02/05...
Page 413 Evaluation Board User Manual Issue Date: 01/02/05 Table 3-2: Connectors Pinout for Channel A6 Channel A6 S1D13505 Signal Pin # SmXY WE0# RD/WR# WAIT# Page 15 FPGA Signal S1D13505 Signal dc5v DC5V dc3v...
Page 414 S5U13505-D9000 X23A-G-002-04 Channel A6 S1D13505 Signal Pin # M/R# WE1# RESET# Epson Research and Development Vancouver Design Center FPGA Signal S1D13505 Signal chA6p34 chA6p33 chA6p32 chA6p31 Evaluation Board User Manual...
Page 415: Memory Address (Cs#, M/R#) Decoding
Vancouver Design Center 3.1.2 Memory Address (CS#, M/R#) Decoding The S1D13505 is a memory-mapped device for both the registers and the display buffer access. The specific memory address is solely controlled by the CS# and M/R# decode logic. The memory space requirements are: •...
Page 416: Parts List
Page 18 4 Parts List Item # Reference C1,C2,C3,C4,C5,C6,C7, C8,C9,C11,C21,C26,C27,C29, C34,C35,C37,C38, C39,C40 C10,C24,C25,C32,C33 C22,C30 D1,D2,D3 FPS2,LCDVCC1 JP2,JP3,JP4,JP5 LCD1 L1,L2,L3,L4,L5 R1,R2,R5,R6,R7,R8,R17 R9,R10,R11 R12,R13 R18,R19,R20,R27 S5U13505-D9000 X23A-G-002-04 Part 0.1uF 0.1uF ceramic capacitor 10uF 10uF tantalum capacitor 47uF/10V 47uF/10V tantalum capacitor 22uF/63V 22uF/63V electrolytic, aluminum can capacitor 10uF/63V 10uF/63V electrolytic, aluminum can capacitor 4.7uF...
Page 417: Schematic Diagrams
Epson Research and Development Vancouver Design Center 5 Schematic Diagrams Figure 5-1: S5U13505-D9000 Schematic Diagram (1 of 3) Evaluation Board User Manual Issue Date: 01/02/05 Page 19 S5U13505-D9000 X23A-G-002-04...
Page 418 Page 20 S5U13505-D9000 X23A-G-002-04 Figure 5-2: S5U13505-D9000 Schematic Diagram (2 of 3) Epson Research and Development Vancouver Design Center DC_OUT VOUT_ADJ REMOTE DC_IN Evaluation Board User Manual Issue Date: 01/02/05...
Page 419 Epson Research and Development Vancouver Design Center Figure 5-3: S5U13505-D9000 Schematic Diagram (3 of 3) Evaluation Board User Manual Issue Date: 01/02/05 Page 21 S5U13505-D9000 X23A-G-002-04...
Page 420: Component Placement
Page 22 Epson Research and Development Vancouver Design Center 6 Component Placement Figure 6-1: Component Placement S5U13505-D9000 Evaluation Board User Manual X23A-G-002-04 Issue Date: 01/02/05...
Page 421: Power Consumption
S1D13505 Embedded RAMDAC LCD/CRT Controller Power Consumption Document Number: X23A-G-006-03 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 422 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Power Consumption X23A-G-006-03 Issue Date: 01/02/05...
Page 423 • Internal CLK divide: internal registers allow the input clock to be divided before going to the internal logic blocks – the higher the divide, the lower the power consumption. There are two power save modes in the S1D13505: Software and Hardware SUSPEND. The power consumption of these modes is affected by various system design variables.
Page 424 LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the S1D13505 can be configured to be an extremely power-efficient LCD Controller with high performance and flexibility.
Page 425 S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the Philips MIPS PR31500/PR31700 Processor Document Number: X23A-G-001-07 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 426 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Philips MIPS PR31500/PR31700 Processor X23A-G-001-07 Issue Date: 01/02/05...
Page 427 Interfacing to the PR31500/PR31700 ......8 S1D13505 Host Bus Interface ......9 PR31500/PR31700 Host Bus Interface Pin Mapping .
Page 428 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Philips MIPS PR31500/PR31700 Processor X23A-G-001-07 Issue Date: 01/02/05...
Page 429 Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping ....9 Table 4-1: S1D13505 Configuration for Direct Connection..... . 12 Table 4-2: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection .
Page 430 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Philips MIPS PR31500/PR31700 Processor X23A-G-001-07 Issue Date: 01/02/05...
Page 431: Introduction
1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the Philips MIPS PR31500/PR31700 Processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 432: Interfacing To The Pr31500/Pr31700
2 Interfacing to the PR31500/PR31700 The Philips MIPS PR31500/PR31700 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the S1D13505 connects to the PR31500/PR31700 processor. The S1D13505 can be successfully interfaced using one of the following configurations: •...
Page 433: S1D13505 Host Bus Interface
The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the PR31500/PR31700 microprocessor. The PR31500/PR31700 host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset, the bus interface signals assume their selected configuration.
Page 434: Pr31500/Pr31700 Host Bus Interface Signals
When the S1D13505 is configured to operate with the PR31500/PR31700, the host interface requires the following signals: • BUSCLK is a clock input required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and should be driven by the PR31500/PR31700 bus clock output DCLKOUT.
Page 435: Direct Connection To The Philips Pr31500/Pr31700
Vancouver Design Center 4 Direct Connection to the Philips PR31500/PR31700 The S1D13505 was specifically designed to support the Philips MIPS PR31500/PR31700 processor. When configured, the S1D13505 will utilize one of the PC Card slots supported by the processor. 4.1 Hardware Description In this example implementation, the S1D13505 occupies one PC Card slot and resides in the Attribute and IO address range.
Page 436: S1D13505 Configuration
The S1D13505 also has internal CLKI dividers providing additional flexibility. 4.2 S1D13505 Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
Page 437: Memory Mapping And Aliasing
Register 3 bit CARD1IOEN (or CARD2IOEN if slot 2 is used). As a result, the PR31500/PR31700 sees the S1D13505 on its PC Card slot as described in the table below. Table 4-2: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection...
Page 438: System Design Using The It8368E Pc Card Buffer
5 System Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple-function IO buffers, the S1D13505 can be interfaced so as to share one of the PC Card slots. 5.1 Hardware Description...
Page 439: It8368E Configuration
IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13505 this is not necessary as the Direct Connection described in Section 4, “Direct Connection to the Philips PR31500/PR31700” on page 11 can be used.
Page 440: Software
Page 16 6 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source.
Page 441: References
Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. • Epson Research and Development, Inc., S1D13505 Programming Notes and Examples, Document Number X23A-G-003-xx. 7.2 Document Sources • Philips Electronics Website: http://www-us2.semiconductors.philips.com.
Page 442: Technical Support
20/F., Harbour Centre Temasek Avenue #36-00 25 Harbour Road Millenia Tower Wanchai, Hong Kong Singapore, 039192 Tel: 2585-4600 Tel: 337-7911 Fax: 2827-4346 Fax: 334-2716 Interfacing to the Philips MIPS PR31500/PR31700 Processor Epson Research and Development Vancouver Design Center Issue Date: 01/02/05...
Page 443 S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the PC Card Bus Document Number: X23A-G-005-06 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 444 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the PC Card Bus X23A-G-005-06 Issue Date: 01/02/05...
Page 445 Memory Access Cycles ....... . . 8 S1D13505 Host Bus Interface ......11 PC Card Host Bus Interface Pin Mapping PC Card Host Bus Interface Signals .
Page 446 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the PC Card Bus X23A-G-005-06 Issue Date: 01/02/05...
Page 447 Figure 2-2: PC Card Write Cycle ........10 Figure 4-1: Typical Implementation of PC Card to S1D13505 Interface ....14...
Page 448 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the PC Card Bus X23A-G-005-06 Issue Date: 01/02/05...
Page 449: Introduction
1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the PC Card (PCMCIA) bus. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 450: Interfacing To The Pc Card Bus
D[7:0]. If both CE1# and CE2# are driven low, a 16-bit word transfer takes place. If only CE2# is driven low, an odd byte transfer occurs on data lines D[15:8]. S1D13505 X23A-G-005-06 Epson Research and Development...
Page 451 Figure 2-1: illustrates a typical memory access read cycle on the PC Card bus. A[25:0] REG# CE1# CE2# WAIT# Hi-Z D[15:0] Transfer Start Interfacing to the PC Card Bus Issue Date: 01/02/05 ADDRESS VALID Figure 2-1: PC Card Read Cycle Page 9 Hi-Z DATA VALID Transfer Complete S1D13505 X23A-G-005-06...
Page 452 Figure 2-2: illustrates a typical memory access write cycle on the PC Card bus. A[25:0] REG# CE1# CE2# WAIT# Hi-Z D[15:0] Transfer Start S1D13505 X23A-G-005-06 ADDRESS VALID DATA VALID Figure 2-2: PC Card Write Cycle Epson Research and Development Vancouver Design Center Hi-Z Transfer Complete...
Page 453: S1D13505 Host Bus Interface
The S1D13505 implements a 16-bit PC Card (PCMCIA) host bus interface which is used to interface to the PC Card bus. The PC Card host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration. For details on S1D13505 configuration, see Section 4.2, “S1D13505 Hardware Configuration”...
Page 454: Pc Card Host Bus Interface Signals
The S1D13505 PC Card host bus interface requires the following signals from the PC Card bus. • BUSCLK is a clock input which is required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
Page 455: Pc Card To S1D13505 Interface
The S1D13505 provides a “glueless” interface to the PC Card bus except for the following. • The RESET# signal on the S1D13505 is active low and must be inverted to support the active high RESET provided by the PC Card interface.
Page 456 D[15:0] WAIT# Note: When connecting the S1D13505 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: Typical Implementation of PC Card to S1D13505 Interface...
Page 457: S1D13505 Hardware Configuration
Vancouver Design Center 4.2 S1D13505 Hardware Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
Page 458: Register/Memory Mapping
Page 16 4.4 Register/Memory Mapping The S1D13505 is a memory mapped device. The internal registers require 47 bytes and are mapped in the lower PC Card memory address space starting at zero.The display buffer requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card address space (ranging from 200000h to 3FFFFFh).
Page 459: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source.
Page 460: References
• PC Card (PCMCIA) Standard, March 1997 • Epson Research and Development, Inc., S1D13505 Hardware Functional Specification, Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S1D13505 Programming Notes and Examples, Document Number X23A-G-003-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx.
Page 461: Technical Support
Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd.
Page 462 Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the PC Card Bus X23A-G-005-06 Issue Date: 01/02/05...
Page 463 S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the NEC VR4102/VR4111™ Microprocessors Document Number: X23A-G-007-06 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 464 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC VR4102/VR4111™ Microprocessors X23A-G-007-06 Issue Date: 01/02/05...
Page 465 LCD Memory Access Cycles ......9 S1D13505 Host Bus Interface ......10 Host Bus Interface Pin Mapping .
Page 466 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC VR4102/VR4111™ Microprocessors X23A-G-007-06 Issue Date: 01/02/05...
Page 467 Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles ......9 Figure 4-1: NEC VR4102/VR4111 to S1D13505 Configuration Schematic ....12 Interfacing to the NEC VR4102/VR4111™...
Page 468 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC VR4102/VR4111™ Microprocessors X23A-G-007-06 Issue Date: 01/02/05...
Page 469: Introduction
1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the NEC V The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 470: Interfacing To The Vr4102/Vr4111
CPU. A 16M byte block of memory is assigned for the LCD controller and its own chip select and ready signals are available. Word or byte accesses are controlled by the system high byte signal (SHB#). S1D13505 X23A-G-007-06 Epson Research and Development Vancouver Design Center Interfacing to the NEC VR4102/VR4111™...
Page 471: Lcd Memory Access Cycles
LCD controller interface. TCLK ADD[25:0] SHB# LCDCS# WR#,RD# D[15:0] (write) D[15:0] (read) LCDRDY Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles Interfacing to the NEC VR4102/VR4111™ Microprocessors Issue Date: 01/02/05 VALID VALID Hi-Z Page 9 Hi-Z VALID S1D13505 X23A-G-007-06...
Page 472: S1D13505 Host Bus Interface
MIPS/ISA Host Bus Interface which is most suitable for direct connection to the VR4102/VR4111 microprocessor. The MIPS/ISA host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Page 473: Host Bus Interface Signals Descriptions
The S1D13505 MIPS/ISA Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13505 Host Bus Interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
Page 474: Vr4102/Vr4111 To S1D13505 Interface
DAT[15:0] BUSCLK Note: When connecting the S1D13505 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: NEC V Note For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,”...
Page 475: S1D13505 Hardware Configuration
Vancouver Design Center 4.2 S1D13505 Hardware Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
Page 476: Software
Page 14 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source.
Page 477: References
Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. • Epson Research and Development, Inc., S1D13505 Programming Notes and Examples, Document Number X23A-G-003-xx. 6.2 Document Sources • NEC Electronics Website: http://www.necel.com.
Page 478: Technical Support
Page 16 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road...
Page 479 S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the Motorola MPC821 Microprocessor Document Number: X23A-G-008-05 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 480 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Motorola MPC821 Microprocessor X23A-G-008-05 Issue Date: 01/02/05...
Page 481 User-Programmable Machine (UPM) ......12 S1D13505 Host Bus Interface ......13 PowerPC Host Bus Interface Pin Mapping .
Page 482 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Motorola MPC821 Microprocessor X23A-G-008-05 Issue Date: 01/02/05...
Page 483 Table 3-1: PowerPC Host Bus Interface Pin Mapping ......13 Table 4-1: List of Connections from MPC821ADS to S1D13505 ....16 Table 4-2: Summary of Power-On/Reset Options .
Page 484 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Motorola MPC821 Microprocessor X23A-G-008-05 Issue Date: 01/02/05...
Page 485: Introduction
1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the Motorola MPC821 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 486: Interfacing To The Mpc821
The bus can support both normal and burst cycles. Burst memory cycles are used to fill on-chip cache memory, and for certain on-chip DMA operations. Normal cycles are used for all other data transfers. S1D13505 X23A-G-008-05 Epson Research and Development...
Page 487: Normal (Non-Burst) Bus Transactions
Power PC system bus. SYSCLK A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Transfer Start Interfacing to the Motorola MPC821 Microprocessor Issue Date: 01/02/05 Wait States Transfer Complete Figure 2-1: Power PC Memory Read Cycle Page 9 Sampled when TA low Next Transfer Starts S1D13505 X23A-G-008-05...
Page 488: Burst Cycles
• Always attempt to transfer four 32-bit words sequentially. • Always address longword-aligned memory (i.e. A30 and A31 are always 0:0). • Do not increment address bits A28 and A29 between successive transfers; the addressed device must increment these address bits internally. S1D13505 X23A-G-008-05 Valid Transfer Start...
Page 489: Memory Controller Module
S1D13505, therefore the interfaces described in this document do not attempt to support burst cycles. However, the example interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the S1D13505 address space. 2.3 Memory Controller Module 2.3.1 General-Purpose Chip Select Module (GPCM)
Page 490: User-Programmable Machine (Upm)
In this application note, the GPCM is used instead of the UPM, since the GPCM has enough flexibility to accommodate the S1D13505 and it is desirable to leave the UPM free to handle other interfacing duties, such as EDO DRAM.
Page 491: S1D13505 Host Bus Interface
The S1D13505 implements a 16-bit native PowerPC host bus interface which is used to interface to the MPC821 microprocessor. The PowerPC host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Page 492: Powerpc Host Bus Interface Signals
3.2 PowerPC Host Bus Interface Signals The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
Page 493: Mpc821 To S1D13505 Interface
MPC821’s on-chip LCD controller. The S1D13505, through the use of the MPC821 chip selects, can share the system bus with all other MPC821 peripherals. The following figure demonstrates a typical implementation of the S1D13505 to MPC821 interface.
Page 494: Hardware Connections
Page 16 Table 4-1:,“List of Connections from MPC821ADS to S1D13505” on page 16 shows the connections between the pins and signals of the MPC821 and the S1D13505. Note The interface was designed using a Motorola MPC821 Application Development System (ADS). The ADS board has 5 volt logic connected to the data bus, so the interface included two 74F245 octal buffers on D[0:15] between the ADS and the S1D13505.
Page 495 Epson Research and Development Vancouver Design Center Table 4-1: List of Connections from MPC821ADS to S1D13505 (Continued) MPC821 Signal Name SRESET SYSCLK TSIZ0 TSIZ1 Note Note that the bit numbering of the Power PC bus signals is reversed. e.g. the most significant address bit is A0, the next is A1, A2, etc.
Page 496: S1D13505 Hardware Configuration
The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the S1D13505 is addressed starting at 40 0000h. A total of 4M bytes of address space is used, where the lower 2M bytes is reserved for the S1D13505 on-chip registers and the upper 2M bytes is used to access the S1D13505 display buffer.
Page 497: Mpc821 Chip Select Configuration
Chip select 4 is used to control the S1D13505. The following options are selected in the base address register (BR4): • BA[0:16] = 0000 0000 0100 0000 0 – set starting address of S1D13505 to 40 0000h. • AT[0:2] = 0 – ignore address type bits.
Page 498: Test Software
The test software is very simple. It configures chip select 4 (CS4) on the MPC821 to map the S1D13505 to an unused 4M byte block of address space. Next, it loads the appropriate values into the option register for CS4 and writes the value 0 to the S1D13505 register REG[1Bh] to enable the S1D13505 host interface.
Page 499: Software
OEM for different panel types, resolutions and color depths only by modifying the source. The S1D13505 test utilities and Windows CE display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com. Interfacing to the Motorola MPC821 Microprocessor...
Page 500: References
• Motorola Inc., Power PC MPC821 Portable Systems Microprocessor User’s Manual; Motorola Publication no. MPC821UM/AD. • Epson Research and Development, Inc., S1D13505 Hardware Functional Specification, Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00B Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-001-xx.
Page 501: Technical Support
Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd.
Page 502 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Motorola MPC821 Microprocessor X23A-G-008-05 Issue Date: 01/02/05...
Page 503 S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the Toshiba MIPS TX3912 Processor Document Number: X23A-G-010-04 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 504 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Toshiba MIPS TX3912 Processor X23A-G-010-04 Issue Date: 01/02/05...
Page 505 Interfacing to the TX3912 S1D13505 Host Bus Interface ......9 TX3912 Host Bus Interface Pin Mapping ..... 9 TX3912 Host Bus Interface Signals .
Page 506 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Toshiba MIPS TX3912 Processor X23A-G-010-04 Issue Date: 01/02/05...
Page 507 Table 3-1: TX3912 Host Bus Interface Pin Mapping ......9 Table 4-1: S1D13505 Configuration for Direct Connection..... . 12 Table 4-2: TX3912 to PC Card Slots Address Remapping for Direct Connection .
Page 508 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the Toshiba MIPS TX3912 Processor X23A-G-010-04 Issue Date: 01/02/05...
Page 509: Introduction
1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the Toshiba MIPS TX3912 Processor. The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 510: Interfacing To The Tx3912
The Toshiba MIPS TX3912 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the S1D13505 connects to the TX3912 processor. The S1D13505 can be successfully interfaced using one of the following configurations: •...
Page 511: S1D13505 Host Bus Interface
The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the TX3912 microprocessor. The TX3912 host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset, the bus interface signals assume their selected configuration. For details on S1D13505 configuration, see Section 4.2, “S1D13505 Configuration”...
Page 512: Tx3912 Host Bus Interface Signals
When the S1D13505 is configured to operate with the TX3912, the host interface requires the following signals: • BUSCLK is a clock input required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and should be driven by the TX3912 bus clock output DCLKOUT.
Page 513: Direct Connection To The Toshiba Tx3912
Vancouver Design Center 4 Direct Connection to the Toshiba TX3912 The S1D13505 was specifically designed to support the Toshiba MIPS TX3912 processor. When configured, the S1D13505 will utilize one of the PC Card slots supported by the processor. 4.1 Hardware Description In this example implementation, the S1D13505 occupies one PC Card slot and resides in the Attribute and IO address range.
Page 514: S1D13505 Configuration
The S1D13505 also has internal CLKI dividers providing additional flexibility. 4.2 S1D13505 Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
Page 515: Memory Mapping And Aliasing
Vancouver Design Center 4.3 Memory Mapping and Aliasing The TX3912 uses a portion of the PC Card Attribute and IO space to access the S1D13505. The S1D13505 responds to both PC Card Attribute and IO bus accesses, thus freeing the programmer from having to set the TX3912 Memory Configuration Register 3 bit CARD1IOEN (or CARD2IOEN if slot 2 is used).
Page 516: System Design Using The It8368E Pc Card Buffer
5 System Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple-function IO buffers, the S1D13505 can be interfaced so as to share one of the PC Card slots. 5.1 Hardware Description...
Page 517: It8368E Configuration
IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13505 this is not necessary as the Direct Connection described in Section 4, “Direct Connection to the Toshiba TX3912” on page 11 can be used.
Page 518: Software
Page 16 6 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source.
Page 519: References
Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. • Epson Research and Development, Inc., S1D13505 Programming Notes and Examples, Document Number X23A-G-003-xx. 7.2 Document Sources • Toshiba America Electrical Components Website: http://www.toshiba.com/taec.
Page 520: Technical Support
Page 18 8 Technical Support 8.1 EPSON LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 8.2 Toshiba MIPS TX3912 Processor...
Page 521 S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the NEC VR4121™ Microprocessor Document Number: X23A-G-011-04 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 522 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC VR4121™ Microprocessor X23A-G-011-04 Issue Date: 01/02/05...
Page 523 LCD Memory Access Cycles ......9 S1D13505 Host Bus Interface ......10 Host Bus Interface Pin Mapping .
Page 524 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC VR4121™ Microprocessor X23A-G-011-04 Issue Date: 01/02/05...
Page 525 Figure 2-1: NEC VR4121 Read/Write Cycles ......9 Figure 4-1: NEC VR4121 to S1D13505 Configuration Schematic ....12 Interfacing to the NEC VR4121™...
Page 526 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC VR4121™ Microprocessor X23A-G-011-04 Issue Date: 01/02/05...
Page 527: Introduction
1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the NEC V The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 528: Interfacing To The Nec Vr4121
A 16M byte block of memory is assigned for the LCD controller and its own chip select and ready signals are available. Word or byte accesses are controlled by the system high byte signal (SHB#). S1D13505 X23A-G-011-04 Epson Research and Development 4121 Interfacing to the NEC VR4121™...
Page 529: Lcd Memory Access Cycles
The following figure illustrates typical NEC VR4121 memory read and write cycles to the LCD controller interface. TCLK ADD[25:0] SHB# LCDCS# WR#,RD# D[15:0] (write) D[15:0] (read) LCDRDY Interfacing to the NEC VR4121™ Microprocessor Issue Date: 01/02/05 VALID Hi-Z Figure 2-1: NEC VR4121 Read/Write Cycles VALID VALID X23A-G-011-04 Page 9 Hi-Z S1D13505...
Page 530: S1D13505 Host Bus Interface
MIPS/ISA Host Bus Interface which is most suitable for direct connection to the VR4121 microprocessor. The MIPS/ISA host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Page 531: Host Bus Interface Signal Descriptions
The S1D13505 MIPS/ISA Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13505 Host Bus Interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
Page 532: Vr4121 To S1D13505 Interface
+3.3V +2.5V Note: When connecting the S1D13505 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: NEC V Note For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,”...
Page 533: S1D13505 Configuration
Vancouver Design Center 4.2 S1D13505 Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
Page 534: Memory Mapping And Aliasing
ADD21 (connected to M/R#) is used to select between the S1D13505 display buffer (ADD21=1) and the S1D13505 internal registers (ADD21=0). NEC V ADD[23:22] are ignored, thus the S1D13505 is aliased four times at 4M byte intervals over the LCD controller address range. Address lines ADD[25:24] are set at 10b and never change while the LCD controller is being addressed.
Page 535: Software
Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source.
Page 536: References
Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. • Epson Research and Development, Inc., S1D13505 Programming Notes and Examples, Document Number X23A-G-003-xx. 6.2 Document Sources • NEC Electronics Website: http://www.necel.com.
Page 537: Technical Support
Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd.
Page 538 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC VR4121™ Microprocessor X23A-G-011-04 Issue Date: 01/02/05...
Page 539 S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the NEC V832™ Microprocessor Document Number: X23A-G-012-02 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
Page 540 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC V832™ Microprocessor X23A-G-012-02 Issue Date: 01/02/05...
Page 541 Host Bus Interface Signal Descriptions V832 to S1D13505 Interface ......12 Hardware Description .
Page 542 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC V832™ Microprocessor X23A-G-012-02 Issue Date: 01/02/05...
Page 543 Figure 2-1: NEC V832 Read/Write Cycles ....... 9 Figure 4-1: NEC V832 to S1D13505 Configuration Schematic ....12 Interfacing to the NEC V832™...
Page 544 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 Interfacing to the NEC V832™ Microprocessor X23A-G-012-02 Issue Date: 01/02/05...
Page 545: Introduction
1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the NEC V832 The designs described in this document are presented only as examples of how such interfaces might be implemented.
Page 546: Interfacing To The Nec V832
A 16M byte block of addressing space can be assigned for the LCD controller and its own chip select and ready signals are available. Word or byte accesses are controlled by system byte enable signals (LLBEN and LUBEN). S1D13505 X23A-G-012-02 Epson Research and Development Vancouver Design Center Interfacing to the NEC V832™...
Page 547: Access Cycles
(CSn) is driven low. The read or write enable signals (IORD or IOWR) are driven low and READY is driven low by the S1D13505 to insert wait states into the cycle. The byte enable signals (LLBEN and LUBEN) allow byte steering.
Page 548: S1D13505 Host Bus Interface
PC Card (PCMCIA) Host Bus Interface which is most suitable for direct connection to the V832 microprocessor. The PC Card host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration. For details on S1D13505 configuration, see Section 4.2, “S1D13505 Hardware Configuration”...
Page 549: Host Bus Interface Signal Descriptions
3.2 Host Bus Interface Signal Descriptions The S1D13505 PC Card Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13505 Host Bus Interface. It is driven by the V832 signal SDCLKOUT.
Page 550: V832 To S1D13505 Interface
+2.5V VDD_I Note: When connecting the S1D13505 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states). Figure 4-1: NEC V832 to S1D13505 Configuration Schematic Note For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,”...
Page 551: S1D13505 Hardware Configuration
Vancouver Design Center 4.2 S1D13505 Hardware Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
Page 552: Nec V832 Configuration
The NEC V832 should access the S1D13505 in non-burst mode only. This is ensured by using any one of the CS3 to CS6 lines to control the S1D13505 and setting that line to respond to IO operations using the NEC V832 BCTC register. For example, if line CS5 is designated to control the S1D13505, then bit 5 (CT5) of the BCTC register should be set to 1 (IO cycle).
Page 553: Memory Mapping And Aliasing
Epson Research and Development Vancouver Design Center 4.4 Memory Mapping and Aliasing The CSn line selected determines the address range to be reserved for the S1D13505. The table below summarizes the S1D13505 address mapping. Table 4-3: NEC CSn Line NEC V832 IO Address...
Page 554: Software
Page 16 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source.
Page 555: References
Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. • Epson Research and Development, Inc., S1D13505 Programming Notes and Examples, Document Number X23A-G-003-xx. 6.2 Document Sources • NEC Electronics Website: http://www.necel.com.
Page 556: Technical Support
Page 18 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road...

Epson S1D13505 Technical Manual

Table of Contents

1 Introduction

2 Features

3 Typical System Implementation Diagrams

4 Internal Description

5 Pins

6 C. Characteristics

7 C. Characteristics

8 Registers

9 Display Buffer

10 Display Configuration

11 Look-Up Table Architecture

12 Ink/Cursor Architecture

13 Swivelview

14 Clocking

15 Power Save Modes

16 Mechanical Data

Table of Contents

1 Introduction

2 Initialization

3 Memory Models

4 Look-Up Table (LUT)

5 Advanced Techniques

6 LCD Power Sequencing and Power Save Modes

7 Hardware Cursor/Ink Layer

8 Swivelview

9 CRT Considerations

10 Identifying the S1D13505

11 Hardware Abstraction Layer (HAL)

12 Sample Code

Appendix A Supported Panel Values

Quick Links

Chapters

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Summary of Contents for Epson S1D13505