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Philips Semiconductors
1.3GHz low voltage fractional-N synthesizer
Charge pump currents
CP0
I
PHP
0
3xI
1
1xl
NOTES:
1. I
=V
/R
: bias current for charge pumps.
SET
SET
SET
2. I
is the total current at pin PHP during speed up condition.
PHP–SU
Lock Detect
The output LOCK maintains a logic '1' when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than
frequency at the input REFin+, –. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock (logic
'0') is indicated when both counters are powered down.
1999 Nov 04
I
PHP–SU
15xl
SET
SET
5xl
SET
SET
1 period of the
Power-down mode
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.
10
Product specification
SA7016
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