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3DQDVRQLF
1.1.6 Color Decoder
See also the related block diagram as well as the diagrams at the end of the report.
The main functions are:
* PLL/VCXO
* PAL/NTSC identification
* SECAM identification
* ASM ( Automatic System Manager )
* (R-Y)/(B-Y) demodulation
* PLL/VCXO
The PLL operates during the burstkey period; it generates a VCXO reference signal ( f
), in
VCXO
phaselock with the incoming burst signal ( f
). Prior to lock condition, the signals f
and f
BURST
VCXO
BURST
are not synchronous and are present at phase detector input. The loop filter averages the phase
detector output current and the resulting control signal to the VCXO is proportional to Sin(2π∆ft) where
∆f = f
- f
.
VCXO
BURST
A lock situation occurs when ∆f < VCXO holding range; once in lock, the phase detector output current
is proportional to θ
= θ
- θ
(θ
is the static phase error).
E
VCXO
BURST
E
The combined phase detector and VCXO sensitivity is high to ensure a small static phase error.
For fast color acquisition, the phase detector is in high gain mode when a color system is not yet
identified.
The VCXO loop (not to be confused with phase locked loop, PLL) compensates for any attenuation
loss or phase shift in the crystal so that the it's loop gain is unity and loop phase shift is zero. The
VCXO reference outputs (0° and 90°) are stable sinusoids.
VCXO oscillation is at series resonance of the selected Xtal. Since the PLL automatically tunes the
VCXO to the burst (if inside the PLL holding range) fine tuning of the VCXO with a trimming
capacitance is not necessary.
The motional capacitance of the Xtal is damped by the internal resistance of the VCXO pins (i.e. 1K )
in order to realize the holding range.
The catching range (pull-in) of the PLL loop is governed by the PLL loop filter; the loop filter can be
chosen so that PLL holding and catching range are similar (direct catching).
The HUE phase rotator is inoperational when the PLL is active (i.e. no phase rotation during the
burstkey period). Outside the burstkey period, the hue control rotates the VCXO reference phases
from -40° to 40° linearly for I²C bus command (HUE: 0 --> 63), see also device specification.
* PAL/NTSC demodulation
The 0° and 90° reference signals from the VCXO are supplied to the HUE phase rotator; it's outputs
(H0, H90) are supplied to the (B-Y) and (R-Y) burst demodulators respectively.
The demodulated burst from the (B-Y) demodulator supplies NTSC ident information to the ASM (IDN
signal). The demodulated burst from (R-Y) demodulator supplies PAL ident information to the ASM
(IDP signal). For correct demodulation of (R-Y) PAL burst and chroma signals, then the H90 signal
requires 180° phase shift on alternate lines. This is realized with the H/2 switch before the (R-Y)
demodulator. It is not active during demodulation of NTSC signals.
The (B-Y)/(R-Y) baseband signals are obtained from the chroma signal by the (B-Y)/(R-Y)
demodulators, filtered and supplied via the PAL/SECAM switch (PS) to the internal baseband delay
line.
The demodulator gain ratio (B-Y)/(R-Y) is typically 1.78 in order to compensate for scaling in the
transmitter. For NTSC applications it is possible to bypass the delay line via I2C bus command BPS;
the gain is also corrected then by a factor two. The V
and U
signals from delay line outputs are fed
INT
INT
to the YUV selection circuit (see YUV/RGB processing part).
* SECAM demodulation
SECAM demodulation is realized with a PLL type demodulator.
When the VCXO is connected to pin 35 (controlled by XTS) and if a 4.43MHz Xtal is present on that
pin then SECAM demodulation is possible. The auto tuning loop, consisting of PLL demodulator and
oscillator, ensures that the PLL oscillator is locked to the 4.43MHz Xtal frequency during calibration
time in the vertical retrace period. The SECAM reference voltage, generated at pin 16, is regulated in
order that the PLL demodulator output is set to a reference voltage derived from a stable bandgap
voltage.
Outside calibration the oscillator remains tracking the SECAM chrominance resulting in the
corresponding demodulated voltage. This is delivered to the LF de-emphasis stage and to the line
15
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