Sharp FO-CC500 Service Manual page 66

FO-CC500A
FO-K01A
4) Baseband Modem
The baseband modem section in each of the Merlin ASICs performs
all of the spread spectrum modulation and demodulation, data timing
recovery, AFC, AGC, framing, and rate adaptation required for a DSS
system.
Transmit/Receive Data Paths. The transmit data path consists of a
parallel-to-serial converter, scrambler, differential encoder, spreader,
and modulator. The receive data path comprises A/D converters,
matched filter with frequency compensation insertion, data
demodulator, descrambler, and a serial-to-parallel converter.
Scrambler/Descrambler. The scrambler/descrambler is a 16-bit maxi-
mum length Pseudorandom Noise (PN) sequence generator. The PN
sequence is XORed with Tx data for scrambling and XORed with Rx
data for descrambling. The voice and supervisory bits are scrambled.
The PN sequence generator's starting location is programmable us-
ing one memory mapped register along with the two ID registers. This
starting location is used to initialize the PN generator at the start of
each link. The MSB of the PN generator is used to scramble/
descramble. The first frame bit scrambled/descrambled uses the ini-
tialized value of the MSB.
Differential Encoder. When this block is enabled, data is differen-
tially encoded. The encoder is initialized to zero during the Tx frame's
first "zero bit." In DBPSK, a data symbol is inferred by the presence or
absence of a 180-degree phase shift or inversion in the carrier signal
at regular intervals. A phase shift therefore indicates a change of state
from one to zero, or zero to one. To determine which of these two
possibilities was intended, the spread data is differentially encoded.
Spread Spectrum Spreader. A 12-chip spreading code is used to
meet FCC part 15.247 requirements for a DSS system. The spread-
ing code cyclic duration is 12 times that of the encoded data. The
code starts and stops on encoded bit boundaries. The spreading code
may be configured by the controller.
Modulation. The data from the differential encoder is input to the
modulator. An analog block exists at the Tx output that maintains a
constant voltage level independent of supply operation.
Receiver A/D Converters. Baseband I/Q signals from the radio are
sampled at 1.92 MHz and converted to digital with 3-bit flash A/D
converters.
AFC/Timing. Internal AFC allows a crystal tolerance of up to ±90
ppm for a 900 MHz radio or ±40 ppm for a 2.4 GHz radio.
This allows for a total system clock error of 180 ppm for a 900 MHz
radio or 80 ppm for a 2.4 GHz radio. The modem uses a standard
early-late mechanism to maintain timing locks.
Matched Filters. The spreading code is removed (despread) from
the received, digitized I/Q signals with matched filters.
Data Demodulation. This block determines the value for the received
bit and determines a frequency error estimate used for the AFC. Data
is demodulated by using I/Q matched filter data which is exactly one
bit time apart.
Signal Quality. A signal quality metric is accumulated over each frame
and can be read by the microcontroller at any time.
ID Detector. A 32-bit ID word (16-bit programmable) is used during
acquisition to verify the RF link and initialize frame timing.
Time Division Duplex Controller (TDDC). The TDDC handles the
spread spectrum protocol.
AGC and Gain Imbalance. The signal energy is compared to a pro-
grammable threshold and scaled with programmable gain.
The digital AGC value is output to the radio by an 8-bit D/A converter.
The gain imbalance of the I/Q system is automatically calculated and
removed during calibration of the system.
Clock Oscillator. A highly accurate crystal oscillator (TCXO etc.) is
needed to register multi cordless handsets to fax machine by wire-
less. And its output level convert to meet Merlin specification using
high speed inverter or high speed rail-to-rail input and output opera-
tional amplifiers. A 19.2 MHz crystal oscillator generates a 19.2 MHz
clock and a 9.6 MHz clock. The 19.2 MHz clock is used only for the
DSP core. The 9.6 MHz clock is the main system clock used by the
controller and the rest of the system.
5) DSP Core Audio Coprocessor
The DSP audio coprocessor is connected to the microcontroller via
the internal data bus and memory mapped registers. The DSP con-
verts ADPCM data to/from 16-bit linear Codec data, generates audio
tones, and performs CID signal processing.
ADPCM Coder/Decoder. The ADPCM coder/decoder is the DSP core
main block. This block performs the processing that encodes linear
speech data, passes it to the radio as ADPCM compressed speech,
and decodes ADPCM data received from the radio into linear speech
data.
Using the ITU G.726 32 kbps ADPCM audio compression algorithm,
14-bit linear samples are compressed to 4 bits at a rate of 8 k samples
per second.
Tone Generators. The DSP core also contains three independent
tone generators. The tone generators are used to create DTMF
signaling as required by the telephone system, and to create all MMI
audio alert signals.
CID Processing. The DSP core contains a demodulator for decoding
CID FSK signals. The DSP core also performs CPE Alert Signal (CAS)
detection for CID type ll, stutter dial tone detection, and Visual Mes-
sage Waiting Indication (VMWI) processing. No external CID devices
are required. The DSP CID processing supports the following:
• CID types 1, 2, and 2.5
• VMWI
• Synchronous Call Logging (SCL)
• Stutter dial tone detection
6) Audio Codec
The audio Codec is a monolithic CMOS integrated circuit packaged
in all of the Merlin devices except for the XROM ASIC. The Codec
consists of an A/D and D/A converter path, with digital filtering and
analog signal processing circuits to realize a compliant ITU G.714-
compatible voice frequency linear coder/decoder (see Fig. 11). The
user word rate to and from the device is 8 k words per second.
MICIN
LINEIN
MICBIAS
SPKRO
LINEO
Fig. 11 Merlin Codec Block Diagram
ASIC Interface Port. Six interface lines are used to link the audio
Codec and ASIC. Two lines are used for clocks (CDCMCLK and
CDCICLK) and a third creates an 8 kHz framing pulse. The remaining
lines are for data in and data out lines as well as a reset line. The
clocks and framing pulse are synchronous to each other. The data I/O
port will be time-multiplexed between data and control words.
5 – 16
Modulator 16-bit
and filter register
CDCMCLK
FSYNC
Control
CDCICLK
register
SIN
SOUT
Modulator 16-bit
and filter register