Philips TDA9964 Specifications page 13

Philips Semiconductors
SDATA
SCLK
SEN
OFDOUT DAC
SCLK
LATCHES
FLIP-FLOP
8-bit DAC
Fig 9. Serial interface block diagram.
SDATA A3
SCLK
SEN
t su1
t = t = t = 10 ns (min.); t
su1 su2 su3
Fig 10. Loading sequence of control input data via the serial interface.
9397 750 07918
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
SD0 SD1 SD2 SD3
SD4 SD5
LSB
12
8 8
PGA GAIN ADC CLAMP
LATCHES LATCHES
FLIP-FLOP FLIP-FLOP
ADC clamp
PGA control
control
MSB
A2 A1 A0 SD10
SD11
= t = 10 ns (min.)
hd3 hd4
Rev. 03 — 16 January 2001
SHIFT REGISTER
SD6 SD7 SD8 SD9 SD10 SD11
7 10
CONTROL PULSE
POLARITY
LATCHES
control pulses
polarity settings
t su2
t hd4
SD9 SD8 SD7 SD6 SD5
TDA9964
A0
A1 A2
MSB
LATCH
SELECTION
VSYNC
FCE523
LSB
SD4 SD3 SD2 SD1 SD0
© Philips Electronics N.V. 2001. All rights reserved.
A3
t su3
t hd3
FCE524
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