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Philips Semiconductors
11. Application information
handbook, full pagewidth
(2)
CCD
1 F
V CCA
100
nF
(1) Pins SEN and VSYNC should be interconnected when the vertical sync signal is not available.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals t
"Characteristics").
Fig 11. Application diagram.
9397 750 07918
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Table 12: Output enable control by serial interface (register address A3 = 0, A2 = 0,
A1 = 1 and A0 = 1); output enable pin (OE) connected to ground
SD6
0
1
V CCA1
V CCA
1
AGND1
2
AGND2
3
IN
4
AGND3
5
AGND4
6
V CCA2
7
CPCDS1
8
1
CPCDS2
F
9
1
DCLPC
F
10
1
OFDOUT
F
11
TEST
12
Rev. 03 — 16 January 2001
ADC digital outputs D11 to D0
high impedance
active binary
V CCA
(2)
(2)
48 47 46 45 44 43 42 41 40 39 38 37
TDA9964
13 14 15 16 17 18 19 20 21 22 23 24
100 nF
(1)
serial
interface
V CCA
h(IN;SHP)
TDA9964
V CCD
V CCD
V CCO
100 nF
100 nF
D11
36
D10
35
D9
34
D8
33
D7
32
D6
31
D5
30
D4
29
D3
28
D2
27
D1
26
D0
25
100 nF
100 nF
V CCD
V CCO
FCE525
and t
(see
Section 10
h(IN;SHD)
© Philips Electronics N.V. 2001. All rights reserved.
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