Philips TDA9964 Specifications page 14

Philips Semiconductors
9397 750 07918
Objective specification
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Table 7: Serial interface programming
Address bits Data bits D9 to D0
A3 A2 A1 A0
0 0 0 0 PGA gain control (SD7 to SD0)
0 0 0 1 DAC OFDOUT output control (SD7 to SD0)
0 0 1 0 ADC clamp reference control (SD6 to SD0); from code 0 to 127
0 0 1 1 control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK)
polarity settings; SD2, SD6, SD7 and SD9 should be set to logic 1;
for SD6 and SD7 see
0 1 0 0 SD7 = 0 by default; SD7 = 1 PGA gain up to 36 dB but noise and
clamp behaviour are not guaranteed
1 1 1 1 initialization (SD11 to SD0 = 0)
other addresses test modes
Table 8: Polarity settings
Symbol Pin
SHP and SHD 45 and 46 SD4
CLK 47
CLPDM 48
CLPOB 44
BLK 43
VSYNC 20
Table 9: Standby control using pin STDBY
Bit SD7 of STDBY
register 0011
1 1
0
0 1
0
Table 10: Output enable selection using output enable pin (OE)
Bit SD6 of register 0011
1
0
Table 11: Standby control by serial interface (register
address A3 = 0, A2 = 0, A1 = 1 and A0 = 1); pin STDBY connected to ground
SD7 ADC digital outputs D11 to D0
0 last logic state
1 active
Rev. 03 — 16 January 2001
Table 9, 10, 11, and
Serial control bit
SD5
SD0
SD1
SD3
SD8
ADC digital outputs
D11 to D0
last logic state
active
active
test logic state
OE ADC digital outputs D11 to D0
0 active, binary
1 high impedance
0 high impedance
1 active binary
I + I + I
CCA CCO
1.5 mA
65 mA
TDA9964
12
Active edge or level
1 = HIGH; 0 = LOW
1 = rising; 0 = falling
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
0 = rising; 1 = falling
I + I + I (typ.)
CCA CCO CCD
1.5 mA
65 mA
65 mA
1.5 mA
(typ.)
CCD
© Philips Electronics N.V. 2001. All rights reserved.
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