Enable Registers - Sony 3026 Programmer's Manual

Status and Events
Operational Status
Register (OSB)
Questionable Status
Register (QSB)
Instrument Summary
Registers (OISR and
QISR)

Enable Registers

Event Status Enable
Register (ESER)
3 4
Only bit 13 (OSB) of the Operational Status Register is used by the realtime
spectrum analyzer. This bit indicates the status of the Operational Instrument
Summary Register (OISR). Use :STAT:OPER:COND? to perform a non-destruc-
tive query of this register.
Only bit 13 (QSB) of the Questionable Status Register is used by the realtime
spectrum analyzer. This bit indicates the status of the Questionable Instrument
Summary Register (QISR). Use :STAT:QUEST:COND? to perform a non-destruc-
tive query of this register.
Both the Operational Register and Questionable Register receive status from
their Instrument Summary Registers (OISR and QISR). The OISR indicates
which slots are occupied in the realtime spectrum analyzer. The QISR indicates
which modules have reported malfunctions during their power on diagnostics.
Use :STAT:QUEST:INST:COND? or :STAT:OPER:INST:COND? to perform a
non-destructive query of these registers. The query will return an integer value
whose bits represent the status of each slot.
NOTE. The most significant bit (MSB) of each ISR is always set to "0".
For example: given the following response to the :CAT:FULL? query:
"CPU:0","CLOCK:1","BG1:2","AGL1:3","AVG1:7","DVG1:8"
The response from the STAT:OPER:INST:COND? query will be 399. Converting
the decimal integer 399 to binary gives 110001111. Starting at the least
significant digit, this value indicates that slots 0, 1, 2, 3, 7, and 8 are occupied.
There are two types of enable registers: the Event Status Enable Register
(ESER) and the Service Request Enable Register (SRER).
Each bit in these enable registers corresponds to a bit in the controlling status
register. By setting and resetting the bits in the enable register, the user can
determine whether or not events that occur will be registered to the status register
and queue.
The ESER is made up of bits defined exactly the same as bits 0 through 7 in the
SESR (see Figure 3-3). This register is used by the user to designate whether the
SBR ESB bit should be set when an event has occurred and whether the
corresponding SESR bit has been set.
3026 Programmer Manual