NEC MuPD78F0132H User Manual

8-bit single-chip microcontrollers, 78k0/ke1plus

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User's Manual

78K0/KE1+

8-Bit Single-Chip Microcontrollers

PD78F0132H

PD78F0133H

PD78F0134H

PD78F0136H

PD78F0138H

PD78F0138HD

Document No. U16899EJ2V0UD00 (2nd edition)

Date Published April 2005 N CP(K)

Printed in Japan

2003

Table of Contents

Summary of Contents for NEC MuPD78F0132H

Page 1 User’s Manual 78K0/KE1+ 8-Bit Single-Chip Microcontrollers µ PD78F0132H µ PD78F0133H µ PD78F0134H µ PD78F0136H µ PD78F0138H µ PD78F0138HD Document No. U16899EJ2V0UD00 (2nd edition) Date Published April 2005 N CP(K) 2003 Printed in Japan...
Page 2 [MEMO] User’s Manual U16899EJ2V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KE1+ and design and develop application systems and programs for these devices. The target products are as follows. µ 78K0/KE1+: PD78F0132H, 78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD Purpose This manual is intended to give users an understanding of the functions described in the...
Page 7 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name) Note: Footnote for item marked with Note in the text. Caution: Information requiring particular attention Remark: Supplementary information ...
Page 8 Document No. SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ..........................16 Features ............................16 Applications..........................17 Ordering Information ......................... 18 Pin Configuration (Top View)....................19 Kx1 Series Lineup........................22 1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup .....................22 1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup ...................25 Block Diagram..........................28 Outline of Functions ........................29 CHAPTER 2 PIN FUNCTIONS .......................
Page 10 Instruction Address Addressing ....................70 3.3.1 Relative addressing ........................70 3.3.2 Immediate addressing ........................71 3.3.3 Table indirect addressing....................... 72 3.3.4 Register addressing........................72 Operand Address Addressing ....................73 3.4.1 Implied addressing......................... 73 3.4.2 Register addressing........................74 3.4.3 Direct addressing........................... 75 3.4.4 Short direct addressing ........................
Page 11 Time Required for CPU Clock Switchover ................130 Clock Switching Flowchart and Register Setting ..............131 5.8.1 Switching from Ring-OSC clock to high-speed system clock............131 5.8.2 Switching from high-speed system clock to Ring-OSC clock............132 5.8.3 Switching from high-speed system clock to subsystem clock............133 5.8.4 Switching from subsystem clock to high-speed system clock............134 5.8.5...
Page 12 Cautions for Watch Timer ....................... 230 CHAPTER 10 WATCHDOG TIMER ..................... 231 10.1 Functions of Watchdog Timer ....................231 10.2 Configuration of Watchdog Timer ..................233 10.3 Registers Controlling Watchdog Timer ................. 234 10.4 Operation of Watchdog Timer....................237 10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by option byte ..237 10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software”...
Page 13 14.4.1 Operation stop mode ........................304 14.4.2 Asynchronous serial interface (UART) mode................305 14.4.3 Dedicated baud rate generator .....................319 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11..............326 15.1 Functions of Serial Interfaces CSI10 and CSI11 ..............326 15.2 Configuration of Serial Interfaces CSI10 and CSI11 ............327 15.3 Registers Controlling Serial Interfaces CSI10 and CSI11............
Page 14 21.2 Configuration of Clock Monitor ....................397 21.3 Registers Controlling Clock Monitor..................398 21.4 Operation of Clock Monitor..................... 399 CHAPTER 22 POWER-ON-CLEAR CIRCUIT..................404 22.1 Functions of Power-on-Clear Circuit..................404 22.2 Configuration of Power-on-Clear Circuit ................405 22.3 Operation of Power-on-Clear Circuit..................405 22.4 Cautions for Power-on-Clear Circuit ..................
Page 15 26.8.1 Registers used for self-programming function ................448 26.9 Boot Swap Function ........................ 452 26.9.1 Outline of boot swap function .......................452 26.9.2 Memory map and boot area......................453 µ CHAPTER 27 ON-CHIP DEBUG FUNCTION ( PD78F0138HD ONLY).......... 459 CHAPTER 28 INSTRUCTION SET ...................... 460 28.1 Conventions Used in Operation List..................
Page 16: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features µ Minimum instruction execution time can be changed from high speed (0.125 s: @ 16 MHz operation with high- µ speed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits ×...
Page 17: Applications
CHAPTER 1 OUTLINE 1.2 Applications Automotive equipment • System control for body electricals (power windows, keyless entry reception, etc.) • Sub-microcontrollers for control Home audio, car audio AV equipment PC peripheral equipment (keyboards, etc.) Household electrical appliances • Outdoor air conditioner units •...
Page 18: Ordering Information
CHAPTER 1 OUTLINE 1.3 Ordering Information Part Number Package µ 64-pin plastic LQFP (10 × 10) PD78F0132HGB-8EU µ 64-pin plastic LQFP (14 × 14) PD78F0132HGC-8BS µ 64-pin plastic TQFP (12 × 12) PD78F0132HGK-9ET µ 64-pin plastic LQFP (10 × 10) PD78F0133HGB-8EU µ...
Page 19: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 64-pin plastic LQFP (10 × 10) • 64-pin plastic LQFP (14 × 14) • 64-pin plastic TQFP (12 × 12) • 64-pin plastic LQFP (12 × 12) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 FLMD0 RESET P00/TI000...
Page 20 CHAPTER 1 OUTLINE µ • 64-pin plastic FBGA (6 × 6) ( PD78F0138H and 78F0138HD only) Top View Bottom View A B C D E F G H H G F E D C B A Index mark Pin No. Pin Name Pin No.
Page 21 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI7: Analog input P140, P141: Port 14 Analog reference voltage PCL: Programmable clock output Analog ground RESET: Reset BUZ: Buzzer output RxD0, RxD6: Receive data Note Power supply for port SCK10, SCK11 : Serial clock input/output Note Ground for port SI10, SI11...
Page 22: Kx1 Series Lineup
CHAPTER 1 OUTLINE 1.5 Kx1 Series Lineup 1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup • 30-pin SSOP (7.62 mm 0.65 mm pitch) 78K0/KB1 78K0/KB1+ µ µ µ PD78F0103 PD780103 PD78F0103H Mask ROM: 24 KB, Single-power-supply flash memory: 24 KB, Two-power-supply flash memory: 24 KB, RAM: 768 B RAM: 768 B RAM: 768 B...
Page 23 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1 is shown below. Part Number 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins − − − − − − Internal Mask ROM memory...
Page 24 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1+ is shown below. Part Number 78K0/KB1+ 78K0/KC1+ 78K0/KD1+ 78K0/KE1+ 78K0/KF1+ Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins Internal Flash memory 16/24 24/32 24/32 24/32 48/60 memory...
Page 25: V850Es/Kx1, V850Es/Kx1+ Product Lineup
CHAPTER 1 OUTLINE 1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup 64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch) • 64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch) • 64-pin plastic LQFP (14 × 14 mm, 0.8 mm pitch) •...
Page 26 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1 is shown below. Part Number V850ES/KE1 V850ES/KF1 V850ES/KG1 V850ES/KJ1 Item Number of pins 64 pins 80 pins 100 pins 144 pins − − − − − − − Internal Mask ROM 96/128 memory −...
Page 27 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1+ is shown below. Part Number V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ V850ES/KJ1+ Item Number of pins 64 pins 80 pins 100 pins 144 pins − − − − Internal Mask ROM 96/128 128/256 128/256 memory −...
Page 28: Block Diagram
CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 16-bit timer/ Port 0 P00 to P06 event counter 00 TI000/P00 Port 1 P10 to P17 Note 1 Note 1 Note 1 TO01 /TI011 /P06 16-bit timer/ event counter 01 Note 1 TI001 /P05 Port 2 P20 to P27...
Page 29: Outline Of Functions
CHAPTER 1 OUTLINE 1.7 Outline of Functions (1/2) µ µ µ µ µ µ Item PD78F0132H PD78F0133H PD78F0134H PD78F0136H PD78F0138H PD78F0138HD Internal Flash memory 16 K 24 K 32 K 48 K 60 K 60 K memory (self-programming Note 1 (bytes) supported) Note 1...
Page 30 CHAPTER 1 OUTLINE (2/2) µ µ µ µ µ µ Item PD78F0132H PD78F0133H PD78F0134H PD78F0136H PD78F0138H PD78F0138HD • UART mode supporting LIN-bus: 1 channel Serial interface µ • 3-wire serial I/O mode: 1 channel (none in the PD78F0132H) Note 1 •...
Page 31 CHAPTER 1 OUTLINE An outline of the timer is shown below. 16-Bit Timer/ 8-Bit Timer/ 8-Bit Timers H0 and Watch Watchdog Event Counters 00 Event Counters Timer Timer Note 1 and 01 50 and 51 Note 1 TM00 TM01 TM50 TM51 TMH0 TMH1...
Page 32: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AV , EV , and V . The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P27...
Page 33 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Pin Name Function After Reset Alternate Function − P40 to P43 Port 4. Input 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
Page 34 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name Function After Reset Alternate Function INTP0 Input External interrupt request input for which the valid edge (rising Input P120 edge, falling edge, or both rising and falling edges) can be INTP1 to INTP3 P30 to P32 specified...
Page 35 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Pin Name Function After Reset Alternate Function − − Input A/D converter reference voltage input and positive power supply for port 2 − − − A/D converter ground potential. Make the same potential as or V KR0 to KR7 Input...
Page 36: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. The following operation modes can be specified in 1-bit units.
Page 37: P10 To P17 (Port 1)
CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, timer I/O, and flash memory programming mode setting. The following operation modes can be specified in 1-bit units.
Page 38: P20 To P27 (Port 2)
CHAPTER 2 PIN FUNCTIONS 2.2.3 P20 to P27 (port 2) P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit input-only port.
Page 39: P60 To P63 (Port 6)
CHAPTER 2 PIN FUNCTIONS 2.2.7 P60 to P63 (port 6) P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). P60 to P63 are N-ch open-drain pins.
Page 40: Av Ref
CHAPTER 2 PIN FUNCTIONS (b) PCL This is a clock output pin. (c) BUZ This is a buzzer output pin. 2.2.12 AV This is the A/D converter reference voltage input pin. Note When the A/D converter is not used, connect this pin directly to EV or V Note Connect port 2 directly to EV when it is used as a digital port.
Page 41: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2.
Page 42 CHAPTER 2 PIN FUNCTIONS Table 2-2. Pin I/O Circuit Types (2/2) Pin Name I/O Circuit Type Recommended Connection of Unused Pins RESET Input Connect to EV or V Note 1 Connect directly to EV or V − Leave open. − Note 2 Connect directly to EV or V...
Page 43 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 8-A Pullup P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Type 3-C Type 9-C Comparator P-ch N-ch P-ch – Data (threshold voltage) N-ch Input enable...
Page 44 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-W Type 16 Feedback IN/OUT cut-off Data N-ch P-ch Output disable Input enable Middle-voltage input buffer User’s Manual U16899EJ2V0UD...
Page 45: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/KE1+ can each access a 64 KB memory space. Figures 3-1 to 3-6 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/KE1+ are fixed (IMS = CFH, IXS = 0CH).
Page 46 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-1. Memory Map ( PD78F0132H) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 512 × 8 bits Program area Data memory space CALLF entry area Reserved Program area Option byte area...
Page 47 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD78F0133H) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 1024 × 8 bits Program area Data memory space CALLF entry area Reserved Program area Option byte area...
Page 48 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-3. Memory Map ( PD78F0134H) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 1024 × 8 bits Program area Data memory space CALLF entry area Reserved Program area Option byte area...
Page 49 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-4. Memory Map ( PD78F0136H) FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH BFFFH Reserved Program area Data memory...
Page 50 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-5. Memory Map ( PD78F0138H) FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH EFFFH Reserved Program area Data memory...
Page 51 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-6. Memory Map ( PD78F0138HD) FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits Note 1 EFFFH FB00H FAFFH Program area...
Page 52: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KE1+ products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure...
Page 53: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area The option byte area is assigned to the 1-byte area of 0080H. Refer to CHAPTER 24 OPTION BYTE for details. (4) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
Page 54: Special Function Register (Sfr) Area
CHAPTER 3 CPU ARCHITECTURE 3.1.3 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to Table 3-6 Special Function Register List in 3.2.3 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions.
Page 55 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-8. Correspondence Between Data Memory and Addressing ( PD78F0133H) Special function registers (SFR) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 1024 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 56 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-9. Correspondence Between Data Memory and Addressing ( PD78F0134H) Special function registers (SFR) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 1024 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 57 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-10. Correspondence Between Data Memory and Addressing ( PD78F0136H) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 58 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-11. Correspondence Between Data Memory and Addressing ( PD78F0138H) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 59 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-12. Correspondence Between Data Memory and Addressing ( PD78F0138HD) FFFFH Special function registers (SFR) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH...
Page 60: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/KE1+ products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 61 CHAPTER 3 CPU ARCHITECTURE (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
Page 62 CHAPTER 3 CPU ARCHITECTURE Figure 3-16. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
Page 63 CHAPTER 3 CPU ARCHITECTURE Figure 3-17. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15 to PC8...
Page 64: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 65: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions.
Page 66 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (1/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port register 0 √ √ − FF01H Port register 1 √...
Page 67 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (2/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF30H Pull-up resistor option register 0 √ √ −...
Page 68 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (3/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF6CH 8-bit timer H mode register 1 TMHMD1 √...
Page 69 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (4/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FFBCH Capture/compare control register 00 CRC00 √ √ −...
Page 70: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 71: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 72: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 73: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed.
Page 74: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 75: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code OP code [Illustration]...
Page 76: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 77: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 78: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces.
Page 79: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 80: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 81: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
Page 82: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AV and EV . The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P27...
Page 83 CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (1/2) Pin Name Function After Reset Alternate Function Port 0. Input TI000 7-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. Note SO11 Use of an on-chip pull-up resistor can be specified by a Note SI11 software setting.
Page 84: Port Configuration
CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (2/2) Pin Name Function After Reset Alternate Function P120 Port 12. Input INTP0 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting. − P130 Output Port 13.
Page 85: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Page 86 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 and P06 PU01, PU06 P-ch Alternate function PORT Output latch P01/TI010/TO00, (P01, P06) Note Note P06/TI011 /TO01 PM01, PM06 Alternate function µ Note Available only in the PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD. PU0: Pull-up resistor option register 0 PM0:...
Page 87 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 PU02 P-ch PORT Output latch Note P02/SO11 (P02) PM02 Alternate function µ Note Available only in the PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD. PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal...
Page 88 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P04 PU04 P-ch Alternate function PORT Output latch Note P04/SCK11 (P04) PM04 Alternate function µ Note Available only in the PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD. PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal...
Page 89: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
Page 90 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10/RxD0, (P11, P14) P14/RxD6 PM11, PM14 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U16899EJ2V0UD...
Page 91 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P12 and P15 PU12, PU15 P-ch PORT Output latch P12/SO10 (P12, P15) P15/TOH0 PM12, PM15 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U16899EJ2V0UD...
Page 92 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P13 PU13 P-ch PORT Output latch P13/TxD6 (P13) PM13 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U16899EJ2V0UD...
Page 93 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TOH1/INTP5, (P16, P17) P17/TI50/TO50/FLMD1 PM16, PM17 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal User’s Manual U16899EJ2V0UD...
Page 94: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-11 shows a block diagram of port 2. Figure 4-11. Block Diagram of P20 to P27 A/D converter P20/ANI0 to P27/ANI7 Read signal...
Page 95: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
Page 96 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/INTP4/TI51/TO51 (P33) PM33 Alternate function PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal User’s Manual U16899EJ2V0UD...
Page 97: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is a 4-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (PU4).
Page 98: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is a 4-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 5 (PU5).
Page 99: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 6 Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The P60 to P63 pins are N-ch open-drain pins. RESET input sets port 6 to input mode.
Page 100: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
Page 101: Port 12
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 102: Port 13
CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 13 Port 13 is a 1-bit output-only port. Figure 4-19 shows a block diagram of port 13. Figure 4-19. Block Diagram of P130 PORT Output latch P130 (P130) Read signal WR××: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal.
Page 103: Port 14
CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 14 Port 14 is a 2-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 and P141 pins are used as an input port, use of an on-chip pull- up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Page 104: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM3 to PM7, PM12, PM14) • Port registers (P0 to P7, P12 to P14) •...
Page 105 CHAPTER 4 PORT FUNCTIONS Table 4-4. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name Alternate Function PM×× P×× Function Name × TI000 Input × TI010 Input TO00 Output Note SO11 Output × Note SI11 Input ×...
Page 106 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read.
Page 107 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P40 to P43, P50 to P53, P70 to P77, P120, or P140 and P141 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3 to PU5, PU7, PU12, and PU14.
Page 108: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit.
Page 109: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three system clock oscillators are available. • High-speed system clock oscillator The high-speed system clock oscillator oscillates a clock of f = 2.0 to 16.0 MHz.
Page 110 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus Oscillation Main OSC Processor clock Main clock stabilization time control mode register control register select register register (PCC) (MCM) (OSTS) (MOC) MSTOP MCM0 OSTS2 OSTS1 OSTS0 CSS PCC2 PCC1 PCC0 Oscillation stabilization STOP...
Page 111: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The following six registers are used to control the clock generator. • Processor clock control register (PCC) • Ring-OSC mode register (RCM) • Main clock mode register (MCM) • Main OSC control register (MOC) •...
Page 112 CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Processor Clock Control Register (PCC) Note 1 Address: FFFBH After reset: 00H Symbol <7> <6> <5> <4> PCC2 PCC1 PCC0 Note 2 Control of high-speed system clock oscillator operation Oscillation possible Oscillation stopped Note 3 Subsystem clock feedback resistor selection On-chip feedback resistor used...
Page 113 CHAPTER 5 CLOCK GENERATOR Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM) 2. f : Main system clock oscillation frequency (high-speed system clock oscillation frequency or Ring- OSC clock oscillation frequency) 3. f : Ring-OSC clock oscillation frequency 4.
Page 114 CHAPTER 5 CLOCK GENERATOR (3) Main clock mode register (MCM) This register sets the CPU clock (high-speed system clock/Ring-OSC clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-4. Format of Main Clock Mode Register (MCM) Note Address: FFA1H After reset: 00H...
Page 115 CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the high-speed system clock oscillator operation when the CPU is operating with the Ring-OSC clock.
Page 116 CHAPTER 5 CLOCK GENERATOR (5) Oscillation stabilization time counter status register (OSTC) This is the status register of the high-speed system clock oscillation stabilization time counter. If the Ring-OSC clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
Page 117 CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) This register is used to select the high-speed system clock oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the high-speed system clock selected as CPU clock.
Page 118: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 High-speed system clock oscillator The high-speed system clock oscillator oscillates with a crystal resonator or ceramic resonator connected to the X1 and X2 pins. An external clock can be input to the high-speed system clock oscillator. In this case, input the clock signal to the X1 pin and input the inverse signal to the X2 pin.
Page 119 CHAPTER 5 CLOCK GENERATOR Caution When using the high-speed system clock oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-8 and 5-9 to avoid an adverse effect from wiring capacitance. •...
Page 120 CHAPTER 5 CLOCK GENERATOR Figure 5-10. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
Page 121: When Subsystem Clock Is Not Used
CHAPTER 5 CLOCK GENERATOR 5.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows. Note XT1: Connect directly to EV or V XT2: Leave open Note When the subsystem clock is not used, the on-chip feedback resistor must be set after a reset is released...
Page 122: Clock Generator Operation
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. • High-speed system clock f • Ring-OSC clock f • Subsystem clock f •...
Page 123 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Timing Diagram of CPU Default Start Using Ring-OSC High-speed system clock Ring-OSC clock Subsystem clock RESET Switched by software High-speed system clock CPU clock Ring-OSC clock Operation stopped: 17/f High-speed system clock oscillation stabilization time: Note to 2 Note Check using the oscillation stabilization time counter status register (OSTC).
Page 124 CHAPTER 5 CLOCK GENERATOR A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 5-3 and 5-4, respectively.
Page 125 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Status Transition Diagram (2/4) (2) When “Ring-OSC can be stopped by software” is selected by option byte (when subsystem clock is used) Status 6 CPU clock: f : Oscillation stopped : Oscillating/ oscillation stopped Interrupt MCC = 0 MCC = 1...
Page 126 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Status Transition Diagram (3/4) (3) When “Ring-OSC cannot be stopped” is selected by option byte (when subsystem clock is not used) HALT HALT HALT instruction Interrupt Interrupt instruction Interrupt HALT instruction Status 3 Status 2 Status 1 Note 2 MCM0 = 0...
Page 127 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Status Transition Diagram (4/4) (4) When “Ring-OSC cannot be stopped” is selected by option byte (when subsystem clock is used) Status 5 CPU clock: f : Oscillation stopped : Oscillating Interrupt MCC = 0 MCC = 1 HALT instruction Status 4...
Page 128 CHAPTER 5 CLOCK GENERATOR Table 5-3. Relationship Between Operation Clocks in Each Operation Status Status High-Speed System Ring-OSC Oscillator Subsystem CPU Clock Prescaler Clock Clock Oscillator Clock After Supplied to Peripherals Oscillator Release MSTOP = 0 MSTOP = 1 Note 1 Note 2 Operation MCC = 0...
Page 129: Time Required To Switch Between Ring-Osc Clock And High-Speed System Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Time Required to Switch Between Ring-OSC Clock and High-Speed System Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and high- speed system clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch clock after switching MCM0 (see Table 5-5).
Page 130: Time Required For Cpu Clock Switchover
CHAPTER 5 CLOCK GENERATOR 5.7 Time Required for CPU Clock Switchover The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on the pre-switchover clock for several instructions (see Table 5-6).
Page 131: Clock Switching Flowchart And Register Setting
CHAPTER 5 CLOCK GENERATOR 5.8 Clock Switching Flowchart and Register Setting 5.8.1 Switching from Ring-OSC clock to high-speed system clock Figure 5-14. Switching from Ring-OSC Clock to High-Speed System Clock (Flowchart) After reset PCC = 00H RCM = 00H ; Ring-OSC oscillation Register value MCM = 00H ;...
Page 132: Switching From High-Speed System Clock To Ring-Osc Clock
CHAPTER 5 CLOCK GENERATOR 5.8.2 Switching from high-speed system clock to Ring-OSC clock Figure 5-15. Switching from High-Speed System Clock to Ring-OSC Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; High-speed system clock oscillation in high-speed system PCC.4 (CSS) = 0 ;...
Page 133: Switching From High-Speed System Clock To Subsystem Clock
CHAPTER 5 CLOCK GENERATOR 5.8.3 Switching from high-speed system clock to subsystem clock Figure 5-16. Switching from High-Speed System Clock to Subsystem Clock (Flowchart) Register setting PCC.7 (MCC) = 0 ; High-speed system clock oscillation in high-speed system PCC.4 (CSS) = 0 ;...
Page 134: Switching From Subsystem Clock To High-Speed System Clock
CHAPTER 5 CLOCK GENERATOR 5.8.4 Switching from subsystem clock to high-speed system clock Figure 5-17. Switching from Subsystem Clock to High-Speed System Clock (Flowchart) PCC.4 (CSS) = 1 ; Subsystem clock operation MCM = 03H No: High-speed system clock oscillating MCC = 1? ;...
Page 135: Register Settings
CHAPTER 5 CLOCK GENERATOR 5.8.5 Register settings The table below shows the statuses of the setting flags and status flags when each mode is set. Table 5-7. Clock and Register Setting Mode Setting Flag Status Flag PCC Register Register Register Register Register Register...
Page 136: Chapter 6 16-Bit Timer/Event Counters 00 And 01
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 µ µ PD78F0132H incorporates 16-bit timer/event counter 00, and the PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD incorporate 16-bit timer/event counters 00 and 01. 6.1 Functions of 16-Bit Timer/Event Counters 00 and 01 Note 16-bit timer/event counters 00 and 01 have the following functions.
Page 137: Configuration Of 16-Bit Timer/Event Counters 00 And 01
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Configuration Timer counter 16 bits (TM0n) Register 16-bit timer capture/compare register: 16 bits (CR00n, CR01n)
Page 138 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-2. Block Diagram of 16-Bit Timer/Event Counter 01 µ PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD Only) Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 To CR011 INTTM001 16-bit timer capture/compare Noise elimi- TI011/TO01/P06 register 001 (CR001)
Page 139 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 6-3. Format of 16-Bit Timer Counter 0n (TM0n) Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) After reset: 0000H Symbol...
Page 140 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 6-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins (1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1) CR00n Capture Trigger TI00n Pin Valid Edge ES0n1 ES0n0 Falling edge...
Page 141 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n (CRC0n).
Page 142: Registers Controlling 16-Bit Timer/Event Counters 00 And 01
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 The following six registers are used to control 16-bit timer/event counters 00 and 01. • 16-bit timer mode control register 0n (TMC0n) • Capture/compare control register 0n (CRC0n) •...
Page 143 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear TO00 inversion timing selection Interrupt request generation mode selection Operation stop...
Page 144 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address FFB6H After reset: 00H Symbol <0> TMC01 TMC013 TMC012 TMC011 OVF01 TMC013 TMC012 TMC011 Operating mode and clear TO01 inversion timing selection Interrupt request generation mode selection Operation stop...
Page 145 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) This register controls the operation of the 16-bit timer capture/compare registers (CR00n, CR01n). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC0n to 00H. µ...
Page 146 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-9. Format of Capture/Compare Control Register 01 (CRC01) Address: FFB8H After reset: 00H Symbol CRC01 CRC012 CRC011 CRC010 CRC012 CR011 operating mode selection Operates as compare register Operates as capture register CRC011 CR001 capture trigger selection Captures on valid edge of TI011 pin...
Page 147 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-10. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger control via software No one-shot pulse output trigger One-shot pulse output trigger OSPE00...
Page 148 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-11. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 OSPT01 One-shot pulse output trigger control via software No one-shot pulse output trigger One-shot pulse output trigger OSPE01...
Page 149 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) This register is used to set the 16-bit timer counter 0n (TM0n) count clock and TI00n and TI01n pin input valid edges. PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM0n to 00H.
Page 150 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 16-bit timer/event counter 00 is not guaranteed.
Page 151 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-13. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H Symbol PRM01 ES111 ES110 ES011 ES010 PRM011 PRM010 ES111 ES110 TI011 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES011...
Page 152 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 16-bit timer/event counter 01 is not guaranteed.
Page 153: Operation Of 16-Bit Timer/Event Counters 00 And 01
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4 Operation of 16-Bit Timer/Event Counters 00 and 01 6.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 6-15 allows operation as an interval timer. Setting The basic operation setting procedure is as follows.
Page 154 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-15. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0...
Page 155 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-16. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00n (CR00n) INTTM00n Note 1 Note 1 Note 2 16-bit timer counter 0n OVF0n Note 1 (TM0n) Noise TI000/P00 eliminator Note 1 (TI001/P05) Clear circuit...
Page 156: Ppg Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.2 PPG output operations Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 6-18 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows.
Page 157 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-18. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0...
Page 158 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-19. Configuration Diagram of PPG Output 16-bit timer capture/compare register 00n (CR00n) Note Note Clear 16-bit timer counter 0n Note circuit (TM0n) Noise TI000/P00 Note (TI001/P05) eliminator TO00/TI010/P01 ( TO01/TI011/P06 ) 16-bit timer capture/compare register 01n (CR01n) Note Frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in...
Page 159: Pulse Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00n pin and TI01n pin using 16-bit timer counter 0n (TM0n). There are two measurement methods: measuring with TM0n used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00n pin.
Page 160 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an external interrupt request signal (INTTM01n) is set.
Page 161 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-23. Configuration Diagram for Pulse Width Measurement with Free-Running Counter Note 16-bit timer counter 0n Note OVF0n (TM0n) Note 16-bit timer capture/compare TI00n register 01n (CR01n) INTTM01n Internal bus Note Frequencies without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16- bit timer/event counter 01.
Page 162 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI00n pin and the TI01n pin. When the edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set.
Page 163 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-26. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 D2 + 2 TM0n count value TI00n pin input CR01n capture value...
Page 164 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI00n pin. When the rising or falling edge specified by bits 4 and 5 (ES0n0 and ES0n1) of prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is taken into 16-bit timer capture/compare register 01n (CR01n) and an interrupt request signal (INTTM01n) is set.
Page 165 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-28. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM0n count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1...
Page 166 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-29. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts at valid edge of TI00n pin. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1...
Page 167: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 6-31 for the set value). <2> Set the count clock by using the PRM0n register. <3>...
Page 168 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-31. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1...
Page 169 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-32. Configuration Diagram of External Event Counter Internal bus 16-bit timer capture/compare register 00n (CR00n) Match INTTM00n Clear Noise eliminator Note OVF0n 16-bit timer counter 0n (TM0n) Valid edge of TI00n pin Note OVF0n is set to 1 only when CR00n is set to FFFFH.
Page 170: Square-Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figure 6-34 for the set value). <3>...
Page 171 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-34. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n TOC0n Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting “11”...
Page 172: One-Shot Pulse Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.6 One-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI00n pin input). Setting The basic operation setting procedure is as follows. <1>...
Page 173 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-36. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Free-running mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n CR00n as compare register...
Page 174 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-37. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0n to 04H (TM0n count starts) Count clock TM0n count 0000H 0001H N + 1 0000H N – 1 M – 1 M + 1 M + 2 CR01n set value CR00n set value...
Page 175 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-38. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n TMC0n Clears and starts at valid edge of TI00n pin.
Page 176 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-39. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC0n is set to 08H (TM0n count starts) Count clock TM0n count value 0000H 0001H 0000H N + 1 N + 2 M –...
Page 177: Cautions For 16-Bit Timer/Event Counters 00 And 01
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.5 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 0n (TM0n) is started asynchronously to the count clock.
Page 178 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (6) Operation of OVF0n flag <1> The OFV0n flag is also set to 1 in the following case. When any of the following modes is selected: the mode in which clear & start occurs on a match between TM0n and CR00n, the mode in which clear &...
Page 179 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (8) Timer operation <1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit timer capture/compare register 01n (CR01n). <2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI00n/TI01n pins are not acknowledged.
Page 180: Chapter 7 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output Figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
Page 181 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus 8-bit timer compare Selector INTTM51 register 51 (CR51) TI51/TO51/P33/INTP4 Note 1 Match 8-bit timer TO51/TI51/ counter 51 (TM51) P33/INTP4 Clear Note 2 Output latch PM33 (P33)
Page 182: Configuration Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register 8-bit timer compare register 5n (CR5n)
Page 183 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match.
Page 184: Registers Controlling 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
Page 185 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 Note TCL512 TCL511 TCL510 Count clock selection TI51 falling edge TI51 rising edge (10 MHz) /2 (5 MHz) (625 kHz)
Page 186 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3>...
Page 187 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Note Address: FF43H After reset: 00H Symbol <7> <3> <2> <0> TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516...
Page 188 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50/FLMD1 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0.
Page 189: Operations Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
Page 190 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt acknowledged Interrupt acknowledged Interval time...
Page 191: Operation As External Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 192: Square-Wave Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.
Page 193: Pwm Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-13. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM5n count value Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
Page 194 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. • Clear the port output latch (P17 or P33) Note Note and port mode register (PM17 or PM33) to 0. • TCL5n: Select the count clock. •...
Page 195 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-14. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n <5>...
Page 196 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 7-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change. Count clock TM5n N N + 1 N + 2...
Page 197: Cautions For 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Page 198: Chapter 8 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. • Interval timer • PWM output mode • Square-wave output • Carrier generator mode (8-bit timer H1 only) 8.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware.
Page 199 Figure 8-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H 8-bit timer H compare register compare register 00 (CMP00) 10 (CMP10) Decoder TOH0/P15 Selector Output latch...
Page 200 Figure 8-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode 8-bit timer H carrier register 1 (TMHMD1) control register 1 (TMCYC1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 8-bit timer H 8-bit timer H RMC1 NRZB1 NRZ1 compare compare register 1 1...
Page 201 CHAPTER 8 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 8-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) After reset: 00H Symbol...
Page 202: Registers Controlling 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register 1 (TMCYC1) Note •...
Page 203 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H <7> <1> <0> TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) Note 1 CKS02...
Page 204 CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H0 is not guaranteed.
Page 205 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH After reset: 00H <7> <1> <0> TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) Note CKS12...
Page 206 CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H1 is not guaranteed (except when CKS12, CKS11, CKS10 = 1, 0, 1 (f 2.
Page 207 CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 208: Operation Of 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4 Operation of 8-Bit Timers H0 and H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
Page 209 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n...
Page 210 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn...
Page 211: Operation As Pwm Output Mode
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
Page 212 CHAPTER 8 8-BIT TIMERS H0 AND H1 <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after the count operation is enabled. When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active.
Page 213 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H ≤...
Page 214 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n CMP1n...
Page 215 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn INTTMHn...
Page 216 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n...
Page 217: Carrier Generator Mode Operation (8-Bit Timer H1 Only)
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output.
Page 218 CHAPTER 8 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal.
Page 219 CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 8-14. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11...
Page 220 CHAPTER 8 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/f Duty = High-level width : Carrier clock output width = ( M + 1) : (N + M + 2) Cautions 1.
Page 221 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer Hn count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H Hn count value CMPn0...
Page 222 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer Hn count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H Hn count value CMPn0...
Page 223 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1...
Page 224: Chapter 9 Watch Timer
CHAPTER 9 WATCH TIMER 9.1 Functions of Watch Timer The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 9-1 shows the watch timer block diagram. Figure 9-1.
Page 225 CHAPTER 9 WATCH TIMER (1) Watch timer When the high-speed system clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 9-1. Watch Timer Interrupt Time Interrupt Time When Operated at f = 32.768 kHz When Operated at f = 10 MHz µ...
Page 226: Configuration Of Watch Timer
CHAPTER 9 WATCH TIMER 9.2 Configuration of Watch Timer The watch timer includes the following hardware. Table 9-3. Watch Timer Configuration Item Configuration 5 bits × 1 Counter 11 bits × 1 Prescaler Control register Watch timer operation mode register (WTM) 9.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM).
Page 227 CHAPTER 9 WATCH TIMER Figure 9-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF6FH After reset: 00H Symbol <1> <0> WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 Watch timer count clock selection (78.125 kHz) (32.768 kHz) WTM6 WTM5 WTM4...
Page 228: Watch Timer Operations
CHAPTER 9 WATCH TIMER 9.4 Watch Timer Operations 9.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval by using the high-speed system clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts.
Page 229: Interval Timer Operation
CHAPTER 9 WATCH TIMER 9.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM).
Page 230: Cautions For Watch Timer
CHAPTER 9 WATCH TIMER 9.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2 and WTM3) of WTM.
Page 231: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, refer to CHAPTER 20 RESET FUNCTION.
Page 232 CHAPTER 10 WATCHDOG TIMER Table 10-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Ring-OSC Cannot Be Stopped Ring-OSC Can Be Stopped by Software • Selectable by software (f Note 1 Watchdog timer clock Fixed to f or stopped) •...
Page 233: Configuration Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes following hardware. Table 10-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 10-1. Block Diagram of Watchdog Timer Clock Output 16-bit...
Page 234: Registers Controlling Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer mode register (WDTM) • Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released.
Page 235 CHAPTER 10 WATCHDOG TIMER Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM when the CPU is operating on the subsystem clock and the high-speed system clock is stopped. For details, see CHAPTER 32 CAUTIONS FOR WAIT. 2.
Page 236 CHAPTER 10 WATCHDOG TIMER The relationship between the watchdog timer operation and the internal reset signal generated by the watchdog timer is shown below. Table 10-4. Relationship Between Watchdog Timer Operation and Internal Reset Signal Generated by Watchdog Timer Watchdog Timer “Ring-OSC Cannot Be “Ring-OSC Can Be Stopped by Software”...
Page 237: Operation Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to the Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 238: Watchdog Timer Operation When "Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte
CHAPTER 10 WATCHDOG TIMER 10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the high-speed system clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 239: Watchdog Timer Operation In Stop Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte)
CHAPTER 10 WATCHDOG TIMER 10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the high-speed system clock or Ring-OSC clock is being used. (1) When the CPU clock and the watchdog timer operation clock are the high-speed system clock (f ) when the STOP instruction is executed...
Page 240 CHAPTER 10 WATCHDOG TIMER (3) When the CPU clock is the Ring-OSC clock (f ) and the watchdog timer operation clock is the high-speed system clock (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is stopped until the timing of <1>...
Page 241: Watchdog Timer Operation In Halt Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte)
CHAPTER 10 WATCHDOG TIMER (4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (f ) during STOP instruction execution When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped.
Page 242: Chapter 11 Clock Output/Buzzer Output Controller
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 11.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS.
Page 243: Configuration Of Clock Output/Buzzer Output Controller
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 11.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 11-1. Clock Output/Buzzer Output Controller Configuration Item Configuration Control registers Clock output selection register (CKS) Port mode register 14 (PM14) Port register 14 (P14) 11.3 Register Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller.
Page 244 CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 11-2. Format of Clock Output Selection Register (CKS) Address: FF40H After reset: 00H Symbol <7> <4> BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ output enable/disable specification Clock division circuit operation stopped. BUZ fixed to low level. Clock division circuit operation enabled.
Page 245: Clock Output/Buzzer Output Controller Operations
CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output and the P141/INTP7/BUZ pin for buzzer output, set PM140, PM141 and the output latch of P140, P141 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 246: Chapter 12 A/D Converter
CHAPTER 12 A/D CONVERTER 12.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI7.
Page 247: Configuration Of A/D Converter
CHAPTER 12 A/D CONVERTER 12.2 Configuration of A/D Converter The A/D converter includes the following hardware. Table 12-1. Registers of A/D Converter Used on Software Item Configuration Registers A/D conversion result register (ADCR) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT) (1) ANI0 to ANI7 pins...
Page 248 CHAPTER 12 A/D CONVERTER (6) A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register (SAR) to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its higher 10 bits (the lower 6 bits are fixed to 0).
Page 249: Registers Used In A/D Converter
CHAPTER 12 A/D CONVERTER 12.3 Registers Used in A/D Converter The A/D converter uses the following five registers. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • A/D conversion result register (ADCR) • Power-fail comparison mode register (PFM) •...
Page 250 CHAPTER 12 A/D CONVERTER Table 12-2. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Note Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates) Note Data of first conversion cannot be used.
Page 251 CHAPTER 12 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 12-5.
Page 252 CHAPTER 12 A/D CONVERTER (3) A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from the most significant bit (MSB).
Page 253 CHAPTER 12 A/D CONVERTER (4) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the ADCR register) and the value of the power-fail comparison threshold register (PFT). PFM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 254: A/D Converter Operations
CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Operations 12.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). µ <2> Set ADCE to 1 and wait for 14 s or longer. <3>...
Page 255 CHAPTER 12 A/D CONVERTER Figure 12-9. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 256: Input Voltage And Conversion Results
CHAPTER 12 A/D CONVERTER 12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression. ×...
Page 257: A/D Converter Operation Mode
CHAPTER 12 A/D CONVERTER 12.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting of bit 7 (PFEN) of the power-fail comparison mode register (PFM).
Page 258 CHAPTER 12 A/D CONVERTER (2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started.
Page 259 CHAPTER 12 A/D CONVERTER The setting methods are described below. • When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
Page 260: How To Read A/D Converter Characteristics Table
CHAPTER 12 A/D CONVERTER 12.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 261 CHAPTER 12 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 262: Cautions For A/D Converter
CHAPTER 12 A/D CONVERTER 12.6 Cautions for A/D Converter (1) Operating current in standby mode The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 (see Figure 12-2). (2) Input range of ANI0 to ANI7 Observe the rated range of the ANI0 to ANI7 input voltage.
Page 263 CHAPTER 12 A/D CONVERTER (5) ANI0/P20 to ANI7/P27 <1> The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access port 2 while conversion is in progress;...
Page 264 CHAPTER 12 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 265 CHAPTER 12 A/D CONVERTER (11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). The delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 12-21 and Table 12-3.
Page 266 CHAPTER 12 A/D CONVERTER (13) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 12-22. Internal Equivalent Circuit of ANIn Pin ANIn Table 12-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 2.7 V 12 kΩ...
Page 267: Chapter 13 Serial Interface Uart0
CHAPTER 13 SERIAL INTERFACE UART0 13.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 268: Configuration Of Serial Interface Uart0
CHAPTER 13 SERIAL INTERFACE UART0 13.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 13-1. Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0)
Page 269 Figure 13-1. Block Diagram of Serial Interface UART0 Filter SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial Asynchronous serial INTSR0 Reception control Receive buffer register 0 Baud rate interface operation mode interface reception error (RXB0) generator register 0 (ASIM0) status register 0 (ASIS0) Reception unit Internal bus 8-bit timer/...
Page 270 CHAPTER 13 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0).
Page 271: Registers Controlling Serial Interface Uart0
CHAPTER 13 SERIAL INTERFACE UART0 13.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. • Asynchronous serial interface operation mode register 0 (ASIM0) • Asynchronous serial interface reception error status register 0 (ASIS0) •...
Page 272 CHAPTER 13 SERIAL INTERFACE UART0 Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 273 CHAPTER 13 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. RESET input or clearing bit 7 (POWER0) or bit 5 (RXE0) of ASIM0 to 0 clears this register to 00H.
Page 274 CHAPTER 13 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH.
Page 275 CHAPTER 13 SERIAL INTERFACE UART0 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring- OSC clock, the operation of serial interface UART0 is not guaranteed.
Page 276: Operation Of Serial Interface Uart0
CHAPTER 13 SERIAL INTERFACE UART0 13.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 13.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode.
Page 277: Asynchronous Serial Interface (Uart) Mode
CHAPTER 13 SERIAL INTERFACE UART0 13.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 278 CHAPTER 13 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 13-6 and 13-7 show the format and waveform example of the normal transmit/receive data. Figure 13-6. Format of Normal UART Transmit/Receive Data 1 data frame Start Parity...
Page 279 CHAPTER 13 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 280 CHAPTER 13 SERIAL INTERFACE UART0 (c) Transmission The T D0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0).
Page 281 CHAPTER 13 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the R D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the R D0 pin input is detected.
Page 282 CHAPTER 13 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated.
Page 283: Dedicated Baud Rate Generator
CHAPTER 13 SERIAL INTERFACE UART0 13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 284 CHAPTER 13 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter.
Page 285 CHAPTER 13 SERIAL INTERFACE UART0 (3) Example of setting baud rate Table 13-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%] TPS00 Value TPS00...
Page 286 CHAPTER 13 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 287 CHAPTER 13 SERIAL INTERFACE UART0 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 288: Chapter 14 Serial Interface Uart6
CHAPTER 14 SERIAL INTERFACE UART6 14.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 289 CHAPTER 14 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
Page 290 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-2. LIN Reception Operation Wakeup Synchronous Synchronous Identifier Data field Data field Checksum signal frame break field field field field Sleep Data Data Data Note 5 reception reception reception reception reception Note 2 13 bits reception Disable Enable...
Page 291 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0 INTP0 input Port mode Port input (PM120) switch control (ISC0) Output latch <ISC0> (P120) 0: Select INTP0 (P120) 1: Select RxD6 (P14) Selector...
Page 292: Configuration Of Serial Interface Uart6
CHAPTER 14 SERIAL INTERFACE UART6 14.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 14-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Page 293 Figure 14-4. Block Diagram of Serial Interface UART6 Note TI000, INTP0 Filter INTSR6 Reception control INTSRE6 Receive shift register 6 (RXS6) Asynchronous serial Asynchronous serial Asynchronous serial interface Baud rate Receive buffer register 6 interface operation mode interface reception error control register 6 (ASICL6) generator (RXB6)
Page 294 CHAPTER 14 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows.
Page 295: Registers Controlling Serial Interface Uart6
CHAPTER 14 SERIAL INTERFACE UART6 14.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
Page 296 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity.
Page 297 CHAPTER 14 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. RESET input or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H.
Page 298 CHAPTER 14 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 299 CHAPTER 14 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 300 CHAPTER 14 SERIAL INTERFACE UART6 Remarks 1. Figures in parentheses are for operation with f = 10 MHz 2. f : High-speed system clock oscillation frequency 3. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6.
Page 301 CHAPTER 14 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 302 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
Page 303 CHAPTER 14 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input source is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 304: Operation Of Serial Interface Uart6
CHAPTER 14 SERIAL INTERFACE UART6 14.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 305: Asynchronous Serial Interface (Uart) Mode
CHAPTER 14 SERIAL INTERFACE UART6 14.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 306 CHAPTER 14 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 PM14 UART6 Pin Function Operation TxD6/P13 RxD6/P14 Note Note Note Note × ×...
Page 307 CHAPTER 14 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-13 and 14-14 show the format and waveform example of the normal transmit/receive data. Figure 14-13. Format of Normal UART Transmit/Receive Data 1.
Page 308 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...
Page 309 CHAPTER 14 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 310 CHAPTER 14 SERIAL INTERFACE UART6 (c) Normal transmission The T D6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
Page 311 CHAPTER 14 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
Page 312 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-16 shows an example of the continuous transmission processing flow. Figure 14-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6. Transmission completion interrupt occurs?
Page 313 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-17 shows the timing of starting continuous transmission, and Figure 14-18 shows the timing of ending continuous transmission. Figure 14-17. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6...
Page 314 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-18. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6...
Page 315 CHAPTER 14 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the R D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
Page 316 CHAPTER 14 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Page 317 CHAPTER 14 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 318 CHAPTER 14 SERIAL INTERFACE UART6 SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 14-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
Page 319: Dedicated Baud Rate Generator
CHAPTER 14 SERIAL INTERFACE UART6 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 320 CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-24. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6...
Page 321 CHAPTER 14 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
Page 322 CHAPTER 14 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 14-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS60...
Page 323 CHAPTER 14 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 324 CHAPTER 14 SERIAL INTERFACE UART6 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 325 CHAPTER 14 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 326: Chapter 15 Serial Interfaces Csi10 And Csi11
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 µ µ PD78F0132H incorporate serial interface CSI10, and the PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD incorporate serial interfaces CSI10 and CSI11. 15.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes. •...
Page 327: Configuration Of Serial Interfaces Csi10 And Csi11
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 include the following hardware. Table 15-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Configuration Registers Transmit buffer register 1n (SOTB1n) Serial I/O shift register 1n (SIO1n) Control registers Serial operation mode register 1n (CSIM1n)
Page 328 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-2. Block Diagram of Serial Interface CSI11 µ PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD Only) Internal bus Serial I/O shift Transmit buffer Output SI11/P03 register 11 (SIO11) register 11 (SOTB11) SO11/P02 selector Output latch Transmit data Output latch...
Page 329: Registers Controlling Serial Interfaces Csi10 And Csi11
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. • Serial operation mode register 1n (CSIM1n) • Serial clock selection register 1n (CSIC1n) •...
Page 330 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-4. Format of Serial Operation Mode Register 11 (CSIM11) Note 1 Address: FF88H After reset: 00H R/W Symbol <7> CSIM11 CSIE11 TRMD11 SSE11 DIR11 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 2 Note 3 Disables operation...
Page 331 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 332 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Cautions 1. When the Ring-OSC clock is selected as the clock supplied to the CPU, the clock of the Ring- OSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI10 is not guaranteed.
Page 333 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Note Set the serial clock so that the following conditions are satisfied. • V = 4.0 to 5.5 V: Serial clock ≤ 5 MHz • V = 3.3 to 4.0 V: Serial clock ≤ 4.19 MHz •...
Page 334 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (3) Port mode registers 0 and 1 (PM0, PM1) These registers set port 0 and 1 input/output in 1-bit units. Note When using P10/SCK10 and P04/SCK11 as the clock output pins of the serial interface, clear PM10 and PM04 to 0 and set the output latches of P10 and P04 to 1.
Page 335: Operation Of Serial Interfaces Csi10 And Csi11
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 15.4.1 Operation stop mode Serial communication is not executed in this mode.
Page 336: 3-Wire Serial I/O Mode
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 15.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines.
Page 337 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 PM12 PM10 CSI10 Pin Function Operation SI10/RxD0/ SO10/P12 SCK10/...
Page 338 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Table 15-2. Relationship Between Register Settings and Pins (2/2) µ (b) Serial interface CSI11 ( PD78F0133H, 78F0134H, 78F0136H, 78F0138H and 78F0138HD only) CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05 CSI11 Pin Function Operation...
Page 339 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n).
Page 340 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-9. Timing in 3-Wire Serial I/O Mode (1/2) Note (1) Transmission/reception timing (Type 1; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
Page 341 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-9. Timing in 3-Wire Serial I/O Mode (2/2) Note (2) Transmission/reception timing (Type 2; TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
Page 342 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 Figure 15-10. Timing of Clock/Data Phase (a) Type 1; CKP1n = 0, DAP1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n (b) Type 2; CKP1n = 0, DAP1n = 1 SCK1n SI1n capture SO1n...
Page 343 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 15-11.
Page 344 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 15-12. Output Value of SO1n Pin (Last Bit) (1) Type 1;...
Page 345 CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is cleared to 0. Table 15-3. SO1n Output Status Note 1 TRMD1n DAP1n DIR1n...
Page 346: Chapter 16 Multiplier/Divider
CHAPTER 16 MULTIPLIER/DIVIDER 16.1 Functions of Multiplier/Divider The multiplier/divider has the following functions. • 16 bits × 16 bits = 32 bits (multiplication) • 32 bits ÷ 16 bits = 32 bits, 16-bit remainder (division) 16.2 Configuration of Multiplier/Divider The multiplier/divider includes the following hardware. Table 16-1.
Page 347 Figure 16-1. Block Diagram of Multiplier/Divider Internal bus Multiplier/divider control register 0 (DMUC0) Multiplication/division data register A0 Multiplication/division data register B0 Remainder data register 0 DMUSEL0 DMUE (MDB0 (MDB0H + MDB0L) (SDR0 (SDR0H + SDR0L) (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL) ) Start MDA000 INTDMU...
Page 348 CHAPTER 16 MULTIPLIER/DIVIDER (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. This register can be read by an 8-bit or 16-bit memory manipulation instruction. RESET input clears this register to 0000H.
Page 349 CHAPTER 16 MULTIPLIER/DIVIDER The functions of MDA0 when an operation is executed are shown in the table below. Table 16-2. Functions of MDA0 During Operation Execution DMUSEL0 Operation Mode Setting Operation Result Division mode Dividend Division result (quotient) Multiplication mode Higher 16 bits: 0, Lower 16 Multiplication result bits: Multiplier A...
Page 350: Register Controlling Multiplier/Divider
CHAPTER 16 MULTIPLIER/DIVIDER 16.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. This register can be read by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 351: Operations Of Multiplier/Divider
CHAPTER 16 MULTIPLIER/DIVIDER 16.4 Operations of Multiplier/Divider 16.4.1 Multiplication operation • Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start. •...
Page 352 Figure 16-6. Timing Chart of Multiplication Operation (00DAH × 0093H) Operation clock DMUE DMUSEL0 Internal clock Counter XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SDR0 0000 0049 0024 005B 0077 003B 0067...
Page 353: Division Operation
CHAPTER 16 MULTIPLIER/DIVIDER 16.4.2 Division operation • Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively. Operation will start.
Page 354 Figure 16-7. Timing Chart of Division Operation (DCBA2586H ÷ 0018H) Operation clock DMUE DMUSEL0 “0” Internal clock 1B 1C 1D 1E Counter XXXX 0000 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 SDR0 B974 72E8...
Page 355: Chapter 17 Interrupt Functions
CHAPTER 17 INTERRUPT FUNCTIONS 17.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated.
Page 356 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (1/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Note 3 Maskable INTLVI Low-voltage detection Internal 0004H INTP0 Pin input edge detection External 0006H INTP1...
Page 357 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (2/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Maskable INTDMU End of multiply/divide operation Internal 0034H Note 3 INTCSI11 End of CSI11 communication 0036H...
Page 358 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP7) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...
Page 359: Registers Controlling Interrupt Functions
CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus Interrupt Vector table Priority controller request address generator interrupt detector 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus Interrupt...
Page 360 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-2. Flags Corresponding to Interrupt Request Sources Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Request Register Register Register INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2...
Page 361 CHAPTER 17 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input.
Page 362 CHAPTER 17 INTERRUPT FUNCTIONS Caution 3. Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of the interrupt request flag register. A 1-bit manipulation instruction such as “IF0L.0 = 0;” and “_asm(“clr1 IF0L, 0”);” should be used when describing in C language, because assembly instructions after compilation must be 1-bit memory manipulation instructions (CLR1).
Page 363 CHAPTER 17 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set with a 16-bit memory manipulation instruction.
Page 364 CHAPTER 17 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set with a 16-bit memory manipulation instruction.
Page 365 CHAPTER 17 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP7. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 366 CHAPTER 17 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
Page 367: Interrupt Servicing Operations
CHAPTER 17 INTERRUPT FUNCTIONS 17.4 Interrupt Servicing Operations 17.4.1 Maskable interrupt acknowledgement A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 368 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-7. Interrupt Request Acknowledgement Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 369: Software Interrupt Request Acknowledgement
CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-8. Interrupt Request Acknowledgement Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 17-9.
Page 370: Multiple Interrupt Servicing
CHAPTER 17 INTERRUPT FUNCTIONS 17.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgement.
Page 371 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 372 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx (PR = 0) RETI IE = 1 IE = 0...
Page 373: Interrupt Request Hold
CHAPTER 17 INTERRUPT FUNCTIONS 17.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 374: Chapter 18 Key Interrupt Function
CHAPTER 18 KEY INTERRUPT FUNCTION 18.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a rising edge to the key interrupt input pins (KR0 to KR7). Table 18-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0...
Page 375: Register Controlling Key Interrupt
CHAPTER 18 KEY INTERRUPT FUNCTION 18.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. This register is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 376: Chapter 19 Standby Function
CHAPTER 19 STANDBY FUNCTION 19.1 Standby Function and Configuration 19.1.1 Standby function Table 19-1. Relationship Between Operation Clocks in Each Operation Status Status High-Speed System Ring-OSC Oscillator Subsystem CPU Clock Prescaler Clock Clock Oscillator Clock After Supplied to Peripherals Oscillator Release MSTOP = 0 MSTOP = 1...
Page 377 CHAPTER 19 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation.
Page 378: Registers Controlling Standby Function
CHAPTER 19 STANDBY FUNCTION 19.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the high-speed system clock oscillation stabilization time counter.
Page 379 CHAPTER 19 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the high-speed system clock oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the high-speed system clock is selected as the CPU clock.
Page 380: Standby Function Operation
CHAPTER 19 STANDBY FUNCTION 19.2 Standby Function Operation 19.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, Ring-OSC clock, or subsystem clock. The operating statuses in the HALT mode are shown below.
Page 381 CHAPTER 19 STANDBY FUNCTION Table 19-2. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When High-Speed System Clock Oscillation Continues When High-Speed System Clock Oscillation Stopped When Ring-OSC When Ring-OSC When Ring-OSC When Ring-OSC...
Page 382 CHAPTER 19 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.
Page 383 CHAPTER 19 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 19-4.
Page 384 CHAPTER 19 STANDBY FUNCTION Figure 19-4. HALT Mode Release by RESET Input (2/2) (3) When subsystem clock is used as CPU clock HALT instruction RESET signal Operating Reset Operation Status of CPU mode period stopped HALT mode Operating mode (17/f (Ring-OSC clock) Subsystem clock...
Page 385: Stop Mode
CHAPTER 19 STANDBY FUNCTION 19.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set when the CPU clock before the setting was the high-speed system clock or Ring-OSC clock. Caution Because the interrupt request signal is used to release the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately released if set.
Page 386 CHAPTER 19 STANDBY FUNCTION (2) STOP mode release Figure 19-5. Operation Timing When STOP Mode Is Released STOP mode release STOP mode High-speed system clock Ring-OSC clock High-speed system clock is selected as CPU HALT status High-speed system clock clock when STOP (oscillation stabilization time set by OSTS) instruction is executed Ring-OSC clock is...
Page 387 CHAPTER 19 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 19-6.
Page 388 CHAPTER 19 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 19-7. STOP Mode Release by RESET Input (1) When high-speed system clock is used as CPU clock STOP instruction...
Page 389: Chapter 20 Reset Function
CHAPTER 20 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor high-speed system clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 390 Figure 20-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF CLMRF LVIRF Watchdog timer reset signal Clear Clear Clear Clock monitor reset signal Reset signal to LVIM/LVIS register RESET Power-on-clear circuit reset signal Reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit.
Page 391 CHAPTER 20 RESET FUNCTION Figure 20-2. Timing of Reset by RESET Input Ring-OSC clock High-speed system clock Operation stop Normal operation Reset period CPU clock Normal operation (17/f (Reset processing, Ring-OSC clock) (Oscillation stop) RESET Internal reset signal Delay Delay Port pin Hi-Z (except P130)
Page 392 CHAPTER 20 RESET FUNCTION Figure 20-4. Timing of Reset in STOP Mode by RESET Input Ring-OSC clock High-speed system clock STOP instruction execution Operation stop Normal Normal operation Reset period Stop status CPU clock (17/f operation (Reset processing, Ring-OSC clock) (Oscillation stop) (Oscillation stop) RESET...
Page 393 CHAPTER 20 RESET FUNCTION Table 20-1. Hardware Statuses After Reset Acknowledgment (1/3) Hardware Status After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
Page 394 CHAPTER 20 RESET FUNCTION Table 20-1. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Status After Reset Acknowledgment Clock output/buzzer Clock output selection register (CKS) output controller Watchdog timer Mode register (WDTM) Enable register (WDTE) A/D converter Conversion result register (ADCR) Undefined Mode register (ADM) Analog input channel specification register (ADS)
Page 395 CHAPTER 20 RESET FUNCTION Table 20-1. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Acknowledgment Note 1 Reset function Reset control flag register (RESF) Note 1 Low-voltage detector Low-voltage detection register (LVIM) Note 1 Low-voltage detection level selection register (LVIS) Interrupt Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H) Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L)
Page 396: Register For Confirming Reset Source
CHAPTER 20 RESET FUNCTION 20.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KE1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Page 397: Chapter 21 Clock Monitor
CHAPTER 21 CLOCK MONITOR 21.1 Functions of Clock Monitor The clock monitor samples the high-speed system clock using the on-chip Ring-OSC, and generates an internal reset signal when the high-speed system clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1.
Page 398: Registers Controlling Clock Monitor
CHAPTER 21 CLOCK MONITOR 21.3 Registers Controlling Clock Monitor The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 399: Operation Of Clock Monitor
CHAPTER 21 CLOCK MONITOR 21.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows. <Monitor start condition> When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1). <Monitor stop condition>...
Page 400 CHAPTER 21 CLOCK MONITOR Figure 21-3. Timing of Clock Monitor (1/4) (1) When internal reset is executed by oscillation stop of high-speed system clock 4 clocks of Ring-OSC clock High-speed system clock Ring-OSC clock Internal reset signal CLME CLMRF (2) Clock monitor status after RESET input (CLME = 1 is set after RESET input and during high-speed system clock oscillation stabilization time) Clock supply Normal...
Page 401 CHAPTER 21 CLOCK MONITOR Figure 21-3. Timing of Clock Monitor (2/4) (3) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of high-speed system clock oscillation stabilization time) Normal Clock supply operation CPU operation Reset...
Page 402 CHAPTER 21 CLOCK MONITOR Figure 21-3. Timing of Clock Monitor (3/4) (5) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode) Clock supply Normal stopped Normal operation operation...
Page 403 CHAPTER 21 CLOCK MONITOR Figure 21-3. Timing of Clock Monitor (4/4) (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software Normal operation (high-speed system clock or subsystem clock) CPU operation High-speed system clock Ring-OSC clock Oscillation stopped Note RSTOP CLME...
Page 404: Chapter 22 Power-On-Clear Circuit
CHAPTER 22 POWER-ON-CLEAR CIRCUIT 22.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V = 2.1 V ±0.1 V), and generates internal reset signal ) and detection voltage (V when V <...
Page 405: Configuration Of Power-On-Clear Circuit
CHAPTER 22 POWER-ON-CLEAR CIRCUIT 22.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 22-1. Figure 22-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 22.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (V ) and detection voltage (V ) are compared, and when V...
Page 406: Cautions For Power-On-Clear Circuit
CHAPTER 22 POWER-ON-CLEAR CIRCUIT 22.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 407 CHAPTER 22 POWER-ON-CLEAR CIRCUIT Figure 22-3. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF register = 1?
Page 408: Chapter 23 Low-Voltage Detector
CHAPTER 23 LOW-VOLTAGE DETECTOR 23.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V < V •...
Page 409: Registers Controlling Low-Voltage Detector
CHAPTER 23 LOW-VOLTAGE DETECTOR 23.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 410 CHAPTER 23 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 23-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H Symbol...
Page 411: Operation Of Low-Voltage Detector
CHAPTER 23 LOW-VOLTAGE DETECTOR 23.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when <...
Page 412 CHAPTER 23 LOW-VOLTAGE DETECTOR Figure 23-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (V LVI detection voltage POC detection voltage Time <2> LVIMK flag (set by software) Note 1 <1> LVION flag Not cleared Not cleared (set by software) <3>...
Page 413 CHAPTER 23 LOW-VOLTAGE DETECTOR (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS).
Page 414 CHAPTER 23 LOW-VOLTAGE DETECTOR Figure 23-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (V LVI detection voltage POC detection voltage Time <2> LVIMK flag (set by software) Note 1 <1> <7> Cleared by software LVION flag (set by software) <3>...
Page 415: Cautions For Low-Voltage Detector
CHAPTER 23 LOW-VOLTAGE DETECTOR 23.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
Page 416 CHAPTER 23 LOW-VOLTAGE DETECTOR Figure 23-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
Page 417 CHAPTER 23 LOW-VOLTAGE DETECTOR Figure 23-6. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF register = 1?
Page 418: Chapter 24 Option Byte
CHAPTER 24 OPTION BYTE The 78K0/KE1+ has an area called an option byte at address 0080H of the flash memory. When using the product, be sure to set the following functions by using the option byte. Ring-OSC oscillation • Can be stopped by software. •...
Page 419: Chapter 25 Rom Correction
CHAPTER 25 ROM CORRECTION 25.1 Functions of ROM Correction µ PD78F0136H, 78F0138H, and 78F0138HD can replace part of a program in the flash memory with a program in the internal expansion RAM. Program bugs found in the flash memory can be avoided, and program flow can be changed by using the ROM correction.
Page 420 CHAPTER 25 ROM CORRECTION (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the flash memory. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1.
Page 421: Register Controlling Rom Correction
CHAPTER 25 ROM CORRECTION 25.3 Register Controlling ROM Correction The ROM correction is controlled by the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1.
Page 422: Rom Correction Usage Example
CHAPTER 25 ROM CORRECTION 25.4 ROM Correction Usage Example The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 25-4. ROM Correction Usage Example Internal flash memory Internal expansion RAM F400H 0000H...
Page 423: Rom Correction Application
CHAPTER 25 ROM CORRECTION 25.5 ROM Correction Application How to apply the example shown in 25.4 is described below. (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well.
Page 424 CHAPTER 25 ROM CORRECTION (2) Assemble in advance the initial setting routine as shown in Figure 25-6 to correct the program. Figure 25-6. Initial Setting Routine Initial setting Is ROM ROM correction Note correction used ? Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction operation enabled...
Page 425 CHAPTER 25 ROM CORRECTION Figure 25-7. ROM Correction Operation Internal flash memory program start Does fetch address match with correction address? ROM correction Set correction status flag Correction branch (branch to address F7FDH) Correction program execution User’s Manual U16899EJ2V0UD...
Page 426: Program Execution Flow
CHAPTER 25 ROM CORRECTION 25.6 Program Execution Flow Figures 25-8 and 25-9 show the program transition diagrams when the ROM correction is used. Figure 25-8. Program Transition Diagram (When One Place Is Corrected) FFFFH F7FFH BR !JUMP F7FDH Correction program JUMP Internal flash memory Correction place...
Page 427 CHAPTER 25 ROM CORRECTION Figure 25-9. Program Transition Diagram (When Two Places Are Corrected) FFFFH F7FFH BR !JUMP F7FDH Correction program 2 yyyyH Correction program 1 xxxxH Branch destination judgment program JUMP Internal flash memory Correction place 2 Internal flash memory Correction place 1 Internal flash memory 0000H...
Page 428: Cautions For Rom Correction
CHAPTER 25 ROM CORRECTION 25.7 Cautions for ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag (COREN0, COREN1) is 0 (when the correction branch is in disabled state).
Page 429: Chapter 26 Flash Memory
CHAPTER 26 FLASH MEMORY µ PD78F0132H, 78F0133H, 78F0134H, 78F0136H, and 78F0138H/HD replace the internal mask ROM of the µ PD780132, 780133, 780134, 780136, and 780138 of the 78K0/KE1 respectively with flash memory to which a program can be written, erased, and overwritten while mounted on the board. Table 26-1 lists the differences between the 78K0/KE1+ and the 78K0/KE1.
Page 430: Internal Memory Size Switching Register
CHAPTER 26 FLASH MEMORY 26.1 Internal Memory Size Switching Register The internal memory capacity can be selected using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Caution The initial value of IMS is CFH.
Page 431: Internal Expansion Ram Size Switching Register
CHAPTER 26 FLASH MEMORY 26.2 Internal Expansion RAM Size Switching Register The internal expansion RAM capacity can be selected using the internal expansion RAM size switching register (IXS). This register is set by an 8-bit memory manipulation instruction. RESET input sets IXS to 0CH. Caution The initial value of IXS is 0CH.
Page 432: Writing With Flash Programmer
CHAPTER 26 FLASH MEMORY 26.3 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0/KE1+ has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system.
Page 433 CHAPTER 26 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 26-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode (2.7 to 5.5 V) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD2 (LVDD)
Page 434 CHAPTER 26 FLASH MEMORY Figure 26-4. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode (2.7 to 5.5 V) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD2 (LVDD) /RESET FLMD0 FLMD1...
Page 435 CHAPTER 26 FLASH MEMORY Figure 26-5. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode (2.7 to 5.5 V) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD2 (LVDD) /RESET FLMD0 FLMD1...
Page 436: Programming Environment
CHAPTER 26 FLASH MEMORY 26.4 Programming Environment The environment required for writing a program to the flash memory of the 78K0/KE1+ is illustrated below. Figure 26-6. Environment for Writing Program to Flash Memory FLMD0 RS-232C FLMD1 Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 78K0/KE1+ Dedicated flash...
Page 437 CHAPTER 26 FLASH MEMORY (2) CSI communication mode supporting handshake Transfer rate: 200 kHz to 2 MHz Figure 26-8. Communication with Dedicated Flash Programmer (CSI10 + HS) FLMD0 FLMD0 FLMD1 FLMD1 Axxxx Bxxxxx /RESET RESET Cxxxxxx STATVE PG-FP4 SI/RxD SO10 SO/TxD SI10 Dedicated flash...
Page 438 CHAPTER 26 FLASH MEMORY If Flashpro IV is used as the dedicated flash programmer, Flashpro IV generates the following signal for the 78K0/KE1+. For details, refer to the Flashpro IV manual. Table 26-5. Pin Connection Flashpro IV 78K0/KE1+ Connection Signal Name Pin Function Pin Name CSI10...
Page 439: Connection Of Pins On Board
CHAPTER 26 FLASH MEMORY 26.6 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 440: Serial Interface Pins
CHAPTER 26 FLASH MEMORY 26.6.3 Serial interface pins The pins used by each serial interface are listed below. Table 26-6. Pins Used by Each Serial Interface Serial Interface Pins Used CSI10 SO10, SI10, SCK10 CSI10 + HS SO10, SI10, SCK10, HS/P15 UART6 TxD6, RxD6 To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on...
Page 441 CHAPTER 26 FLASH MEMORY (2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction.
Page 442: Reset Pin
CHAPTER 26 FLASH MEMORY 26.6.4 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator.
Page 443: Programming Method
CHAPTER 26 FLASH MEMORY 26.7 Programming Method 26.7.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 26-15. Flash Memory Manipulation Procedure Start Flash memory programming FLMD0 pulse supply mode is set Selecting communication mode Manipulate flash memory End? User’s Manual U16899EJ2V0UD...
Page 444: Flash Memory Programming Mode
CHAPTER 26 FLASH MEMORY 26.7.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0/KE1+ in the flash memory programming mode. To set the mode, set the FLMD0 pin to V and clear the reset signal.
Page 445: Selecting Communication Mode
CHAPTER 26 FLASH MEMORY 26.7.3 Selecting communication mode In the 78K0/KE1+, a communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin after the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash programmer.
Page 446: Communication Commands
CHAPTER 26 FLASH MEMORY 26.7.4 Communication commands The 78K0/KE1+ communicates with the dedicated flash programmer by using commands. The signals sent from the flash programmer to the 78K0/KE1+ are called commands, and the commands sent from the 78K0/KE1+ to the dedicated flash programmer are called response commands.
Page 447: Flash Memory Programming By Self-Writing
CHAPTER 26 FLASH MEMORY 26.8 Flash Memory Programming by Self-Writing The 78K0/KE1+ supports a self-programming function that can be used to rewrite the flash memory via a user program, so that the program can be upgraded in the field. The programming mode is selected by bits 0 and 1 (FLSPM0 and FLSPM1) of the flash programming mode control register (FLPMC).
Page 448: Registers Used For Self-Programming Function
CHAPTER 26 FLASH MEMORY 26.8.1 Registers used for self-programming function The following three registers are used for the self-programming function. • Flash programming mode control register (FLPMC) • Flash protect command register (PFCMD) • Flash status register (PFS) (1) Flash programming mode control register (FLPMC) This register is used to enable or disable writing or erasing of the flash memory and to set the operation mode during self-programming.
Page 449 CHAPTER 26 FLASH MEMORY Figure 26-19. Format of Flash Programming Mode Control Register (FLPMC) Note 1 Note 2 Address: FFC4H After reset: 0×H Symbol FLPMC FWEDIS FWEPR FLSPM1 FLSPM0 FWEDIS Control of flash memory writing/erasing Note 3 Writing/erasing enabled Writing/erasing disabled FWEPR Status of FLMD0 pin Low level...
Page 450 CHAPTER 26 FLASH MEMORY (2) Flash protect command register (PFCMD) If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system.
Page 451 CHAPTER 26 FLASH MEMORY The operating conditions of the FPRERR flag are as follows. <Setting conditions> • If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to write a specific value (A5H) to PFCMD •...
Page 452: Boot Swap Function
CHAPTER 26 FLASH MEMORY 26.9 Boot Swap Function The 78K0/KE1+ has a boot swap function. Even if a momentary power failure occurs for some reason while the boot area is being rewritten by self- programming and the program in the boot area is lost, the boot swap function can execute the program correctly after re-application of power, reset, and start.
Page 453: Memory Map And Boot Area
CHAPTER 26 FLASH MEMORY 26.9.2 Memory map and boot area Figure 26-23 shows the memory map and boot area. The boot program area of the 78K0/KE1+ is in 4 KB units. When boot swap is executed, boot cluster 0 and boot cluster 1 in the figure are exchanged. Figure 26-23.
Page 454 CHAPTER 26 FLASH MEMORY Figure 26-23. Memory Map and Boot Area (2/6) µ PD78F0133H FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits 5FFFH FB00H FAFFH...
Page 455 CHAPTER 26 FLASH MEMORY Figure 26-23. Memory Map and Boot Area (3/6) µ PD78F0134H Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 1024 × 8 bits 7FFFH Data memory space × 24576 8 bits Reserved...
Page 456 CHAPTER 26 FLASH MEMORY Figure 26-23. Memory Map and Boot Area (4/6) µ PD78F0136H FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH BFFFH...
Page 457 CHAPTER 26 FLASH MEMORY Figure 26-23. Memory Map and Boot Area (5/6) µ PD78F0138H FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH EFFFH...
Page 458 CHAPTER 26 FLASH MEMORY Figure 26-23. Memory Map and Boot Area (6/6) µ PD78F0138HD FFFFH Special function registers (SFR) 256 × 8 bits FF00H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits Note 1 FB00H FAFFH...
Page 459: Chapter 27 On-Chip Debug Function ( Μ Pd78F0138Hd Only)
µ CHAPTER 27 ON-CHIP DEBUG FUNCTION ( PD78F0138HD ONLY) µ PD78F0138HD uses the V , FLMD0, RESET, X1 (or P31), X2 (or P32), and V pins to communicate with the host machine via an on-chip debug emulator (QB-78K0MINI) for on-chip debugging. Whether X1 and P31, or X2 and P32 are used can be selected.
Page 460: Chapter 28 Instruction Set
CHAPTER 28 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KE1+ in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 28.1 Conventions Used in Operation List 28.1.1 Operand identifiers and specification methods Operands are written in the “Operand”...
Page 461: Description Of Operation Column
CHAPTER 28 INSTRUCTION SET 28.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 462: Operation List
CHAPTER 28 INSTRUCTION SET 28.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 r ← byte − 8-bit data r, #byte transfer (saddr) ← byte saddr, #byte − sfr ← byte sfr, #byte −...
Page 463 CHAPTER 28 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word transfer (saddrp) ← word saddrp, #word − sfrp ← word sfrp, #word AX ←...
Page 464 CHAPTER 28 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte operation (saddr), CY ← (saddr) − byte × ×...
Page 465 CHAPTER 28 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte operation (saddr) ← (saddr) ∨ byte × saddr, #byte − A ← A ∨ r ×...
Page 466 CHAPTER 28 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation − AX, CY ← AX − word ×...
Page 467 CHAPTER 28 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ saddr.bit) × AND1 CY, saddr.bit manipulate − CY ← CY ∧ sfr.bit × CY, sfr.bit − CY ← CY ∧ A.bit ×...
Page 468 CHAPTER 28 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ← addr16, SP ← SP − 2 −...
Page 469 CHAPTER 28 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 Conditional saddr.bit, $addr16 branch − PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 −...
Page 470: Instructions Listed By Addressing Type
CHAPTER 28 INSTRUCTION SET 28.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand [HL + byte] #byte saddr !addr16...
Page 471 CHAPTER 28 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 472 CHAPTER 28 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User’s Manual U16899EJ2V0UD...
Page 473: Chapter 29 Electrical Specifications
CHAPTER 29 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +6.5 −0.3 to +0.3 −0.3 to +0.3 −0.3 to V Note + 0.3 −0.3 to +0.3 −0.3 to V Note Input voltage P00 to P06, P10 to P17, P20 to P27, P30...
Page 474 CHAPTER 29 ELECTRICAL SPECIFICATIONS High-Speed System Clock (Crystal/Ceramic) Oscillator Characteristics = −40 to +85°C, 2.5 V ≤ V ≤ 5.5 V, 2.5 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN.
Page 475 CHAPTER 29 ELECTRICAL SPECIFICATIONS Recommended Oscillator Constants = −40 to +85°C) Ceramic Resonator (T Manufacturer Part Number SMD/Lead Frequency Recommended Circuit Oscillation Voltage Range (MHz) Constants MIN. MAX. (pF) (pF) Murata Mfg. CSTCC2M00G56-R0 2.00 Internal Internal (47) (47) CSTCR4M00G55-R0 4.00 Internal Internal (39)
Page 476 CHAPTER 29 ELECTRICAL SPECIFICATIONS Ring-OSC Oscillator Characteristics = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V, 2.0 V ≤ AV ≤ V = EV = EV = AV = 0 V) Resonator Parameter Conditions MIN. TYP. MAX. Unit On-chip Ring-OSC oscillator Oscillation frequency (f Subsystem Clock Oscillator Characteristics...
Page 477 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics (1/3) = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V , 2.0 V ≤ AV ≤ V Note 1 Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 478 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics (2/3) = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V , 2.0 V ≤ AV ≤ V Note 1 Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 479 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics (3/3) = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V , 2.0 V ≤ AV ≤ V Note 1 Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN.
Page 480 CHAPTER 29 ELECTRICAL SPECIFICATIONS AC Characteristics (1) Basic operation = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V , 2.0 V ≤ AV ≤ V Note 1 Note 1 = EV = EV = AV = 0 V) Parameter Symbol Conditions...
Page 481 CHAPTER 29 ELECTRICAL SPECIFICATIONS vs. V (Main System Clock Operation) 33.3 20.0 16.0 10.0 4.17 Guaranteed operation range 0.238 0.125 Supply voltage V Remark The values indicated by the shaded section are only when the Ring-OSC clock is selected. User’s Manual U16899EJ2V0UD...
Page 482 CHAPTER 29 ELECTRICAL SPECIFICATIONS (2) Serial interface = −40 to +85°C, 2.5 V ≤ V ≤ 5.5 V, 2.5 V ≤ AV ≤ V = EV = EV = AV = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions...
Page 483 CHAPTER 29 ELECTRICAL SPECIFICATIONS AC Timing Test Points (Excluding X1, XT1) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) (MAX.) (MIN.) (MAX.) TI Timing TIL0 TIH0 Note Note TI000, TI010, TI001 , TI011 TIL5 TIH5 TI50, TI51 Interrupt Request Input Timing INTL INTH INTP0 to INTP7...
Page 484 CHAPTER 29 ELECTRICAL SPECIFICATIONS RESET Input Timing RESET Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK1n SIKm KSIm SI1n Input data KSOm SO1n Output data Remark m = 1, 2 µ n = 0: PD78F0132H µ n = 0, 1: PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD User’s Manual U16899EJ2V0UD...
Page 485 CHAPTER 29 ELECTRICAL SPECIFICATIONS A/D Converter Characteristics = −40 to +85°C, 2.5 V ≤ V ≤ 5.5 V, 2.5 V ≤ AV ≤ V = EV = EV = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 4.0 V ≤...
Page 486 CHAPTER 29 ELECTRICAL SPECIFICATIONS = −40 to +85°C) POC Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage : 0 V → 2.0 V Power supply rise time 0.0015 Note 1 Response delay time 1 When power supply rises, after reaching PTHD detection voltage (MAX.) Note 2...
Page 487 CHAPTER 29 ELECTRICAL SPECIFICATIONS = −40 to +85°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage LVI0 LVI1 LVI2 LVI3 LVI4 3.15 3.45 LVI5 2.95 3.25 LVI6 2.85 LVI7 LVI8 2.25 2.35 2.45 LVI9 Note 1 Response time Minimum pulse width Note 2...
Page 488 CHAPTER 29 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics = −10 to +65°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = 0 V) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit supply current = 16 MHz, V = 5.5 V Note 1 Unit erase time...
Page 489: Chapter 30 Package Drawings
CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC LQFP (10x10) detail of lead end ITEM MILLIMETERS 12.0±0.2 10.0±0.2 10.0±0.2 12.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.) NOTE 1.0±0.2 Each lead centerline is located within 0.08 mm of 0.17 +0.03 its true position (T.P.) at maximum material condition. −0.07 0.08 0.1±0.05...
Page 490 CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC LQFP (14x14) detail of lead end ITEM MILLIMETERS 17.2±0.2 14.0±0.2 14.0±0.2 17.2±0.2 0.37 +0.08 −0.07 0.20 0.8 (T.P.) 1.6±0.2 NOTE 0.17 +0.03 Each lead centerline is located within 0.20 mm of −0.06 its true position (T.P.) at maximum material condition. 0.10 1.4±0.1 0.127±0.075...
Page 491 CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC TQFP (12x12) detail of lead end ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.125 1.125 0.32 +0.06 −0.10 0.13 0.65 (T.P.) 1.0±0.2 0.17 +0.03 NOTE −0.07 Each lead centerline is located within 0.13 mm of 0.10 its true position (T.P.) at maximum material condition.
Page 492 CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC FBGA (6x6) H G F E D C B A INDEX MARK (UNIT:mm) ITEM DIMENSIONS 6.00±0.10 6.00±0.10 0.20 1.43±0.10 0.30±0.05 φ S AB 1.13 0.65 0.325 0.325 0.40±0.05 0.08 0.10 0.20 0.725 0.725 P64F1-65-BA2 User’s Manual U16899EJ2V0UD...
Page 493 CHAPTER 30 PACKAGE DRAWINGS 64-PIN PLASTIC LQFP (12x12) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 14.8±0.4 its true position (T.P.) at maximum material condition. 12.0±0.2 12.0±0.2 14.8±0.4 1.125 1.125 0.32±0.08 0.13 0.65 (T.P.) 1.4±0.2 0.6±0.2...
Page 494: Chapter 31 Recommended Soldering Conditions
CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website.
Page 495: Chapter 32 Cautions For Wait
CHAPTER 32 CAUTIONS FOR WAIT 32.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
Page 496: Peripheral Hardware That Generates Wait
CHAPTER 32 CAUTIONS FOR WAIT 32.2 Peripheral Hardware That Generates Wait Table 32-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 32-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Register Access...
Page 497: Example Of Wait Occurrence
CHAPTER 32 CAUTIONS FOR WAIT 32.3 Example of Wait Occurrence <1> Watchdog timer <On execution of MOV WDTM, A> Number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).) <On execution of MOV WDTM, #byte>...
Page 498: Appendix A Development Tools
Unless otherwise specified, “Windows” means the following OSs. • Windows 3.1 • Windows 95 • Windows 98 • Windows NT Ver 4.0 • Windows 2000 • Windows XP Caution For the development tools of the 78K0/KE1+, contact an NEC Electronics sales representative. User’s Manual U16899EJ2V0UD...
Page 499 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) • When using the in-circuit emulator QB-78K0KX1H Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package • System simulator •...
Page 500 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) • When using the on-chip debug emulator QB-78K0MINI Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package • System simulator •...
Page 501: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package µ Part number: S××××SP78K0 Remark ×××× in the part number differs depending on the host machine and OS used. µ...
Page 502: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 µ S××××CC78K0-L ×××× Host Machine Supply Medium AB17 PC-9800 series, Windows (Japanese version) CD-ROM IBM PC/AT compatibles BB17 Windows (English version) 3P17...
Page 503: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulator QB-78K0KX1H Note QB-78K0KX1H The in-circuit emulator serves to debug hardware and software when developing application In-circuit emulator systems using the 78K0/Kx1 or 78K0/Kx1+. It supports the integrated debugger (ID78K0- QB).
Page 504: When Using On-Chip Debug Emulator Qb-78K0Mini
APPENDIX A DEVELOPMENT TOOLS A.5.2 When using on-chip debug emulator QB-78K0MINI QB-78K0MINI The on-chip debug emulator serves to debug hardware and software when developing On-chip debug emulator application systems using the 78K0/Kx1+. It supports the integrated debugger (ID78K0- QB) supplied with the QB-78K0MINI. This emulator uses a connection cable and a USB interface cable that is used to connect the host machine.
Page 505: Appendix B Notes On Target System Design
APPENDIX B NOTES ON TARGET SYSTEM DESIGN This section shows areas on the target system where component mounting is prohibited and areas where there are component mounting height restrictions when using the QB-78K0KX1H. (a) For 64-pin GB package Figure B-1. Restricted Areas on Target System (64-Pin GB Package) 13.375 17.375 Note...
Page 506 APPENDIX B NOTES ON TARGET SYSTEM DESIGN (b) For 64-pin GK package Figure B-2. Restricted Areas on Target System (64-Pin GK Package) 13.375 17.375 Note : Exchange adapter area: Components up to 17.45 mm in height can be mounted Note : Emulation probe tip area: Components up to 24.45 mm in height can be mounted Note Height can be regulated by using space adapters (each adds 2.4 mm)
Page 507: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register (ADCR) ........................252 A/D converter mode register (ADM)..........................249 Analog input channel specification register (ADS) ......................251 Asynchronous serial interface control register 6 (ASICL6)..................301 Asynchronous serial interface operation mode register 0 (ASIM0) ................271 Asynchronous serial interface operation mode register 6 (ASIM6) ................295 Asynchronous serial interface reception error status register 0 (ASIS0)..............273...
Page 508 APPENDIX C REGISTER INDEX Flash programming mode control register (FLPMC) ....................448 Flash protect command register (PFCMD)........................450 Flash status register (PFS)............................450 Input switch control register (ISC) ..........................303 Internal expansion RAM size switching register (IXS)....................431 Internal memory size switching register (IMS)......................430 Interrupt mask flag register 0H (MK0H)........................363 Interrupt mask flag register 0L (MK0L)........................363 Interrupt mask flag register 1H (MK1H)........................363 Interrupt mask flag register 1L (MK1L)........................363...
Page 509 APPENDIX C REGISTER INDEX Port register 13 (P13)..............................106 Port register 14 (P14)..............................106 Port register 2 (P2)..............................106 Port register 3 (P3)..............................106 Port register 4 (P4)..............................106 Port register 5 (P5)..............................106 Port register 6 (P6)..............................106 Port register 7 (P7)..............................106 Power-fail comparison mode register (PFM).......................253 Power-fail comparison threshold register (PFT)......................253 Prescaler mode register 00 (PRM00)..........................149 Prescaler mode register 01 (PRM01)..........................149...
Page 510 APPENDIX C REGISTER INDEX 16-bit timer counter 01 (TM01)............................139 16-bit timer mode control register 00 (TMC00)......................142 16-bit timer mode control register 01 (TMC01)......................142 16-bit timer output control register 00 (TOC00)......................146 16-bit timer output control register 01 (TOC01)......................146 Timer clock selection register 50 (TCL50)........................184 Timer clock selection register 51 (TCL51)........................184 Transmit buffer register 10 (SOTB10) .........................328 Transmit buffer register 11 (SOTB11) .........................328...
Page 511: Register Index (In Alphabetical Order With Respect To Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR: A/D conversion result register .........................252 ADM: A/D converter mode register ........................249 ADS: Analog input channel specification register .....................251 ASICL6: Asynchronous serial interface control register 6..................301 ASIF6: Asynchronous serial interface transmission status register 6..............298 ASIM0:...
Page 512 APPENDIX C REGISTER INDEX FLPMC: Flash programming mode control register ....................448 IF0H: Interrupt request flag register 0H ......................361 IF0L: Interrupt request flag register 0L ......................361 IF1H: Interrupt request flag register 1H ......................361 IF1L: Interrupt request flag register 1L ......................361 IMS: Internal memory size switching register....................430 ISC: Input switch control register........................303...
Page 513 APPENDIX C REGISTER INDEX PFS: Flash status register ..........................450 PFT: Power-fail comparison threshold register ....................253 PM0: Port mode register 0........................ 104, 152, 334 PM1: Port mode register 1..................104, 188, 207, 275, 303, 334 PM12: Port mode register 12..........................104 PM14: Port mode register 14........................104, 245 PM3: Port mode register 3........................104, 188...
Page 514 APPENDIX C REGISTER INDEX TMC00: 16-bit timer mode control register 00 .......................142 TMC01: 16-bit timer mode control register 01 .......................142 TMC50: 8-bit timer mode control register 50 ......................186 TMC51: 8-bit timer mode control register 51 ......................187 TMCYC1: 8-bit timer H carrier control register 1 ......................206 TMHMD0: 8-bit timer H mode register 0 ........................202 TMHMD1: 8-bit timer H mode register 1 ........................202 TOC00:...
Page 515: Appendix D List Of Cautions
APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. “Classification (hard/soft)” in table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs (1/24) Function Details of Cautions Page Function...
Page 516 APPENDIX D LIST OF CAUTIONS (2/24) Function Details of Cautions Page Function − PCC: Be sure to clear bit 3 to 0. p. 112 Processor clock control register Ring-OSC RCM: Ring- Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before p.
Page 517 APPENDIX D LIST OF CAUTIONS (3/24) Function Details of Cautions Page Function Main OSTS: To set the STOP mode when the high-speed system clock is used as the CPU p. 117 clock Oscillation clock, set OSTS before executing a STOP instruction. stabilization Before setting OSTS, confirm with OSTC that the desired oscillation stabilization p.
Page 518 APPENDIX D LIST OF CAUTIONS (4/24) Function Details of Cautions Page Function 16-bit CR00n: 16-bit Set a value other than 0000H in CR00n in the mode in which clear & start occurs p. 140 timer/ timer on a match of TM0n and CR00n. event capture/compare If CR00n is cleared to 0000H in the free-running mode and in the clear mode...
Page 519 APPENDIX D LIST OF CAUTIONS (5/24) Function Details of Cautions Page Function 16-bit CRC00: Timer operation must be stopped before setting CRC00. p. 145 timer/ Capture/ When the mode in which clear & start occurs on a match between TM00 and p.
Page 520 APPENDIX D LIST OF CAUTIONS (6/24) Function Details of Cautions Page Function 16-bit PRM00: If the TI000 or TI010 pin is high level immediately after system reset, the rising p. 150 timer/ Prescaler mode edge is immediately detected after the rising edge or both the rising and falling event register 00 edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the...
Page 521 APPENDIX D LIST OF CAUTIONS (7/24) Function Details of Cautions Page Function 16-bit Pulse width To use two capture registers, set the TI00n and TI01n pins. p. 159 timer/ measurement event External event When reading the external event counter count value, TM0n should be read. p.
Page 522 APPENDIX D LIST OF CAUTIONS (8/24) Function Details of Cautions Page Function 16-bit OVF0n flag The OVF0n flag is also set to 1 in the following case. p. 178 timer/ operation When any of the following modes is selected: the mode in which clear & start event occurs on a match between TM0n and CR00n, the mode in which clear &...
Page 523 APPENDIX D LIST OF CAUTIONS (9/24) Function Details of Cautions Page Function 8-bit CR5n: 8-bit In the mode in which clear & start occurs on a match of TM5n and CR5n p. 183 timer/ timer compare (TMC5n6 = 0), do not write other values to CR5n during operation. event register 5n In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock...
Page 524 APPENDIX D LIST OF CAUTIONS (10/24) Function Details of Cautions Page Function 8-bit TMHMD0: 8-bit When TMHE0 = 1, setting the other bits of the TMHMD0 register is prohibited. p. 204 timers H0, timer H mode In the PWM output mode, be sure to set 8-bit timer H compare register 10 p.
Page 525 APPENDIX D LIST OF CAUTIONS (11/24) Function Details of Cautions Page Function Watch WTM: Watch Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to p. 227 timer timer operation WTM7) of WTM) during watch timer operation. mode register Interrupt When operation of the watch timer and 5-bit counter is enabled by the watch timer...
Page 526 APPENDIX D LIST OF CAUTIONS (12/24) Function Details of Cautions Page Function ADM: A/D If data is written to ADM, a wait cycle is generated. Do not write data to ADM p. 250 converter converter mode when the CPU is operating on the subsystem clock and the high-speed system register clock is stopped.
Page 527 APPENDIX D LIST OF CAUTIONS (13/24) Function Details of Cautions Page Function Noise To maintain the 10-bit resolution, attention must be paid to noise input to the p. 262 converter countermeasures pin and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 12-19, to reduce noise.
Page 528 APPENDIX D LIST OF CAUTIONS (14/24) Function Details of Cautions Page Function A/D converter The A/D converter sampling time differs depending on the set value of the A/D p. 265 converter sampling time converter mode register (ADM). and A/D The delay time exists until actual sampling is started after A/D converter operation conversion start is enabled.
Page 529 APPENDIX D LIST OF CAUTIONS (15/24) Function Details of Cautions Page Function Serial BRGC0: Baud When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the p. 275 interface rate generator clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the UART0 control register base clock is the Ring-OSC clock, the operation of serial interface UART0 is not...
Page 530 APPENDIX D LIST OF CAUTIONS (16/24) Function Details of Cautions Page Function Serial ASIM6: At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, p. 296 interface Asynchronous clear TXE6 to 0, and then clear POWER6 to 0. UART6 serial interface At startup, set POWER6 to 1 and then set RXE6 to 1.
Page 531 APPENDIX D LIST OF CAUTIONS (17/24) Function Details of Cautions Page Function Serial ASICL6: The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 p. 302 interface Asynchronous after SBF reception has been correctly completed. UART6 serial interface Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6...
Page 532 APPENDIX D LIST OF CAUTIONS (18/24) Function Details of Cautions Page Function Serial Serial clock Keep the baud rate error during transmission to within the permissible error p. 321 interface generation range at the reception destination. UART6 Make sure that the baud rate error during reception satisfies the range shown in p.
Page 533 APPENDIX D LIST OF CAUTIONS (19/24) Function Details of Cautions Page Function Multiplier/ SDR0: The value read from SDR0 during operation processing (while bit 7 (DMUE) of p. 348 divider Remainder data multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed. register 0 SDR0 is reset when the operation is started (when DMUE is set to 1).
Page 534 APPENDIX D LIST OF CAUTIONS (20/24) Function Details of Cautions Page Function Interrupt PR1H: Priority Be sure to set bits 4 to 7 of PR1H to 1. p. 364 specification flag register EGP, EGN: Select the port mode by clearing EGPn and EGNn to 0 because an edge may be p.
Page 535 APPENDIX D LIST OF CAUTIONS (21/24) Function Details of Cautions Page Function Standby OSTC: The wait time when STOP mode is released does not include the time after STOP p. 378 function Oscillation mode release until clock oscillation starts (“a” below) regardless of whether STOP stabilization mode is released by RESET input or interrupt generation.
Page 536 APPENDIX D LIST OF CAUTIONS (22/24) Function Details of Cautions Page Function Power- Power-on-clear If an internal reset signal is generated in the POC circuit, the reset control flag p. 404 on-clear circuit functions register (RESF) is cleared to 00H. circuit The supply voltage is V = 2.0 to 5.5 V when the Ring-OSC clock or subsystem...
Page 537 APPENDIX D LIST OF CAUTIONS (23/24) Function Details of Cautions Page Function Cautions for Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) p. 428 correction ROM correction must be addresses where instruction codes are stored. Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when p.
Page 538 APPENDIX D LIST OF CAUTIONS (24/24) Function Details of Cautions Page Function Electrical Absolute Product quality may suffer if the absolute maximum rating is exceeded even p. 473 specifications maximum momentarily for any parameter. That is, the absolute maximum ratings are rated ratings values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute...
Page 539: Appendix E Revision History
APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition (1/2) Page Description µ p. 18 Addition of PD78F0138HF1-BA2, 78F0138HDGK-8A8, and 78F0138HDF1-BA2 to 1.3 Ordering Information p. 22 Modification of 1.5 Kx1 Series Lineup p. 42 Modification of recommended connection for unused RESET pin in Table 2-2 Pin I/O Circuit Types p.
Page 540 APPENDIX E REVISION HISTORY (2/2) Page Description p. 505 Revision of APPENDIX B NOTES ON TARGET SYSTEM DESIGN p. 515 Addition of APPENDIX D LIST OF CAUTIONS p. 539 Addition of APPENDIX E REVISION HISTORY User’s Manual U16899EJ2V0UD...

This manual is also suitable for:

Mupd78f0138h Mupd78f0136h Mupd78f0134h Mupd78f0138hd Mupd78f0133h

NEC MuPD78F0132H User Manual

Chapter 1 Outline

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer/Event Counters 00 and 01

Chapter 7 8-Bit Timer/Event Counters 50 and 51

Chapter 8 8-Bit Timers H0 and H1

Chapter 9 Watch Timer

Chapter 10 Watchdog Timer

Chapter 11 Clock Output/Buzzer Output Controller

Chapter 12 A/D Converter

Chapter 13 Serial Interface Uart0

Chapter 14 Serial Interface Uart6

Chapter 15 Serial Interfaces Csi10 and Csi11

Chapter 16 Multiplier/Divider

Chapter 17 Interrupt Functions

Chapter 18 Key Interrupt Function

Chapter 19 Standby Function

Chapter 20 Reset Function

Chapter 21 Clock Monitor

Chapter 22 Power-On-Clear Circuit

Chapter 23 Low-Voltage Detector

Chapter 24 Option Byte

Chapter 25 Rom Correction

Chapter 26 Flash Memory

CHAPTER 27 ON-CHIP DEBUG FUNCTION ( Μ PD78F0138HD ONLY)

Chapter 28 Instruction Set

Chapter 29 Electrical Specifications

Chapter 30 Package Drawings

Chapter 31 Recommended Soldering Conditions

Chapter 32 Cautions for Wait

Appendix A Development Tools

Appendix B Notes on Target System Design

Appendix C Register Index

Appendix D List of Cautions

Appendix E Revision History

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