NEC MuPD754144 Datasheet
NEC MuPD754144 Datasheet

NEC MuPD754144 Datasheet

Mos integrated circuit, 4-bit single-chip microcontrollers

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DESCRIPTION
The µ PD754244 is a 4-bit single-chip microcontroller which incorporates the EEPROM
application.
It incorporates a 16 × 8-bit EEPROM, a 4-Kbyte mask ROM to store software, a 128 × 4-bit RAM to store the
processing data, a processing CPU, and a carrier generator which easily outputs waveforms for infrared remote
controller.
The details of functions are described in the following user's manual. Be sure to read it before designing.
FEATURES
On-chip EEPROM: 16 × 8 bits (mapped to the data memory)
On-chip key return reset function for key-less entry
System clock oscillation circuit
• µ PD754144: RC oscillator (external resistor and capacitor)
• µ PD754244: Crystal/ceramic oscillator
Low-voltage operation: V
Timer function (4 channels)
• Basic interval timer/watchdog timer: 1 channel
• 8-bit timer counter
On-chip memory
• Program memory (ROM)
4096 × 8 bits
• Data memory (static RAM)
128 × 4 bits
Instruction execution time variable function suited for power saving.
• µ PD754144:
4, 8, 16, 64 µ s (at fcc = 1.0-MHz operation)
• µ PD754244:
0.95, 1.91, 3.81, 15.3 µ s (at fx = 4.19-MHz operation)
0.67, 1.33, 2.67, 10.7 µ s (at fx = 6.0-MHz operation)
APPLICATIONS
Automotive appliances such as key-less entry, compact data carrier, etc.
Unless contextually excluded, references in this data sheet to the µPD754244 (crystal/ceramic oscillation: f
mean the µ PD754144.
The µ PD754144 and µ PD754244 differ in the notation of their RC oscillation: whenever f
for µ PD754244) is described, f
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U10040EJ2V1DS00 (2nd edition)
Date Published August 2005 N CP(K)
Printed in Japan
DATA SHEET
µ PD754144, 754244
4-BIT SINGLE-CHIP MICROCONTROLLERS
µ PD754144, 754244 User's Manual: U10676E
= 1.8 to 6.0 V
DD
: 3 channels
should be substituted for the µ PD754144.
CC
The mark
shows major revised points.
MOS INTEGRATED CIRCUIT
*
TM
for key-less entry
)
X
(RC oscillation notation
X
1995

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Summary of Contents for NEC MuPD754144

  • Page 1 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
  • Page 2 µ PD754144, 754244 ORDERING INFORMATION Part Number Package µ PD754144GS-xxx-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch) ★ µ PD754144GS-xxx-BA5-A 20-pin plastic SOP (300 mil, 1.27-mm pitch) µ PD754144GS-xxx-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) ★ µ PD754144GS-xxx-GJG-A 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) µ...
  • Page 3 µ PD754144, 754244 Functional Outline µ PD754144 µ PD754244 Parameter • 4, 8, 16, 64 µ s • 0.95, 1.91, 3.81, 15.3 µ s Instruction execution time (at fcc = 1.0-MHz operation) (at fx = 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µ s (at fx = 6.0-MHz operation) 4096 ×...
  • Page 4: Table Of Contents

    µ PD754144, 754244 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ....................6 2. BLOCK DIAGRAM ..........................8 3. PIN FUNCTION ............................. 9 3.1 Port Pins ............................9 3.2 Non-port Pins ..........................10 3.3 Pin Input/Output Circuits ......................11 3.4 Recommended Connection of Unused Pins ................12 4.
  • Page 5 µ PD754144, 754244 15. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUES) ..72 16. PACKAGE DRAWINGS ........................76 17. RECOMMENDED SOLDERING CONDITIONS .................. 78 APPENDIX A. COMPARISON OF FUNCTIONS AMONG µ PD754144, 754244, AND 75F4264 ... 81 APPENDIX B. DEVELOPMENT TOOLS ....................82 APPENDIX C.
  • Page 6: Pin Configuration (Top View)

    µ PD754144, 754244 1. PIN CONFIGURATION (TOP VIEW) • µ PD754144 • 20-pin Plastic SOP (300 mil, 1.27-mm pitch) µ PD754144GS-×××-BA5 ★ µ PD754144GS-×××-BA5-A • 20-pin Plastic Shrink SOP (300 mil, 0.65-mm pitch) µ PD754144GS-×××-GJG µ PD754144GS-×××-GJG-A ★ RESET KRREN P30/PTO0 P31/PTO1 P32/PTO2...
  • Page 7 µ PD754144, 754244 • µ PD754244 • 20-pin Plastic SOP (300 mil, 1.27-mm pitch) µ PD754244GS-×××-BA5 µ PD754244GS-×××-BA5-A • 20-pin Plastic Shrink SOP (300 mil, 0.65-mm pitch) µ PD754244GS-×××-GJG µ PD754244GS-×××-GJG-A RESET KRREN P30/PTO0 P31/PTO1 P32/PTO2 P60/AV P70/KR4 P61/INT0 P71/KR5 P62/PTH00 P72/KR6 P63/PTH01...
  • Page 8: Block Diagram

    µ PD754144, 754244 2. BLOCK DIAGRAM BASIC INTERVAL PORT3 P30 to P33 TIMER/WATCHDOG TIMER SP (8) INTBT RESET PORT6 P60 to P63 8-BIT TIMER PTO0/P30 COUNTER#0 INTT0 TOUT PROGRAM COUNTER INTT1 BANK PORT7 P70 to P73 8-BIT PTO1/P31 TIMER GENERAL REG. COUNTER#1 CASCADED 16-BIT...
  • Page 9: Pin Function

    µ PD754144, 754244 3. PIN FUNCTION 3.1 Port Pins Alternate 8-bit I/O Circuit Pin Name Input/Output Function After Reset Function TYPE Note 1 Input/Output PTO0 Programmable 4-bit input/output port – Input (PORT3). PTO1 This port can be specified input/output bit- wise.
  • Page 10: Non-Port Pins

    µ PD754144, 754244 3.2 Non-port Pins Alternate I/O Circuit Pin Name Input/Output Function After Reset Note Function TYPE PTO0 Output Timer counter output pins Input PTO1 PTO2 INT0 Input Edge detection vectored Noise elimination Input F -A interrupt input pin circuit can be (detected edge can be selected.
  • Page 11: Pin Input/Output Circuits

    µ PD754144, 754244 3.3 Pin Input/Output Circuits The µ PD754244 pin input/output circuits are shown schematically. TYPE A TYPE D data P-ch P-ch N-ch output N-ch disable Push-pull output that can be placed in output CMOS specification input buffer. high-impedance (both P-ch, N-ch off). TYPE E-B TYPE B P.U.R.
  • Page 12: Recommended Connection Of Unused Pins

    µ PD754144, 754244 3.4 Recommended Connection of Unused Pins Table 3-1. List of Recommended Connection of Unused Pins Recommended Connecting Method P30/PTO0 Input state : Independently connect to V or V via a resistor. P31/PTO1 Output state: Leave open. P32/PTO2 P60/AV P61/INT0 P62/PTH00...
  • Page 13: Switching Function Between Mk I Mode And Mk Ii Mode

    µ PD754144, 754244 4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE 4.1 Difference between Mk I and Mk II Modes The µ PD754244 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the Stack Bank Select register (SBS).
  • Page 14: Setting Method Of Stack Bank Select Register (Sbs)

    µ PD754144, 754244 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program.
  • Page 15: Memory Configuration

    µ PD754144, 754244 5. MEMORY CONFIGURATION • Program memory (ROM) 4096 x 8 bits • • • • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written.
  • Page 16 µ PD754144, 754244 Figure 5-1. Program Memory Map Address 0000H Internal reset start address (high-order 4 bits) 0001H Internal reset start address (low-order 8 bits) 0002H INTBT start address (high-order 4 bits) CALLF !faddr instruction entry address 0003H INTBT start address (low-order 8 bits) INT0 start address (high-order 4 bits)
  • Page 17 µ PD754144, 754244 Figure 5-2. Data Memory Map Data memory Memory bank 000H General-purpose (32 × 4) register area 01FH 020H Data area Stack area static RAM (128 × 4) 128 × 4 (96 × 4) 07FH 080H 0FFH Not incorporated 400H Data area 16 ×...
  • Page 18: Eeprom

    µ PD754144, 754244 6. EEPROM The µ PD754244 incorporates 16 words × 8 bit EEPROM (Electrically Erasable PROM) as well as static RAM (128 words × 4 bit) as a data memory. The EEPROM incorporated into the µ PD754244 has the following features. (1) Written data is retained if power is turned off.
  • Page 19: Peripheral Hardware Functions

    µ PD754144, 754244 7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Digital Input/Output Ports The following two types of I/O ports are provided. • CMOS input (Port 7) • CMOS I/O (Ports 3, 6, 8) Total : 13 Table 7-1. Types and Features of Digital Ports Port Name Function Operation and Features...
  • Page 20 µ PD754144, 754244 Figure 7-1. µ PD754144 (RC Oscillation) Clock Generator Block Diagram · Basic interval timer (BT) · Timer counter · INT0 noise eliminator 1/1~1/4096 System clock Divider oscillator 1/2 1/4 1/16 Oscillation stops Divider Φ · CPU · INT0 noise eliminator PCC0 PCC1...
  • Page 21 µ PD754144, 754244 Figure 7-2. µ PD754244 (Crystal/Ceramic Oscillation) Clock Generator Block Diagram · Basic interval timer (BT) · Timer counter · INT0 noise eliminator 1/1~1/4096 System clock Divider oscillator 1/2 1/4 1/16 Oscillation stops Divider Φ · CPU · INT0 noise eliminator PCC0 PCC1...
  • Page 22 µ PD754144, 754244 7.3 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program and reset the CPU (c) Selects and counts the wait time when the standby mode is released ( µ...
  • Page 23 µ PD754144, 754244 7.4 Timer Counter The µ PD754244 incorporates three channels of timer counters. Its configuration is shown in Figures 7-4 to 7-6. The timer counter has the following functions. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) Count value read function The timer counter can operate in the following four modes as set by the mode register.
  • Page 24 Internal bus SET1 Note TOE0 PORT3.0 PMGA bit 0 TMOD0 Port 3 Modulo register (8) – TM06 TM05 TM04 TM03 TM02 input/output enable flag Output latch mode Match TOUT Comparator (8) P30/PTO0 Output buffer Reset From clock Count register (8) INTT0 generator ...
  • Page 25 Internal bus Note TOE1 PORT3.1 PMGA bit 1 Port 3 – TM16 TM15 TM14 TM13 TM12 TM11 TM10 input/output enable flag Output latch mode TMOD1 Decoder Modulo register (8) P31/PTO1 Match TOUT Comparator (8) Output buffer Timer counter (channel 2) output Reset From clock Count register (8)
  • Page 26 Internal bus Note TMODH TMOD2 PORT3.2 PMGA bit 2 High-level period Port 3 – TM26 TM25 TM24 TM23 TM22 TM21 TM20 Modulo register (8) – – – TOE2 REMC NRZB NRZ Output setting modulo register (8) input/output latch mode Reload Decoder MPX (8) P32/PTO2...
  • Page 27: Programmable Threshold Port (Analog Input Port)

    µ PD754144, 754244 7.5 Programmable Threshold Port (Analog Input Port) The µ PD754244 provides analog input pins (PTH00, PTH01) whose threshold voltage (reference voltage) is selectable within sixteen steps. The following operations can be performed with these analog input pins. Comparator operation 4-bit resolution A/D converter operation (controlled by software) Caution...
  • Page 28: Bit Sequential Buffer

    µ PD754144, 754244 7.6 Bit Sequential Buffer ..16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise.
  • Page 29: Interrupt Function And Test Function

    µ PD754144, 754244 8. INTERRUPT FUNCTION AND TEST FUNCTION Figure 8-1 shows the interrupt control circuit. Each hardware device is mapped in the data memory space. The interrupt control circuit of the µ PD754244 has the following functions. (1) Interrupt function •...
  • Page 30 Internal bus IST1 IST0 Interrupt enable flag (IE×××) Decoder VRQn INTBT IRQBT Edge IRQ0 INT0/P61 Note1 detector Vector table INTT0 IRQT0 address Priority control generator ciricuit INTT1 IRQT1 INTT2 IRQT2 INTEE IRQEE KR4/P70 Falling edge IRQ2 detector Note2 KR7/P73 Key return reset circuit Standby release signal...
  • Page 31: Standby Function

    µ PD754144, 754244 9. STANDBY FUNCTION In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µ PD754244. Table 9-1. Operation Status in Standby Mode Mode STOP Mode HALT Mode...
  • Page 32: Reset Function

    µ PD754144, 754244 10. RESET FUNCTION 10.1 Configuration and Operation Status of RESET Function There are three kinds of reset input: the external reset signal (RESET), the reset signal sent from the basic interval/watchdog timer, and the reset signal generated by a falling edge signal from KRn in the STOP mode. When any of these reset signals is input, an internal reset signal is generated.
  • Page 33 µ PD754144, 754244 Each hardware is initialized by the RESET signal generation as listed in Table 10-1. Figure 10-2 shows the timing chart of the reset operation. Figure 10-2. Reset Operation by RESET Signal Generation Note Wait RESET signal generated Operation mode or standby mode HALT mode...
  • Page 34 µ PD754144, 754244 Table 10-1. Hardware Status After Reset (1/3) RESET signal generation RESET signal generation Hardware in the standby mode in operation Program counter (PC) Sets the low-order 4 bits of Sets the low-order 4 bits of program memory’s address program memory’s address 0000H to the PC11-PC8 and the 0000H to the PC11-PC8 and the...
  • Page 35 µ PD754144, 754244 Table 10-1. Hardware Status After Reset (2/3) RESET signal generation RESET signal generation Hardware in the standby mode in operation Programmable threshold port mode register (PTHM) Clock generator Processor clock control register (PCC) Interrupt Interrupt request flag (IRQ×××) Reset (0) Reset (0) function...
  • Page 36: Watchdog Flag (Wdf), Key Return Flag (Krf)

    µ PD754144, 754244 10.2 Watchdog Flag (WDF), Key Return Flag (KRF) The WDF is cleared by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by the KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal is generated.
  • Page 37 µ PD754144, 754244 Figure 10-4. KRF Operation in Generating Each Signal Reset signal Reset signal generation by generation by the KRn input the KRn input STOP instruction External RESET STOP instruction KRF clear instruction execution signal generation execution execution External RESET STOP HALT Operation...
  • Page 38: Mask Option

    µ PD754144, 754244 11. MASK OPTION The µ PD754244 has the following mask options: • Mask option of P70/KR4 to P73/KR7 On-chip pull-up resistor connection can be specified for these pins. (1) Do not connect an on-chip pull-up resistor (2) Connect the 100-kΩ (typ.) pull-up resistor bit-wise •...
  • Page 39: Instruction Sets

    µ PD754144, 754244 12. INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to “RA75X ASSEMBLER PACKAGE USERS’...
  • Page 40 µ PD754144, 754244 (2) Legend in explanation of operation : A register, 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair...
  • Page 41 µ PD754144, 754244 (3) Explanation of symbols under addressing area column MB = MBE•MBS (MBS = 0, 4, 15) MB = 0 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) Data memory addressing MBE = 1 : MB = MBS (MBS = 0, 4, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH...
  • Page 42 µ PD754144, 754244 Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles A ← n4 Transfer A, #n4 String effect A instruction reg1 ← n4 reg1, #n4 XA ← n8 XA, #n8 String effect A HL ←...
  • Page 43 µ PD754144, 754244 Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles CY ← (fmem.bit) Bit transfer MOV1 CY, fmem.bit instructions CY ← (pmem CY, pmem.@L .bit(L 7–2 3–2 1–0 CY ← (H+mem CY, @H+mem.bit .bit) 3–0...
  • Page 44 µ PD754144, 754244 Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles reg ← reg+1 Increment INCS reg=0 rp1 ← rp1+1 Decrement rp1=00H instructions (HL) ← (HL)+1 (HL)=0 (mem) ← (mem)+1 (mem)=0 reg ← reg–1 DECS reg=FH rp' ←...
  • Page 45 µ PD754144, 754244 Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles Memory bit SKTCLR fmem.bit Skip if (fmem.bit)=1 and clear (fmem.bit)=1 manipulation instructions pmem.@L Skip if (pmem .bit(L ))=1 and clear (pmem.@L)=1 7–2 3–2 1–0...
  • Page 46 µ PD754144, 754244 Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles (SP–2) ← ×, ×, MBE, RBE Note Subroutine CALLA !addr1 (SP–6) (SP–3) (SP–4) ← PC stack control 11–0 (SP–5) ← 0, 0, 0, 0 instructions ←...
  • Page 47 µ PD754144, 754244 Number Instruction Number Addressing Mnemonic Operand of machine Operation Skip condition group of bytes area cycles IME (IPS.3) ← 1 Interrupt control IE××× ← 1 instructions IE××× IME (IPS.3) ← 0 IE××× ← 0 IE××× A ← PORTn Note 1 Input/output A, PORTn...
  • Page 48: Electrical Specifications

    µ PD754144, 754244 13. ELECTRICAL SPECIFICATIONS 13.1 µ PD754144 ° Absolute Maximum Ratings (T = 25 Parameter Symbol Test Conditions Ratings Unit Power supply voltage V –0.3 to +7.0 Input voltage –0.3 to V + 0.3 Output voltage –0.3 to V + 0.3 Output current, high Per pin...
  • Page 49 µ PD754144, 754244 • µ PD754144 ° System Clock Oscillator Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Resonator Recommended Constant Parameter Testing Conditions MIN. TYP. MAX. Unit Oscillation Note oscillator frequency (f • Note Only the oscillator characteristics are shown. For the instruction execution time and oscillation frequency characteristics, refer to AC Characteristics.
  • Page 50 µ PD754144, 754244 • µ PD754144 ° DC Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit High-level output Per pin P30, P31, P33, –5 current P60 to P63, P80 P32, V = 3.0 V, –7...
  • Page 51 µ PD754144, 754244 • µ PD754144 ° DC Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 2 = 5.0 V ± 10% Power supply 1.0-MHz Note 1 Note 3 = 3.0 V ±...
  • Page 52 µ PD754144, 754244 • µ PD754144 ° AC Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit CPU clock cycle time Note1 µ s (Minimum instruction execution time = 1 machine cycle) Note 2 RC oscillation frequency R = 22 kΩ,...
  • Page 53 µ PD754144, 754244 • µ PD754144 ° EEPROM Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ± 10% EEPROM 1.0 MHz, = 3.0 V ± 10% write current RC oscillation Note...
  • Page 54 µ PD754144, 754244 • µ PD754144 AC Timing Test Points (MIN.) (MIN.) (MAX.) (MAX.) (MIN.) (MIN.) (MAX.) (MAX.) Interrupt Input Timing INTL INTH INT0, KR4 to KR7 RESET Input Timing RESET ° Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (T = –40 to +85 Parameter Symbol...
  • Page 55 µ PD754144, 754244 • µ PD754144 Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode SREL Execution of STOP instruction RESET WAIT Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Operation mode...
  • Page 56: Pd754244

    µ PD754144, 754244 13.2 µ PD754244 ° Absolute Maximum Ratings (T = 25 Parameter Symbol Test Conditions Ratings Unit Power supply voltage V –0.3 to +7.0 Input voltage –0.3 to V + 0.3 Output voltage –0.3 to V + 0.3 Output current, high Per pin P30, P31, P33, P60 to P63, P80...
  • Page 57 µ PD754144, 754244 • µ PD754244 ° System Clock Oscillator Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Resonator Recommended Constant Parameter Testing Conditions MIN. TYP. MAX. Unit Notes2, 3, 4 Ceramic Oscillation Note1 resonator frequency (f Oscillation After V...
  • Page 58 µ PD754144, 754244 • µ PD754244 Recommended Oscillator Constants ° Ceramic resonator (T = –20 to +80 Manufacturer Part Number Frequency Recommended Circuit Oscillation Voltage Remark Constant (pF) Range (V (MHz) MN. (V) MAX. (V) Kyocera KBR-1000F/Y — KBR-2.0MS KBR-4.19MSB 4.19 KBR-4.19MKC —...
  • Page 59 µ PD754144, 754244 Note When using the CSB1000J (1.0 MHz) made by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 2.2 kΩ) is necessary (refer to the figure below). This resistor is not necessary when using the other recommended resonators.
  • Page 60 µ PD754144, 754244 • µ PD754244 ° DC Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit High-level output Per pin P30, P31, P33, –5 current P60 to P63, P80 P32, V = 3.0 V, –7...
  • Page 61 µ PD754144, 754244 • µ PD754244 ° DC Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 2 = 5.0 V ± 10% Power supply 4.19-MHz Note 1 Note 3 = 3.0 V ±...
  • Page 62 µ PD754144, 754244 • µ PD754244 ° AC Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit µ s CPU clock cycle time Note 1 = 1.8 to 2.0 V 64.0 µ...
  • Page 63 µ PD754144, 754244 • µ PD754244 ° EEPROM Characteristics (T = –40 to +85 C, V = 1.8 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit = 5.0 V ± 10% EEPROM 4.19 MHz, = 3.0 V ± 10% write current crystal oscillation EEPROM...
  • Page 64 µ PD754144, 754244 • µ PD754244 AC Timing Test Points (Excluding X1 Input) (MIN.) (MIN.) (MAX.) (MAX.) (MIN.) (MIN.) (MAX.) (MAX.) Clock Timing X1 input – 0.1 V 0.1 V Data Sheet U10040EJ2V1DS...
  • Page 65 µ PD754144, 754244 • µ PD754244 Interrupt Input Timing INTL INTH INT0, KR4 to KR7 RESET Input Timing RESET ° Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (T = –40 to +85 Parameter Symbol Test Conditions MIN. TYP. MAX.
  • Page 66 µ PD754144, 754244 Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode Operation mode STOP mode Data retention mode SREL Execution of STOP instruction RESET WAIT Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Operation mode...
  • Page 67: Characteristics Curves (Reference Values)

    µ PD754144, 754244 14. CHARACTERISTICS CURVES (REFERENCE VALUES) 14.1 µ PD754144 vs. V (RC Oscillation, R = 22 kΩ, C = 22 pF) = 25°C) PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 0.05 0.01 0.005...
  • Page 68 µ PD754144, 754244 • µ PD754144 vs. V (RC Oscillation, R = 5.1 kΩ, C = 120 pF) = 25°C) PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 and System clock HALT mode 0.05 0.01 0.005 5.1 kΩ...
  • Page 69: Pd754244

    µ PD754144, 754244 14.2 µ PD754244 vs. V (System Clock: 6.0-MHz Crystal Resonator) = 25°C) PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 0.05 0.01 0.005 Crystal resonator 6.0 MHz 22 pF 22 pF 0.001 Power Supply Voltage V...
  • Page 70 µ PD754144, 754244 • µ PD754244 vs. V (System Clock: 4.19-MHz Crystal Resonator) = 25°C) PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 0.05 0.01 0.005 Crystal resonator 4.19 MHz 22 pF 22 pF 0.001 Power Supply Voltage V...
  • Page 71 µ PD754144, 754244 • µ PD754244 vs. V (System Clock: 2.0-MHz Crystal Resonator) = 25°C) PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 0.05 0.01 0.005 Crystal resonator 2.0 MHz 47 pF 47 pF 0.001 Power Supply Voltage V...
  • Page 72: Rc Oscillation Frequency Characteristics Examples (Reference Values)

    µ PD754144, 754244 15. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUES) vs. V (RC Oscillation, R = 22 kΩ, C = 22 pF) = –40°C) 22 kΩ 22 pF Sample C Sample B Sample A Power Supply Voltage V = 25°C) 22 kΩ...
  • Page 73 µ PD754144, 754244 vs. T (RC Oscillation, R = 22 kΩ, C = 22 pF) (Sample A) 22 kΩ 22 pF = 5.0 V = 6.0 V = 3.0 V = 2.2 V = 1.8 V –60 –40 –20 +100 Operating Ambient Temperature T (°C) (Sample B)
  • Page 74 µ PD754144, 754244 vs. V (RC Oscillation, R = 5.1 kΩ , C = 120 pF) = –40°C) 5.1 kΩ 120 pF Sample C Sample B Sample A Power Supply Voltage V = 25°C) 5.1 kΩ 120 pF Sample C Sample B Sample A Power Supply Voltage V...
  • Page 75 µ PD754144, 754244 vs. T (RC Oscillation, R = 5.1 kΩ, C = 120 pF) (Sample A) 5.1 kΩ 120 pF = 5.0 V = 6.0 V = 3.0 V = 2.2 V = 1.8 V –60 –40 –20 +100 Operating Ambient Temperature T (°C) (Sample B)
  • Page 76: Package Drawings

    µ PD754144, 754244 16. PACKAGE DRAWINGS 20-pin Plastic SOP (300 mils) detail of lead end NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0.12 mm (0.005 inch) of 12.7±0.3 0.500±0.012 its true position (T.P.) at maximum material condition. 0.78 MAX.
  • Page 77 µ PD754144, 754244 20-pin Plastic shrink SOP (300 mils) detail of lead end NOTE ITEM MILLIMETERS INCHES 1. Controlling dimension millimeter. 0.264 +0.012 6.7±0.3 –0.013 2. Each lead centerline is located within 0.12 mm (0.005 inch) of 0.575 MAX. 0.023 MAX. its true position (T.P.) at maximum material condition.
  • Page 78: Recommended Soldering Conditions

    – Caution Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. (2) µ PD754144GS-xxx-GJG: 20-pin plastic shrink SOP (300 mil, 0.65 mm pitch)
  • Page 79 Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative.
  • Page 80 µ PD754144, 754244 Table 17-1. Surface Mounting Type Soldering Conditions (3/3) (5) µ PD754144GS-xxx-BA5-A: 20-pin plastic SOP (300 mil, 1.27 mm pitch) µ PD754144GS-xxx-GJG-A: 20-pin plastic shrink SOP (300 mil, 0.65 mm pitch) µ PD754144GS-xxx-GJG-A: 20-pin plastic shrink SOP (300 mil, 0.65 mm pitch) Undefined Remark Products with -A at the end of the part number are lead-free products.
  • Page 81: Appendix A. Comparison Of Functions Among Μ Pd754144, 754244, And 75F4264

    µ PD754144, 754244 APPENDIX A. COMPARISON OF FUNCTIONS AMONG µ PD754144, 754244, AND 75F4264 µ PD754144 µ PD754244 µ PD75F4264 Note Item Program memory Mask ROM Flash memory 0000H to 0FFFH 0000H to 0FFFH (4096 x 8 bits) (4096 x 8 bits) Data Static RAM 000H to 07FH...
  • Page 82: Appendix B Development Tools

    µ PD754144, 754244 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for system development using the µ PD754244. In the 75XL series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Part number...
  • Page 83 µ PD754144, 754244 Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µ PD754244. The system configurations are described as follows. Hardware IE-75000-R Note 1 In-circuit emulator for debugging the hardware and software when developing applica- tion systems that use the 75X series and 75XL series.
  • Page 84 µ PD754144, 754244 OS for IBM PC The following IBM PC OS’s are supported. Version PC DOS Ver. 5.02 to Ver. 6.3 Note Note J6.1/V to J6.3/V MS-DOS Ver. 5.0 to Ver. 6.22 Note Note 5.0/V to J6.2/V IBM DOS J5.02/V Note Note Supported only English mode.
  • Page 85: Appendix C. Related Documents

    Document Number Document Name Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Static Electricity Discharge (ESD) Test MEM-539 –...
  • Page 86 µ PD754144, 754244 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
  • Page 87 µ PD754144, 754244 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 88 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

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