NEC V850ES/SA2 UPD703201 Manual

32-bit single-chip microcontrollers

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Preliminary User's Manual

V850ES/SA2

32-Bit Single-Chip Microcontrollers

Hardware

V850ES/SA2:

µ µ µ µ PD703201

µ µ µ µ PD703201Y

µ µ µ µ PD70F3201

µ µ µ µ PD70F3201Y

Document No. U15905EJ1V0UD00 (1st edition)

Date Published March 2002 N CP(K)

2002

2001

Printed in Japan

, V850ES/SA3

V850ES/SA3:

µ µ µ µ PD703204

µ µ µ µ PD703204Y

µ µ µ µ PD70F3204

µ µ µ µ PD70F3204Y

Table of Contents

Summary of Contents for NEC V850ES/SA2 UPD703201

Page 1 Preliminary User’s Manual V850ES/SA2 , V850ES/SA3 32-Bit Single-Chip Microcontrollers Hardware V850ES/SA2: V850ES/SA3: µ µ µ µ PD703201 µ µ µ µ PD703204 µ µ µ µ PD703201Y µ µ µ µ PD703204Y µ µ µ µ PD70F3201 µ µ µ µ PD70F3204 µ...
Page 2 [MEMO] Preliminary User’s Manual U15905EJ1V0UD...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. V850 Series, V850ES/SA2, V850ES/SA3, and V850/SA1 are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/SA2 ( µ PD703201, 703201Y, 70F3201, 70F3201Y) and V850ES/SA3 ( µ PD703204, 703204Y, 70F3204, 70F3204Y) and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/SA2 and V850ES/SA3 shown in the Organization below.
Page 7 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 8: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION........................23 Overview ............................23 Features .............................24 Application Fields........................25 Ordering Information........................26 1.4.1 V850ES/SA2 ..........................26 1.4.2 V850ES/SA3 ..........................26 Pin Configuration (Top View) ....................27 Function Block Configuration ....................31 1.6.1 Internal block diagram.........................31 1.6.2 Internal units..........................33 CHAPTER 2 PIN FUNCTIONS ........................36 Pin Function List........................36 Pin Status ..........................43 Description of Pin Functions....................44 Types of Pin I/O Circuits, I/O Buffer Power Supplies, and Connection of Unused Pins ...56...
Page 9 4.2.2 V850ES/SA3 ..........................95 Port Configuration........................96 4.3.1 Port 0 ............................97 4.3.2 Port 2 ............................104 4.3.3 Port 3 ............................111 4.3.4 Port 4 ............................118 4.3.5 Port 7 ............................128 4.3.6 Port 8 ............................130 4.3.7 Port 9 ............................132 4.3.8 Port CD .............................
Page 10 CHAPTER 6 CLOCK GENERATION FUNCTION................205 Overview ..........................205 Configuration ..........................206 Control Registers........................208 Operation ..........................211 6.4.1 Operation of each clock ......................211 6.4.2 Clock output function.........................211 Prescaler 3..........................212 6.5.1 Control register..........................213 6.5.2 Generation of baud rate ......................214 CHAPTER 7 TIMER/COUNTER FUNCTION..................215 16-Bit Timer/Event Counters (TM0 and TM1) ...............215 7.1.1 Features ............................215 7.1.2...
Page 11 Functions ..........................273 Configuration ..........................275 Watchdog Timer Control Registers ..................275 Operation..........................278 9.4.1 Operation as watchdog timer ....................278 9.4.2 Operation as interval timer......................279 9.4.3 Oscillation stabilization time selection function ................. 280 CHAPTER 10 A/D CONVERTER ......................281 10.1 Function ..........................281 10.2 Configuration ..........................283 10.3 Control Registers ........................285 10.4 Operation..........................290 10.4.1...
Page 12 12.4.1 Configuration..........................346 12.4.2 C control registers ........................348 12.4.3 C bus mode functions ......................359 12.4.4 C bus definitions and control methods ..................360 12.4.5 C interrupt request (INTIIC).....................367 12.4.6 Interrupt request (INTIIC) generation timing and wait control ...........385 12.4.7 Address match detection method....................386 12.4.8 Error detection...........................386 12.4.9...
Page 13 14.2 Non-Maskable Interrupts .......................421 14.2.1 Operation ..........................423 14.2.2 Restore ............................. 424 14.2.3 NP flag ............................425 14.2.4 Eliminating noise on NMI pin ....................425 14.2.5 Function to detect edge of NMI pin ................... 425 14.3 Maskable Interrupts........................427 14.3.1 Operation ..........................427 14.3.2 Restore .............................
Page 14 15.9 Control Registers........................466 CHAPTER 16 RESET FUNCTION......................467 16.1 Overview ..........................467 16.2 Configuration ..........................467 16.3 Operation ..........................468 CHAPTER 17 ROM CORRECTION FUNCTION ..................471 17.1 Overview ..........................471 17.2 Control Registers........................472 17.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3) .............472 17.2.2 Correction control register (CORCN) ..................473 17.3 ROM Correction Operation and Program Flow..............473 CHAPTER 18 FLASH MEMORY ......................475...
Page 15 LIST OF FIGURES (1/5) Figure No. Title Page Pin I/O Circuits ..............................58 CPU Address Space ............................70 Image on Address Space ..........................71 Data Memory Map (Physical Addresses) ......................73 Program Memory Map............................. 74 Internal RAM Area (16 KB)..........................77 Internal Peripheral I/O Area..........................
Page 16 LIST OF FIGURES (2/5) Figure No. Title Page 4-31 Block Diagram of PCT2, PCT3, PCT5, and PCT7..................165 4-32 Block Diagram of PDH0 to PDH7 ........................169 4-33 Block Diagram of PDL0 to PDL15 .........................173 Data Memory Map ............................183 Little Endian Address in Word ........................186 Example of Inserting Wait States in Separate Bus Mode................193 Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) ..............199 Multiplexed Bus Read Timing (Bus Size: 8 Bits) ...................199...
Page 17 LIST OF FIGURES (3/5) Figure No. Title Page 7-19 Timing of External Event Counter Operation (with Rising Edge Specified)........... 252 7-20 Timing of Square-Wave Output Operation ....................254 7-21 Timing of PWM Output Operation ......................... 256 7-22 Timing of Operation Based on CRn Register Transitions ................257 7-23 Cascade Connection Mode with 16-Bit Resolution (When TM2 and TM3 Are Connected) ......
Page 18 LIST OF FIGURES (4/5) Figure No. Title Page 12-21 Block Diagram of I C............................344 12-22 Example of Serial Bus Configuration Using I C Bus ..................345 12-23 C Transfer Clock Frequency (f ).......................357 12-24 Pin Configuration Diagram ..........................359 12-25 C Bus Serial Data Transfer Timing......................360 12-26 Start Conditions .............................360 12-27...
Page 19 LIST OF FIGURES (5/5) Figure No. Title Page 15-3 Oscillation Stabilization Time ........................457 15-4 Backup Mode ..............................462 15-5 Procedure of Setting and Releasing Backup Mode..................463 16-1 Reset Block Diagram............................. 467 16-2 Hardware Status on RESET Input......................... 470 16-3 Operation on Power Application........................
Page 20 LIST OF TABLES (1/3) Table No. Title Page V850ES/SA2 and V850ES/SA3 Product Lineup....................23 I/O Buffer Power Supply for Each Pin ......................36 Differences in Pins of V850ES/SA2 and V850ES/SA3..................36 Operating Status of Each Pin in Each Operation Mode ..................43 Program Registers............................62 System Register Numbers..........................63 Interrupt/Exception Table ..........................76 Port Configuration (V850ES/SA2) ........................96...
Page 21 LIST OF TABLES (2/3) Table No. Title Page Control Registers of Real-Time Counter ....................... 264 Configuration of Watchdog Timer........................275 Program Loop Detection Time of Watchdog Timer ..................278 Interval Time of Interval Timer........................279 10-1 Configuration of A/D Converter ........................283 10-2 Example of A/D Conversion Time Setting .....................
Page 22 LIST OF TABLES (3/3) Table No. Title Page 15-8 Operation Status in Subclock Operation Mode .....................459 15-9 Operation After Releasing Sub-IDLE Mode by Interrupt Request ..............460 15-10 Operation Status in Sub-IDLE Mode ......................461 15-11 Operation Status in Backup Mode.........................465 16-1 Hardware Status on RESET Pin Input......................469 16-2 Hardware Status on Occurrence of WDTRES....................469...
Page 23: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850ES/SA2 and V850ES/SA3 are low-power models of NEC’s V850 Series of single-chip microcontrollers for real-time control. Overview The V850ES/SA2 and V850ES/SA3 are 32-bit single-chip microcontrollers that employ the V850ES CPU core and integrate peripheral functions such as ROM/RAM, timers/counters, serial interfaces, an A/D converter, a D/A converter, and a DMA controller.
Page 24: Features
CHAPTER 1 INTRODUCTION Features Number of instructions Minimum instruction execution time 59 ns (main clock (f ) = 17 MHz) 30.5 µ s (subclock (f ) = 32.768 kHz) 32 bits × 32 registers General-purpose registers Signed multiplication (16 × 16 → 32): 1 to 2 clocks Instruction set Signed multiplication (32 ×...
Page 25: Application Fields
CHAPTER 1 INTRODUCTION Serial interface (SIO) Asynchronous serial interface (UART) Clocked serial interface (CSI) C bus interface (I ( µ PD703201Y, 703204Y, 70F3201Y, and 70F3204Y only) CSI/UART: 1 ch UART: 1 ch CSI/I CSI: 2 ch (V850ES/SA2), 3 ch (V850ES/SA3) A/D converter 10-bit resolution: 12 ch (V850ES/SA2) 16 ch (V850ES/SA3)
Page 26: Ordering Information
CHAPTER 1 INTRODUCTION Ordering Information 1.4.1 V850ES/SA2 Part Number Package Internal ROM µ PD703201GC-×××-YEU 100-pin plastic TQFP (fine pitch) (14 × 14) Mask ROM (256 KB) µ PD703201YGC-×××-YEU 100-pin plastic TQFP (fine pitch) (14 × 14) Mask ROM (256 KB) µ...
Page 27: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION Pin Configuration (Top View) V850ES/SA2 100-pin plastic TQFP (fine pitch) (14 × 14) • µ PD703201GC-×××-YEU • µ PD70F3201GC-YEU • µ PD703201YGC-×××-YEU • µ PD70F3201YGC-YEU PDH4/A20 REF0 PDH3/A19 PDH2/A18 P80/ANO0 PDH1/A17 P81/ANO1 PDH0/A16 PDL15/AD15 REF1 P00/NMI PDL14/AD14 P30/SI1/RXD0 PDL13/AD13 P31/SO1/TXD0...
Page 28 CHAPTER 1 INTRODUCTION V850ES/SA3 121-pin plastic FGBA (12 × 12) µ PD703204F1-×××-EA6 µ PD70F3204F1-EA6 µ PD703204YF1-×××-EA6 µ PD70F3204YF1-EA6 Top View Bottom View A B C D E F G H J K L M N N M L K J H G F E D C B A Pin No.
Page 29 CHAPTER 1 INTRODUCTION (2/2) Pin No. Name Pin No. Name Pin No. Name PDL3/AD3 PCS4 PDL10/AD10 P93/A3/INTP6 PCM0/WAIT P94/A4/TO2 PCM2/HLDAK P911/A11/SO2 PCT3 SSBU P914/A14/SO3 PCT4/RD DDBU P915/A15/SCK3 PCT7 PDL8/AD8 PDL0/AD0 Notes 1, 2 IC/FLMD0 PCS0/CS0 P96/A6/TO4 PDL9/AD9 PCS2/CS2 P98/A8/RXD1 P20/SI4 PCM4 P910/A10/SI2 P91/A1...
Page 30 CHAPTER 1 INTRODUCTION Pin Identification A0 to A23: Address bus PCD1 to PCD3: Port CD AD0 to AD15: Address/data bus PCM0 to PCM5: Port CM ADTRG: A/D trigger input PCS0 to PCS7: Port CS ANI0 to ANI15: Analog input PCT0 to PCT7: Port CT ANO0, ANO1: Analog output...
Page 31: Function Block Configuration
CHAPTER 1 INTRODUCTION Function Block Configuration 1.6.1 Internal block diagram • V850ES/SA2 INTC Instruction INTP0 to INTP6 Note 1 queue HLDRQ INTP00, INTP01, 32-bit Multiplier HLDAK INTP10, INTP11 16 × 16 → 32 barrel shifter Timer/counter ASTB TCLR0, TCLR1 16-bit timer: TI0, TI1 WAIT System...
Page 32 CHAPTER 1 INTRODUCTION • V850ES/SA3 INTC Instruction INTP0 to INTP6 Note 1 queue HLDRQ INTP00, INTP01, 32-bit Multiplier HLDAK INTP10, INTP11 16 × 16 → 32 barrel shifter Timer/counter ASTB TCLR0, TCLR1 16-bit timer: TI0, TI1 WAIT System 2 ch 16 KB registers WR0, WR1...
Page 33: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU can execute almost all instruction processing, such as address calculation, arithmetic logic operations, and data transfer, with 1 clock, using a 5-stage pipeline. The CPU has dedicated hardware units such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) to speed up complicated instruction processing.
Page 34 CHAPTER 1 INTRODUCTION (10) Serial interface (SIO) The V850ES/SA2 and V850ES/SA3 have asynchronous serial interfaces (UART0 and UART1), clocked serial interfaces (V850ES/SA2: CSI0 to CSI3, V850ES/SA3: CSI0 to CSI4), and an I C bus interface (I C) as the serial interfaces. The V850ES/SA2 can use up to four channels, and the V850ES/SA3 can use up to five channels at the same time.
Page 35 CHAPTER 1 INTRODUCTION (15) Ports Some port pins have a control function as well as a general-purpose port function, as shown below. Port Port Function Control Function 6-bit I/O General-purpose port NMI, external interrupt, timer input Note 3-bit I/O Serial interface 3-bit I/O Serial interface 7-bit I/O...
Page 36: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS Pin Function List This chapter explains the names and functions of the pins in the V850ES/SA2 and V850ES/SA3, classified into port pins and non-port pins. Two power supplies are available for the pin I/O buffers: AV and EV .
Page 37 CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/3) Pin Name On-Chip Pull-up Function Alternate-Function Resistor Provided Port 0. 6-bit I/O port. INTP0/TI2 Can be set to input or output in 1-bit units. INTP1/TI3 INTP2/TI4 INTP3/TI5 INTP4 [P20] Provided Port 2. [SI4] 3-bit I/O port.
Page 38 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name On-Chip Pull-up Function Alternate-Function Resistor Input None Port 8. ANO0 2-bit input port ANO1 Provided Port 9. 16-bit I/O port. Can be set to input or output in 1-bit units. A2/INTP5 Can be specified as an N-ch open drain port in 1-bit units A3/INTP6 (P911, P912, P914, and P915 only).
Page 39 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name On-Chip Pull-up Function Alternate-Function Resistor PDH0 None Port DH. 6-bit I/O port (V850ES/SA2). PDH1 8-bit I/O port (V850ES/SA3). PDH2 Can be set to input or output in 1-bit units. PDH3 PDH4 PDH5 [PDH6] [A22] [PDH7] [A23]...
Page 40 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name On-Chip Pull-up Function Alternate- Resistor Function Pin Output Provided Address bus for external memory (when separate bus is used) P92/INTP5 P93/INTP6 P94/TO2 P95/TO3 P96/TO4 P97/TO5 P98/RXD1 P99/TXD1 P910/SI2 P911/SO2 P912/SCK2 P913/SI3 P914/SO3 P915/SCK3...
Page 41 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name On-Chip Pull-up Function Alternate- Resistor Function Pin − − − Positive power supply for A/D converter (same potential as V − − Input Reference voltage input for A/D converter REF0 − Reference voltage input for D/A converter REF1 −...
Page 42 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name On-Chip Pull-up Function Alternate-Function Pin Resistor 490 Output Provided Serial transmit data output (CSI0) P41/SDA Serial transmit data output (CSI1) P31/TXD0 Serial transmit data output (CSI2) P911/A11 Serial transmit data output (CSI3) P914/A14 [SO4] Serial transmit data output (CSI4) [P21]...
Page 43: Pin Status
CHAPTER 2 PIN FUNCTIONS Pin Status The operating status of each pin in each operation mode is shown below. Table 2-3. Operating Status of Each Pin in Each Operation Mode 490 Bus Control Pins Reset HALT Mode or IDLE and STOP Idle State Bus Hold DMA Transfer...
Page 44: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS Description of Pin Functions (1) P00 to P05 (Port 0) … 3-state I/O Port 0 is a 6-bit I/O port that can be set to the input or output in 1-bit units. Besides functioning as I/O port pins, P00 to P05 also operate as NMI input, external interrupt request, and timer/counter input pins.
Page 45 CHAPTER 2 PIN FUNCTIONS (3) P30 to P32 (Port 3) … 3-state I/O Port 3 is a 3-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, P30 to P32 also operate as the I/O pins of the serial interface. These pins can be set to the port or control mode in 1-bit units.
Page 46 CHAPTER 2 PIN FUNCTIONS (iv) SI0 (serial input 0) … Input This pin inputs the serial receive data of CSI0. (v) SO0 (serial output 0) … Output This pin outputs the serial transmit data of CSI0. (vi) SCK0 (serial clock 0) … 3-state I/O This is the serial clock I/O pin of CSI0.
Page 47 CHAPTER 2 PIN FUNCTIONS [V850ES/SA3] Port 7 is a 16-bit input port with all its bits fixed to the input mode. Besides functioning as input port pins, P70 to P715 also operate as the analog input pins of the A/D converter in the control mode.
Page 48 CHAPTER 2 PIN FUNCTIONS (7) P90 to P915 (Port 9) … 3-state I/O Port 9 is a 16-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, P90 to P915 also operate as the I/O pins of the serial interface and timer/counters, the address bus pins to extend the memory externally, and external interrupt request input pins.
Page 49 CHAPTER 2 PIN FUNCTIONS (9) PCM0 to PCM3 (Port CM) (V850ES/SA2) … 3-state I/O PCM0 to PCM5 (Port CM) (V850ES/SA3) … 3 state I/O [V850ES/SA2] Port CM is a 4-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, in the control mode PCM0 to PCM3 also operate as the bus hold control signal output and bus clock output pins, and as the control signal that inserts a wait state (WAIT) in the bus cycle.
Page 50 CHAPTER 2 PIN FUNCTIONS [V850ES/SA3] Port CM is a 6-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, in the control mode PCM0 to PCM5 also operate as the bus hold control signal output and bus clock output pins, and as the control signal that inserts a wait state (WAIT) in the bus cycle.
Page 51 CHAPTER 2 PIN FUNCTIONS (10) PCS0 to PSC3 (Port CS) (V850ES/SA2) … 3-state I/O PCS0 to PCS5 (Port CS) (V850ES/SA3) … 3-state I/O [V850ES/SA2] Port CS is a 4-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, in the control mode PCS0 to PSC3 also operate as the control signal output pins when the memory and peripheral I/O are expanded externally.
Page 52 CHAPTER 2 PIN FUNCTIONS (11) PCT0, PCT1, PCT4 to PCT7 (Port CT) (V850ES/SA2) … 3-state I/O PCT0 to PCT7 (Port CT) (V850ES/SA3) … 3-state I/O [V850ES/SA2] Port CT is a 6-bit port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, in the control mode PCT0, PCT1, and PCT4 to PCT7 also operate as the control signal output pins when the memory is expanded externally.
Page 53 CHAPTER 2 PIN FUNCTIONS (iii) RD (read strobe) … Output This is the read strobe signal output pin for the external 16-bit data bus. (iv) ASTB (address strobe) … Output This is the latch strobe signal output pin of the external address bus. The output signal goes low at the falling edge of the T1 state in the bus cycle, and goes high at the falling edge of the T3 state.
Page 54 CHAPTER 2 PIN FUNCTIONS (13) PDL0 to PDL15 (Port DL) … 3-state I/O Port DL is a 16-bit I/O port that can be set to the input or output mode in 1-bit units. Besides functioning as I/O port pins, PDL0 to PDL15 also operate a time-division address/data bus (AD0 to AD15) when the memory is externally expanded.
Page 55 CHAPTER 2 PIN FUNCTIONS (22) V (Ground for backup) $$& This is a ground pin for backup. (23) EV (Power supply for port) This pin supplies positive power for the I/O ports and pins with alternate functions. (24) EV (Ground for port) This is a ground pin for the I/O ports and pins with alternate functions.
Page 56: Types Of Pin I/O Circuits, I/O Buffer Power Supplies, And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS Types of Pin I/O Circuits, I/O Buffer Power Supplies, and Connection of Unused Pins (1/2) Alternate Function I/O Circuit Type Recommended Connection Input: Independently connect to EV or EV via a resistor. P01 to P04 INTP0/TI2 to INTP3/TI5 Output: Leave open.
Page 57 CHAPTER 2 PIN FUNCTIONS (2/2) Alternate Function I/O Circuit Type Recommended Connection Input: Independently connect to EV or EV via a PCS0 to PCS3 CS0 to CS3 resistor. − [PCS4 to PCS7] Output: Leave open. PCT0, PCT1 WR0, WR1 − [PCT2, PCT3] PCT4 −...
Page 58 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (1/2) Type 2 Type Pull-up P-ch enable Data P-ch IN/OUT Output N-ch disable Input Schmitt-triggered input with hysteresis characteristics. enable Type 5 Type Data P-ch P-ch Comparator IN/OUT − N-ch Output N-ch disable (Threshold voltage)
Page 59 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (2/2) Type 10-F Type 34 Pull-up P-ch enable P-ch Analog IN/OUT Data output voltage P-ch N-ch IN/OUT Open drain N-ch Output Input enable disable Input enable Type 16 Feedback cut-off P-ch Preliminary User’s Manual U15905EJ1V0UD...
Page 60: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850ES/SA2 and V850ES/SA3 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. Features Minimum instruction execution time: 58.9 ns (at 17 MHz operation: 2.2 V to 2.7 V) 30.5 ns (with subclock (f = 32.768 kHz operation)) Memory space...
Page 61: Cpu Register Set
CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/SA2 and V850ES/SA3 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User’s Manual. (1) Program register set (2) System register set (Zero register)
Page 62: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable.
Page 63: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2.
Page 64 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
Page 65 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW.
Page 66 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution.
Page 67 CHAPTER 3 CPU FUNCTION Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
Page 68 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW.
Page 69: Operation Modes
CHAPTER 3 CPU FUNCTION Operation Modes 3.3.1 Operation modes The V850ES/SA2 and V850ES/SA3 have the following operation modes. (1) Normal operation mode In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Page 70: Address Space
CHAPTER 3 CPU FUNCTION Address Space 3.4.1 CPU address space The CPU of the V850ES/SA2 and V850ES/SA3 has 32-bit architecture and supports up to 4 GB of linear address space (data space) for operand addressing (data access). It also supports up to 64 MB of linear address space (program space) for instruction addressing.
Page 71: Image
CHAPTER 3 CPU FUNCTION 3.4.2 Image For instruction addressing, up to 16 MB of linear address space (program space) and an internal RAM area are supported. Up to 4 GB of linear address space (data space) is supported for operand addressing (data access). In the 4 GB address space, it seems that there are sixty-four 64 MB physical address spaces.
Page 72: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the lowest address of the program space, 00000000H, and the highest address, 03FFFFFFH, are contiguous addresses.
Page 73: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.4 Memory map The V850ES/SA2 and V850ES/SA3 reserve the areas shown in Figure 3-3. Figure 3-3. Data Memory Map (Physical Addresses) 3 F F F F F F H 3 F F F F F F H Internal peripheral I/O area (4 KB) 3 F F F 0 0 0 H...
Page 74 CHAPTER 3 CPU FUNCTION Figure 3-4. Program Memory Map 0 3 F F F F F F H Use prohibited (program fetch prohibited area) 0 3 F F F 0 0 0 H 0 3 F F E F F F H Internal RAM area (16 KB) 3 F F B 0 0 0 H 3 F E A F F F H...
Page 75: Areas
CHAPTER 3 CPU FUNCTION 3.4.5 Areas (1) Internal ROM area (a) Memory map 1 MB of addresses 0000000H to 00FFFFFH is reserved as the internal ROM area. <1> µ µ µ µ PD703201, 703201Y, 703204, and 703204Y 256 KB are mapped to the following addresses as the physical internal ROM (mask ROM). •...
Page 76 CHAPTER 3 CPU FUNCTION • Interrupt/exception table The V850ES/SA2 and V850ES/SA3 speed up the interrupt response time by fixing handler addresses corresponding to interrupts/exceptions. A collection of these handler addresses is called an interrupt/exception table, which is mapped to the internal ROM area.
Page 77 CHAPTER 3 CPU FUNCTION (2) Internal RAM area 60 KB of addresses 3FF0000H to 3FFEFFFH are reserved as the internal RAM area. The V850ES/SA2 and V850ES/SA3 map 16 KB of addresses 3FFB000H to 3FFEFFFH as physical internal RAM. Figure 3-5. Internal RAM Area (16 KB) 3 F F E F F F H Internal RAM area (16 KB) 3 F F B 0 0 0 H...
Page 78 CHAPTER 3 CPU FUNCTION (3) Internal peripheral I/O area 4 KB of addresses 3FFF000H to 3FFFFFFH are allocated as the internal peripheral I/O area. Figure 3-6. Internal Peripheral I/O Area 3 F F F F F F H Internal peripheral I/O area (4 KB) 3 F F F 0 0 0 H Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the...
Page 79: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTION 3.4.6 Recommended use of address space The architecture of the V850ES/SA2 and V850ES/SA3 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
Page 80 CHAPTER 3 CPU FUNCTION Figure 3-7. Recommended Memory Map Program space Data space F F F F F F F F H Internal peripheral I/O F F F F F 0 0 0 H F F F F E F F F H Internal RAM x F F F F F F F H F F F F C 0 0 0 H...
Page 81: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.7 Peripheral I/O registers (1/8) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF004H Port DL Undefined √ √ FFFFF004H Port DLL PDLL √ √ FFFFF005H Port DLH PDLH √ √ FFFFF006H Port DH √...
Page 82 CHAPTER 3 CPU FUNCTION (2/8) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF0C0H DMA transfer count register 0 DBC0 Undefined √ FFFFF0C2H DMA transfer count register 1 DBC1 √ FFFFF0C4H DMA transfer count register 2 DBC2 √ FFFFF0C6H DMA transfer count register 3 DBC3...
Page 83 CHAPTER 3 CPU FUNCTION (3/8) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF13AH Interrupt control register CSIIC1 √ √ FFFFF13CH Interrupt control register SREIC0 √ √ FFFFF13EH Interrupt control register SRIC0 √ √ FFFFF140H Interrupt control register STIC0 √...
Page 84 CHAPTER 3 CPU FUNCTION (4/8) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF420H Port mode register 0 √ √ Note FFFFF424H Port mode register 2 √ √ FFFFF426H Port mode register 3 √ √ FFFFF428H Port mode register 4 √...
Page 85 CHAPTER 3 CPU FUNCTION (5/8) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF644H Timer clock select register 23 TCL23 0000H √ FFFFF644H Timer clock select register 2 TCL2 √ FFFFF645H Timer clock select register 3 TCL3 √ FFFFF646H Timer mode control register 23 TMC23...
Page 86 CHAPTER 3 CPU FUNCTION (6/8) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF6EEH Week count setting register WEEKB 0000H √ FFFFF6EEH Week count setting register L WEEKBL √ FFFFF6EFH Week count setting register H WEEKBH √ √ FFFFF802H System status register √...
Page 87 CHAPTER 3 CPU FUNCTION (7/8) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFFC00H External interrupt falling edge specification register 0 INTF0 √ FFFFFC12H External interrupt falling edge specification register 9 INTF9 0000H √ √ FFFFFC12H External interrupt falling edge specification register 9L INTF9L √...
Page 88 CHAPTER 3 CPU FUNCTION (8/8) Address Function Register Name Symbol Manipulatable Bits Default Value √ Note 1 FFFFFD44H Clocked serial interface transmit buffer register 4 SOTB4 √ Note 2 FFFFFD80H IIC shift register √ √ Note 2 FFFFFD82H IIC control register IICC √...
Page 89: Special Registers
CHAPTER 3 CPU FUNCTION 3.4.8 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/SA2 and V850ES/SA3 have the following four special registers. • Power save control register (PSC) •...
Page 90 CHAPTER 3 CPU FUNCTION Cautions 1. When a store instruction is executed to store data in the command register, an interrupt is not acknowledged. This is because it is assumed that steps <3> and <4> above are performed by successive store instructions. If another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction.
Page 91 CHAPTER 3 CPU FUNCTION The PRERR flag operates under the following conditions. (a) Set condition (PRERR = 1) (i) When data is written to a special register without writing anything to the PRCMD register (when <4> is executed without executing <3> in 3.4.8 (1) Setting special register) (ii) When data is written to a peripheral I/O register other than a special register (including execution of a bit manipulation instruction) after writing data to the PRCMD register (if <4>...
Page 92: Notes
CHAPTER 3 CPU FUNCTION 3.4.9 Notes Be sure to set the following register first when using the V850ES/SA2 and V850ES/SA3: • System wait control register (VSWC) After setting the VSWC register, set the other registers as necessary. When using the external bus, initialize each register in the following order after setting the above register. <1>...
Page 93: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS Features 4.1.1 V850ES/SA2 Input ports: 14 pins I/O ports: 68 pins I/O pins function alternately as other peripheral functions Can be set to input or output mode in 1-bit units. 4.1.2 V850ES/SA3 Input ports: 18 pins I/O ports: 84 pins I/O pins function alternately as other peripheral functions Can be set to input or output mode in 1-bit units.
Page 94: Basic Configuration Of Port
CHAPTER 4 PORT FUNCTIONS Basic Configuration of Port 4.2.1 V850ES/SA2 The V850ES/SA2 has a total of 82 input/output port pins (of which 14 are input-only port pins): ports 0, 3, 4, 7 to 9, CM, CS, CT, DH, and DL. The port configuration is shown below. Figure 4-1.
Page 95: V850Es/Sa3
CHAPTER 4 PORT FUNCTIONS 4.2.2 V850ES/SA3 The V850ES/SA3 has a total of 102 input/output port pins (of which 18 are input-only port pins): ports 0, 2 to 4, 7 to 9, CD, CM, CS, CT, DH, and DL. The port configuration is shown below. Figure 4-2.
Page 96: Port Configuration
CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-1. Port Configuration (V850ES/SA2) Item Configuration Control registers Port mode register (PMn: n = 0, 3, 4, 9, CM, CS, CT, DH, DL) Pull-up resistor option register (PUn: n = 0, 3, 4, 9) Ports I/O: 68 pins, Input: 14 pins Pull-up resistor...
Page 97: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 can be set to the input or output mode in 1-bit units. The number of I/O port bits of each product is the same. Commercial Name Number of I/O Port Bits V850ES/SA2 6-bit I/O port V850ES/SA3...
Page 98 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 0 (P0) Port register 0 (P0) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF400H...
Page 99 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register 0 (PMC0) This is an 8-bit register that specifies the port mode or control mode. This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF440H PMC0 PMC05 PMC04...
Page 100 CHAPTER 4 PORT FUNCTIONS (d) Pull-up resistor option register 0 (PU0) This is an 8-bit register that specifies connection of an internal pull-up resistor. This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFFC40H PU05 PU04 PU03...
Page 101 CHAPTER 4 PORT FUNCTIONS (f) External interrupt rising edge specification register 0 (INTR0) This 8-bit register specifies detection of the rising edge of the external interrupt pins. It can be read or written in 8-bit or 1-bit units. Caution Set the port mode after clearing the INTF0n and INTR0n bits to 0 when switching from the external interrupt function (alternate function) to the port function because an edge may be detected.
Page 102 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-3. Block Diagram of P00 and P05 P-ch PU0n INTR INTR0 INTR0n INTF INTF0 INTF0n PMC0 PMC0n PM0n PORT P00/NMI, P05/INTP4 Address Noise elimination, NMI, INTP4 input edge detection Remarks 1. P0: Port register 0 PM0: Port mode register 0...
Page 103 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P01 to P04 P-ch PU0n INTR INTR0 INTR0n INTF INTF0 INTF0n PMC0 PMC0n PM0n PORT P01/INTP0/TI2, P02/INTP1/TI3, P03/INTP2/TI4, P04/INTP3/TI5 Address Noise elimination, Noise elimination, edge detection edge detection INTP0 to INTP3 input TI2 to TI5 input Remarks 1.
Page 104: Port 2
CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 2 Port 2 can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name Number of I/O Port Bits − V850ES/SA2 V850ES/SA3 3-bit I/O port...
Page 105 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 2 (P2) Port register 2 (P2) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF404H...
Page 106 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register 2 (PMC2) This is an 8-bit register that specifies the port mode or control mode. This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF444H PMC2 PMC22 PMC21...
Page 107 CHAPTER 4 PORT FUNCTIONS (e) Pull-up resistor option register 2 (PU2) This is an 8-bit register that specifies connection of an internal pull-up resistor. This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFFC44H PU22 PU21 PU20...
Page 108 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-5. Block Diagram of P20 P-ch PU20 PMC2 PMC20 PM20 PORT P20/SI4 Address SI4 input Remark Port register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 PU2: Pull-up resistor option register 2 Preliminary User’s Manual U15905EJ1V0UD...
Page 109 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P21 P-ch PU21 PF21 PMC2 PMC21 PM21 PORT SO4 output P-ch P21/SO4 N-ch Address Remark Port register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 PU2: Pull-up resistor option register 2 Preliminary User’s Manual U15905EJ1V0UD...
Page 110 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P22 PU22 P-ch PF22 SCK4 output PMC2 enable signal PMC22 PM22 PORT SCK4 output P-ch P22/SCK4 N-ch Address SCK4 input Remark Port register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 PF2: Port function register 2 PU2:...
Page 111: Port 3
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 3 Port 3 can be set to the input or output mode in 1-bit units. The number of I/O port bits of each product is the same. Commercial Name Number of I/O Port Bits V850ES/SA2 3-bit I/O port V850ES/SA3...
Page 112 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 3 (P3) Port register 3 (P3) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF406H...
Page 113 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register 3 (PMC3) This is an 8-bit register that specifies the port mode or control mode. This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF446H PMC3 PMC32 PMC31...
Page 114 CHAPTER 4 PORT FUNCTIONS (e) Port function register 3 (PF3) This 8-bit register specifies normal output or N-ch open-drain output. It can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFFC66H PF32 PF31 PF3n Controls normal output or N-ch open-drain output (n = 1, 2) Normal output N-ch open-drain output Cautions 1.
Page 115 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-8. Block Diagram of P30 P-ch PU30 PFC3 PFC30 PMC3 PMC30 PM30 PORT P30/SI1/RXD0 Address SI1 input RXD0 input Remark Port register 3 PM3: Port mode register 3 PMC3: Port mode control register 3 PFC3: Port function control register 3 PU3: Pull-up resistor option register 3...
Page 116 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P31 P-ch PU31 PF31 PFC3 PFC31 PMC3 PMC31 PM31 SO1 output PORT TXD output P-ch P31/SO1/ TXD0 N-ch Address Remark Port register 3 PM3: Port mode register 3 PMC3: Port mode control register 3 PFC3: Port function control register 3 PF3: Port function register 3...
Page 117 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P32 PU32 P-ch PF32 SCK1 output PMC3 enable signal PMC32 PM32 PORT SCK1 output P-ch P32/SCK1 N-ch Address SCK1 input Remark Port register 3 PM3: Port mode register 3 PMC3: Port mode control register 3 PFC3: Port function control register 3 PU3: Pull-up resistor option register 3...
Page 118: Port 4
CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 can be set to the input or output mode in 1-bit units. The number of I/O port bits each product is the same. Commercial Name Number of I/O Port Bits V850ES/SA2 7-bit I/O port V850ES/SA3 7-bit I/O port...
Page 119 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 4 (P4) Port register 4 (P4) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF408H...
Page 120 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register 4 (PMC4) This is an 8-bit register that specifies the port mode or control mode. This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF448H PMC4 PMC46 PMC45...
Page 121 CHAPTER 4 PORT FUNCTIONS (d) Port function control register 4 (PFC4) This 8-bit register specifies control mode 1 or control mode 2. It can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF468H PFC4 PFC46 PFC44 PFC42 PFC41 PFC46...
Page 122 CHAPTER 4 PORT FUNCTIONS (e) Port function register 4 (PF4) This 8-bit register specifies normal output or N-ch open-drain output. It can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFFC68H PF42 PF41 PF4n Controls normal output or N-ch open-drain output (n = 1, 2) Normal output N-ch open-drain output...
Page 123 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-11. Block Diagram of P40 P-ch PU40 PMC4 PMC40 PM40 PORT P40/SI0 Address Input signal in control mode Remark Port register 4 PM4: Port mode register 4 PMC4: Port mode control register 4 PU4: Pull-up resistor option register 4 Preliminary User’s Manual U15905EJ1V0UD...
Page 124 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P41 P-ch PU41 PF41 PFC4 PFC41 PMC4 PMC41 PM41 SO0 output PORT SDA output P-ch P41/SO0/ N-ch Address SDA input Remark Port register 4 PM4: Port mode register 4 PMC4: Port mode control register 4 PFC4: Port function control register 4 PF4: Port function register 4...
Page 125 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P42 P-ch PU42 PF42 SCK0 output enable signal PFC4 PFC42 PMC4 PMC42 PM42 SCK0 output PORT SCL output P-ch P42/SCK0/ N-ch Address SCK0 input SCL input Remark Port register 4 PM4: Port mode register 4 PMC4: Port mode control register 4 PFC4: Port function control register 4...
Page 126 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P43 and P45 P-ch PU4n PMC4 PMC4n PM4n PORT P43/INTP00/TI0/TCLR0, P45/INTP10/TI1/TCLR1 Address INTP00/TI0/TCLR0, Noise INTP10/TI1/TCLR1 input elimination Remarks 1. P4: Port register 4 PM4: Port mode register 4 PMC4: Port mode control register 4 PU4: Pull-up resistor option register 4 2.
Page 127 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P44 and P46 P-ch PU4n PFC4 PFC4n PMC4 PMC4n PM4n PORT TO0, TO1 output P44/INTP01/TO0, P46/INTP11/TO1 Address Noise INTP01, INTP11 input elimination Remarks 1. P4: Port register 4 PM4: Port mode register 4 PMC4: Port mode control register 4 PFC4: Port function control register 4 PU4:...
Page 128: Port 7
CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 7 All the pins of port 7 are fixed to the input mode. The number of input port bits differs depending on the product. Commercial Name Number of I/O Port Bits V850ES/SA2 12-bit input port V850ES/SA3 16-bit input port (1) Function of port 7...
Page 129 CHAPTER 4 PORT FUNCTIONS (2) Register (a) Port register 7 (P7) Port register 7 is a 16-bit register that is used to read the pin level. This register is read-only, in 16-bit units. If the higher 8 bits of the P7 register are used as P7H, and the lower 8 bits as P7L, however, this register can be read in 8-bit or 1-bit units.
Page 130: Port 8
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 8 Port 8 can control input/output in 1-bit units. The number of I/O port bits of each product is the same. Commercial Name Number of I/O Port Bits V850ES/SA2 2-bit I/O port V850ES/SA3 2-bit I/O port (1) Function of port 8 Input data can be specified in 1-bit units by using port register 8 (P8).
Page 131 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-17. Block Diagram of P80 and P81 P80/ANO0, P81/ANO1 P-ch ANO0, ANO1 output N-ch Preliminary User’s Manual U15905EJ1V0UD...
Page 132: Port 9
CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 9 Port 9 can be set to the input or output mode in 1-bit units. The number of I/O port bits each product is the same. Commercial Name Number of I/O Port Bits V850ES/SA2 16-bit I/O port V850ES/SA3 16-bit I/O port...
Page 133 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register 9 (P9) Port register 9 (P9) is a 16-bit register that controls reading a pin level and writing an output level. This register can be read or written in 8-bit or 1-bit units. If the higher 8 bits of the P9 register is used as P9H and the lower 8 bits as P9L, however, P9H and P9L can be manipulated in 8-bit or 1-bit units.
Page 134 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register 9 (PMC9) This is a 16-bit register that specifies the port mode or control mode. This register can be read or written only in 16-bit units. If the higher 8 bits of the PMC9 register is used as PMC9H and the lower 8 bits as PMC9L, however, PMC9H and PMC9L can be manipulated in 8-bit or 1-bit units.
Page 135 CHAPTER 4 PORT FUNCTIONS (2/2) PMC98 Specifies operation mode of P98 pin I/O port A8/RXD1 PMC97 Specifies operation mode of P97 pin I/O port A7/TO5 output PMC96 Specifies operation mode of P96 pin I/O port A6/TO4 output PMC95 Specifies operation mode of P95 pin I/O port A5/TO3 output...
Page 136 CHAPTER 4 PORT FUNCTIONS (d) Port function control register 9 (PFC9) This 16-bit register specifies control mode 1 or control mode 2. It can be read or written only in 16-bit units. If the higher 8 bits of the PFC9 register are used as PFC9H and the lower 8 bits as PFC9L, however, PFC9H and PFC9L can be manipulated in 8-bit or 1-bit units.
Page 137 CHAPTER 4 PORT FUNCTIONS (2/2) PFC98 Specifies operation mode of P98 pin in control mode output (with separate bus) RXD1 input PFC97 Specifies operation mode of P97 pin in control mode output (with separate bus) output PFC96 Specifies operation mode of P96 pin in control mode output (with separate bus) output PFC95...
Page 138 CHAPTER 4 PORT FUNCTIONS (e) Port function register 9 (PF9) This 16-bit register specifies normal output or N-ch open-drain output. The PF9 register can be read or written only in 16-bit units. If the higher 8 bits of the PF9 register are used as PF9H and the lower 8 bits as PF9L, however, PF9H and PF9L can be manipulated in 8-bit or 1-bit units.
Page 139 CHAPTER 4 PORT FUNCTIONS (g) External interrupt falling edge specification register 9 (INTF9) This 16-bit register specifies detection of the falling edge of the external interrupt pins. It can be read or written only in 16-bit units. If the higher 8 bits of the INTF9 register are used as INTF9H and the lower 8 bits as INTF9L, however, INTF9H and INTF9L can be manipulated in 8-bit or 1-bit units.
Page 140 CHAPTER 4 PORT FUNCTIONS Table 4-11. Specifying Valid Edge INTF9n INTR9n Specifies valid edge (n = 2 or 3). Detects no edge. Rising edge Falling edge Both edges Caution When INTP5 and INTP6 are not used, be sure to clear INTF9n and INTR9n to “00”. Remark n = 2 or 3: Control of INTP5 or INTP6 pin Preliminary User’s Manual U15905EJ1V0UD...
Page 141 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-18. Block Diagram of P90 and P91 P-ch PU9n PMC9 PMC9n Output buffer OFF signal PM9n A0, A1 output PORT P90/A0, P91/A1 Address Remarks 1. P9: Port register 9 PM9: Port mode register 9 PMC9: Port mode control register 9 PU9: Pull-up resistor option register 9...
Page 142 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P92 and P93 PU9n P-ch INTR9 INTR9n INTF9 INTF9n PFC9 PFC9n PMC9 PMC9n Output buffer OFF signal PM9n A2, A3 output PORT P92/A2/INTP5, P93/A3/INTP6 Address Noise elimination, INTP5, INTP6 input edge detection Remarks 1.
Page 143 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P94 to P97 and P99 P-ch PU9n PFC9 PFC9n PMC9 PMC9n Output buffer OFF signal PM9n A4 to A9 output P94/A4/TO2, PORT TO2 to TO5, TXD1 output P95/A5/TO3, P96/A6/TO4, P97/A7/TO5, P99/A9/TXD1 Address Remarks 1.
Page 144 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of P98, P910, and P913 P-ch PU9n PFC9 PFC9n PMC9 PMC9n Output buffer OFF signal PM9n A8, A10, A13 output PORT P98/A8/RXD1, P910/A10/SI2, P913/A13/SI3 Address RXD1, SI2, SI3 input Remarks 1. P9: Port register 9 PM9: Port mode register 9...
Page 145 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of P911 and P914 P-ch PU9n PF9n PFC9 PFC9n PMC9 PMC9n Output buffer OFF signal PM9n A11, A14 output PORT SO2, SO3 output P-ch P911/A11/SO2, P914/A14/SO3 N-ch Address Remarks 1. P9: Port register 9 PM9: Port mode register 9 PMC9: Port mode control register 9...
Page 146 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P912 and P915 PU9n P-ch PF9n PFC9 PFC9n PMC9 PMC9n Output enable signal of SCK2 and SCK3 Output buffer OFF signal PM9n A12, A15 output PORT SCK2, SCK3 output P-ch P912/A12/SCK2, P915/A15/SCK3 N-ch Address...
Page 147: Port Cd
CHAPTER 4 PORT FUNCTIONS 4.3.8 Port CD Port CD can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name Number of I/O Port Bits − V850ES/SA2 V850ES/SA3 3-bit I/O port...
Page 148 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register CD (PCD) Port register CD (PCD) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF00EH...
Page 149 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-24. Block Diagram of PCD1 to PCD3 PMCD PMCDn PORT PCDn PCD1 to PCD3 Address Remarks 1. PCD: Port register CD PMCD: Port mode register CD 2. n = 1 to 3 Preliminary User’s Manual U15905EJ1V0UD...
Page 150: Port Cm
CHAPTER 4 PORT FUNCTIONS 4.3.9 Port CM Port CM can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name Number of I/O Port Bits V850ES/SA2 4-bit I/O port V850ES/SA3 6-bit I/O port...
Page 151 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register CM (PCM) Port register PCM (PCM) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF00CH...
Page 152 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register CM (PMCCM) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF04CH PMCCM PMCCM3 PMCCM2 PMCCM1 PMCCM0 PMCCM3 Specifies operation mode of PCM3 pin...
Page 153 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-25. Block Diagram of PCM0 and PCM3 PMCCM PMCCMn PMCM PMCMn PORT PCMn PCM0/WAIT, PCM3/HLDRQ Address WAIT, HLDRQ input Remarks 1. PCM: Port register CM PMCM: Port mode register CM PMCCM: Port mode control register CM 2.
Page 154 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of PCM1 and PCM2 PMCCM PMCCMn PMCM PMCMn CLKOUT, HLDAK output PORT PCM1/CLKOUT, PCM2/HLDAK PCMn Address Remarks 1. PCM: Port register CM PMCM: Port mode register CM PMCCM: Port mode control register CM 2.
Page 155 CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of PCM4 and PCM5 PMCM PMCMn PORT PCMn PCM4, PCM5 Address Remarks 1. PCM: Port register CM PMCM: Port mode register CM 2. n = 4 or 5 Preliminary User’s Manual U15905EJ1V0UD...
Page 156: Port Cs
CHAPTER 4 PORT FUNCTIONS 4.3.10 Port CS Port CS can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name Number of I/O Port Bits V850ES/SA2 4-bit I/O port V850ES/SA3 8-bit I/O port...
Page 157 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register CS (PCS) Port register CS (PCS) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF008H...
Page 158 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register CS (PMCCS) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF048H PMCCS PMCCS3 PMCCS2 PMCCS1 PMCCS0 PMCCSn Specifies operation mode of PCSn pin (n = 0 to 3)
Page 159 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-28. Block Diagram of PCS0 to PCS3 PMCCS PMCCSn PMCS PMCSn CS0 to CS3 output PORT PCS0/CS0 to PCS3/CS3 PCSn Address Remarks 1. PCS: Port register CS PMCS: Port mode register CS PMCCS: Port mode control register CS 2.
Page 160 CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of PCS4 to PCS7 PMCS PMCSn PORT PCSn PCS4 to PCS7 Address Remarks 1. PCS: Port register CS PMCS: Port mode register CS 2. n = 4 to 7 Preliminary User’s Manual U15905EJ1V0UD...
Page 161: Port Ct
CHAPTER 4 PORT FUNCTIONS 4.3.11 Port CT Port CT can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name Number of I/O Port Bits V850ES/SA2 6-bit I/O port V850ES/SA3 8-bit I/O port...
Page 162 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register CT (PCT) Port register PCT (PCT) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF00AH...
Page 163 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register CT (PMCCT) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF04AH PMCCT PMCCT6 PMCCT4 PMCCT1 PMCCT0...
Page 164 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-30. Block Diagram of PCT0, PCT1, PCT4, and PCT6 PMCCT PMCCTn PMCT PMCTn WR0, WR1, RD, ASTB output PORT PCT0/WR0, PCT1/WR1, PCT4/RD, PCTn PCT6/ASTB Address Remarks 1. PCT: Port register CT PMCT: Port mode register CT PMCCT: Port mode control register CT 2.
Page 165 CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of PCT2, PCT3, PCT5, and PCT7 PMCT PMCTn PORT PCTn PCT2, PCT3, PCT5, PCT7 Address Remarks 1. PCT: Port register CT PMCT: Port mode register CT 2. n = 2, 3, 5, or 7 Preliminary User’s Manual U15905EJ1V0UD...
Page 166: Port Dh
CHAPTER 4 PORT FUNCTIONS 4.3.12 Port DH Port DH can be set to the input or output mode in 1-bit units. The number of I/O port bits differs depending on the product. Commercial Name Number of I/O Port Bits V850ES/SA2 6-bit I/O port V850ES/SA3 8-bit I/O port...
Page 167 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register DH (PDH) Port register PDH (PDH) is an 8-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. After reset: Undefined Address: FFFFF006H...
Page 168 CHAPTER 4 PORT FUNCTIONS (c) Port mode control register DH (PMCDH) This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF046H Note Note PMCDH PMCDH7...
Page 169 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-32. Block Diagram of PDH0 to PDH7 PUDH P-ch PUDHn PMCDH PMCDHn Output buffer OFF signal PMDH PMDHn Output signal in PORT control mode PDH0/A16 to PDH7/A23 PDHn Address Remarks 1. PDH: Port register DH PMDH: Port mode register DH PMCDH: Port mode control register DH...
Page 170: Port Dl
CHAPTER 4 PORT FUNCTIONS 4.3.13 Port DL Port DL can be set to the input or output mode in 1-bit units. The number of I/O port bits of each product is the same. Commercial Name Number of I/O Port Bits V850ES/SA2 16-bit I/O port V850ES/SA3...
Page 171 CHAPTER 4 PORT FUNCTIONS (2) Registers (a) Port register DL (PDL) Port register DL (PDL) is a 16-bit register that controls reading the pin level and writing the output level. This register can be read or written in 8-bit or 1-bit units. If the higher 8 bits of the PDL register are used as PDLH, and the lower 8 bits as PDLL, however, PDLH and PDLL can be used as an 8-bit I/O port whose input or output can be manipulated in 8-bit or 1-bit units.
Page 172 CHAPTER 4 PORT FUNCTIONS (c) Port DL mode control register (PMCDL) This is a 16-bit register that specifies the port mode or control mode. It can be read or written only in 16-bit units. If the higher 8 bits of the PMCDL register are used as PMCDLH, and the lower 8 bits as PMCDLL, however, PMCDLH and PMCDLL can be read or written in 8-bit units.
Page 173 CHAPTER 4 PORT FUNCTIONS (3) Block diagram Figure 4-33. Block Diagram of PDL0 to PDL15 PMCDL PMCDLn Output enable signal of AD0 to AD15 Output buffer OFF signal PMDL PMDLn Output of AD0 to AD15 PORT PDL0/AD0 to PDL15/AD15 PDLn Address Input enable signal of AD0 to AD15...
Page 174 Table 4-18. Using Alternate Function of Port Pins (1/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn PMCnx Bit of PFCnx Bit of Register PMCn Register PFCn Register Name − Input PMC00 = 1 INTR00 (INT P00 = Setting not needed PM00 = Setting not needed −...
Page 175 Table 4-18. Using Alternate Function of Port Pins (2/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn PMCnx Bit of PFCnx Bit of Register PMCn Register PFCn Register Name − INTP00 Input PMC43 = 1 ETI0 = 0 (TM P43 = Setting not needed PM43 = Setting not needed...
Page 176 Table 4-18. Using Alternate Function of Port Pins (3/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn PMCnx Bit of PFCnx Bit of Register PMCn Register PFCn Register Name − − − P711 ANI11 Input P711 = Setting impossible −...
Page 177 Table 4-18. Using Alternate Function of Port Pins (4/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn PMCnx Bit of PFCnx Bit of Register PMCn Register PFCn Register Name Output PMC99 = 1 PFC99 = 0 Note P99 = Setting not needed PM99 = Setting not needed...
Page 178 Table 4-18. Using Alternate Function of Port Pins (5/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of PMCn Register PFCn Register Name − PCM0 WAIT Input PMCCM0 = 1 PCM0 = Setting not needed PMCM0 = Setting not needed −...
Page 179 Table 4-18. Using Alternate Function of Port Pins (6/6) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of PMCn Register PFCn Register Name − PDH0 Output PMCDH0 = 1 PDH0 = Setting not needed PMDH0 = Setting not needed −...
Page 180: Operation Of Port Function
CHAPTER 4 PORT FUNCTIONS Operation of Port Function The operation of a port differs depending on whether the port is in the input or output mode, as described below. 4.4.1 Writing data to I/O port (1) In output mode A value can be written to the output latch by using a transfer instruction. The contents of the output latch are output from the pin.
Page 181: Chapter 5 Bus Control Function
CHAPTER 5 BUS CONTROL FUNCTION The V850ES/SA2 and V850ES/SA3 are provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. Features Output is selectable from a multiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles.
Page 182: Pin Status When Internal Rom, Internal Ram, Or Peripheral I/O Is Accessed
CHAPTER 5 BUS CONTROL FUNCTION Table 5-2. External Control Pins (Separate Bus) Bus Control Pin Alternate-Function Pin Function AD0 to AD15 PDL0 to PDL15 Data bus A0 to A15 P90 to P915 Output Address bus Note A16 to A23 PDH0 to PDH7 Output Address bus WAIT...
Page 183: Memory Block Function
CHAPTER 5 BUS CONTROL FUNCTION Memory Block Function The 64 MB memory space is divided into memory blocks of (lower) 2 MB, 2MB, 4MB, and 8MB. programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units.
Page 184: Chip Select Control Function
CHAPTER 5 BUS CONTROL FUNCTION 5.3.1 Chip select control function Of the 64 MB (linear) address space, the lower 16 MB (0000000H to 0FFFFFFH) include four chip select functions, CS0 to CS3. The areas that can be selected by CS0 to CS3 are fixed. By using these chip select functions, the memory block can be divided to enable effective use of the memory space.
Page 185: Bus Access
CHAPTER 5 BUS CONTROL FUNCTION Bus Access 5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Internal ROM (32 bits) Internal RAM (32 bits) External Memory (16 bits) Bus Cycle Type Note Instruction fetch (normal access)
Page 186: Access By Bus Size
CHAPTER 5 BUS CONTROL FUNCTION 5.5.3 Access by bus size The V850ES/SA2 and V850ES/SA3 access the peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the peripheral I/O is fixed to 16 bits. •...
Page 187 CHAPTER 5 BUS CONTROL FUNCTION (2) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Second access Address Address Address 2n + 1 2n + 1 2n + 2 Halfword data...
Page 188 CHAPTER 5 BUS CONTROL FUNCTION (3) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address Address 4n + 1 4n + 3 4n + 2 Word data External data Word data External data <2>...
Page 189 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External data Word data External data <4>...
Page 190 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External data Word data External data Word data...
Page 191 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External data Word data...
Page 192: Wait Function
CHAPTER 5 BUS CONTROL FUNCTION Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each CS space. The number of wait states can be programmed by using data wait control register 0 (DWC0).
Page 193: External Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.2 External wait function To synchronize an extremely slow external device, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal ROM, internal RAM, and internal peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function.
Page 194: Programmable Address Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control register (AWC). Address wait insertion is set for each chip select area (CS0 to CS3). If an address setup wait is inserted, it seems that the high-clock period of T1 state is extended by 1 clock.
Page 195: Idle State Insertion Function
CHAPTER 5 BUS CONTROL FUNCTION Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select function in the multiplexed address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state.
Page 196: Bus Hold Function
CHAPTER 5 BUS CONTROL FUNCTION Bus Hold Function 5.8.1 Functional outline The HLDAK and HLDRQ functions are valid if the PCM2 and PCM3 pins are set in the control mode. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
Page 197: Bus Hold Procedure
CHAPTER 5 BUS CONTROL FUNCTION 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status <5>...
Page 198: Bus Priority
CHAPTER 5 BUS CONTROL FUNCTION Bus Priority Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the external bus cycle. Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive).
Page 199: Bus Timing
CHAPTER 5 BUS CONTROL FUNCTION 5.11 Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 Idle state Programmable External wait wait 8-bit access Odd address Even address −...
Page 200 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 WR1, WR0 Programmable External wait wait 8-bit access Odd address Even address −...
Page 201 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT HLDRQ HLDAK Hi-Z A23 to A16 Hi-Z AD15 to AD0 Hi-Z ASTB Hi-Z Hi-Z CS3 to CS0 Remark For the status of each pin during bus hold, refer to Table 2-3. Preliminary User’s Manual U15905EJ1V0UD...
Page 202 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-9. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS0 to CS3 WAIT A0 to A23 AD0 to AD15 Programmable External Idle state wait wait 8-bit access Odd address Even address −...
Page 203 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS0 to CS3 WAIT A0 to A23 WR0, WR1 AD0 to AD7 Programmable External wait wait Figure 5-12. Separate Bus Write Timing (Bus Size: 8 Bits) CLKOUT CS0 to CS3 WAIT...
Page 204 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-13. Separate Bus Hold Timing (Bus Size: 8 Bits, During Write) CLKOUT HLDRQ HLDAK A0 to A23 AD0 to AD7 WR0, WR1 CS0 to CS3 Figure 5-14. Address Wait Timing (Separate Bus Read, Bus Size: 16 Bits, 16-Bit Access) (a) Without wait inserted (b) With wait inserted TASW...
Page 205: Chapter 6 Clock Generation Function
CHAPTER 6 CLOCK GENERATION FUNCTION Overview The features of the clock generation function are as follows. Main clock oscillator (f • 2 to 17 MHz (at 2.2 to 2.7 V operation) Subclock oscillator (f • 32.768 kHz Generation of internal system clock (f •...
Page 206: Configuration
CHAPTER 6 CLOCK GENERATION FUNCTION Configuration Figure 6-1. Clock Generator FRC bit Subclock oscillator RTC clock to f Prescaler 3 A/D converter IDLE IDLE control MFRC bit CK3 to CK0 bits IDLE Main clock Prescaler 2 control oscillator HALT mode Main clock oscillator HALT...
Page 207 CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator This circuit oscillates the following frequency (f • 2 to 17 MHz (at 2.2 to 2.7 V operation) (2) Subclock oscillator This circuit oscillates a frequency of 32.768 kHz (f (3) Main clock resonator stop control This circuit generates a control signal that stops oscillation of the main clock resonator.
Page 208: Control Registers
CHAPTER 6 CLOCK GENERATION FUNCTION Control Registers (1) Processor clock control register (PCC) The processor clock control register (PCC) is a special register. Data can be written to it only in combination of specific sequences (refer to 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units.
Page 209 CHAPTER 6 CLOCK GENERATION FUNCTION Examples of settings to change between the main clock and subclock are shown below (a) Example of setting when changing from main clock to subclock <1> Checking internal system clock: Check if the following condition is satisfied. •...
Page 210 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Power save control register (PSC) The power save control register (PSC) is a special register. Data can be written to this register only in combination of specific sequences (refer to 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF1FEH...
Page 211: Operation
CHAPTER 6 CLOCK GENERATION FUNCTION Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock CLS bit = 0 CLS bit = 1 CLS bit = 1 MCK bit = 0 MCK bit = 0 MCK bit = 1...
Page 212: Prescaler 3
CHAPTER 6 CLOCK GENERATION FUNCTION Prescaler 3 Prescaler 3 has the following functions. • Generation of baud rate for count clock of watch timer (source clock: main clock oscillation) • Generation of baud rate for count clock of A/D converter (source clock: main clock oscillator) •...
Page 213: Control Register
CHAPTER 6 CLOCK GENERATION FUNCTION 6.5.1 Control register (1) Prescaler mode register (PRSM) The PRSM register controls generation of the baud rate signal of the watch timer and A/D converter. This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF8B0H...
Page 214: Generation Of Baud Rate
CHAPTER 6 CLOCK GENERATION FUNCTION (2) Prescaler compare register (PRSCM) This is an 8-bit compare register. It can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF8B1H PRSCM PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0 Cautions 1.
Page 215: Chapter 7 Timer/Counter Function
CHAPTER 7 TIMER/COUNTER FUNCTION 16-Bit Timer/Event Counters (TM0 and TM1) 7.1.1 Features The 16-bit timer/event counters (TM0 and TM1) can perform the following operations. • Interval timer function • PWM output • External signal cycle measurement 7.1.2 Function overview • 16-bit timer/counter •...
Page 216: Basic Configuration Of 16-Bit Timer/Event Counters (Tm0 And Tm1)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.3 Basic configuration of 16-bit timer/event counters (TM0 and TM1) Table 7-1. 16-Bit Timer/Event Counter Configuration Timer Count Clock Register Read/Write Generated Capture Trigger Timer Output Interrupt Signal TM0, TM1 /2, f Read INTOVF0 – – /8, f /16, CC00...
Page 217 CHAPTER 7 TIMER/COUNTER FUNCTION (1) Timers 0 and 1 (TM0 to TM1) TMn functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being used for cycle measurement, TMn can be used for pulse output (n = 0, 1). TMn is read-only, in 16-bit units.
Page 218 CHAPTER 7 TIMER/COUNTER FUNCTION (b) Selection of the internal count clock TMn operates as a free-running timer. When the internal clock is specified as the count clock by timer mode control register n1 (TMCn1), TMn is counted up for each input clock cycle specified by the CSn0 to CSn2 bits of the TMCn0 register (n = 0, 1). Division by the prescaler can be selected for the count clock from among f /2, f /4, f...
Page 219 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Capture/compare registers n0 and n1 (CCn0 and CCn1) (n = 0, 1) These capture/compare registers (n0 and n1) are 16-bit registers. They can be used as capture registers or compare registers according to the CMSn0 and CMSn1 bit specifications of timer mode control register n1 (TMCn1) (n = 0, 1).
Page 220 CHAPTER 7 TIMER/COUNTER FUNCTION (b) Setting these registers as compare registers (CMSn0 and CMSn1 of TMCn1 = 1) When these registers are set as compare registers, the TMn and register values are compared for each count clock, and an interrupt is generated by a match. If the CCLRn bit of timer mode control register n1 (TMCn1) is set (1), the TMn value is cleared (0) at the same time as a match with the CCn0 register (it is not cleared (0) by a match with the CCn1 register) (n = 0, 1).
Page 221: Control Registers
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.4 Control registers (1) Timer mode control registers 00 and 10 (TMC00 and TMC10) The TMCn0 registers control the operation of TMn (n = 0, 1). These registers can be read or written in 8-bit or 1-bit units. Be sure to set bits 3 and 2 to 0.
Page 222 CHAPTER 7 TIMER/COUNTER FUNCTION (2/2) CSn2 CSn1 CSn0 Internal count clock selection /128 /256 TMCEn TMn register operation control Count disabled (stops at 0000H and does not operate). Counting operation is performed. When TMCEn = 0, the external pulse output (TOn) becomes inactive (the active level of TOn output is set by the ALVn bit of the TMCn1 register).
Page 223 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Timer mode control registers 01 and 11 (TMC01 and TMC11) The TMCn1 registers control the operation of TMn (n = 0, 1). These registers can be read or written in 8-bit units. Cautions 1. The various bits of the TMCn1 register must not be changed during timer operation. If they are to be changed, they must be changed after setting the TMCEn bit of the TMCn0 register to 0.
Page 224 CHAPTER 7 TIMER/COUNTER FUNCTION (2/2) ALVn External pulse output (TOn) active level specification Low level High level The initial value of the ALVn bit is 1. ETIn Count clock external/internal switch specification Specifies the input clock (internal). Specifies the external clock (TIn0). •...
Page 225 CHAPTER 7 TIMER/COUNTER FUNCTION (3) Valid edge select registers 0 and 1 (SES0 and SES1) These registers specify the valid edge of an external interrupt request (INTP00, INTP01, INTP10, INTP11, TI0, and TI1) from an external pin. The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin.
Page 226: 16-Bit Timer/Event Counter Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.5 16-bit timer/event counter operation (1) Count operation The 16-bit timer/event counter can function as a 16-bit free-running timer or as an external signal event counter. The setting for the type of operation is specified by timer mode control registers n0 and n1 (TMCn0 and TMCn1) (n = 0, 1).
Page 227 CHAPTER 7 TIMER/COUNTER FUNCTION (2) Overflow When the TMn register has counted the count clock from FFFFH to 0000H, the OVFn bit of the TMCn0 register is set (1), and an overflow interrupt (INTOVFn) is generated at the same time (n = 0, 1). However, if the CCn0 register is set to compare mode (CMSn0 bit = 1) and to the value FFFFH when match clearing is enabled (CCLRn bit = 1), then the TMn register is considered to be cleared and the OVFn bit is not set (1) when the TMn register changes from FFFFH to 0000H.
Page 228 CHAPTER 7 TIMER/COUNTER FUNCTION (3) Capture operation The TMn register has two capture/compare registers. These are the CCn0 register and the CCn1 register. A capture operation or a compare operation is performed according to the settings of both the CMSn1 and CMSn0 bits of the TMCn1 register.
Page 229 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-5. TM1 Capture Operation Example (When Both Edges Are Specified) (TM1 count values) ∆ ∆ Count start Overflow TMCE1←1 OVF1←1 Interrupt request (INTP11) Capture register (CC11) Remark D0 to D2: TM1 register count values Preliminary User’s Manual U15905EJ1V0UD...
Page 230 CHAPTER 7 TIMER/COUNTER FUNCTION (4) Compare operation The TMn register has two capture/compare registers. These are the CCn0 register and the CCn1 register. A capture operation or a compare operation is performed according to the settings of both the CMSn1 and CMSn0 bits of the TMCn1 register.
Page 231 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-7. Compare Operation Example (When CCLR1 = 1 and CC10 Is 0000H) Count-up FFFFH 0000H 0000H 0001H Compare register 0000H (CC10) INTOVF1 Match detection (INTCC10) Remark A match is detected immediately after the count-up, and the match detection signal is generated. Preliminary User’s Manual U15905EJ1V0UD...
Page 232 CHAPTER 7 TIMER/COUNTER FUNCTION (5) External pulse output The 16-bit timer/event counter has two timer output pins (TOn). An external pulse output (TOn) is generated when a match of the two compare registers (CCn0 and CCn1) and the TMn register is detected. If a match is detected when the TMn register count value and the CCn0 value are compared, the output level of the TOn pin is set.
Page 233: Application Examples (16-Bit Timer/Event Counter)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.6 Application examples (16-bit timer/event counter) (1) Interval timer By setting the TMCn0 and TMCn1 registers as shown in Figure 7-9, the 16-bit timer/event counter operates as an interval timer that repeatedly generates interrupt requests with the value that was preset in the CCn0 register as the interval.
Page 234 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-10. Interval Timer Operation Timing Example Count clock TMn register 0000H 0001H 0000H 0001H 0000H 0001H Clear Clear Count start CCn0 register INTCCn0 interrupt Interval time Interval time Interval time Remarks 1. p: Setting value of CCn0 register (0000H to FFFFH) t: Count clock cycle Interval time = (p + 1) ×...
Page 235 CHAPTER 7 TIMER/COUNTER FUNCTION (2) PWM output By setting the TMCn0 and TMCn1 registers as shown in Figure 7-11, the 16-bit timer/event counter can output a PWM signal, whose frequency is determined according to the setting of the CSn2 to CSn0 bits of the TMCn0 register, with the values that were preset in the CCn0 and CCn1 registers determining the intervals.
Page 236 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-12. PWM Output Timing Example Count clock 0000H 0001H FFFFH 0000H 0001H register Count start Clear CCn0 register CCn1 register INTCCn0 interrupt INTCCn1 interrupt (output) Remarks 1. p: Setting value of CCn0 register (0000H to FFFFH) q: Setting value of CCn1 register (0000H to FFFFH) p ≠...
Page 237 CHAPTER 7 TIMER/COUNTER FUNCTION (3) One-shot pulse output By setting the TMCn0 and TMCn1 registers as shown in Figure 7-13, the 16-bit timer/event counter can output a one-shot pulse from the TOn pin by using the valid edge of the TCLRn pin as an external trigger. The valid edge of the TCLRn pin is selected according to the CESn0 and CESn1 bits of the SESn register.
Page 238 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-14. One-Shot Pulse Output Operation Timing Example Count clock 0000H 0001H FFFFH 0000H register Count start Count stop CCn0 register CCn1 register INTCCn0 interrupt INTCCn1 interrupt (output) Remarks 1. p: Setting value of CCn0 register (0000H to FFFFH) q: Setting value of CCn1 register (0000H to FFFFH) p ≠...
Page 239 CHAPTER 7 TIMER/COUNTER FUNCTION (4) Cycle measurement By setting the TMCn0 and TMCn1 registers as shown in Figure 7-15, the 16-bit timer/event counter can measure the cycle of signals input to the INTPn0 or INTPn1 pin. The valid edge of the INTPn0 pin is selected according to the IESn01 and IESn00 bits of the SESn register, and the valid edge of the INTPn1 pin is selected according to the IESn11 and IESn10 bits of the SESn register.
Page 240 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-15. Contents of Register Settings When 16-Bit Timer/Event Counter Is Used for Cycle Measurement OVFn CSn2 CSn1 CSn0 TMCEn TMCAEn TMCn0 Supply input clocks to internal units Enable count operation OSTn ENTOn ALVn ETIn CCLRn ECLRn CMSn1 CMSn0 TMCn1...
Page 241 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-16. Cycle Measurement Operation Timing Example Count clock 0000H 0001H FFFFH 0000H 0001H register Count start Clear INTPn0 (input) CCn0 register INTCCn0 interrupt INTOVFn interrupt (D1 − D0) × t {(10000H − D1) + D2} × t (D3 −...
Page 242: Cautions (16-Bit Timer/Event Counter)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.1.7 Cautions (16-bit timer/event counter) Various cautions concerning the 16-bit timer/event counter are shown below. (1) If a conflict occurs between the reading of the CCn0 register and a capture operation when the CCn0 register is used in capture mode, an external trigger (INTPn0) valid edge is detected and an external interrupt request signal (INTCCn0) is generated, however, the timer value is not stored in the CCn0 register.
Page 243: 8-Bit Timer/Event Counters 2 To 5 (Tm2 To Tm5)
CHAPTER 7 TIMER/COUNTER FUNCTION 8-Bit Timer/Event Counters 2 to 5 (TM2 to TM5) 7.2.1 Function outline 8-bit timer/event counter n has the following two modes (n = 2 to 5). • Mode using 8-bit timer/event counter alone (individual mode) • Mode using cascade connection (16-bit resolution: cascade connection mode) These two modes are described below.
Page 244: Configuration Of 8-Bit Timer/Event Counter N
CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-17. Block Diagram of 8-Bit Timer/Event Counter n Internal bus 8-bit timer compare Selector INTTMn register n (CRn) Match Note 2 8-bit timer counter n Note 1 Count clock (TMn) Clear Invert level Selector TCLn2 TCLn1 TCLn0 TCEn TMCn6 TMCm4 LVSn LVRn TMCn1 TOEn Timer clock selection 8-bit timer mode control...
Page 245 CHAPTER 7 TIMER/COUNTER FUNCTION (1) 8-bit timer counters 2 to 5 (TM2 to TM5) The TMn register is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. TM2 and TM3, and TM4 and TM5 can be used as 16-bit timers when they are connected in cascade.
Page 246: Registers Controlling 8-Bit Timer/Event Counters 2 To 5
CHAPTER 7 TIMER/COUNTER FUNCTION 7.2.3 Registers controlling 8-bit timer/event counters 2 to 5 The following two registers are used to control 8-bit timer/event counter n. • Timer clock selection register n (TCLn) • 8-bit timer mode control register n (TMCn) Remark To use the functions of the TIn and TOn pins, refer to Table 4-18 Using Port Pins for Alternate Function.
Page 247 CHAPTER 7 TIMER/COUNTER FUNCTION After reset: 00H Address: TCL4 FFFFF654H, TCL5 FFFFF655H TCLn TCLn2 TCLn1 TCLn0 (n = 4, 5) TCLn2 TCLn1 TCLn0 Count clock selection Clock 17 MHz 13.5 MHz − − Falling edge of TIn − − Rising edge of TIn 235 ns 296 ns 470 ns...
Page 248 CHAPTER 7 TIMER/COUNTER FUNCTION (2) 8-bit timer mode control registers 2 to 5 (TMC2 to TMC5) The TMCn register performs the following six settings. • Controls counting by 8-bit timer counters 2 to 5 (TM2 toTM5) • Selects the operation mode of the TMn register •...
Page 249 CHAPTER 7 TIMER/COUNTER FUNCTION After reset: 00H Address: TMC3 FFFFF646H TMC3 FFFFF647H TMC4 FFFFF656H TMC5 FFFFF657H <7> Note TMCn TCEn TMCn6 TMCm4 LVSn LVRn TMCn1 TOEn (n = 2 to 5, m = 3, 5) TCEn Control of count operation of 8-bit timer/event counter n Counting is disabled after the counter is cleared to 0 (counter disabled) Start count operation TMCn6...
Page 250: Operation Of 8-Bit Timer/Event Counters 2 To 5
CHAPTER 7 TIMER/COUNTER FUNCTION Operation of 8-Bit Timer/Event Counters 2 to 5 7.3.1 Operation as interval timer (8 bits) 8-bit timer/event counter n operates as an interval timer that repeatedly generates interrupts at the interval of the count value preset in 8-bit timer compare register n (CRn). If the count value in 8-bit timer counter n (TMn) matches the value set in the CRn register, the value of the TMn register is cleared to 0 and counting is continued, and at the same time, an interrupt request signal (INTTMn) is generated.
Page 251 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-18. Timing of Interval Timer Operation (2/2) When CRn register = 00H Count clock TMn count value TCEn INTTMn Interval time Remark n = 2 to 5 When CRn register = FFH Count clock TMn count value FEH FFH FEH FFH TCEn...
Page 252: Operation As External Event Counter (8 Bits)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.2 Operation as external event counter (8 bits) The external event counter counts the number of clock pulses input to the TIn pin from an external source by using 8-bit timer counter n (TMn). Each time the valid edge specified by timer clock selection register n (TCLn) is input to the TIn pin, the TMn register is incremented.
Page 253: Square-Wave Output Operation (8-Bit Resolution)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.3 Square-wave output operation (8-bit resolution) A square wave with any frequency can be output at an interval specified by the value preset in 8-bit timer compare register n (CRn). By setting the TOEn bit of 8-bit timer mode control register n (TMCn) to 1, the output status of the TOn pin is inverted at an interval specified by the count value preset in the CRn register.
Page 254 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-20. Timing of Square-Wave Output Operation Count clock N − 1 N − 1 TMn count value Count start TCEn INTTMn Note The initial value of the TOn output can be set using the LVSn and LVRn bits of the TMCn register. Remark n = 0, 1 Preliminary User’s Manual U15905EJ1V0UD...
Page 255: 8-Bit Pwm Output Operation
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.4 8-bit PWM output operation By setting the TMCn6 bit of 8-bit timer mode control register n (TMCn) to 1, 8-bit timer/event counter n performs PWM output. Pulses with the duty factor determined by the value set in 8-bit timer compare register n (CRn) are output from the TOn pin.
Page 256 CHAPTER 7 TIMER/COUNTER FUNCTION (a) Basic operation of PWM output Figure 7-21. Timing of PWM Output Operation Basic operation (active level = H) Count clock TMn count value N + 1 TCEn INTTMn Active level Inactive level Active level When CRn register = 00H Count clock TMn count value N + 1 N + 2...
Page 257 CHAPTER 7 TIMER/COUNTER FUNCTION (b) Operation based on CRn register transitions Figure 7-22. Timing of Operation Based on CRn Register Transitions When the value of the CRn register changes from N to M before the rising edge of the FFH clock →...
Page 258: Operation As Interval Timer (16 Bits)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.5 Operation as interval timer (16 bits) The V850ES/SA2 and V850ES/SA3 are provided with a 16-bit register that can be used only during cascade connection. The 16-bit resolution timer/event counter mode is selected by setting the TMC34 and TMC54 bits of 8-bit timer mode control registers 3 and 5 (TMC3 and TMC5) to 1.
Page 259 CHAPTER 7 TIMER/COUNTER FUNCTION Figure 7-23 shows a timing example of the cascade connection mode with 16-bit resolution. Figure 7-23. Cascade Connection Mode with 16-Bit Resolution (When TM2 and TM3 Are Connected) Count clock TM2 count value N + 1 M −...
Page 260: Operation As External Event Counter (16 Bits)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.6 Operation as external event counter (16 bits) The V850ES/SA2 and V850ES/SA3 are provided with a 16-bit register that can be used only during cascade connection. The 16-bit resolution timer/event counter mode is selected by setting the TMC34 and TMC54 bits of 8-bit timer mode control registers 3 and 5 (TMC3 and TMC5) to 1.
Page 261: Square-Wave Output Operation (16-Bit Resolution)
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.7 Square-wave output operation (16-bit resolution) The V850ES/SA2 and V850ES/SA3 are provided with a 16-bit register that can be used only during cascade connection. The 16-bit resolution timer/event counter mode is selected by setting the TMC34 and TCM54 bits of 8-bit timer mode control registers 3 and 5 (TMC3 and TMC5) to 1.
Page 262: Cautions
CHAPTER 7 TIMER/COUNTER FUNCTION 7.3.8 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 8-bit timer counter n (TMn) is started asynchronously to the count pulse. Figure 7-24.
Page 263: Chapter 8 Real-Time Counter Function
CHAPTER 8 REAL-TIME COUNTER FUNCTION Function The real-time counter has the following functions. • Week, day, hour, minute, and second counters that can count up to 4,095 weeks • Week, day, hour, minute, and second counters can be read while they are operating/stopped •...
Page 264: Real-Time Counter Control Registers
CHAPTER 8 REAL-TIME COUNTER FUNCTION Real-Time Counter Control Registers The registers listed in the table below control the real-time counter. Table 8-1. Control Registers of Real-Time Counter Register Name Function Instruction Unit Reset Value RTCC0 RTC control register 0 8/1-bit instruction RTCC1 RTC control register 1 8/1-bit instruction...
Page 265 CHAPTER 8 REAL-TIME COUNTER FUNCTION (2) RTC control register 1 (RTCC1) The RTCC1 register is an 8-bit register that controls the operation of the real-time counter. This register can be read or written in 8-bit or 1-bit units. RESET input sets this register to 8xH. Note 1 After reset: Address:...
Page 266 CHAPTER 8 REAL-TIME COUNTER FUNCTION (3) Sub-count register (SUBC) The SUBC register is a 15-bit register that counts the reference time of the real-time counter. It counts 1 second using the 32.768 kHz clock. This register is read-only, in 16-bit or 8-bit units. This register is not initialized by RESET input or when RTCE = 0.
Page 267 CHAPTER 8 REAL-TIME COUNTER FUNCTION (6) Minute count register (MIN) This 8-bit uses a value of 0 to 59 (decimal) to indicate the count value in minutes. This register is read-only, in 8-bit units. This register is not initialized by RESET input or when RTCE = 0. After reset: Undefined Address: FFFFF6E5H...
Page 268 CHAPTER 8 REAL-TIME COUNTER FUNCTION (9) Hour count setting register (HOURB) This is an 8-bit register for setting the hour count. This register is read-only, in 8-bit units. Set a count value in a range of 0 to 23 (decimal) to this register. Do not set a count value of 24 (decimal) or greater. RESET input clears this register to 00H.
Page 269 CHAPTER 8 REAL-TIME COUNTER FUNCTION (12) Week count register (WEEK) This 16-bit register uses a value of 0 to 4,095 (decimal) to indicate the count value in weeks. This register is read-only, in 8-bit or 16-bit units. This register is not initialized by RESET input or when RTCE = 0. After reset: Undefined Address: FFFFF6E8H...
Page 270: Operation
CHAPTER 8 REAL-TIME COUNTER FUNCTION Operation 8.3.1 Initializing counter and count-up <1> When the RESET input signal is asserted (0), the values of RTC control registers 0 and 1 (RTCC0 and RTCC1) are initialized. Real-time counter clock operation is enabled when RTCAE of the RTCC0 register is set to 1, and real-time counter count operation is enabled when RTCE of the RTCC1 register is set to 1.
Page 271: Controlling Interrupt Request Signal Output
CHAPTER 8 REAL-TIME COUNTER FUNCTION 8.3.3 Controlling interrupt request signal output This section explains how to control interrupt request signals, taking INTS0 to INTS3 = 0111B (every second) and INTS0 to INTS3 = 1000B (every minute) as an example. <1> When the RESET input signal is asserted (0), the values of the RTCC0 and RTCC1 registers are initialized. Real-time counter clock operation is enabled when RTCAE is set to 1, and real-time counter count operation is enabled when RTCE is set to 1.
Page 272 CHAPTER 8 REAL-TIME COUNTER FUNCTION (4) Write data to each count setting register using the following procedure: • To clear the sub-count register (SUBC) <1> Using the procedure described in (3) above, read the values of all the count registers (this may be omitted), and clear RTCAE to 0.
Page 273: Chapter 9 Watchdog Timer Functions
CHAPTER 9 WATCHDOG TIMER FUNCTIONS Functions The watchdog timer has the following operation modes. • Watchdog timer • Interval timer • Selecting the oscillation stabilization time The following functions are realized from the above-listed operation modes. • Generation of non-maskable interrupt request signal (INTWDT) upon overflow of watchdog timer •...
Page 274 CHAPTER 9 WATCHDOG TIMER FUNCTIONS Figure 9-1. Block Diagram of Watchdog Timer OSCMD Clear 13-bit division circuit Clear 8-bit counter INTWDTM Output INTWDT control WDTRES OSTOVF OSTS0 to OSTS2, WDCS0 to WDCS2 WDTM3, WDTM4 Remark INTWDTM: Request signal for maskable interrupt through WDT overflow INTWDT: Request signal for non-maskable interrupt through WDT overflow WDTRES: Reset signal through WDT overflow...
Page 275: Configuration
CHAPTER 9 WATCHDOG TIMER FUNCTIONS Configuration The watchdog timer consists of the following hardware. Table 9-1. Configuration of Watchdog Timer Item Configuration Control register Oscillation stabilization time selection register (OSTS) Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM) Watchdog Timer Control Registers The registers that control the watchdog timer are as follows.
Page 276 CHAPTER 9 WATCHDOG TIMER FUNCTIONS (2) Watchdog timer clock selection register (WDCS) This register sets the overflow time of the watchdog timer and the interval timer. The WDCS register is set by an 8-bit or 1-bit memory manipulation instruction. RESET input clears WDCS to 00H. After reset: Address: FFFF6C1H...
Page 277 CHAPTER 9 WATCHDOG TIMER FUNCTIONS (3) Watchdog timer mode register (WDTM) This register sets the watchdog timer operation mode and enables/disables count operations. This register is a special register that can be written only in a special sequence (refer to 3.4.8 Special registers).
Page 278: Operation
CHAPTER 9 WATCHDOG TIMER FUNCTIONS Operation 9.4.1 Operation as watchdog timer Watchdog timer operation to detect a program loop is selected by setting bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to 1. The count clock (program loop detection time interval) of the watchdog timer can be selected with bits WDCS0 to WDCS2 of the watchdog timer clock selection register (WDCS).
Page 279: Operation As Interval Timer
CHAPTER 9 WATCHDOG TIMER FUNCTIONS 9.4.2 Operation as interval timer The watchdog timer can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by setting bit 4 (WDTM4) of the watchdog timer mode register (WDTM) to When the watchdog timer operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification flags (WDTPR0 to WDTPR2) of the WDTIC register are valid and maskable interrupt request signals (INTWDTM) can be generated.
Page 280: Oscillation Stabilization Time Selection Function
CHAPTER 9 WATCHDOG TIMER FUNCTIONS 9.4.3 Oscillation stabilization time selection function The wait time until the oscillation stabilizes after the STOP mode is released is controlled by the oscillation stabilization time register (OSTS). The OSTS register is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 281: Chapter 10 A/D Converter
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Page 283: Configuration
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Page 285: Control Registers
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Page 290: Operation
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Page 291: Chapter 11 D/A Converter
CHAPTER 11 D/A CONVERTER 11.1 Functions The D/A converter has the following functions. 8-bit resolution × 2 channels (DAC0, DAC1) R string method Conversion time: 20 µ s max. (AV = 2.2 to 2.7 V) REF1 × m/256 (m = 0 to 255; value set to DACSn register) Analog output voltage: AV REF1 Operation modes: Normal mode, real-time output mode...
Page 292: Configuration
CHAPTER 11 D/A CONVERTER 11.2 Configuration The D/A converter consists of the following hardware. Table 11-1. Configuration of D/A Converter Item Configuration Control registers D/A converter mode register (DAM) D/A conversion value setting registers 0 and 1 (DACS0 and DACS1) 11.3 D/A Converter Control Registers The registers that control the D/A converter are as follows.
Page 293 CHAPTER 11 D/A CONVERTER (2) D/A conversion value setting registers 0 and 1 (DACS0 and DACS1) These registers set the analog voltage value output to the ANO0 and ANO1 pins. These registers are set by an 8-bit memory manipulation instruction. RESET input clears DACS0 and DACS1 to 00H.
Page 294: Operation
CHAPTER 11 D/A CONVERTER 11.4 Operation 11.4.1 Operation in normal mode D/A conversion is performed using a write operation to D/A conversion value setting register n (DACSn) as the trigger. The setting method is described below. <1> Set the DAMDn bit of the D/A converter mode register (DAM) to 0 (normal mode). <2>...
Page 295: Cautions
CHAPTER 11 D/A CONVERTER 11.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/SA2 and V850ES/SA3. (1) Do not change the set value of the DACSn register while the trigger signal is being issued in the real-time output mode.
Page 296: Chapter 12 Serial Interface Function
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.1 Features The serial interface function provides three types of serial interfaces combining a total of seven or eight transmit/receive channels. Five or six of these channels can be used simultaneously. The three interface formats are as follows. (1) Asynchronous serial interface (UARTm): 2 channels (2) Clocked serial interface (CSIn): 4 channels (V850ES/SA2)
Page 297: Selecting Csi1 Or Uart0 Mode
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.1.1 Selecting CSI1 or UART0 mode CSI1 and UART0 of the V850ES/SA2 and V850ES/SA3 share pins, and therefore these interfaces cannot be used at the same time. Select CSI1 or UART0 in advance by using port mode control register 3 (PMC3) and port function control register 3 (PFC3) (refer to 4.3.3 Port 3).
Page 298: Selecting Csi0 Or I C Mode
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.1.2 Selecting CSI0 or I C mode CSI0 and I C of the V850ES/SA2 and V850ES/SA3 share pins, and therefore these interfaces cannot be used at the same time. Select CSI0 or I C in advance by using port mode control register 4 (PMC4) and port function control register 4 (PFC4) (refer to 4.3.5 Port 4).
Page 299: Asynchronous Serial Interface N (Uartn)
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.2 Asynchronous Serial Interface n (UARTn) 12.2.1 Features • Transfer rate: 300 bps to 312.5 kbps (using a dedicated baud rate generator and an internal system clock of 17 MHz) • Full-duplex communications On-chip receive buffer register n (RXBn) On-chip transmit buffer register n (TXBn) •...
Page 300: Configuration
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.2.2 Configuration UARTn is controlled by asynchronous serial interface mode register n (ASIMn), asynchronous serial interface status register n (ASISn), and asynchronous serial interface transmission status register n (ASIFn). Receive data is maintained in receive buffer register n (RXBn), and transmit data is written to transmit buffer register n (TXBn). Figure 12-3 shows the configuration of asynchronous serial interface n (UARTn).
Page 301 CHAPTER 12 SERIAL INTERFACE FUNCTION (8) Transmit buffer register n (TXBn) TXBn is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXBn. The transmission completion interrupt request (INTSTn) is generated synchronized with the completion of transmission of one frame.
Page 302: Control Registers
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.2.3 Control registers (1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register that controls the UARTn transfer operation. This register can be read or written in 8-bit or 1-bit units. Caution When using UARTn, be sure to set the external pins related to UARTn functions to the control mode before setting clock select register n (CKSRn) and baud rate generator control register n (BRGCn), and then set the UARTCAEn bit to 1.
Page 303 CHAPTER 12 SERIAL INTERFACE FUNCTION (2/3) RXEn Enables/disables reception Disables reception Enables reception • Set the RXEn bit to 1 after setting the UARTCAEn bit to 1 at startup. Set the UARTCAEn bit to 0 after setting the RXEn bit to 0 to stop. •...
Page 304 CHAPTER 12 SERIAL INTERFACE FUNCTION (3/3) Specifies character length of 1 frame of transmit/receive data 7 bits 8 bits • To overwrite the CL bit, first clear (0) the TXEn and RXEn bits. Specifies stop bit length of transmit data 1 bit 2 bits •...
Page 305 CHAPTER 12 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status register n (ASISn) The ASISn register, which consists of 3 error flag bits (PEn, FEn and OVEn), indicates the error status when UARTn reception is complete. The status flag, which indicates a reception error, always indicates the status of the error that occurred most recently.
Page 306 CHAPTER 12 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface transmission status register n (ASIFn) The ASIFn register, which consists of 2 status flag bits, indicates the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmit shift register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 307 CHAPTER 12 SERIAL INTERFACE FUNCTION (4) Receive buffer register n (RXBn) The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the receive shift register. When reception is enabled (RXEn bit = 1 in the ASIMn register), receive data is transferred from the receive shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame.
Page 308 CHAPTER 12 SERIAL INTERFACE FUNCTION (5) Transmit buffer register n (TXBn) The TXBn register is an 8-bit buffer register for setting transmit data. When transmission is enabled (TXEn bit = 1 in the ASIMn register), the transmit operation is started by writing data to TXBn register.
Page 309: Interrupt Requests
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.2.4 Interrupt requests The following three types of interrupt requests are generated from UARTn. • Reception error interrupt (INTSREn) • Reception completion interrupt (INTSRn) • Transmission completion interrupt (INTSTn) The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt.
Page 310: Operation
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.2.5 Operation (1) Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 12-4. The character bit length within one data frame, the type of parity, and the stop bit length are specified by asynchronous serial interface mode register n (ASIMn).
Page 311 CHAPTER 12 SERIAL INTERFACE FUNCTION (2) Transmit operation When the UARTCAEn bit is set to 1 in the ASIMn register, a high level is output from the TXDn pin. Then, when the TXEn bit is set to 1 in the ASIMn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmit buffer register n (TXBn).
Page 312 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-5. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 Start TXDn (output) Parity Stop INTSTn (output) (b) Stop bit length: 2 Stop Parity TXDn (output) Start INTSTn (output) Preliminary User’s Manual U15905EJ1V0UD...
Page 313 CHAPTER 12 SERIAL INTERFACE FUNCTION (3) Continuous transmission operation UARTn can write the next transmit data to the TXBn register at the timing that the transmit shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the INTSTn interrupt servicing after the transmission of one data frame.
Page 314 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-6. Continuous Transmission Processing Flow Set registers Write transmit data to TXBn register When reading ASIFn register, TXBFn = 0? Interrupt occurrence Required number of transfers performed? When reading When reading ASIFn register, ASIFn register, TXSFn = 0? TXSFn = 1? Write transmit data to...
Page 315 CHAPTER 12 SERIAL INTERFACE FUNCTION (a) Starting procedure The procedure to start continuous transmission is shown below. Figure 12-7. Continuous Transmission Starting Procedure Start Start Stop Stop TXDn (output) Data (1) Data (2) <1> <2> <3> <4> <5> INTSTn (output) TXBn register Data (1) Data (2)
Page 316 CHAPTER 12 SERIAL INTERFACE FUNCTION (b) Ending procedure The procedure for ending continuous transmission is shown below. Figure 12-8. Continuous Transmission End Procedure Start Start Stop Stop TXDn (output) Data (m − 1) Data (m) <6> <7> <8> <9> <10> <11>...
Page 317 CHAPTER 12 SERIAL INTERFACE FUNCTION (4) Receive operation The awaiting reception state is set by setting the UARTCAEn bit to 1 in the ASIMn register and then setting the RXEn bit to 1 in the ASIMn register. To start the receive operation, first perform start bit detection. The start bit is detected by sampling the RXDn pin.
Page 318 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-9. Asynchronous Serial Interface Reception Completion Interrupt Timing Start RXDn (input) Parity Stop INTSRn (output) RXBn register Cautions 1. Be sure to read receive buffer register n (RXBn) even when a reception error occurs. If RXBn is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely.
Page 319 CHAPTER 12 SERIAL INTERFACE FUNCTION (a) Separation of reception error interrupt A reception error interrupt can be separated from the INTSRn interrupt and generated as the INTSREn interrupt by clearing the ISRMn bit of the ASIMn register to 0. Figure 12-10. When Reception Error Interrupt Is Separated from Reception Completion Interrupt (INTSRn) (ISRMn Bit = 0) (a) No error occurs during reception (b) An error occurs during reception...
Page 320 CHAPTER 12 SERIAL INTERFACE FUNCTION (6) Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used on the transmission and reception sides. (a) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 321 CHAPTER 12 SERIAL INTERFACE FUNCTION (7) Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output base clock (Clock). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 12-13).
Page 322: Dedicated Baud Rate Generator N (Brgn)
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.2.6 Dedicated baud rate generator n (BRGn) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by UARTn. The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 323 CHAPTER 12 SERIAL INTERFACE FUNCTION (2) Serial clock generation A serial clock can be generated according to the settings of the CKSRn and BRGCn registers. The base clock to the 8-bit counter is selected by the TPSn3 to TPSn0 bits of the CKSRn register. The 8-bit counter divisor value can be set by the MDLn7 to MDLn0 bits of the BRGCn register.
Page 324 CHAPTER 12 SERIAL INTERFACE FUNCTION (b) Baud rate generator control register n (BRGCn) The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. This register can be read or written in 8-bit units. Caution If the MDLn7 to MDLn0 bits are to be overwritten, the TXEn and RXEn bits should be set to 0 in the ASIMn register first.
Page 325 CHAPTER 12 SERIAL INTERFACE FUNCTION (c) Baud rate The baud rate is the value obtained by the following formula. Baud rate [bps] × = Frequency [Hz] of base clock (Clock) selected by TPSn3 to TPSn0 bits of CKSRn register. k = Value set by MDLn7 to MDLn0 bits of BRGCn register (k = 8, 9, 10, ..., 255) (d) Baud rate error The baud rate error is obtained by the following formula.
Page 326 CHAPTER 12 SERIAL INTERFACE FUNCTION (3) Baud rate setting example Table 12-3. Baud Rate Generator Setting Data Baud Rate = 17 MHz = 13.5 MHz = 8 MHz = 2 MHz [bps] −0.12 /128 0.16 /512 /512 0.16 /256 0.16 −0.12 0.16 /256...
Page 327 CHAPTER 12 SERIAL INTERFACE FUNCTION (4) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 328 CHAPTER 12 SERIAL INTERFACE FUNCTION Therefore, the transfer destination’s maximum receivable baud rate (BRmax) is as follows. − BRmax (FLmin/11) Brate Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. − × × − × FLmax × ×...
Page 329: Cautions
CHAPTER 12 SERIAL INTERFACE FUNCTION (5) Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock (Clock) longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 330: Clocked Serial Interface N (Csin)
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.3 Clocked Serial Interface n (CSIn) 12.3.1 Features • Transfer rate: Master mode: Maximum 5 Mbps (when internal system clock operates at 10 MHz) Slave mode: Maximum 5 Mbps • Half-duplex communications • Master mode and slave mode can be selected •...
Page 331 CHAPTER 12 SERIAL INTERFACE FUNCTION (7) Serial clock counter The serial clock counter counts serial clocks that are output or input during transmit and receive operations and checks that 8-bit data has been transmitted or received. (8) Interrupt controller The interrupt controller controls whether or not an interrupt request is generated when the serial clock counter has counted eight serial clocks.
Page 332: Control Registers
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.3.3 Control registers (1) Clocked serial interface mode register n (CSIMn) The CSIn register controls the operation of CSIn. This register can be read or written in 8-bit or 1-bit units. Caution To use CSIn, be sure to set the external pins related to the CSIn function to control mode and set the CSICn register.
Page 333 CHAPTER 12 SERIAL INTERFACE FUNCTION After reset: Address: CSIM0: FFFFFD00H, CSIM1: FFFFFD10H, CSIM2: FFFFFD20H Note CSIM3: FFFFFD30H, CSIM4 : FFFFFD40H <7> <6> <0> CSIMn CSIEn TRMDn DIRn CSOTn CSIEn CSIn operation enable/disable specification CSIn operation is disabled (SOn = low level, SCKn = high level) CSIn operation is enabled •...
Page 334 CHAPTER 12 SERIAL INTERFACE FUNCTION (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the transmit operation of CSIn. This register can be read or written in 8-bit units. Caution The CSICn register can only be overwritten after CSIEn is cleared to 0 in the CSIMn register. After reset: Address: CSIC0: FFFFFD01H, CSIC1: FFFFFD11H, CSIC2: FFFFFD21H...
Page 335 CHAPTER 12 SERIAL INTERFACE FUNCTION (a) Transfer rate selection example CKSn2 CKSn1 CKSn0 Baud Rate (bps) 17 MHz 13.5 MHz 10 MHz 8 MHz 4 MHz Operation Operation Operation Operation Operation Setting Setting 5,000,000 4,000,000 2,000,000 prohibited prohibited 4,250,000 3,375,000 2,500,000 2,000,000 1,000,000...
Page 336 CHAPTER 12 SERIAL INTERFACE FUNCTION (3) Serial I/O shift register n (SIOn) The SIOn register is an 8-bit shift register that converts parallel data to serial data. If TRMDn = 0 in the CSIMn register, the transfer is started by reading SIOn. Except when a reset is input, the SIOn register becomes 00H even when the CSIEn bit of the CSIMn register is cleared (0).
Page 337 CHAPTER 12 SERIAL INTERFACE FUNCTION (5) Clocked serial interface transmit buffer register n (SOTBn) The SOTBn register is an 8-bit buffer register for storing transmit data. If transmission/reception mode is set (TRMDn = 1 in the CSIMn register), a transmit operation is started by writing data to the SOTBn register.
Page 338: Operation
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.3.4 Operation (1) Transfer mode CSIn transmits and receives data using three lines: 1 clock line and 2 data lines. In reception-only mode (TRMDn = 0 in the CSIMn register), the transfer is started by reading the SIOn register. To read the value of the SIOn register without starting reception, read the SIOEn register.
Page 339 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-18. Transfer Timing (a) When TRMDn = 1, DIRn = 0, CKPn = 0, and DAPn = 0 SCKn Reg-R/W (Write 55H to SOTBn) SOTBn 55H (transmission data) SIOn CSOTn bit INTCSIn interrupt (AAH) (55H) Remark n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)
Page 340 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-19. Clock Timing (a) When CKPn = 0 and DAPn = 0 SCKn SIn capture SIOn Reg-R/W INTCSIn interrupt CSOTn bit (b) When CKPn = 1 and DAPn = 0 SCKn SIn capture SIOn Reg-R/W INTCSIn interrupt CSOTn bit...
Page 341: Output Pins
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.3.5 Output pins (1) SCKn pin When CSIn operation is disabled (CSIEn = 0), the SCKn pin output state is as follows. CKPn SCKn Pin Output Fixed to high level Fixed to low level Remarks 1. When the CKPn bit is overwritten, the SCKn pin output changes. 2.
Page 342: System Configuration Example
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.3.6 System configuration example CSIn performs 8-bit length data transfer using three signal lines: a serial clock (SCKn), serial input (SIn), and serial output (SOn). This is effective when connecting peripheral I/O that incorporate a conventional clocked serial interface, or a display controller to the V850ES/SA2 or V850ES/SA3 (n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)).
Page 343: I C Bus
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4 I C Bus To use the I C bus function, set the P41/SO0/SDA and P42/SCK0/SCL pins to N-ch open drain output. C has the following two modes. • Operation stopped mode • I C (Inter IC) bus mode (multiple masters supported) (1) Operation stopped mode This mode is used when serial transfers are not performed.
Page 344 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-21. Block Diagram of I Internal bus IIC status register (IICS) MSTS TRC ACKD IIC control register (IICC) Slave address register (SVA) IICE LREL WREL SPIE WTIM ACKE Match CLEAR signal Noise eliminator SO latch IIC shift register (IIC) CL1,...
Page 345 CHAPTER 12 SERIAL INTERFACE FUNCTION A serial bus configuration example is shown below. Figure 12-22. Example of Serial Bus Configuration Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC...
Page 346: Configuration
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.1 Configuration C includes the following hardware. Table 12-5. Configuration of I Item Configuration Registers IIC shift register (IIC) Slave address register (SVA) Control registers IIC control register (IICC) IIC status register (IICS) IIC clock selection register (IICCL) IIC clock expansion register (IICCE) IICC function expansion register (IICX) (1) IIC shift register (IIC)
Page 347 CHAPTER 12 SERIAL INTERFACE FUNCTION (6) Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIIC).
Page 348: C Control Registers
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.2 I C control registers C is controlled by the following registers. • IIC control register (IICC) • IIC status register (IICS) • IIC clock selection register (IICCL) • IIC function expansion register (IICX) The following registers are also used. •...
Page 349 CHAPTER 12 SERIAL INTERFACE FUNCTION (1/4) After reset: Address: FFFFFD82H <7> <6> IICC IICE LREL WREL SPIE WTIM ACKE IICE C operation enable/disable specification Operation stopped. IIC status register (IICS) preset. Internal operation stopped. Operation enabled. Condition for clearing (IICE = 0) Condition for setting (IICE = 1) •...
Page 350 CHAPTER 12 SERIAL INTERFACE FUNCTION (2/4) WREL Wait cancellation control Wait not canceled Wait canceled. This setting is automatically cleared after wait is canceled. Note Condition for clearing (WREL = 0) Condition for setting (WREL = 1) • Automatically cleared after execution •...
Page 351 CHAPTER 12 SERIAL INTERFACE FUNCTION (3/4) ACKE Acknowledge control Acknowledgement disable. Acknowledgement enabled. During the ninth clock period, the SDA line is set to low level. However, ACK is invalid during address transfers and is valid when EXC = 1. Condition for clearing (ACKE = 0)Note Condition for setting (ACKE = 1) •...
Page 352 CHAPTER 12 SERIAL INTERFACE FUNCTION (4/4) Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device s transfer). After the SDA line goes to low level, either set the SCL line to high level or wait until it goes to high level.
Page 353 CHAPTER 12 SERIAL INTERFACE FUNCTION (2) IIC status register (IICS) The IICS register is used to indicate the status of I The IICS register can be set by an 8-bit or 1-bit memory manipulation instruction. IICS is a read-only register. RESET input clears the IICS register to 00H.
Page 354 CHAPTER 12 SERIAL INTERFACE FUNCTION (2/3) Detection of matching addresses Addresses do not match. Addresses match. Condition for clearing (COI = 0) Condition for setting (COI = 1) • When a start condition is detected • When the received address matches the local •...
Page 355 CHAPTER 12 SERIAL INTERFACE FUNCTION (3/3) ACKD Detection of acknowledge Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKD = 0) Condition for setting (ACKD = 1) • After the SDA line is set to low level at the rising •...
Page 356 CHAPTER 12 SERIAL INTERFACE FUNCTION (3) IIC clock selection register (IICCL) The IICCL register is used to set the transfer clock for I The IICCL register can be set by an 8-bit or 1-bit memory manipulation instruction. Set the SMC, CL1, and CL0 bits in combination with the CLX bit of the IIC function expansion register (IICX) (see Table 12-6 Selection Clock Setting).
Page 357 CHAPTER 12 SERIAL INTERFACE FUNCTION (4) IIC function expansion register (IICX) The IICX register is used to set the function expansion of I C (valid only in high-speed mode). The IICX register is set by an 8-bit or 1-bit memory manipulation instruction. Set the CLX bit in combination with the SMC, CL1, and CL0 bits of the IIC clock selection register (IICCL) (see Table 12-6 Transfer Clock Setting).
Page 358 CHAPTER 12 SERIAL INTERFACE FUNCTION Table 12-6. Transfer Clock Setting IICX IICCL Transfer Clock Settable Main Clock Operation Mode Frequency (f ) Range Bit 0 Bit 3 Bit1 Bit0 4.0 MHz to 8.38 MHz Normal mode (SMC = 0) /172 8.38 MHz to 16.76 MHz 4.19 MHz to 8.38 MHz Note...
Page 359: I C Bus Mode Functions
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.3 C bus mode functions (1) Pin configuration The serial clock pin (SCL) and serial data bus pin (SDA) are configured as follows. SCL ..... This pin is used for serial clock I/O. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA .....
Page 360: C Bus Definitions And Control Methods
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.4 I C bus definitions and control methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. The transfer timing for the “start condition”, “data”, and “stop condition” output via the I C bus’s serial data bus is shown below.
Page 361 CHAPTER 12 SERIAL INTERFACE FUNCTION (2) Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines.
Page 362 CHAPTER 12 SERIAL INTERFACE FUNCTION (3) Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 363 CHAPTER 12 SERIAL INTERFACE FUNCTION (4) Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data.
Page 364 CHAPTER 12 SERIAL INTERFACE FUNCTION (5) Stop condition When the SCL pin is at high level, changing the SDA pin from low level to high level generates a stop condition. A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed.
Page 365 CHAPTER 12 SERIAL INTERFACE FUNCTION (6) Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL pin to low level notifies the communication partner of the wait status. When the wait status has been canceled for both the master and slave devices, the next data transfer can begin.
Page 366 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-31. Wait Signal (2/2) (2) When master and slave devices both have a nine-clock wait (Master: transmission, slave: reception, and ACKE = 1) Master and slave both wait Master after output of ninth clock. IIC data write (cancel wait) Slave FFH is written to IIC or WREL is set to 1.
Page 367: C Interrupt Request (Intiic)
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.5 I C interrupt request (INTIIC) The following shows the value of the IIC status register (IICS) at the INTIIC interrupt request generation timing and at the INTIIC interrupt timing. (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 368 CHAPTER 12 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIM = 0 STT = 1 SPT = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆7 L1: IICS = 10XXX110B...
Page 369 CHAPTER 12 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIM = 0 SPT = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 ∆5 L1: IICS = 1010X110B L2: IICS = 1010X000B L3: IICS = 1010X000B (WTIM = 1) L4: IICS = 1010XX00B...
Page 370 CHAPTER 12 SERIAL INTERFACE FUNCTION (2) Slave device operation (when receiving slave address data (matches with SVA)) (a) Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIM = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICS = 0001X110B L2: IICS = 0001X000B...
Page 371 CHAPTER 12 SERIAL INTERFACE FUNCTION (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, matches with SVA) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICS = 0001X110B L2: IICS = 0001X000B...
Page 372 CHAPTER 12 SERIAL INTERFACE FUNCTION (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICS = 0001X110B L2: IICS = 0001X000B...
Page 373 CHAPTER 12 SERIAL INTERFACE FUNCTION (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, does not match with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4...
Page 374 CHAPTER 12 SERIAL INTERFACE FUNCTION (3) Slave device operation (when receiving extension code) (a) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIM = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICS = 0010X010B L2: IICS = 0010X000B L3: IICS = 0010X000B ∆...
Page 375 CHAPTER 12 SERIAL INTERFACE FUNCTION (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, matches with SVA) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICS = 0010X010B L2: IICS = 0010X000B...
Page 376 CHAPTER 12 SERIAL INTERFACE FUNCTION (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆5 L1: IICS = 0010X010B L2: IICS = 0010X000B...
Page 377 CHAPTER 12 SERIAL INTERFACE FUNCTION (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM = 0 (after restart, does not match with address (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ∆4...
Page 378 CHAPTER 12 SERIAL INTERFACE FUNCTION (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 ∆1 ∆ 1: IICS = 00000001B Remark ∆: Generated only when SPIE = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data <1>...
Page 379 CHAPTER 12 SERIAL INTERFACE FUNCTION (b) When arbitration loss occurs during transmission of extension code <1> When WTIM = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆4 L1: IICS = 0110X010B (Example: When ALD is read during interrupt servicing) L2: IICS = 0010X000B L3: IICS = 0010X000B ∆...
Page 380 CHAPTER 12 SERIAL INTERFACE FUNCTION (6) Operation when arbitration loss occurs (no communication after arbitration loss) (a) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ∆2 L1: IICS = 01000110B (Example: When ALD is read during interrupt servicing) ∆...
Page 381 CHAPTER 12 SERIAL INTERFACE FUNCTION (c) When arbitration loss occurs during data transfer <1> When WTIM = 0 AD6 to AD0 D7 to D0 D7 to D0 ∆3 L1: IICS = 10001110B L2: IICS = 01000000B (Example: When ALD is read during interrupt servicing) ∆...
Page 382 CHAPTER 12 SERIAL INTERFACE FUNCTION (d) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with SVA) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 ∆3 L1: IICS = 1000X110B L2: IICS = 01000110B (Example: When ALD is read during interrupt servicing) ∆...
Page 383 CHAPTER 12 SERIAL INTERFACE FUNCTION (e) When loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn ∆2 L1: IICS = 1000X110B ∆ 2: IICS = 01000001B Remark L: Always generated ∆: Generated only when SPIE = 1 X: Don’t care Dn = D6 to D0 (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition...
Page 384 CHAPTER 12 SERIAL INTERFACE FUNCTION (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIM = 1 STT = 1 ↓ AD6 to AD0 D7 to D0 ∆3 L1: IICS = 1000X110B L2: IICS = 1000XX00B ∆...
Page 385: Interrupt Request (Intiic) Generation Timing And Wait Control
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.6 Interrupt request (INTIIC) generation timing and wait control The setting of bit 3 (WTIM) of the IIC control register (IICC) determines the timing by which INTIIC is generated and the corresponding wait control, as shown below. Table 12-7.
Page 386: Address Match Detection Method
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.7 Address match detection method When in I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. An interrupt request (INTIIC) occurs when a local address has been set to the slave address register (SVA) and when the address set to SVA matches the slave address sent by the master device, or when an extension code has been received.
Page 387: Arbitration
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.10 Arbitration When several master devices simultaneously output a start condition (when STT is set to 1 before STD is set to Note ), communication among the master devices is performed as the number of clocks is adjusted until the data differs.
Page 388 CHAPTER 12 SERIAL INTERFACE FUNCTION Table 12-9. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing During address transmission At falling edge of eighth or ninth clock following Note 1 byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...
Page 389: Wakeup Function
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.11 Wakeup function The I C bus slave function is a function that generates an interrupt request (INTIIC) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match.
Page 390: Communication Reservation
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.12 Communication reservation To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
Page 391 CHAPTER 12 SERIAL INTERFACE FUNCTION The communication reservation timing is shown below. Figure 12-33. Communication Reservation Timing Write to Program processing Set SPD Communication Hardware processing reservation and INTIIC Output by master with bus access IIC: IIC shift register STT: Bit 1 of IIC control register (IICC) STD: Bit 1 of IIC status register (IICS) SPD: Bit 0 of IIC status register (IICS)
Page 392 CHAPTER 12 SERIAL INTERFACE FUNCTION The communication reservation flow chart is illustrated below. Figure 12-35. Communication Reservation Flow Chart ; Sets STT flag (communication reservation). SET1 STT Define communication ; Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM). ;...
Page 393: Cautions
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.13 Cautions After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
Page 394: Communication Operations
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.14 Communication operations (1) Master operations The following is a flow chart of the master operations. Figure 12-36. Master Operation Flow Chart START ← ××H IICCL Select transfer clock. ← ××H IICC IICE = SPIE = WTIM = 1 ;...
Page 395 CHAPTER 12 SERIAL INTERFACE FUNCTION (2) Slave operation An example of slave operation is shown below. Figure 12-37. Slave Operation Flow Chart START ← ××H IICC IICE = 1 INTIIC = 1? EXC = 1? Communicate? COI = 1? LREL = 1 TRC = 1? WTIM = 0 ACKE = 1...
Page 396: Timing Of Data Communication
CHAPTER 12 SERIAL INTERFACE FUNCTION 12.4.15 Timing of data communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC bit (bit 3 of the IIC status register (IICS)), which specifies the data transfer direction and then starts serial communication with the slave device.
Page 397 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-38. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← address data ACKD WTIM ACKE MSTS WREL INTIIC...
Page 398 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-38. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← data data ACKD WTIM ACKE MSTS WREL INTIIC Transmit Transfer lines Processing by slave device...
Page 399 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-38. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← data address ACKD WTIM ACKE MSTS WREL INTIIC (When SPIE = 1) Transmit...
Page 400 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-39. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← address FFH Note ACKD WTIM ACKE MSTS WREL...
Page 401 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-39. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IIC ← FFH Note IIC ← FFH Note ACKD WTIM ACKE MSTS Note...
Page 402 CHAPTER 12 SERIAL INTERFACE FUNCTION Figure 12-39. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← FFH Note address ACKD WTIM ACKE MSTS Note WREL INTIIC...
Page 403: Chapter 13 Dma Functions (Dma Controller)
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) The V850ES/SA2 and V850ES/SA3 include a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA requests issued by the on-chip peripheral I/O (serial interface, real-time pulse unit, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM or external memory).
Page 404: Configuration
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.2 Configuration On-chip Internal RAM peripheral I/O Internal bus On-chip peripheral I/O bus DMA source address Data Address register n (DSAnH/DSAnL) control control DMA destination address register n (DDAnH/DDAnL) DMA transfer count Count register n (DBCn) control DMA channel control register n (DCHCn)
Page 405: Control Registers
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.3 Control Registers 13.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA source addresses (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAnH and DSAnL.
Page 406: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA destination address (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL.
Page 407: Dma Byte Count Registers 0 To 3 (Dbc0 To Dbc3)
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the byte transfer count for DMA channels n (n = 0 to 3). They store the remaining transfer count during DMA transfer.
Page 408: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers cannot be accessed during DMA operation. They can be read or written in 16-bit units.
Page 409: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bit 1 is write-only. If bit 1 is read, the read value is always 0.) After reset: Address:...
Page 410: Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3)
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors. These registers can be read or written in 8-bit or 1-bit units.
Page 411 CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) Table 13-1. DMA Start Factor IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source DMA request by interrupt disabled INTWDTM INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTRTC INTCC00 INTCC01 INTOVF0 INTCC10 INTCC11 INTOVF1 INTTM2 INTTM3 INTTM4 INTTM5...
Page 412: Dma Bus States
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.4 DMA Bus States 13.4.1 Types of bus states The DMAC bus states consist of the following 10 states. (1) TI state The TI state is an idle state, during which no access request is issued. The DMA request signals are sampled at the rising edge of the CLKOUT signal.
Page 413: Dmac Bus Cycle State Transition
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.4.2 DMAC bus cycle state transition Except for the block transfer mode, each time the processing for a DMA transfer is completed, the bus mastership is released. Figure 13-1. DMAC Bus Cycle (Two-Cycle Transfer) State Transition T1RI T2RI T1WI...
Page 414: Transfer Mode
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.5 Transfer Mode 13.5.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 415: Transfer Object
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.7 Transfer Object 13.7.1 Transfer type and transfer object Table 13-2 shows the relationship between transfer type and transfer object (√: Transfer enabled, ×: Transfer disabled). Table 13-2. Relationship Between Transfer Type and Transfer Object Destination Internal ROM On-Chip...
Page 416: Dma Channel Priorities
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.8 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 These priorities are valid in the TI state only. In the block transfer mode, the channel used for transfer is never switched.
Page 417: Precautions
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER) 13.11 Precautions (1) Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA objects (external memory, internal RAM, or peripheral I/O) during DMA transfer. (2) Transfer of misaligned data DMA transfer of 16-bit bus width misaligned data is not supported.
Page 418: Chapter 14 Interrupt/Exception Processing Function
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/SA2 and V850ES/SA3 are provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 38 to 40 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 419 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 14-1. Interrupt/Exception Source List (1/2) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register − − Reset Interrupt RESET RESET pin input 0000H 00000000H Undefined WDT overflow (WDTRES) −...
Page 420 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 14-1. Interrupt/Exception Source List (2/2) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register INTSRE1 UART1 reception error UART1 0220H 00000220H nextPC SREIC1 Maskable Interrupt INTSR1 UART1 reception completion UART1 0230H 00000230H nextPC...
Page 421: Non-Maskable Interrupts
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts. This product has the following two non-maskable interrupts.
Page 422 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-1. Non-Maskable Interrupt Request Acknowledgement Operation (2/2) (b) Non-maskable interrupt request generated during non-maskable interrupt servicing Non-maskable Non-maskable interrupt request generated during non-maskable interrupt servicing interrupt being INTWDT serviced • NMI request generated during NMI servicing •...
Page 423: Operation
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.2.1 Operation If a non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 424: Restore
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.2.2 Restore (1) From NMI Execution is restored from the NMI by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 425: Np Flag
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is under execution. This flag is set when a non-maskable interrupt request has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. After reset: 00000020H ID SAT CY OV...
Page 426 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register that specifies detection of the rising edge of the NMI pin. This register can be read or written in 8-bit or 1-bit units. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected.
Page 427: Maskable Interrupts
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850ES/SA2 and V850ES/SA3 have 38 to 40 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 428 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-4. Maskable Interrupt Servicing INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 429: Restore
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1>...
Page 430: Priorities Of Maskable Interrupts
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.3 Priorities of maskable interrupts The V850ES/SA2 and V850ES/SA3 provide multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 431 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-6. Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 432 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-6. Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 433 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-7. Example of Servicing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 434: Interrupt Control Register (Xxicn)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. After reset: Address: FFFFF110H to FFFFF15AH...
Page 435 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 14-3. Interrupt Control Register (xxICn) Address Register <7> <6> FFFFF110H WDTIC1 WDTIF WDTMK WDTPR2 WDTPR1 WDTPR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2 PPR22 PPR21 PPR20...
Page 436: Interrupt Mask Registers 0 To 2 (Imr0 To Imr2)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR2 registers is equivalent to the xxMKn bit of the xxICn register. The IMRm register can be read or written in 16-bit units (m = 0 to 2).
Page 437: In-Service Priority Register (Ispr)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 438: Watchdog Timer Mode Register (Wdtm)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.3.8 Watchdog timer mode register (WDTM) This register is a special register and can be written only in a specific sequence. To generate a maskable interrupt (INTWDT), clear the WDTM4 bit of this register to 0. This register can be read or written in 8-bit or 1-bit units (for details, refer to CHAPTER 9 WATCHDOG TIMER FUNCTION).
Page 439 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt rising edge specification register 0 (INTR0) This is an 8-bit register that specifies detection of the rising edge of the INTP0 to INTP4 pins. This register can be read or written in 8-bit or 1-bit units. Caution When the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected.
Page 440 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt rising edge specification register 9 (INTR9) This is an 8-bit register that specifies detection of the rising edge of the INTP5 and INTP6 pins. This register can be read or written in 16-bit units. When the lower 8 bits of the INTR9 register are used as INTR9L register, however, it can be read or written in 8-bit or 1-bit units.
Page 441: Software Exception
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 14.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 442: Restore
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. <2>...
Page 443: Exception Status Flag (Ep)
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.4.3 Exception status flag (EP) The EP flag is bit 6 of the PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H NP EP...
Page 444: Exception Trap
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/SA2 and V850ES/SA3, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
Page 445 CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 14-10. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC Restored PC DBPSW PSW.NP PSW.EP PSW.ID 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 446: Interrupt Acknowledge Time Of Cpu
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.6 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 5 clocks minimum. To input interrupt requests successively, input the next interrupt at least 5 clocks after the preceding interrupt. •...
Page 447: Periods In Which Interrupts Are Not Acknowledged By Cpu
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION 14.7 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows.
Page 448: Chapter 15 Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 15-1. Table 15-1.
Page 449 CHAPTER 15 STANDBY FUNCTION Figure 15-1. Status Transition Normal operation mode (operation with main clock) End of oscillation End of oscillation stabilization time count stabilization time count Note 1 Setting of HALT mode Interrupt request End of oscillation stabilization time count Wait for stabilization Wait for stabilization of oscillation...
Page 450 CHAPTER 15 STANDBY FUNCTION Figure 15-2. Status Transition (During Subclock Operation) Normal operation mode Wait for stabilization of oscillation (operation with main clock) End of oscillation stabilization time count Setting of subclock Setting of normal operation operation RESET pin input Subclock operation mode Setting of IDLE Note 1...
Page 451: Halt Mode
CHAPTER 15 STANDBY FUNCTION 15.2 HALT Mode 15.2.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues.
Page 452 CHAPTER 15 STANDBY FUNCTION (2) Releasing HALT mode by RESET pin input The same operation as the normal reset operation is performed. Table 15-3. Operation Status in HALT Mode Setting of HALT Mode Operation Status Item When Subclock Is Not Used When Subclock Is Used Main clock oscillator Oscillation enabled...
Page 453: Idle Mode
CHAPTER 15 STANDBY FUNCTION 15.3 IDLE Mode 15.3.1 Setting and operation status The IDLE mode is set by clearing the PSM bit of the power save mode register (PSMR) to 0 and setting the STP bit of the power save control register (PSC) to 1 in the normal operation mode. In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral functions stops.
Page 454 CHAPTER 15 STANDBY FUNCTION (2) Releasing IDLE mode by RESET pin input The same operation as the normal reset operation is performed. Table 15-5. Operation Status in IDLE Mode Setting of IDLE Mode Operation Status Item When Subclock Is Not Used When Subclock Is Used Main clock oscillator Oscillation enabled...
Page 455: Software Stop Mode
CHAPTER 15 STANDBY FUNCTION 15.4 Software STOP Mode 15.4.1 Setting and operation status The software STOP mode is set when the PSM bit of the PSMR register is set to 1 and the STP bit of the PSC register is set to 1 in the normal operation mode. In the software STOP mode, the subclock oscillator continues operating but the main clock oscillator stops.
Page 456 CHAPTER 15 STANDBY FUNCTION (2) Releasing software STOP mode by RESET pin input The same operation as the normal reset operation is performed. Table 15-7. Operation Status in Software STOP Mode Setting of Software STOP Mode Operation Status Item When Subclock Is Not Used When Subclock Is Used Main clock oscillator Stops operation...
Page 457: Securing Oscillation Stabilization Time
CHAPTER 15 STANDBY FUNCTION 15.5 Securing Oscillation Stabilization Time When the software STOP mode is released, only the oscillation stabilization time set by the OSTS register elapses. If the software STOP mode has been released by RESET pin input, however, the reset value of the OSTS register, elapses.
Page 458: Subclock Operation Mode
CHAPTER 15 STANDBY FUNCTION 15.6 Subclock Operation Mode 15.6.1 Setting and operation status The subclock operation mode is set when the CK3 bit of the processor clock control register (PCC) is set to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock.
Page 459 CHAPTER 15 STANDBY FUNCTION Table 15-8. Operation Status in Subclock Operation Mode Setting of Subclock Operation Mode Operation Status Item When Main Clock Is Oscillating When Main Clock Is Stopped Subclock oscillator Oscillation enabled Operable Operable Interrupt controller Operable ROM correction Operable 16-bit timer/event counters (TM0, TM1) Stops operation...
Page 460: Sub-Idle Mode
CHAPTER 15 STANDBY FUNCTION 15.7 Sub-IDLE Mode 15.7.1 Setting and operation status The sub-IDLE mode is set when the PSM bit of the power save mode register (PSMR) is cleared to 0 and the STP bit of the power save control register (PSC) is set to 1 in the subclock operation mode. In this mode, the clock oscillator continues operation but clock supply to the CPU and the other on-chip peripheral functions is stopped.
Page 461 CHAPTER 15 STANDBY FUNCTION (2) Releasing sub-IDLE mode by RESET pin input The same operation as the normal reset operation is performed. Table 15-10. Operation Status in Sub-IDLE Mode Setting of Sub-IDLE Mode Operation Status Item When Main Clock Is Oscillating When Main Clock Is Stopped Subclock oscillator Oscillation enabled...
Page 462: Backup Mode
CHAPTER 15 STANDBY FUNCTION 15.8 Backup Mode The V850ES/SA2 and V850ES/SA3 can be placed in a backup mode by stopping power supply other than the backup power supply (V ) in the STOP mode. DDBU The backup power supply supplies power only to the subclock oscillator, real-time counter, and internal RAM, as shown in Figure 15-4.
Page 463: Setting And Operation Status
CHAPTER 15 STANDBY FUNCTION 15.8.1 Setting and operation status The backup mode is set by stopping power supply (0 V) other than the backup power supplies (V and V DDBU SSBU after inputting a low level to the RESET pin in the software STOP mode. The backup power supply is dedicated to the subclock oscillator, real-time counter, and internal RAM.
Page 464: Releasing Backup Mode
CHAPTER 15 STANDBY FUNCTION 15.8.2 Releasing backup mode The backup mode can be released by inputting a high level to the RESET pin after restarting the power supplies other than the backup power supply (V and V DDBU SSBU When the backup mode has been released, the normal operation mode is set after the lapse of the oscillation stabilization time.
Page 465 CHAPTER 15 STANDBY FUNCTION Table 15-11. Operation Status in Backup Mode Item Operation Status Main clock oscillator Power supply stopped Subclock oscillator Oscillation enable Power supply stopped Power supply stopped Interrupt controller Power supply stopped ROM correction Power supply stopped 16-bit timer/event counters (TM0, TM1) Power supply stopped 8-bit timer/event counters (TM2 to TM5)
Page 466: Control Registers
CHAPTER 15 STANDBY FUNCTION 15.9 Control Registers (1) Power save control register (PSC) This is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the software STOP mode. The PSC register is a special register (refer to 3.4.8 Special registers). Data can be written to this register only in a specific sequence so that its contents are not rewritten by mistake due to a program hang-up.
Page 467: Chapter 16 Reset Function
CHAPTER 16 RESET FUNCTION 16.1 Overview The following reset functions are available. • Reset function by RESET pin input • Reset function by WDT overflow (WDTRES) If the RESET pin goes high, the reset status is released, and the CPU starts executing the program. Initialize the contents of each register in the program as necessary.
Page 468: Operation
CHAPTER 16 RESET FUNCTION 16.3 Operation The system is reset, initializing each hardware unit, when a low level is input to the RESET pin by WDT overflow (WDTRES). While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power consumption of the system can be reduced.
Page 469 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status on RESET Pin Input Item During Reset After Reset Main clock oscillator (f Oscillation stops (f = 0 level). Oscillation starts Note 1 Subclock oscillator (f Oscillation can continue without effect from reset Peripheral clock (f to f /512),...
Page 470 CHAPTER 16 RESET FUNCTION Figure 16-2. Hardware Status on RESET Input Initialized to f /8 operation RESET Analog delay Analog Analog delay Analog (eliminated as noise) delay (eliminated as noise) delay Internal system reset signal Oscillation stabilization time count Overflow of timer for oscillation stabilization Figure 16-3.
Page 471: Chapter 17 Rom Correction Function
CHAPTER 17 ROM CORRECTION FUNCTION 17.1 Overview The ROM correction function is used to replace part of the program in the mask ROM with the program of an external RAM or the internal RAM. By using this function, instruction bugs found in the mask ROM can be corrected at up to four places. Figure 17-1.
Page 472: Control Registers
CHAPTER 17 ROM CORRECTION FUNCTION 17.2 Control Registers 17.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3) These registers are used to set the first address (correction address) of the instruction to be corrected in the ROM. The program can be corrected at up to four places because four correction address registers (CORADn) are provided (n = 0 to 3).
Page 473: Correction Control Register (Corcn)
CHAPTER 17 ROM CORRECTION FUNCTION 17.2.2 Correction control register (CORCN) This register disables or enables the correction operation of correction address register n (CORADn) (n = 0 to 3). Each channel can be enabled or disabled by this register. This register is set by using an 8-bit or 1-bit memory manipulation instruction. After reset: Address: FFFFF880H...
Page 474 CHAPTER 17 ROM CORRECTION FUNCTION Figure 17-2. ROM Correction Operation and Program Flow Reset & start Initialize microcontroller Read data for setting ROM correction from external memory Set CORADn register Set CORCN register Fetch address = CORADn Change fetch code to DBTRAP instruction Execute fetch code DBTRAP instruction...
Page 475: Chapter 18 Flash Memory
CHAPTER 18 FLASH MEMORY The following products are the flash memory versions of the V850ES/SA2 and V850ES/SA3. Caution There are differences in the amount of noise tolerance and noise radiation between flash memory versions and mask ROM versions. When considering changing from a flash memory version to a mask ROM version during the process from experimental manufacturing to mass production, make sure to sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
Page 476: Erasure Unit
CHAPTER 18 FLASH MEMORY 18.1.1 Erasure unit The erasure units for 256 KB flash memory versions are shown below. (1) Chip erase The area of xx000000H to xx03FFFFH can be erased at the same time. (2) Block erase Erasure can be performed in block units (60 KB × 4, 4 KB × 4). Block 0: 4 KB Block 1: 4 KB Block 2: 4 KB...
Page 477: Writing With Flash Programmer
CHAPTER 18 FLASH MEMORY 18.2 Writing with Flash Programmer Writing can be performed either on-board or off-board with the dedicated flash programmer. (1) On-board programming The contents of the flash memory are rewritten after the V850ES/SA2 or V850ES/SA3 is mounted on the target system.
Page 478: Communication Mode
CHAPTER 18 FLASH MEMORY 18.4 Communication Mode The communication between the dedicated flash programmer and the V850ES/SA2 or V850ES/SA3 is performed by serial communication using UART0 or CSI0 of the V850ES/SA2, V850ES/SA3. (1) UART0 Transfer rate: 4,800 to 76,800 bps Figure 18-2.
Page 479 CHAPTER 18 FLASH MEMORY (3) CSI0 + + + + HS Serial clock: Up to 1 MHz (MSB first) Figure 18-4. Communication with Dedicated Flash Programmer (CSI0 + + + + HS) FLMD0, FLMD0, FLMD1 FLMD1 RESET RESET Dedicated flash V850ES/SA2, programmer V850ES/SA3...
Page 480: Pin Connection
CHAPTER 18 FLASH MEMORY 18.5 Pin Connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode.
Page 481 CHAPTER 18 FLASH MEMORY (1) Conflict of signals When the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status.
Page 482 CHAPTER 18 FLASH MEMORY (2) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction.
Page 483: Reset Pin
CHAPTER 18 FLASH MEMORY 18.5.3 RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 484: Programming Method
CHAPTER 18 FLASH MEMORY 18.6 Programming Method 18.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 18-9. Procedure for Manipulating Flash Memory Start Switch to flash memory Supplies RESET pulse programming mode Select communication system Manipulate flash memory End? Preliminary User’s Manual U15905EJ1V0UD...
Page 485: Flash Memory Programming Mode
CHAPTER 18 FLASH MEMORY 18.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850ES/SA2 or V850ES/SA3 to the flash memory programming mode. When switching modes, set the FLMD0 and FLMD1 pins before releasing reset.
Page 486: Selection Of Communication Mode
CHAPTER 18 FLASH MEMORY 18.6.3 Selection of communication mode In the V850ES/SA2 and V850ES/SA3, the communication mode is selected by inputting pulses (16 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
Page 487 CHAPTER 18 FLASH MEMORY The following shows the commands for flash memory control of the V850ES/SA2 and V850ES/SA3. All of these commands are issued from the dedicated flash programmer, and the V850ES/SA2 and V850ES/SA3 perform the various processing corresponding to the commands. Table 18-4.
Page 488: Chapter 19 Electrical Specifications (Target)
CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Absolute maximum ratings (T = 25°C, V = 0 V) Parameter Symbol Conditions Ratings Unit −0.5 to +3.6 Supply voltage −0.5 to +3.6 −0.5 to +3.6 −0.5 to +3.6 DDBU −0.5 to +0.5 −0.5 to +0.5 −0.5 to +0.5 SSBU −0.5 to EV...
Page 489 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Capacitance (T = 25°C, V = AV = EV = AV = EV = 0 V) DDBU SSBU Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance = 1 MHz Unmeasured pins returned to 0 V I/O capacitance Output capacitance Operating conditions (V...
Page 490 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Recommended oscillator = − − − − 40 to +85°C) (1) Main clock oscillator (T (a) Connection of ceramic resonator or crystal resonator Parameter Symbol Conditions MIN. TYP. MAX. Unit Oscillation frequency = 2.2 to 2.7 V Oscillation stabilization time Upon reset release Upon STOP mode release...
Page 491 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) = − − − − 40 to +85°C) (2) Subclock oscillator (T (a) Connection of crystal resonator Parameter Symbol Conditions MIN. TYP. MAX. Unit Oscillation frequency 32.768 Oscillation stabilization time Caution Ensure that the duty of the oscillation waveform is between 45% and 55%. Remarks 1.
Page 492 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) DC characteristics = − − − − 40 to +85°C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V) (1/2) DDBU SSBU Parameter Symbol Conditions MIN. TYP.
Page 493 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) = − − − − 40 to +85°C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V) (2/2) DDBU SSBU Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Normal operation...
Page 494 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Data retention characteristics = − − − − 40 to +85°C, V (1) In STOP mode (T = AV = EV = 0 V) SSBU Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage STOP mode DDDR1 µ...
Page 495 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) = − − − − 40 to +85° ° ° ° C, V (2) In backup mode (T = AV = EV = AV = EV = 0 V) SSBU Parameter Symbol Conditions MIN. TYP. MAX.
Page 496 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) AC characteristics AC test input measurement points (V , AV , EV DDBU Measurement points AC test output measurement points Measurement points Load conditions (Device under test) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, reduce the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 497 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Bus timing (1) Multiplexed bus mode (a) CLKOUT asynchronous: In multiplexed bus mode = − − − − 40 to +85°C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V, C = 50 pF) DDBU...
Page 498 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) (b) CLKOUT synchronous: In multiplexed bus mode = − − − − 40 to +85°C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V, C = 50 pF) DDBU SSBU Parameter...
Page 499 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Read cycle (CLKOUT synchronous/asynchronous, 1 wait): In multiplexed bus mode CLKOUT (output) <29> A16 to A23 (output), A0 to A15 (output) <4> <33> <34> <30> Hi-Z AD0 to AD15 (I/O) Address Data <31> <31> <2> <1>...
Page 500 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Write cycle (CLKOUT synchronous/asynchronous, 1 wait): In multiplexed bus mode CLKOUT (output) <29> A16 to A23 (output), A0 to A15 (output) <35> AD0 to AD15 (I/O) Address Data <31> <31> <1> <2> ASTB (output) <12> <9>...
Page 501 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Bus hold: In multiplexed bus mode CLKOUT (output) <38> <38> <39> <24> HLDRQ (input) <41> <41> <27> <28> HLDAK (output) <25> <26> <40> Hi-Z A16 to A23 (output) A0 to A15 (output) Data Hi-Z AD0 to AD15 (I/O) Hi-Z ASTB (output) Hi-Z...
Page 502 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) (2) In separate bus mode (a) Read cycle (CLKOUT asynchronous): In separate bus mode = − − − − 40 to +85° ° ° ° C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V, C...
Page 503 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) (c) Write cycle (CLKOUT asynchronous): In separate bus mode = − − − − 40 to +85° ° ° ° C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V, C = 50 pF) DDBU...
Page 504 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Read cycle (CLKOUT asynchronous, 1 wait): In separate bus mode CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <43> <47> Hi-Z Hi-Z AD0 to AD15 (I/O) <46> <42> <45> <44> RD (output) <51> <49>...
Page 505 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Read cycle (CLKOUT synchronous, 1 wait): In separate bus mode CLKOUT (output) <56> <56> CS0 to CS3 (output) A0 to A23 (output) <57> <58> Hi-Z Hi-Z AD0 to AD15 (I/O) <59> <59> RD (output) <60> <61>...
Page 506 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Write cycle (CLKOUT asynchronous, 1 wait): In separate bus mode CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <63> <68> Hi-Z Hi-Z AD0 to AD15 (I/O) <65> <67> <62> <66> <64> WR0, WR1 (output) <72>...
Page 507 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Write cycle (CLKOUT synchronous, 1 wait): In separate bus mode CLKOUT (output) <77> <77> CS0 to CS3 (output) A0 to A23 (output) <78> <78> Hi-Z Hi-Z AD0 to AD15 (I/O) <79> <79> WR0, WR1 (output) <80>...
Page 508 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Reset/interrupt timing = − − − − 40 to +85°C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V, C = 50 pF) DDBU SSBU Parameter Symbol Conditions MIN.
Page 509 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) Timer timing = − − − − 40 to +85°C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V, C = 50 pF) DDBU SSBU Parameter Symbol Conditions MIN.
Page 510 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) CSI timing (1) Master mode = − − − − 40 to +85°C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V, C = 50 pF) DDBU SSBU Parameter...
Page 511 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) C bus mode ( µ µ µ µ PD703201Y, 703204Y, 70F3201Y, 70F3204Y only) = − − − − 40 to +85°C, V = AV = EV = 2.2 to 2.7 V, V = AV = EV = 0 V) DDBU SSBU...
Page 512 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) C bus mode ( µ µ µ µ PD703201Y, 703204Y, 70F3201Y, 70F3204Y only) <95> <96> SCL (I/O) <97> <101> <100> <98> <99> <102> <94> <103> <94> SDA (I/O) <93> <100> <101> Stop Start Restart Stop condition condition condition...
Page 513 CHAPTER 19 ELECTRICAL SPECIFICATIONS (TARGET) D/A converter = − − − − 40 to +85° ° ° ° C, V = AV = AV = 2.2 to 2.7 V, AV = 0 V, C = 50 pF) REF1 Parameter Symbol Conditions MIN.
Page 514: Chapter 20 Package Drawings
CHAPTER 20 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) Package drawing not available (resin thickness: 1.0 mm, 0.5-mm pitch) Preliminary User’s Manual U15905EJ1V0UD...
Page 515 CHAPTER 20 PACKAGE DRAWINGS 121-PIN PLASTIC FBGA (12x12) N M L K J H G F E D C B A INDEX MARK φ φ ITEM MILLIMETERS 12.00±0.10 12.00±0.10 0.20 1.48±0.10 0.35±0.06 1.13 0.80 0.50 +0.05 −0.10 0.08 0.10 0.20 1.20 1.20 P121F1-80-EA6...
Page 516 [MEMO] Preliminary User’s Manual U15905EJ1V0UD...
Page 517 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.
Page 518 X-ON Electronics Largest Supplier of Electrical and Electronic Components Click to view similar products for category: 8-bit Microcontrollers - MCU Click to view products by manufacturer: Renesas Other Similar products are found below : CY8C20524-12PVXIT CY8C28433-24PVXIT MB95F012KPFT-G-SNE2 MB95F013KPMC-G-SNE2 MB95F263KPF-G-SNE2 MB95F264KPFT-G-SNE2 MB95F398KPMC-G-SNE2 MB95F478KPMC2-G-SNE2 MB95F562KPF-G-SNE2 MB95F564KPF-G-SNE2 MB95F634KPMC-G-SNE2 MB95F636KWQN-G-SNE1 MB95F696KPMC-G-SNE2 MB95F698KPMC1-G-SNE2 MB95F698KPMC2-G- SNE2 MB95F698KPMC-G-SNE2 MB95F818KPMC1-G-SNE2 MC908JK1ECDWER MC9S08PA32AVLD MC9S08PT60AVLD R5F1076CMSPV0 R5F5631ECDFBV0 C8051F389-B-GQ C8051F392-A-GMR ISD-ES1600_USB_PROG 901015X SC705C8AE0VFBE...

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V850es/sa2 upd703201y V850es/sa2 upd70f3201 V850es/sa2 upd70f3201y V850es/sa3 upd703204 V850es/sa3 upd703204y V850es/sa3 upd70f3204 ... Show all

NEC V850ES/SA2 UPD703201 Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Port Functions

Chapter 5 Bus Control Function

Chapter 6 Clock Generation Function

Chapter 7 Timer/Counter Function

Chapter 8 Real-Time Counter Function

Chapter 9 Watchdog Timer Functions

Chapter 10 A/D Converter

Chapter 11 D/A Converter

Chapter 12 Serial Interface Function

Chapter 13 Dma Functions (Dma Controller)

Chapter 14 Interrupt/Exception Processing Function

Chapter 15 Standby Function

Chapter 16 Reset Function

Chapter 17 Rom Correction Function

Chapter 18 Flash Memory

Chapter 19 Electrical Specifications (Target)

Chapter 20 Package Drawings

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Summary of Contents for NEC V850ES/SA2 UPD703201