NEC V850ES/DJ2 User Manual
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NEC V850ES/DJ2 User Manual

NEC V850ES/DJ2 User Manual

32-bit system in package microcontroller
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User's Manual
TM
V850ES/DJ2
32-bit System in Package Microcontroller
Hardware
µPD70F3325
Document No. U17763EE1V1UD00
Date Published September 2005
 NEC Electronics 2005
Printed in Germany

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Summary of Contents for NEC V850ES/DJ2

  • Page 1 User’s Manual V850ES/DJ2 32-bit System in Package Microcontroller Hardware µPD70F3325 Document No. U17763EE1V1UD00 Date Published September 2005  NEC Electronics 2005 Printed in Germany...
  • Page 2 User’s Manual U17763EE1V1UD00...
  • Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
  • Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
  • Page 5 All (other) product, brand, or trade names used in this pamphlet are the trademarks or registered trademarks of their respective owners. Product specifications are subject to change without notice. To ensure that you have the latest product data, please contact your local NEC Electronics sales office. User’s Manual U17763EE1V1UD00...
  • Page 6 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 7 This manual is intented for users who want to understand the functions of the V850ES/DJ2. Purpose This manual presents the hardware manual of the V850ES/DJ2. This User’s Manual is an extension of the F_Line User’s Manual. F_Line Items: For all of the items regarding the FG2 please refer to the F_Line User’s Manual/Data sheet (U17215EJ2V0UD00 (2nd edition) and further releases).
  • Page 8 User’s Manual U17763EE1V1UD00...

  • Page 9: Table Of Contents

    Chapter 1 Introduction........... 17 General .
  • Page 10 Port MT0 ............. 78 4.2.1 Port MT0 functions .
  • Page 11 Chapter 8 Reset Function ..........128 Separated Reset Functions.
  • Page 12 User’s Manual U17763EE1V0UD00...
  • Page 13 Figure 1-1: D_Line SiP ........................18 Figure 1-2: CS Functionality ......................20 Figure 1-3: Pinout of DJ2 ....................... 21 Figure 1-4: Block Diagram of the MTRC..................22 Figure 2-1: Block Diagram ......................27 Figure 2-2: Pin I/O Circuit Types (1/2) ................... 35 Figure 2-3: Figure 2-1.
  • Page 14 Using of the SM ......................125 Figure 7-12: SM Standby Operation ....................126 Figure 8-1: External Reset Circuitry with Pull-Down Resistor............128 Figure 8-2: External Reset Circuitry with Pull-Up Resistor ............129 Figure 10-1: V850ES/DJ2 ......................152 User’s Manual U17763EE1V1UD00...
  • Page 15 Table 1-1: Features (V850ES/D_Line) .................... 17 Table 1-2: Overview of MTRC Functions..................22 Table 1-3: Peripheral I/O Registers ....................23 Table 2-1: Pin I/O Buffer Power Supplies (V850ES/FG2..............28 Table 2-2: Pin List (Port Pins)......................28 Table 2-3: Pin List (Non-Port Pins) ....................30 Table 2-4: Pin I/O Circuit Types and Recommended Connection of Unused Pins......
  • Page 16 User’s Manual U17763EE1V0UD00...

  • Page 17: Chapter 1 Introduction

    1.1 General The V850ES/DJ2 is a 32-bit System in Package (SiP) microcontroller that includes a V850ES CPU core device of the F_Line (V850ES/FG2) and a Meter Controller/Driver (MTRC) in one package. The F_Line includes peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, and an A/D converter.

  • Page 18: About The Subject Of This User's Manual

    Chapter 1 Introduction 1.3 About the Subject of this User’s Manual This User’s Manual is an extension of the F_Line User’s Manual. F_Line Items: For all of the items regarding the FG2 please refer to the F_Line User’s Manual/Data Sheet (U17215EJ2V0UD00 (2nd edition) and further releases).

  • Page 19: Communication Between The Fg2 And Mtrc

    Chapter 1 Introduction 1.5 Communication Between the FG2 and MTRC The clocked synchronous serial interface CSIB1 of the FG2 device is used for the communication with the MTRC. The communication I/F of the MTRC is fixed to the following settings: •...

  • Page 20: Internal Or External Communication Via Csib1

    Chapter 1 Introduction 1.5.2 Internal or external communication via CSIB1 Via the PCM0/CS signal the output functionality of the PMT4 port will be controlled, too. Figure 1-2: CS Functionality V850ES/FG2 MTRC DJ2 pins CLKOUT PMT43/EXCLO SIB1 SOB1 Macro SCKB1 PMT40/EXSI1 PMT41/EXSO1 EXCSI1 PMT42/EXSCK1...

  • Page 21: Pinout Of Dj2

    PMT31 P71/ANI1 P70/ANI0 PMT30 REF0 P10/INTP9 PMT27/SM64 P11/INTP10 PMT26/SM63 PMT25/SM62 P00/TIP31/TOP31 PMT24/SM61 P01/TIP30/TOP30 PMT23/SM54 FLMD0 PMT22/SM53 PMT21/SM52 REGC PMT20/SM51 PMT17/SM44 V850ES/DJ2 RESET PMT16/DM43 PMT15/SM42 PMT14/SM41 P02/NMI PMT13/SM34 P03/INTP0/ADTRG PMT12/SM33 P04/INTP1 PMT11/SM32 PMT10/SM31 P05/INTP2/DRST SM24 P06/INTP3 SM23 P40/SIB0 SM22 P41/SOB0 SM21...

  • Page 22: Overview Of Mtrc Functions

    SM61 - SM64 PMT40 - PMT43 PMT4 EXCLO EXSI1 EXSCK1 EXSO1 MTRESET , MTV , SMV , SMV , SMV , SMV Note: I/O ports of PMT3 are used in the V850ES/DJ2 as follows: • V850ES/DJ2, 144-pin: PMT30-PMT33 User’s Manual U17763EE1V1UD00...

  • Page 23: Peripheral I/O Registers

    Chapter 1 Introduction 1.8 Peripheral I/O Registers Table 1-3: Peripheral I/O Registers Access Initial Value Address Register Name Symbol After Reset 1-bit 8-bit 16-bit Compare Register 10 MCMP10 × Compare Register 11 MCMP11 × Compare Control Register 1 MCMPC1 × Compare Register 20 MCMP20 ×...
  • Page 24 [MEMO] User’s Manual U17763EE1V1UD00...

  • Page 25: Chapter 2 V850Es/Fg2 Introduction

    Chapter 2 V850ES/FG2 Introduction The V850ES/FG2 is one of the products of NEC Electronics’ V850 Series of single-chip microcontrol- lers for real-time control. The V850ES/FG2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and inte- grate peripheral functions such as ROM/RAM, DMA controller, and timers/counters. These microcon- trollers also incorporate a CAN (Controller Area Network) as an automotive LAN.
  • Page 26 Chapter 2 V850ES/FG2 Introduction • Power save function - HALT - IDLE1 - IDLE2 - software STOP - subclock - sub-IDLE modes Pin identification ADTRG: A/D trigger input PCM0 to PCM3: Port CM ANI0 to ANI15: Analog input PCS0, PCS1: Port CS ASCKA0: Asynchronous serial clock...
  • Page 27 Chapter 2 V850ES/FG2 Introduction Figure 2-1: Block Diagram Flash Memory INTC 256 KB, Instruction INTP0 to INTP10 384 KB queue Mask Rom TIQ00 to TIQ10 32-bit barrel Multiplier TIQ01 to TIQ11 128 KB, 16 × 16 → 32 shifter TIQ02 to TIQ12 256 KB TIQ03 to TIQ13 16-bit timer/...

  • Page 28: Pin Functions

    Chapter 2 V850ES/FG2 Introduction 2.1 Pin Functions This section explains the names and functions of the pins of the V850ES/FG2. Three I/O buffer power supplies, AV and EV , are available. The relationship between the REF0, power supplies and the pins is shown below. Table 2-1: Pin I/O Buffer Power Supplies (V850ES/FG2 Power Supply Corresponding Pin...
  • Page 29 Chapter 2 V850ES/FG2 Introduction Table 2-2: Pin List (Port Pins) (Continued) Pin Name Function Alternate Function KR0/TIQ01/TOQ01 KR1/TIQ02/TOQ02 Port 5 KR2/TIQ03/TOQ03/DDI 6-bit I/O port KR3/TIQ00/TOQ00/DDO Input/output can be specified in 1-bit units. KR4/DCK KR5/DMS Port 7 P70 to P715 16-bit I/O port ANI0 to ANI15 Input/output can be specified in 1-bit units.
  • Page 30 Chapter 2 V850ES/FG2 Introduction Table 2-3: Pin List (Non-Port Pins) Pin Name Alternate Function Function External interrupt input Input (non-maskable, with analog noise eliminated) INTP0 P03/ADTRG INTP1 INTP2 P05/DRST INTP3 INTP4 P913/PCL External interrupt request input INTP5 Input P914 (maskable, with analog noise eliminated) INTP6 P915 INTP7...
  • Page 31 Chapter 2 V850ES/FG2 Introduction Table 2-3: Pin List (Non-Port Pins) (Continued) Pin Name Function Alternate Function TOQ00 Timer output (TMQ00) P53/KR3/TIQ00/DDO TOQ01 Timer output (TMQ01) P50/KR0/TIQ01 TOQ02 Timer output (TMQ02) P51/KR1/TIQ02 TOQ03 Timer output (TMQ03) P52/KR2/TIQ03/DDI Output TOQ10 Timer output (TMQ10) P95/TIQ10 TOQ11 Timer output (TMQ11)
  • Page 32 Chapter 2 V850ES/FG2 Introduction Table 2-3: Pin List (Non-Port Pins) (Continued) Pin Name Function Alternate Function Input Debug clock input P54/KR4 DRST Input Debug reset input P05/INTP2 FLMD0 Input Flash programming mode setting pins FLMD1 PDL5 CLKOUT Output Internal system clock output PCM1 Clock output (timing output of X1 input clock and sub- Output...
  • Page 33 Chapter 2 V850ES/FG2 Introduction Table 2-4: Pin I/O Circuit Types and Recommended Connection of Unused Pins I/O Cir- Recommended Connection cuit Type P00/TIP31/TOP31 P01/TIP30/TOP30 Input: Independently connect to EV or EV via a resistor P02/NMI Output: Leave open P03/INTP0/ADTRG P04/INTP1 Input: Independently connect to EV via a resistor P05/INTP2/DRST...
  • Page 34 Chapter 2 V850ES/FG2 Introduction Table 2-4: Pin I/O Circuit Types and Recommended Connection of Unused Pins (Continued) P96/TIP21/TOP21 P97/SIB1/TIP20/TOP20 P98/SOB1 P99/SCKB1 P910 Input: Independently connect to EV or EV via a resistor Output: Leave open P911 P912 P913/INTP4/PCL P914/INTP5 P915/INTP6 PCM0 Input: Independently connect to BV or BV...
  • Page 35 Chapter 2 V850ES/FG2 Introduction Figure 2-2: Pin I/O Circuit Types (1/2) Type 2 Type 5-AF Pullup enable P-ch Data P-ch IN/OUT Output N-ch disable Input enable N-ch Schmitt-triggered input with hysteresis characteristics Pulldown enable Type 5 Type 11-G REF0 Data P-ch IN/OUT Data...
  • Page 36 Chapter 2 V850ES/FG2 Introduction Figure 2-3: Figure 2-1. Pin I/O Circuit Types (2/2) Type 5-A Type 16 Feedback cut-off Pullup P-ch enable P-ch Data P-ch IN/OUT Output N-ch disable Input enable Type 5-W Pullup P-ch enable Data P-ch IN/OUT Output N-ch disable Input...

  • Page 37: Port Functions

    Chapter 2 V850ES/FG2 Introduction 2.2 Port Functions Features • I/O ports: 84 • Port pins function alternately as other peripheral-function I/O pins • Can be set in input or output mode in 1-bit units. The V850ES/FG2 has a total of 84 I/O ports, ports 0, 1, 3 to 5, 7, 9, CM, CS, CT, and DL. The port con- figuration is shown below.

  • Page 38: Cpu Functions

    Chapter 2 V850ES/FG2 Introduction 2.3 CPU Functions Based on the RISC architecture, the CPU of the V850ES/FG2 executes most of the instructions in one clock under control of a five-stage pipeline. Features • Minimum instruction execution time: 50 ns (at 20 MHz operation) •...

  • Page 39: Clock Generation Function

    Chapter 2 V850ES/FG2 Introduction 2.4 Clock Generation Function The following clock generation functions are available. • Main clock oscillator • In clock-through mode = 4 to 5 MHz (f = 4 to 5 MHz) • In PLL (Phase Locked Loop) mode = 4 to 5 MHz (f = 16 to 20 MHz) •...
  • Page 40 Chapter 2 V850ES/FG2 Introduction Figure 2-5: Clock Generator FRC bit Xtal Subclock Watch timer clock oscillator IDLE 1/2 divider control Select IDLE mode 0, 1 oscillator /2 to f Watch timer (WT) clock, Prescaler 3 CSIB0 clock IDLE mode0, 1 PLLON MFRC bit Main clock oscillator...

  • Page 41: 16-Bit Timer/Event Counter P

    Chapter 2 V850ES/FG2 Introduction 2.5 16-bit Timer/event Counter P The V850ES/FG2 includes 16-bit timer/event counter P (TMP0 to TMP3). Features Timer P (TMP) is a 16-bit timer/event counter that can be used in various ways. TMP can perform the following operations. •...
  • Page 42 Chapter 2 V850ES/FG2 Introduction Figure 2-6: Figure 6-1. Block Diagram of Timer P Internal bus TPnCTL0 TPnIOC2 TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnCE TPnCCR0 CCR0 buffer TPnCNT0 Load INTTPnCC0 register Note 1 /128 Note 2 Clear TPnCE Edge Counter control 16-bit counter...

  • Page 43: 16-Bit Timer/Event Counter Q

    Chapter 2 V850ES/FG2 Introduction 2.6 16-bit Timer/event Counter Q The V850ES/FG2 includes 16-bit timer/event counter Q (TMQ0, TMQ1). Features Timer Q (TMQ) is a 16-bit timer/event counter that can be used in various ways. TMQ can perform the following operations. •...
  • Page 44 Chapter 2 V850ES/FG2 Introduction Figure 2-7: Figure 7-1. Block Diagram of Timer Q Internal bus TQnCTL0 TQnIOC2 TQnCE TQnCKS2 TQnCKS1 TQnCKS0 TQnEES1 TQnEES0 TQnETS1 TQnETS0 TQnCE TQnCCR0 CCR0 buffer TQnCNT0 Load INTTQnCC0 register /128 Clear TQnCE Edge Counter control 16-bit counter INTTQnOV detector CCR1 buffer...

  • Page 45: 16-Bit Interval Timer M

    Chapter 2 V850ES/FG2 Introduction 2.7 16-bit Interval Timer M The V850ES/FG2 includes 16-bit interval timer M (TMM0). Features Timer M (TMM) supports only a clear & start mode. It does not support a free-running mode. To use timer M in a manner equivalent to in the free-running mode, set the compare register to FFFFH and start the 16-bit counter.

  • Page 46: Watch Timer Functions

    Chapter 2 V850ES/FG2 Introduction 2.8 Watch Timer Functions Features The watch timer has the following functions. • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. Figure 2-9: Block Diagram of Watch Timer Reset Clear 5-bit counter...
  • Page 47 Chapter 2 V850ES/FG2 Introduction Figure 2-10: Block Diagram of Prescaler 3 3-bit prescaler BGCS 8-bit counter Match Output control Prescaler compare register0 (PRSCM0) BGCE0 BGCS01 BGCS00 Prescaler mode register 0 (PRSM0) Remark: :Prescaler 3 count clock frequency BGCS 1. f :Prescaler 3 output frequency 2.

  • Page 48: Functions Of Watchdog Timer 2

    Chapter 2 V850ES/FG2 Introduction 2.9 Functions of Watchdog Timer 2 Features Watchdog timer 2 has the following functions. • Default-start watchdog timer - →Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) - →Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 Note (generation of INTWDT2 signal) •...

  • Page 49: A/D Converter

    Chapter 2 V850ES/FG2 Introduction 2.10 A/D Converter Features The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 16 analog input signal channels (ANI0 to ANI15). The A/D converter has the following features. •...

  • Page 50: Asynchronous Serial Interface A (Uarta)

    Chapter 2 V850ES/FG2 Introduction 2.11 Asynchronous Serial Interface A (UARTA) The V850ES/FG2 includes asynchronous serial interface A (UARTA). Features • Transfer rate: 300 bps to 312.5 kbps (using internal system clock of 20 MHz and dedicated baud rate generator) • Full-duplex communication - UARTA receive data register n (UAnRX) - UARTA transmit data register n (UAnTX) •...
  • Page 51 Chapter 2 V850ES/FG2 Introduction Figure 2-13: Block Diagram of Asynchronous Serial Interface A Internal bus INTUAnT INTUAnR Reception unit Transmission unit UAnRX UAnTX Transmit Receive shift Reception Transmission shift register register controller controller Filter Baud rate Baud rate Selector TXDAn generator generator RXDAn...

  • Page 52: 3-Wire Serial Interface (Csib)

    Chapter 2 V850ES/FG2 Introduction 2.12 3-Wire Serial Interface (CSIB) The V850ES/FG2 includes a 3-wire serial interface (CSIB). Features • Master mode and slave mode selectable • 3-wire serial interface for 8-bit to 16-bit transfer • Interrupt request signals (INTCBnT and INTCBnR) •...

  • Page 53: Can Controller

    • Automatic block transmission function • Multi-buffer receive block function • Mask setting of four patterns is possible for each channel Figure 2-15: Block Diagram of CAN Module Interrupt request INTCnTRX (NEC peripheral I/O bus) INTCnREC INTCnERR INTCnWUP CAN bus CAN module...

  • Page 54: Interrupt/Exception Processing Function

    Chapter 2 V850ES/FG2 Introduction 2.14 Interrupt/Exception Processing Function The V850ES/FG2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. The V850ES/FG2 can process interrupt request signals from the on-chip peripheral hardware and external sources.

  • Page 55: Dma Controller (Dmac)

    Chapter 2 V850ES/FG2 Introduction 2.15 DMA Controller (DMAC) The V850ES/FG2 incorporates a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The V850ES/FG2 incorporates four independent DMA channels. The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA requests issued by the on-chip peripheral I/O (serial interface, real-time pulse unit, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM or external memory).

  • Page 56: Key Interrupt Function

    Chapter 2 V850ES/FG2 Introduction 2.16 Key Interrupt Function Features A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the key return mode register (KRM). Table 2-5: Assignment of Key Return Detection Pins Flag Pin Description...

  • Page 57: Standby Function

    Chapter 2 V850ES/FG2 Introduction 2.17 Standby Function Overview The power consumption of the system can be effectively reduced by using the standby modes in com- bination and selecting the appropriate mode for the application. The available standby modes are listed below. Table 2-6: Standby Modes Mode Functional Outline...

  • Page 58: Reset Function

    Chapter 2 V850ES/FG2 Introduction 2.18 Reset Function The reset function is outlined below. • Reset function by RESET pin input • Reset function by overflow of watchdog timer 2 (WDT2RES) • System reset by low voltage detector (LVI) • System reset by clock monitor (CLM) Preliminary User’s Manual U17763EE1V1UD00...

  • Page 59: Clock Monitor

    Chapter 2 V850ES/FG2 Introduction 2.19 Clock Monitor The clock monitor samples the main clock by using the on-chip Ring-OSC and generates a reset request signal when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset.

  • Page 60: Low-Voltage Detector

    Chapter 2 V850ES/FG2 Introduction 2.20 Low-voltage Detector Features The low-voltage detector (LVI) has the following functions. • Compares the supply voltage (V ) and detected voltage (V ) and generates an internal LVII interrupt signal or internal reset signal when V <...

  • Page 61: Voltage Regulator

    Chapter 2 V850ES/FG2 Introduction 2.21 Voltage Regulator Features This product has an on-chip regulator to lower the power consumption and noise. This regulator supplies a voltage lower than the supply voltage V to the oscillator block and internal logic circuits (except the A/D converter and I/O buffers). The output voltage of the regulator is set to 2.5 V (±0.2 V).

  • Page 62: Flash Memory

    Chapter 2 V850ES/FG2 Introduction 2.22 Flash Memory The following products are flash memory versions of the V850ES/FG2. Caution: There are differences in the amount of noise tolerance and noise radiation between flash memory versions and mask ROM versions. When considering changing from a flash memory version to a mask ROM version during the process from experimental manufacturing to mass production, make sure to sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.

  • Page 63: Rom Mask Options Function

    Chapter 2 V850ES/FG2 Introduction 2.23 ROM Mask Options Function Mask Options (Flash ROM Product) The flash memory versions in this product series have an option data area where a block subject to mask options is specified. When writing a program to a flash memory version, be sure to set the option data corresponding to the following option in the program at address 007AH as default data.

  • Page 64: On-Chip Debug Unit (Flash Memory Versions Only)

    Chapter 2 V850ES/FG2 Introduction 2.24 On-chip Debug Unit (Flash Memory Versions only) The V850ES/FG2 includes an on-chip debug unit. By connecting an N-Wire emulator, on-chip debug- ging can be executed with the V850ES/FG2 alone. Caution: The following debug functions are supported by the V850ES/FG2, and whether they are usable or not differs depending on the debugger.
  • Page 65 Mask function Each signal can be masked. The correspondence with the mask functions of the debugger (ID850NWC) for the N-Wire emulator (IE- V850E1-CD-NW) of NEC Electronics is shown below. • NMI0 mask function:NMI pin • NMI1 mask function:WDT2 interrupt • NMI2 mask function:–...

  • Page 66: Pin Function Of Mtrc

    Chapter 3 Pin Function of MTRC 3.1 Pin Configuration (Top View) Figure 3-1: Pinout of MTRC PMT27/SM64 PMT26/SM63 PMT17/SM44 PMT25/SM62 PMT16/SM43 PMT24/SM61 PMT15/SM42 PMT23/SM54 PMT14/SM41 PMT22/SM53 PMT13/SM34 PMT21/SM52 PMT12/SM33 PMT20/SM51 PMT11/SM32 PMT43/EXCLO PMT10/SM31 SM24 MTCS SM23 MTRESET SM22 SM21 SM14 SM13 SM12 SM11...

  • Page 67: List Of Pin Functions

    Chapter 3 Pin Function of MTRC 3.2 List of Pin Functions Table 3-1: List of Pin Functions (1/2) Symbol Function Connection PMT00 I/O Port External PMT01 I/O Port External PMT02 I/O Port External PMT03 I/O Port External SM11 O - Hi-Z Meter1 PWM Output Signal (sin+) External SM12...
  • Page 68 Chapter 3 Pin Function of MTRC Table 3-1: List of Pin Functions (2/2) Symbol Function Connection PMT42/EXSCK1 IO/O I/O Port / Expand Pin for SCK External PMT43/EXCLO IO/O I/O Port / Expand Pin for System Clock External SMVDD1 Power Supply Input Voltage for Meter1, Meter2 External SMVSS1 Ground Potential for Meter1, Meter2...
  • Page 69 Chapter 3 Pin Function of MTRC Table 3-2: List of Pin Functions (1/2) Symbol Alternate Function I/O Circuit Recommended connection Input: Independently connect to MTV or MTV via a resistor PMT00 Output: Leave open Input: Independently connect to MTV or MTV via a resistor PMT01 Output: Leave open...
  • Page 70 Chapter 3 Pin Function of MTRC Table 3-2: List of Pin Functions (2/2) Symbol Alternate Function I/O Circuit Recommended connection Input: Independently connect to MTV or MTV via a resistor PMT30 Output: Leave open Input: Independently connect to MTV or MTV via a resistor PMT31 Output: Leave open...

  • Page 71: Pin I/O Circuits

    Chapter 3 Pin Function of MTRC 3.3 Pin I/O Circuits Each type of port block diagram is as follows. Then, the type of each port is shown in each chapter. 3.3.1 Type A-1 Figure 3-2: Type A-1 PMMT PMMTmn PMTmn PMTmn Address 3.3.2 Type B-1...

  • Page 72: Type B-2

    Chapter 3 Pin Function of MTRC 3.3.3 Type B-2 Figure 3-4: Type B-2 PMCMT PMCMTmn PMMT PMMTmn PMTmn PMTmn SM31 - SM34 SM41 - SM44 SM51 - SM54 SM61 - SM64 Address 3.3.4 Type D-1 Figure 3-5: Type D-1 PMCMT PMCMT41 PMMT PMMT41...

  • Page 73: Type D-2

    Chapter 3 Pin Function of MTRC 3.3.5 Type D-2 Figure 3-6: Type D-2 PMCMT PMCMT40 PMMT PMMT40 PMT40 PMT40/EXSI Address EXSI1 3.3.6 Type D-3 Figure 3-7: Type D-3 PMCMT PMCMT42 PMMT PMMT42 PMT42 PMT42/EXSCK1 EXSCK1 Address Preliminary User’s Manual U17763EE1V1UD00...

  • Page 74: Type D-4

    Chapter 3 Pin Function of MTRC 3.3.7 Type D-4 Figure 3-8: Type D-4 PMCMT PMCMT43 PMMT PMMT43 PMT43 PMT43/EXCLO EXCLO Address 3.3.8 Type CLK Figure 3-9: Type CLK pull-down enable N-ch 3.3.9 Type MTCS Figure 3-10: Type MTCS MTCS MTCS pull-down enable N-ch Preliminary User’s Manual U17763EE1V1UD00...

  • Page 75: Type Sck

    Chapter 3 Pin Function of MTRC 3.3.10 Type SCK Figure 3-11: Type SCK P-ch pull-up disable 3.3.11 Type SI Figure 3-12: Type SI pull-down enable N-ch 3.3.12 Type SO Figure 3-13: Type SO Preliminary User’s Manual U17763EE1V1UD00...

  • Page 76: Port Functions

    Chapter 4 Port Functions 4.1 Setting Alternate Pin Functions Set “1” to the PMCmn bit of PMCm register to set the pin to the alternate pin function. Refer to the following table for setting the alternate pin function for every port pin. Not any port provides alternate pin function and therefore this registers has no PMCMTmn register.
  • Page 77 Chapter 4 Port Functions Table 4-1: Alternate Pin Functions (2/2) Setting value when selecting alternate function Alternate Port name pin name PMTmn PMMTmn PMCMTmn Remark Note 4 PMT40 EXSI1 Connect to SO only if MTCS = “0” Note 4 PMT41 EXSO1 Connect to SI only if MTCS = “0”...

  • Page 78: Port Mt0

    Chapter 4 Port Functions 4.2 Port MT0 4.2.1 Port MT0 functions • 4-bit I/O Port • Port I/O data specified in 1-bit units Table 4-2: Port MT0 Functions Register Port Mode Alternate Function TYPE PORT PMT00 × × PMT01 × ×...

  • Page 79: Register

    Chapter 4 Port Functions 4.2.2 Register Port Register 0 (PMT0) MTRC Port register 0 (MT0) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit. Figure 4-1: Port Register 0 (PMT0) Format Initial Address value...

  • Page 80: Port Mt1

    Chapter 4 Port Functions 4.3 Port MT1 4.3.1 Port MT1 functions • 8-bit output port • Port I/O specified in 1-bit units (PMMT1 register) • Port mode/control mode (alternate function) specified in 1-bit units (PMCMT1 register) Table 4-3: Port MT1 Functions Register Port Mode Alternate Function...

  • Page 81: Registers

    Chapter 4 Port Functions 4.3.2 Registers Port Register 1 (PMT1) MTRC Port register 1 (MT1) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit. Figure 4-3: Port Register 1 (PMT1) Format Initial Address value...
  • Page 82 Chapter 4 Port Functions Port Mode Control Register (PMCMT1) It can be read and written in 8-bit unit. Figure 4-5: Port Mode Control Register 1 (PMCMT1) Format Initial Address value PMCMT1 PMCMT17 PMCMT16 PMCMT15 PMCMT14 PMCMT13 PMCMT12 PMCMT11 PMCMT10 0x2A 0x00 PMCMT1n PMMT1n...

  • Page 83: Port Sm1/Sm2

    Chapter 4 Port Functions 4.4 Port SM1/SM2 4.4.1 Port SM1/SM2 functions • 8-bit output port • Port mode/control mode (Hi-Z output as alternate function) specified in 1-bit units (SM12MC register) Table 4-4: Port MT2 Functions Register Port Mode Alternate Function TYPE PORT Hi-Z...

  • Page 84: Port Mt2

    Chapter 4 Port Functions 4.5 Port MT2 4.5.1 Port MT2 functions • 8-bit output port • Port mode/control mode (alternate function) specified in 1-bit units (PMCMT2 register) • Hi-Z output controllable in 1-bit units (PMMT2, PMCMT2 register) Table 4-5: Port MT2 Functions Register Port Mode Alternate Function...

  • Page 85: Registers

    Chapter 4 Port Functions 4.5.2 Registers Port Register 2 (PMT2) MTRC Port register 2 (MT2) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit. Figure 4-7: Port Register 2 (PMT2) Format Initial Address value...
  • Page 86 Chapter 4 Port Functions Port Mode Control Register 2 (PMCMT2) It can be read and written in 8-bit unit. Figure 4-9: Port Mode Control Register 2 (PMCMT2) Format Initial Address value PMCMT2 PMCMT27 PMCMT26 PMCMT25 PMCMT24 PMCMT23 PMCMT22 PMCMT21 PMCMT20 0x2B 0x00 PMCMT2n...

  • Page 87: Port Mt3

    Chapter 4 Port Functions 4.6 Port MT3 Caution: Some ports of are not connected to the D_Line pinout, therefore for at DJ2 n = 0 to 3 has effects only. 4.6.1 Port MT3 functions • 8-bit I/O port • Port I/O specified in 1-bit units Table 4-6: Port MT3 Functions Register Port Mode...

  • Page 88: Registers

    Chapter 4 Port Functions 4.6.2 Registers Port Register 3 (PMT3) MTRC Port register 3 (MT3) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit. Figure 4-10: Port Register 3 (PMT3) Format Initial Address value...

  • Page 89: Port Mt4

    Chapter 4 Port Functions 4.7 Port MT4 4.7.1 Port MT4 functions • 4-bit I/O port • Port I/O specified in 1-bit units (PMMT4 register) • Port mode/control mode (alternate function) specified in 1-bit units (PMCMT4 register) Table 4-7: Port MT4 Functions Register Port Mode Alternate Function...

  • Page 90: Registers

    Chapter 4 Port Functions 4.7.2 Registers Port Register 4 (PMT4) MTRC Port register 4 (MT4) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit. Figure 4-12: Port Register 4 (PMT4) Format Initial Address value...
  • Page 91 Chapter 4 Port Functions Port Mode Control Register 4 (PMCMT4) It can be read and written in 8-bit unit. Figure 4-14: Port Mode Control Register 4 (PMCMT4) Format Initial Address value PMCMT4 PMCMT43 PMCMT42 PMCMT41 PMCMT40 0x2C 0x00 PMCMT43 PMCMT43 mode control I/O port EXCLO output PMCMT42...

  • Page 92: Chapter 5 Clock Generator

    Chapter 5 Clock Generator 5.1 Ring Oscillator To support a high frequency clock source for the MTRC an internal high speed Ring Oscillator is imple- mented in the MTRC. This Ring Oscillator is controlled with SFRs to realize stop, restart and calibra- tion.

  • Page 93: Ring Oscillator Control Registers

    Chapter 5 Clock Generator 5.2 Ring Oscillator Control Registers 5.2.1 RingOSC Control Register (MRCTL) The MRCTL register is an 8-bit register that controls the RingOSC operation. This register can be read or written in 8-bit units. However, bits 1 (MRCALSF) and 0 (MRCALERR) are read-only.
  • Page 94 Chapter 5 Clock Generator Figure 5-1: RingOSC Control Register for the Meter (MRCTL) Format (2/2) MRCALEN Ring Oscillator frequency calibration operation control Calibration disabled Calibration enabled Caution: After the MTRESET pin has been released, the MRCALEN bit can be written only one time.

  • Page 95: Ringosc Calibration Register (Mrcal)

    Chapter 5 Clock Generator 5.2.2 RingOSC Calibration Register (MRCAL) The MRCAL register is a 5-bit register for the RingOSC calibration operation. This register can be read or written in 8-bit units. This register can be set in a range of 0x01to 0x1F. The frequency of RingOSC will be increased by the MRCAL register value.
  • Page 96 Chapter 5 Clock Generator Figure 5-3: Flowchart for Frequency Calibration FG2 pin settings (SOB1, SCKB1, SIB1, PCM0). Initial Settings Setting to form the specified pulse via PCM0 (Timer etc.) MTRESET=1 RingOSC oscillation start, enable MRINGCTL operation Set PCM0 pin=1 (after eliminating noise time of MTCSP pin) wait for eliminating noise time Set PCM0 pin=0 wait for oscillation stabilization time...
  • Page 97 Chapter 5 Clock Generator Figure 5-4: Timing Diagram for Frequency Calibration Ring Oscillator MTRESET pin eliminating noise time PCM0/CS pin Oscillation stabilization time 1st specified pulse 2nd specified pulse MRON bit MRCALSF bit "H" MRCALEN bit RingOSC oscillation start enable MRINGCTL operation RingOSC count start Calibration...

  • Page 98: Mtreset Release Of The Mtrc

    Chapter 5 Clock Generator 5.4 MTRESET Release of the MTRC If the MTRC is reset, the MRCAL register will be reset, too. Therefore the beforehand stored MRCAL register value has to be written back. Please see the following procedure for the MTRESET Release of the MTRC. Figure 5-5: Flowchart for MTRESET Release Ring Oscillator is stopped Initial Settings...
  • Page 99 Chapter 5 Clock Generator Figure 5-6: Timing for MTRES Release Autocalibration won't performed even for rising edge at PCM0/CS pin Ring Oscillator MTRESET pin eliminating noise time PCM0/CS pin Oscillation stabilization time MRON bit MRCALSF bit "L" MRCALEN bit RingOSC oscillation start enable MRINGCTL operation...

  • Page 100: Standby Mode Release Of The Ring Oscillator

    Chapter 5 Clock Generator 5.5 Standby Mode Release of the Ring Oscillator To save power, the ring oscillator could be switched off via setting the MRON bit of the MRCTL register = 0. During the time of the stopped Ring Oscillator, the data retention of the MRCAL register can’t be guar- anteed.
  • Page 101 Chapter 5 Clock Generator Figure 5-8: Timing Diagram for Standby Mode Release Autocalibration won't performed even for rising edge at PCM0/CS pin (Standby mode) Ring Oscillator MTRESET pin Eliminating noise time PCM0/CS pin Oscillation stabilization time MRON bit MRCALSF bit "L"...

  • Page 102: Cautions

    Chapter 5 Clock Generator 5.6 Cautions The calibration has to be performed at the specified conditions (Temperature and Voltage). If performing at other condition, the accuracy of the ring oscillator cannot be guaranteed. The basic calibration pulse must have the specified High and Low pulse width at the PCM0/CS pin.
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  • Page 104: Chapter 6 Serial Interface

    Chapter 6 Serial Interface 6.1 Communication Protocol The CSI of the MTRC is fixed to the following operation mode: Communication protocol: Clocked synchronous serial interface • Data length: 8-bits fixed • Transfer direction: MSB first • Transfer mode: Transmit/Receive mode •...

  • Page 105: Command Byte

    Chapter 6 Serial Interface 6.2.1 Command Byte This is the 1st Received Data at communication start, that was sent from the FG2 device. Command AUTO R/W Selection of MTRC Read Write AUTO Operation mode of Communication Disable Continuous transfer Enable Continuous transfer A5 to A0 Address define address data as 6-bit format...

  • Page 106: Serial I/F Operation

    Chapter 6 Serial Interface 6.3 Serial I/F Operation 6.3.1 Read from MTRC operation After PCM0/CS = “1”, the MTRC is waiting for the command byte via the SI pin. If the read command is received the MTRC outputs data via the SO pin, which were specified with the address bits A5 to A0. When continuous transfer is selected (Auto bit of Command Byte = “1”), the MTRC outputs next data, at the incremented address via the SO pin.

  • Page 107: Timing Of Mtrc Read Operation

    Chapter 6 Serial Interface 6.3.2 Timing of MTRC Read operation Figure 6-2: MTRC Read Operation (Auto=0) After Last data transfer start, FG2 can set CS = 0 (last Data byte will be sent from MTRC) Dummy Write Dummy Write READ command READ command READ data READ data...

  • Page 108: Mtrc Write Operation

    Chapter 6 Serial Interface 6.3.3 MTRC Write operation After CS pin = “1", MTRC received write command/address via SI pin. After receive command, MTRC write next receive data, which is specified address. When select continuous mode (Auto = “1”), next receive data will be written 1 incremented address. When select disable continuous mode (Auto = “0”), After receive 1 byte data, MTRC decide that next received data as command/address Figure 6-4: Operation Flow on MTRC Writing...

  • Page 109: Timing Of Mtrc Write Operation

    Chapter 6 Serial Interface 6.3.4 Timing of MTRC Write operation Figure 6-5: MTRC Write Operation (Auto bit = 0) After Last data transfer start, FG2 can set CS = 0 (last Data byte will be received from MTRC) WRITE command WRITE data WRITE command WRITE data...

  • Page 110: External Csib1 Function (Excsi1)

    Chapter 6 Serial Interface 6.4 External CSIB1 Function (EXCSI1) If the PMT4 port is configured for peripheral mode the PCM0/CS signal controls the output function of the external CSIB1 (EXCSI1) functionality. The EXCSIB1 provide the FG2 CSIB1 communication for external components, too. This function can be used, if there’s no internal communication between the FG2 device and the MTRC (refer to Figure 1-2, “CS Functionality,”...

  • Page 111: Internal Csib1 Function

    Chapter 6 Serial Interface 6.5 Internal CSIB1 Function 6.5.1 Operation of Serial Interface The communication I/F of the MTRC is fixed to the following settings: • I/F: • Mode: Slave mode • Data length: 8-bits (support continuous data transfer, therefore the FG2 CSIB1 can use 16-bit data length) •...
  • Page 112 Chapter 6 Serial Interface Basic operation The MTRC serial interface is only working in slave mode. When iSCK clock is applied the transfer operation is started. There’s a delay between SCK of the CSIB1 from FG2 and the iSCK of the MTRC. The iSCK signal is synchronised with the MTRC Ring Oscillator.
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  • Page 114: Meter Controller Driver

    Chapter 7 Meter Controller Driver This MTRC has 6 × 360° type meters controllable driver. 7.1 Meter Controller Driver Function Outline • 8-bit free run counter × 2 • 8-bit compare register × 12 • 8-bit +1 accuracy PWM output × 24 Figure 7-1: Meter Controller Driver Block Diagram Meter Controller 0 Time Base...

  • Page 115: Register Setting

    Chapter 7 Meter Controller Driver 7.2 Register Setting 7.2.1 Free Running Counter m (MCNTm, m = 0, 1) MCNTm is an 8-bit free running counter. This counter will be incremented by f (n = 0, 1). This fre- quency is generated from CLK1 and the selected prescaler. The counter starts by setting the PCEm bit =”1”...

  • Page 116: Sin Compare Register N0 (Mcmpn0, N = 1 To 6)

    Chapter 7 Meter Controller Driver 7.2.2 Sin Compare Register n0 (MCMPn0, n = 1 to 6) MCMPn0 is an 8-bit register, which continuously compares its value with the MCNTm value. When the two values match, a match signal of sin side of meter n is generated. MCMP10 to MCMP40 are compared with MCNT0, MCMP50 to MCMP60 are compared with MCNT1.

  • Page 117: Cos Compare Register N1 (Mcmpn1, N = 1 To 6)

    Chapter 7 Meter Controller Driver 7.2.3 Cos Compare Register n1 (MCMPn1, n = 1 to 6) MCMPn1 is an 8-bit register, with the same functionality of the MCMPn0 register but for the cos signal. When the above two values match, a match signal of cos side of meter n is generated. MCMP11 to MCMP41 are compared with MCNT0, MCMP51 to MCMP61 are compared with MCNT1.

  • Page 118: Compare Control Register (Mcmpcn, N = 1 To 6)

    Chapter 7 Meter Controller Driver 7.2.4 Compare Control Register (MCMPCn, n = 1 to 6) MCMPCn is an 8-bit register that controls the operation of the compare register and output direction of the PWM pin. TENn bit becomes “0” automatically after finished transmission from master register to slave register.
  • Page 119 Chapter 7 Meter Controller Driver Figure 7-5: Compare Control Register MCMPCn Format (2/2) ADBn1 Control of 1-bit addition circuit (cos side of meter n) No 1-bit addition 1-bit addition ADBn0 Control of 1-bit addition circuit (sin side of meter n) No 1-bit addition 1-bit addition The 1-bit addition adds 1 further PWM tick to the PWM value that was set with the MCMPnm register,...

  • Page 120: Timer Mode Control Register (Mcntm) (M = 0, 1)

    Chapter 7 Meter Controller Driver 7.2.5 Timer Mode Control Register (MCNTm) (m = 0, 1) MCNTCm is an 8-bit register that controls the operation of the timer counter MCNTm. MCNTCm is set with an 8-bit memory instruction. MTRESET =”0” clears MCNTCm to 00H. Figure 7-6: Timer Mode Control Register (MCNTm) Format (1/2) Initial Address...
  • Page 121 Chapter 7 Meter Controller Driver Figure 7-6: Timer Mode Control Register (MCNTm) Format (2/2) SMCLm2 SMCLm1 SMCLm0 Timer counter 1 clock selection / 16 / 32 / 64 / 128 / 256 / 512 Preliminary User’s Manual U17763EE1V1UD00...

  • Page 122: Operation

    Chapter 7 Meter Controller Driver 7.3 Operation 7.3.1 Count timing The counter is counted up by the rising edge of the f clock signal that is selected by the SMCLm2 to 0 bits. The counting operation is enabled or disabled by the PCEm bit of the timer mode control register. The MCNTm register is cleared by MTRESET = “0”...

  • Page 123: Operation Of 1-Bit Addition Circuit

    Chapter 7 Meter Controller Driver 7.3.2 Operation of 1-bit addition circuit 1-bit addition to the PWM output is activated by setting ADBn1, ADBn0 bit of the MCMPCn register to “1”. 1-bit addition mode repeats 1-bit addition/non-addition to PWM output alternately upon MCNTm over- flow output, and enables the state of PWM output between current compare value N and the next com- pare value N+1.

  • Page 124: Pwm Output With 1 Clock Shifted Operation

    Chapter 7 Meter Controller Driver 7.3.3 PWM output with 1 clock shifted operation If the output of the sin/cos signal of meter channel 1 to 4 (5 and 6) rises/falls internally as indicated by the broken line, the SM11 to SM44 (SM51 to SM64) pins always shift the rising edge of the output pin by 1 count clock of the MCNTm counter.

  • Page 125: Method Of Using

    Chapter 7 Meter Controller Driver 7.4 Method of Using Figure 7-11: Using of the SM MCMPn1 setting value MCMPn0 setting value MCNTm SMn1 SMn2 "L" SMn3 SMn4 "L" TENn MCMPn0/MCMPn1, MCMPn0/MCMPn1, (6) ~ (8) (1) ~ (4) ADBn0/ADBn1, ADBn0/ADBn1, DIRn0/DIRn1 transfer DIRn0/DIRn1 transfer Setting SM pin to output mode by Port mode register assigned to SMn1 to SMn4 output Input clock is supplied to the macro by setting CAE = “1”...

  • Page 126: Macro Standby Operation

    Chapter 7 Meter Controller Driver 7.4.1 Macro Standby operation By setting PCE1 and PCE0/CAE = “0” of MCMTCn register, the timer stops count operation and the PWM output is set to “0”. After that the macro is in power saving standby mode state. Figure 7-12: SM Standby Operation MCMPn0/MCMP1 MCMPn0/MCMP1...
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  • Page 128: Chapter 8 Reset Function

    MTRC RESET RESET IC V850ES/DJ2 This circuitry is the best choose for safety applications, but consumes more power in power save modes. If the FG2 will be reset via an internal (LVI or WD) or external function (RESET), the Pxx pin will be set into its reset mode (input) and the pull down resistor will set the MTRC into reset state, too.

  • Page 129: External Reset Circuitry With Pull-Up Resistor

    MTRC RESET RESET IC V850ES/DJ2 This circuitry saves more power, but at internal reset in the FG2 device, the MTRC will be left active with its last configured settings. If MTVDD will be applied, the signal at MTRESET pin will release the reset mode of the MTRC. The capacitor will cause a delay between MTVDD apply and MTRESET release, to ensure the minimum specified time between this points of time.

  • Page 130: Electrical Specification

    Chapter 9 Electrical Specification 9.1 Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit =MTV =SMV -0.3 to +6.5 REF0 =MTV =SMV -0.3 to +6.5 REF0 =MTV =SMV -0.3 to +6.5 REF0 =MTV =SMV -0.3 to +6.5 DD1,2 REF0 =MTV =SMV...
  • Page 131 Chapter 9 Electrical Specification Parameter Symbol Conditions Ratings Unit 1 pin P00-P06, P10-P11, P30-P39, P40-P42, P50-P55, P90-P96, P910-P915 Total 1 pin P70-P715 Total 1 pin PCM2-PCM3, PCS0-PCS1, PCT0, PCT1,PCT4, PCT6, PDL0-PDL13, MTCS Total Low level output current 1 pin PMT10-PMT17 Total 1 pin SM11-SM14, SM21-SM24...

  • Page 132: Capacitance

    Chapter 9 Electrical Specification 9.2 Capacitance =25°C, =MTV =SMV =MTV =SMV =0 V) REF0 Parameter Symbol Conditions MIN. TYP. MAX. Unit Input f=1 MHz, Other than unmeasured pins:0 V capacitance f=1 MHz, Other than unmeasured pins:0 V Input / Output PMT00-PMT03, PMT30-PMT37, capacitance PMT40-PMT43...

  • Page 133: Oscillation Circuit

    Chapter 9 Electrical Specification 9.4 Oscillation Circuit 9.4.1 Main System Clock Oscillation Circuit Characteristics =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C) Resonator Recommended circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillation fre- quency After reset is released Crystal/ Ceramic...

  • Page 134: Sub System Clock Oscillation Circuit Characteristics

    Chapter 9 Electrical Specification 9.4.2 Sub System Clock Oscillation Circuit Characteristics =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C) Recommended cir- Resonator Pyaarameter Conditions MIN. TYP. MAX. Unit cuit Oscillation fre- 32.768 quency (f Crystal resonator Oscillation stabili-...

  • Page 135: Mtrc Ring Oscillator Oscillation Circuit Characteristics

    Chapter 9 Electrical Specification 9.4.3 MTRC Ring Oscillator Oscillation Circuit Characteristics =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C) Resonator Parameter Conditions MIN. TYP. MAX. Unit Oscillation frequency (f Ring Oscillator Oscillation stabilization time Calibration high pulse calibration pulse calibration low pulse...

  • Page 136: Voltage Regulator Characteristics

    Chapter 9 Electrical Specification 9.5 Voltage Regulator Characteristics =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage Output voltage After V reaches MIN.: 3.5 V ± Connect C = 4.7 µF Lock time 20% to REGC...

  • Page 137: Dc Characteristics

    Chapter 9 Electrical Specification 9.6 DC Characteristics 9.6.1 Input/Output Level =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C) Parameter Symbol Conditions MIN. MAX. Unit 0.7 EV P30, P34, P36-P38, P41, P911 P00-P06, P10-P11, P31-P33, P35, P39, P40, P42, 0.8 EV P50-P55, P90-P96, P910, P912-P915 PCM2-PCM3, PCS0-PCS1, PCT0, PCT1, PCT4, PCT6,...

  • Page 138: Pin Leak Current

    Chapter 9 Electrical Specification Parameter Symbol Conditions MIN. MAX. Unit P00-P06, P10-P11, P30-P39, P40-P42, P50-P55, P90-P96, P910-P915 PCM0-PCM3, PCS0-PCS1, =1.0 mA PCT0, PCT1, PCT4, PCT6, PDL0-PDL13 P70-P715 Output =27 mA (T =85°C) voltage, =30 mA (T =25°C) 0.07 =40 mA (T =-40°C) PMT10-PMT17, PMT20-PMT27, SM11-SM14, SM21-SM24...

  • Page 139: Specific Power Supply Current

    Chapter 9 Electrical Specification 9.6.3 Specific Power Supply Current =MTV =SMV =4.0 to 5.5 V =4.0 to 5.5 V REF0 =MTV =SMV =0 V =-40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit =20 MHz (OSC=5 MHz) 32.5 MTRC-Ring Oscillator On IDD1 Operating mode All peripherals stopped MTRC-Ring Oscillator On...

  • Page 140: Data Retention Characteristics

    Chapter 9 Electrical Specification 9.6.4 Data Retention Characteristics =MTV =SMV =2.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage In STOP mode DDDR Data retention current = 2.0 V µA DDDR DDDR...

  • Page 141: Ac Characteristics

    Chapter 9 Electrical Specification 9.7 AC Characteristics AC Test Input Measurement Points (V , AV , EV , MTV , MTV IH (MIN.) IH (MIN.) Measurement points IL (MAX.) IL (MAX.) AC Test Output Measurement Points OH (MIN.) OH (MIN.) Measurement points OL (MAX.) OL (MAX.)

  • Page 142: Exclo Output Timing

    Chapter 9 Electrical Specification 9.7.1 EXCLO output timing =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C, C =50 pF) Parameter Symbol Conditions MIN. MAX. Unit Output cycle 62.5 ns 8 µs /2 - 15 High level width /2 - 15 Low level width...

  • Page 143: Reset, Interrupt, Flmd0 Timing

    Chapter 9 Electrical Specification 9.7.2 RESET, Interrupt, FLMD0 timing =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C, C =50 pF) Parameter Symbol Conditions MIN. MAX. Unit MTRESET input low level width WMRSL Parameter Symbol Conditions MIN.

  • Page 144: Key Return Timing

    Chapter 9 Electrical Specification 9.7.3 Key Return timing =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C, C =50 pF) Parameter Symbol Conditions MIN. MAX. Unit KRn input high-level WKRH width Analog noise elimination (n = 0 to 7) KRn input low-level WKRL width...

  • Page 145: Csi Timing

    9.7.5 CSI timing CSI0 (a) Master Mode =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C, C =50 pF) Parameter Symbol Conditions MIN. MAX. Unit SCKB0 cycle time KCY0 /2-15 SCKB0 high level width KCY0 /2-15 SCKB0 low level width KCY0...

  • Page 146: Uart Timing

    Chapter 9 Electrical Specification CSI1 CSI1 can be only used in Master Mode. (a) Master Mode =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C, C =50 pF) Parameter Symbol Conditions MIN. MAX. Unit EXSCK1 cycle time 250/1000 KCY1 /2 - 30...

  • Page 147: Can Timing

    Chapter 9 Electrical Specification 9.7.7 CAN timing =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C, C =50 pF) Parameter Symbol Conditions MIN. MAX. Unit Transfer rate Mbps Internal delay time Internal delay time (t ) = Internal transfer delay time (t ) + Internal receive delay time (t NODE...

  • Page 148: Ad Converter

    Chapter 9 Electrical Specification 9.7.8 AD Converter =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C, C =50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 4.0 ≤ AV ≤ 5.5 V ±0.15 ±0.45 %FSR Overall error REF0...

  • Page 149: Ram Retention Flag

    Chapter 9 Electrical Specification 9.7.10 RAM retention flag =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C, C =50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage RAMH = 0 V → 3.5 V Supply voltage rise time 0.002 1,800...

  • Page 150: Flash Memory Programming Characteristics

    Chapter 9 Electrical Specification 9.7.11 Flash Memory Programming characteristics =MTV =SMV =4.0 to 5.5 V, REF0 =MTV =SMV =0 V, =-40 to +85°C, C =50 pF) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Operating frequency Supply voltage Number of writes Times Input voltage, high FLMD0...
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  • Page 152: Chapter 10 Package Drawings

    Chapter 10 Package Drawings Figure 10-1: V850ES/DJ2 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 22.0±0.2 its true position (T.P.) at maximum material condition. 20.0±0.2 20.0±0.2 22.0±0.2...
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  • Page 154: Chapter 11 Recommended Soldering Conditions

    Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device: Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended please consult NEC. Symbol of Recommended Soldering Method Soldering Condition...
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  • Page 156 Chapter 11 Recommended Soldering Conditions Preliminary User’s Manual U17763EE1V1UD00...

  • Page 157: Appendix A Index

    Appendix A Index Numerics 3-Wire Serial Interface ............. 52 A/D Converter .
  • Page 158 PMMT1 ............... . 81 PMMT2 .
  • Page 159 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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