Page 1 User’s Manual V850ES/KE1+ 32-bit Single-Chip Microcontrollers Hardware μ PD703302 μ PD703302Y μ PD70F3302 μ PD70F3302Y Document No. U16896EJ2V0UD00 (2nd edition) Date Published August 2006 N CP(K) 2004 Printed in Japan...
Page 2 [MEMO] User’s Manual U16896EJ2V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 Technology, Inc. IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America. EEPROM is a trademark of NEC Electronics Corporation.
Page 5 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 6 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/KE1+ and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/KE1+ shown in the Organization below.
Page 7 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 8: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION........................17 K1 Series Product Lineup ......................17 1.1.1 V850ES/Kx1+, V850ES/Kx1 products lineup................. 17 1.1.2 78K0/Kx1+, 78K0/Kx1 products lineup ..................20 Features ............................23 Applications..........................24 Ordering Information ......................... 24 Pin Configuration (Top View)....................25 Function Block Configuration....................27 Overview of Functions.......................
Page 9 4.3.8 Port DL ............................99 Block Diagrams ........................101 Port Register Setting When Alternate Function Is Used ............. 119 Cautions............................ 123 4.6.1 Cautions on bit manipulation instruction for port n register (Pn) ...........123 4.6.2 Hysteresis characteristics ......................124 CHAPTER 5 CLOCK GENERATION FUNCTION ................125 Overview ...........................
Page 10 7.4.6 PPG output operation ........................271 7.4.7 One-shot pulse output operation....................274 7.4.8 Pulse width measurement operation.................... 279 Special Use of TM01......................... 287 7.5.1 Rewriting CR011 register during TM01 operation................ 287 7.5.2 Setting LVS01 and LVR01 bits ....................287 Cautions ............................ 289 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 ................
Page 11 11.1.1 Functions ............................347 11.1.2 Configuration ..........................349 11.1.3 Registers ............................349 11.1.4 Operation............................351 11.2 Watchdog Timer 2........................353 11.2.1 Functions ............................353 11.2.2 Configuration ..........................354 11.2.3 Registers ............................354 11.2.4 Operation............................356 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)..............357 12.1 Function ............................ 357 12.2 Configuration..........................358 12.3 Registers...........................
Page 12 14.6 Dedicated Baud Rate Generator n (BRGn) ................424 14.6.1 Baud rate generator n (BRGn) configuration ................424 14.6.2 Serial clock generation......................... 425 14.6.3 Baud rate setting example ......................428 14.6.4 Allowable baud rate range during reception................. 429 14.6.5 Transfer rate during continuous transmission ................431 14.7 Cautions ............................
Page 13 16.13.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1) ......514 16.14 Cautions............................ 515 16.15 Communication Operations....................516 16.15.1 Master operation in single master system ..................517 16.15.2 Master operation in multimaster system ..................518 16.15.3 Slave operation..........................521 16.16 Timing of Data Communication....................524 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION..........531 17.1 Overview ...........................
Page 14 19.3.1 Setting and operation status ......................578 19.3.2 Releasing HALT mode......................... 578 19.4 IDLE Mode..........................580 19.4.1 Setting and operation status ......................580 19.4.2 Releasing IDLE mode ........................580 19.5 STOP Mode ..........................582 19.5.1 Setting and operation status ......................582 19.5.2 Releasing STOP mode ........................
Page 15 23.1 Function ............................ 618 23.2 Configuration..........................618 23.3 Operation ..........................619 CHAPTER 24 ROM CORRECTION FUNCTION..................620 24.1 Overview ........................... 620 24.2 Control Registers........................621 24.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3) ............621 24.2.2 Correction control register (CORCN)....................622 24.3 ROM Correction Operation and Program Flow..............
Page 16 APPENDIX A DEVELOPMENT TOOLS....................680 Software Package........................683 Language Processing Software....................683 Control Software ........................683 Debugging Tools (Hardware) ....................684 A.4.1 When using IECUBE QB-V850ESKX1H..................684 A.4.2 When using MINICUBE QB-V850MINI ..................686 <R> Debugging Tools (Software) ....................688 Embedded Software.........................
Page 17: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION 1.1 K1 Series Product Lineup 1.1.1 V850ES/Kx1+, V850ES/Kx1 products lineup • 64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch) • 64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch) V850ES/KE1 V850ES/KE1+ μ μ μ μ...
Page 18 CHAPTER 1 INTRODUCTION The function list of the V850ES/Kx1+ is shown below. Product Name V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ V850ES/KJ1+ Number of pins 64 pins 80 pins 100 pins 144 pins − − − − − − − Internal Mask ROM memory −...
Page 19 CHAPTER 1 INTRODUCTION The function list of the V850ES/Kx1 is shown below. Product Name V850ES/KE1 V850ES/KF1 V850ES/KG1 V850ES/KJ1 Number of pins 64 pins 80 pins 100 pins 144 pins − − − − − − − Internal Mask ROM 96/128 memory (KB) −...
Page 20: 78K0/Kx1+, 78K0/Kx1 Products Lineup
CHAPTER 1 INTRODUCTION 1.1.2 78K0/Kx1+, 78K0/Kx1 products lineup 30-pin SSOP (7.62 mm 0.65 mm pitch) 78K0/KB1 78K0/KB1+ μ μ μ PD78F0103 PD780103 PD78F0103H Mask ROM: 24 KB, Single-power flash: 24 KB, Two-power flash: 24 KB, RAM: 768 B RAM: 768 B RAM: 768 B μ...
Page 21 CHAPTER 1 INTRODUCTION The list of functions in the 78K0/Kx1 is shown below. Part Number 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins − − − − − − Internal Mask ROM memory...
Page 22 CHAPTER 1 INTRODUCTION The list of functions in the 78K0/Kx1+ is shown below. Part Number 78K0/KB1+ 78K0/KC1+ 78K0/KD1+ 78K0/KE1+ 78K0/KF1+ Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins Internal Flash memory 16/24 24/32 24/32 24/32 48/60 memory...
Page 23: Features
CHAPTER 1 INTRODUCTION 1.2 Features Minimum instruction execution time: 50 ns (operation at main clock (f ) = 20 MHz) General-purpose registers: 32 bits × 32 registers Signed multiplication (16 × 16 → 32): 1 to 2 clocks CPU features: (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock...
Page 24: Applications
CHAPTER 1 INTRODUCTION Internal oscillator: 240 kHz (TYP.) Remark For frequency characteristics (error) of internal oscillator, refer to CHAPTER 28 ELECTRICAL SPECIFICATIONS. Reset • Reset by RESET pin • Reset by overflow of watchdog timer 1 (WDTRES1) • Reset by overflow of watchdog timer 2 (WDTRES2) •...
Page 25: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) 64-pin plastic TQFP (12 × 12) 64-pin plastic LQFP (fine pitch) (10 × 10) μ μ PD703302GK-×××-9ET-A PD70F3302GK-9ET-A μ μ PD703302GB-×××-8EU-A PD70F3302GB-8EU-A μ μ PD703302YGK-×××-9ET-A PD70F3302YGK-9ET-A μ μ PD703302YGB-×××-8EU-A PD70F3302YGB-8EU-A 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PDL1 REF0 PDL0...
Page 26 CHAPTER 1 INTRODUCTION Pin identification ADTRG: A/D trigger input PDL0 to PDL7: Port DL RESET: Reset ANI0 to ANI7: Analog input ASCK0: Asynchronous serial clock RTP00 to RTP05: Real-time output port Analog reference voltage RXD0, RXD1: Receive data REF0 Ground for analog SCK00, SCK01: Serial clock CLKOUT:...
Page 27: Function Block Configuration
CHAPTER 1 INTRODUCTION 1.6 Function Block Configuration (1) Internal block diagram INTC Instruction INTP0 to INTP7 queue Note 1 16-bit TI010, TI011 32-bit barrel Multiplier 16 × 16 → 32 timer/event shifter counter 0: 1 ch TO01 System registers 4 KB 16-bit timer/ TIP00, TIP01 General-purpose...
Page 28 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) help accelerate complex processing.
Page 29 CHAPTER 1 INTRODUCTION Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a non- maskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs.
Page 30 CHAPTER 1 INTRODUCTION (q) Power-on-clear (POC) circuit The power-on-clear circuit generates an internal reset signal at power on. The power-on-clear circuit compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when V <...
Page 31: Overview Of Functions
CHAPTER 1 INTRODUCTION 1.7 Overview of Functions μ μ Part Number PD703302, 703302Y PD70F3302, 70F3302Y Internal 128 KB 128 KB (single-power flash memory) memory High-speed RAM 4 KB Memory space 64 MB 32 bits × 32 registers General-purpose registers Main clock Ceramic/crystal/external clock (oscillation frequency) When PLL not used (2 to 10 MHz: 2.7 to 5.5 V)
Page 32: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The names and functions of the pins of the V850ES/KE1+ are described below, divided into port pins and non-port pins. The pin I/O buffer power supplies are divided into two systems; AV and EV . The relationship between these REF0 power supplies and the pins is shown below.
Page 33 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Pin No. Pull-up Resistor Function Alternate Function Port 5 TI011/RTP00/KR0 I/O port TI50/RTP01/KR1 Input/output can be specified in 1-bit units. TO50/RTP02/KR2 RTP03/KR3 RTP04/KR4 RTP05/KR5 Input Port 7 ANI0 Input port ANI1 ANI2 ANI3 ANI4 ANI5 ANI6...
Page 34 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name Pin No. Pull-up Resistor Function Alternate Function ADTRG Input A/D converter external trigger input P32/ASCK0/TO01 ANI0 Input Analog voltage input for A/D converter ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ASCK0 Input UART0 serial clock input...
Page 35 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Pin No. Pull-up Resistor Function Alternate Function RTP00 Output Real-time output port P50/TI011/KR0 RTP01 P51/TI50/KR1 RTP02 P52/TO50/KR2 RTP03 P53/KR3 RTP04 P54/KR4 RTP05 P55/KR5 RXD0 Input Serial receive data input for UART0 P31/INTP7 RXD1 Serial receive data input for UART1 P91/KR7 SCK00...
Page 36: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.2 Pin I/O Circuits and Recommended Connection of Unused Pins (1/2) Alternate Function Pin No. I/O Circuit Type Recommended Connection Input: Independently connect to EV or EV TOH0 via a resistor. TOH1 Output: Leave open. P03 to P06 INTP0 to INTP3 15 to 18 TXD0...
Page 37 CHAPTER 2 PIN FUNCTIONS (2/2) Alternate Function Pin No. I/O Circuit Type Recommended Connection – – Directly connect to V REF0 – – – – – – – – – Note 1 – – Directly connect to EV or V or pull down with a 10 kΩ...
Page 38: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits (1/2) Type 9-C Type 2 P-ch Comparator – N-ch (threshold voltage) REF0 Input enable Schmitt-triggered input with hysteresis characteristics Type 10-A Type 5-A Pull-up P-ch enable Pull-up P-ch enable Data Data P-ch P-ch IN/OUT IN/OUT...
Page 39 CHAPTER 2 PIN FUNCTIONS (2/2) <R> Type 13-AD Type 16 Feedback cut-off IN/OUT Data P-ch Output N-ch disable Input enable Type 13-AE Mask option IN/OUT Data Output N-ch disable Input enable Remark Read V as EV . Also, read V as EV User’s Manual U16896EJ2V0UD...
Page 40: Chapter 3 Cpu Functions
CHAPTER 3 CPU FUNCTIONS The CPU of the V850ES/KE1+ is based on the RISC architecture and executes most instructions in one clock cycle by using 5-stage pipeline control. 3.1 Features Number of instructions: Minimum instruction execution time: 50.0 ns (@ 20 MHz operation: 4.5 to 5.5 V) 100 ns (@ 10 MHz operation: 2.7 to 5.5 V) <R>...
Page 41: Cpu Register Set
CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The CPU registers of the V850ES/KE1+ can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width. For details, refer to the V850ES Architecture User’s Manual. (1) Program register set (2) System register set (Zero register)
Page 42: Program Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable.
Page 43: System Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2.
Page 44 CHAPTER 3 CPU FUNCTIONS (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)).
Page 45 CHAPTER 3 CPU FUNCTIONS (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions.
Page 46 CHAPTER 3 CPU FUNCTIONS (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution.
Page 47 CHAPTER 3 CPU FUNCTIONS (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation result status Flag status Saturated...
Page 48 CHAPTER 3 CPU FUNCTIONS (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW.
Page 49: Operating Modes
CHAPTER 3 CPU FUNCTIONS 3.3 Operating Modes The V850ES/KE1+ has the following operating modes. (1) Normal operating mode After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started.
Page 50: Address Space
CHAPTER 3 CPU FUNCTIONS 3.4 Address Space 3.4.1 CPU address space For instruction addressing, an internal ROM area of up to 1 MB, and an internal RAM area are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported.
Page 51: Wraparound Of Cpu Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0.
Page 52: Memory Map
CHAPTER 3 CPU FUNCTIONS 3.4.3 Memory map The V850ES/KE1+ has reserved areas as shown below. Figure 3-2. Data Memory Map (Physical Addresses) 3FFFFFFH 3FFFFFFH On-chip peripheral I/O area (4 KB) 3FFF000H (80 KB) 3FFEFFFH 3FEC000H 3FEBFFFH Internal RAM area (60 KB) 3FFF000H 3FFEFFFH Use-prohibited area...
Page 53 CHAPTER 3 CPU FUNCTIONS Figure 3-3. Program Memory Map 03FFFFFFH Use-prohibited area (Program fetch disabled area) 03FFF000H 03FFEFFFH Internal RAM area (60 KB) 03FF0000H 03FEFFFFH Use-prohibited area (Program fetch disabled area) 00100000H 000FFFFFH Internal ROM area (1 MB) 00000000H User’s Manual U16896EJ2V0UD...
Page 54: Areas
CHAPTER 3 CPU FUNCTIONS 3.4.4 Areas (1) Internal ROM area An area of 1 MB from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM (128 KB) A 128 KB area from 0000000H to 001FFFFH is provided in the V850ES/KE1+. Addresses 0020000H to 00FFFFFH are an access-prohibited area.
Page 55 CHAPTER 3 CPU FUNCTIONS (3) On-chip peripheral I/O area A 4 KB area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Figure 3-6. On-Chip Peripheral I/O Area Physical address space Logical address space FFFFFFFH 3FFFFFFH On-chip peripheral I/O area (4 KB) 3FFF000H FFFF000H...
Page 56: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.5 Recommended use of address space The architecture of the V850ES/KE1+ requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ±32 KB can be directly accessed by an instruction for operand data.
Page 57 CHAPTER 3 CPU FUNCTIONS Figure 3-7. Recommended Memory Map Program space Data space F F F F F F F F H On-chip peripheral I/O F F F F F 0 0 0 H F F F F E F F F H Internal RAM x F F F F F F F H F F F F C 0 0 0 H...
Page 58: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTIONS 3.4.6 Peripheral I/O registers (1/7) Address Function Register Name Symbol Operable Bit Unit After Reset √ √ Note 1 FFFFF004H Port DL register √ √ Note 1 FFFFF00CH Port CM register √ √ FFFFF024H Port DL mode register PMDL √...
Page 59 CHAPTER 3 CPU FUNCTIONS (2/7) Address Function Register Name Symbol Operable Bit Unit After Reset √ √ FFFFF148H Interrupt control register WTIIC √ √ FFFFF14AH Interrupt control register WTIC √ √ FFFFF14CH Interrupt control register BRGIC √ √ FFFFF170H Interrupt control register LVIIC √...
Page 60 CHAPTER 3 CPU FUNCTIONS (3/7) Address Function Register Name Symbol Operable Bit Unit After Reset √ FFFFF446H Port 3 mode control register PMC3 0000H √ √ FFFFF446H Port 3 mode control register L PMC3L √ √ FFFFF447H Port 3 mode control register H PMC3H √...
Page 61 CHAPTER 3 CPU FUNCTIONS (4/7) Address Function Register Name Symbol Operable Bit Unit After Reset √ FFFFF5C6H 16-bit timer mode control register 5 TMC5 0000H √ √ FFFFF5C6H 8-bit timer mode control register 50 TMC50 √ √ FFFFF5C7H 8-bit timer mode control register 51 TMC51 √...
Page 62 CHAPTER 3 CPU FUNCTIONS (5/7) Address Function Register Name Symbol Operable Bit Unit After Reset √ √ FFFFF820H Power save mode register PSMR √ √ FFFFF828H Processor clock control register √ √ FFFFF82EH CPU operation clock status register CCLS √ FFFFF840H Correction address register 0 CORAD0...
Page 63 CHAPTER 3 CPU FUNCTIONS (6/7) Address Function Register Name Symbol Operable Bit Unit After Reset √ √ FFFFFB00H TIP00 noise elimination control register P0NFC √ √ FFFFFB04H TIP01 noise elimination control register P1NFC √ √ FFFFFC00H External interrupt falling edge specification register 0 INTF0 √...
Page 64 CHAPTER 3 CPU FUNCTIONS (7/7) Address Function Register Name Symbol Operable Bit Unit After Reset √ FFFFFD1AH Serial I/O shift register 1 SIO01 √ FFFFFD1AH Serial I/O shift register 1L SIO01L 0000H √ Note FFFFFD80H IIC shift register 0 IIC0 √...
Page 65: Special Registers
CHAPTER 3 CPU FUNCTIONS 3.4.7 Special registers Special registers are registers that prevent invalid data from being written when an inadvertent program loop occurs. The V850ES/KE1+ has the following six special registers. • Power save control register (PSC) • Processor clock control register (PCC) •...
Page 66 CHAPTER 3 CPU FUNCTIONS [Description Example] When using PSC register (standby mode setting) ST.B r11, PSMR[r0] ; PSMR register setting (IDLE, STOP mode setting) <1> MOV 0x02, r10 <2> ST.B r10, PRCMD[r0] ; PRCMD register write <3> ST.B r10, PSC[r0] ;...
Page 67 CHAPTER 3 CPU FUNCTIONS (3) System status register (SYS) This register is allocated with status flags showing the operating state of the entire system. This register can be read or written in 8-bit or 1-bit units. After reset: 00H Address: FFFFF802H <...
Page 68: Cautions
CHAPTER 3 CPU FUNCTIONS 3.4.8 Cautions (1) Wait when accessing register Be sure to set the following register before using the V850ES/KE1+. • System wait control register (VSWC) After setting the VSWC register, set the other registers as required. When using an external bus, set the VSWC register and then set the various pins to the control mode by setting the port-related registers.
Page 69 CHAPTER 3 CPU FUNCTIONS Peripheral Function Register Name Access Watchdog timer 1 (WDT1) WDTM1 Write 1 to 5 Note 1 <Calculation of number of waits > ) × 2/((2 + m)/f k = {(1/f )} + 1 : Main clock oscillation frequency Watchdog timer 2 (WDT2) WDTM2 Write...
Page 70 CHAPTER 3 CPU FUNCTIONS (2) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 71: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Features Input-only ports: 8 pins I/O ports: 43 pins • Fixed to N-ch open-drain output: 2 • Switchable to N-ch open-drain output: 4 Input/output can be specified in 1-bit units 4.2 Basic Port Configuration The V850ES/KE1+ incorporates a total of 51 I/O port pins consisting of ports 0, 3 to 5, 7, 9, CM, and DL (including 8 input-only port pins).
Page 72: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.3 Port Configuration Table 4-2. Port Configuration Item Configuration Port n register (Pn: n = 0, 3 to 5, 7, 9, CM, DL) Control registers Port n mode register (PMn: n = 0, 3 to 5, 9, CM, DL) Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM) Port n function control register (PFCn: n = 3, 5, 9) Port n function register (PFn: n = 3, 4, 9)
Page 73 CHAPTER 4 PORT FUNCTIONS (1) Port n register (Pn) Data I/O with external devices is performed by writing to and reading from the Pn register. The Pn register is configured of a port latch that retains the output data and a circuit that reads the pin status. Each bit of the Pn register corresponds to one pin of port n and can be read or written in 1-bit units.
Page 74 CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) PMn specifies the input mode/output mode of the port. Each bit of the PMn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: PMn7 PMn6 PMn5...
Page 75 CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) PFCn is a register that specifies the alternate function to be used when one pin has two or more alternate functions. Each bit of the PFCn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: PFCn PFCn7...
Page 76 CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) PFn is a register that specifies normal output/N-ch open-drain output. Each bit of the PFn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: PFn7 PFn6...
Page 77 CHAPTER 4 PORT FUNCTIONS (8) Port settings Set the ports as follows. Figure 4-1. Register Settings and Pin Functions Port mode Output mode “0” PMn register Input mode “1” Alternate function (when two alternate functions are available) “0” Alternate function 1 “0”...
Page 78: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate functions. Table 4-4. Alternate-Function Pins of Port 0 Note 1 Pin No.
Page 79 CHAPTER 4 PORT FUNCTIONS (3) Port 0 mode control register (PMC0) After reset: 00H Address: FFFFF440H PMC0 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 PMC06 Specification of P06 pin operation mode I/O port INTP3 input PMC05 Specification of P05 pin operation mode I/O port INTP2 input PMC04...
Page 80: Port 3
CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 3 Port 3 is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate functions. Table 4-5. Alternate-Function Pins of Port 3 Note 1 Pin No.
Page 81 CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) After reset: 00H (output latch) Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H Note P3 (P3H (P3L) Control of output data (in output mode) (n = 0 to 5, 8, 9) 0 is output 1 is output Note When reading from or writing to bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P3H register.
Page 82 CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) After reset: 0000H Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H Note 1 Note 2 Note 2 PMC3 (PMC3H PMC39 PMC38 (PMC3L) PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 Specification of P39 pin operation mode I/O port SCL0 I/O PMC38...
Page 83 CHAPTER 4 PORT FUNCTIONS (4) Port 3 function register H (PF3H) After reset: 00H Address: FFFFFC67H PF3H PF39 PF38 PF3n Specification of normal port/alternate function (n = 8, 9) When used as normal port (N-ch open-drain output) When used as alternate-function (N-ch open-drain output) Caution When using P38 and P39 as N-ch open-drain-output alternate-function pins, set in the following sequence.
Page 84 CHAPTER 4 PORT FUNCTIONS (7) Specifying alternate-function pins of port 3 PFC35 Specification of Alternate-Function Pin of P35 Pin TI010 input TO01 output PFCE34 PFC34 Specification of Alternate-Function Pin of P34 Pin Setting prohibited Setting prohibited TIP01 input TOP01 output PFCE33 PFC33 Specification of Alternate-Function Pin of P33 Pin...
Page 85: Port 4
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 4 Port 4 is a 3-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 4 includes the following alternate functions. Table 4-6. Alternate-Function Pins of Port 4 Note Pin No. Pin Name Alternate Function PULL...
Page 86 CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H Address: FFFFF448H PMC4 PMC42 PMC41 PMC40 PMC42 Specification of P42 pin operation mode I/O port SCK00 I/O PMC41 Specification of P41 pin operation mode I/O port SO00 output PMC40 Specification of P40 pin operation mode...
Page 87: Port 5
CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 5 Port 5 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 5 includes the following alternate functions. Table 4-7. Alternate-Function Pins of Port 5 Note Pin No. Pin Name Alternate Function PULL...
Page 88 CHAPTER 4 PORT FUNCTIONS (3) Port 5 mode control register (PMC5) After reset: 00H Address: FFFFF44AH PMC5 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 PMC55 Specification of P55 pin operation mode I/O port/KR5 input RTP05 output PMC54 Specification of P54 pin operation mode I/O port/KR4 input RTP04 output PMC53...
Page 89 CHAPTER 4 PORT FUNCTIONS (4) Port 5 function control register (PFC5) Caution When the P5n pin is specified as an alternate function by the PMC5.PMC5n bit with the PFC5n bit maintaining the initial value (0), output becomes undefined. Therefore, to specify the P5n pin as alternate function 2, set the PFC5n bit to 1 first and then set the PMC5n bit to 1 (n = 3 to 5).
Page 90: Port 7
CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 7 Port 7 is an 8-bit input-only port for which all the pins are fixed to input. Port 7 includes the following alternate functions. Table 4-8. Alternate-Function Pins of Port 7 Note Pin No. Pin Name Alternate Function PULL...
Page 91: Port 9
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 9 Port 9 is a 9-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate functions. Table 4-9. Alternate-Function Pins of Port 9 Note Pin No. Pin Name Alternate Function PULL...
Page 92 CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 00H (output latch) Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H Note P9 (P9H P915 P914 P913 (P9L) Control of output data (in output mode) (n = 0, 1, 6 to 9, 13 to 15) 0 is output 1 is output Note When reading from or writing to bits 8 to 15 of the P9 register in 8-bit or 1-bit units,...
Page 93 CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) After reset: 0000H Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H Note PMC9 (PMC9H PMC915 PMC914 PMC913 PMC99 PMC98 PMC97 PMC96 PMC91 PMC90 (PMC9L) PMC915 Specification of P915 pin operation mode I/O port INTP6 input PMC914...
Page 94 CHAPTER 4 PORT FUNCTIONS (4) Port 9 function register H (PF9H) After reset: 00H Address: FFFFFC73H PF9H PF99 PF98 PF9n Control of normal output/N-ch open-drain output (n = 8, 9) Normal output N-ch open-drain output Caution When using P98 and P99 as N-ch open-drain-output alternate-function pins, set in the following sequence.
Page 95 CHAPTER 4 PORT FUNCTIONS (5) Port 9 function control register (PFC9) Caution When port 9 is specified as an alternate function by the PMC9.PMC9n bit with the PFC9n bit maintaining the initial value (0), output becomes undefined. Therefore, to specify port 9 as alternate function 2, set the PFC9n bit to 1 first and then set the PMC9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15).
Page 96 CHAPTER 4 PORT FUNCTIONS (6) Pull-up resistor option register 9 (PU9) After reset: 0000H Address: PU9 FFFFFC52H, PU9L FFFFFC52H, PU9H FFFFFC53H Note PU9 (PU9H PU915 PU914 PU913 PU99 PU98 (PU9L) PU97 PU96 PU91 PU90 PU9n Control of on-chip pull-up resistor connection (n = 0, 1, 6 to 9, 13 to 15) Not connected Connected Note When reading from or writing to bits 8 to 15 of the PU9 register in 8-bit or 1-bit units,...
Page 97: Port Cm
CHAPTER 4 PORT FUNCTIONS 4.3.7 Port CM Port CM is a 2-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate functions. Table 4-10. Alternate-Function Pins of Port CM Note Pin No. Pin Name Alternate Function PULL...
Page 98 CHAPTER 4 PORT FUNCTIONS (4) Pull-up resistor option register CM (PUCM) After reset: 00H Address: FFFFFF4CH PUCM PUCM1 PUCM0 PUCMn Control of on-chip pull-up resistor connection (n = 0, 1) Not connected Connected User’s Manual U16896EJ2V0UD...
Page 99: Port Dl
CHAPTER 4 PORT FUNCTIONS 4.3.8 Port DL Port DL is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate functions. Table 4-11. Alternate-Function Pins of Port DL Note Pin No. Pin Name Alternate Function PULL...
Page 100 CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 00H (output latch) Address: FFFFF004H PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn Control of output data (in output mode) (n = 0 to 7) 0 is output 1 is output (2) Port DL mode register (PMDL) After reset: FFH...
Page 101: Block Diagrams
CHAPTER 4 PORT FUNCTIONS 4.4 Block Diagrams Figure 4-2. Block Diagram of Type A-A P-ch A/D input signal N-ch Figure 4-3. Block Diagram of Type C-U P-ch PUmn PMmn PORT Output latch (Pmn) Address User’s Manual U16896EJ2V0UD...
Page 102 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type D0-U PUmn P-ch PMCmn PMmn Output signal of PORT alternate function 1 Output latch (Pmn) Address User’s Manual U16896EJ2V0UD...
Page 103 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type D0-UF PUmn P-ch PFmn PMCmn PMmn Output signal of PORT alternate function 1 P-ch Output latch (Pmn) N-ch Address User’s Manual U16896EJ2V0UD...
Page 104 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type D1-SUIL P-ch PUmn INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT Output latch (Pmn) Note 2 Address Input signal of Noise elimination alternate function 1 Edge detection Notes 1.
Page 105 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D1-SUIHL PUmn P-ch INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT Output latch (Pmn) Note 2 Address Noise elimination Input signal of Edge detection alternate function 1-2 Input signal of alternate function 1-1 Notes 1.
Page 106 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type D1-SUL P-ch PUmn PMCmn PMmn PORT Output latch (Pmn) Note Address Input signal of alternate function 1 Note There are no hysteresis characteristics in the port mode. User’s Manual U16896EJ2V0UD...
Page 107 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type D2-SNMUFH PFmn PMCmn PMmn Mask option Output signal of PORT alternate function 1 N-ch Output latch (Pmn) Note Address Input signal of alternate function 1 Note There are no hysteresis characteristics in the port mode. User’s Manual U16896EJ2V0UD...
Page 108 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type D2-SUFL P-ch PUmn PFmn Output enable signal of alternate function 1 PMCmn PMmn Output signal of PORT alternate function 1 P-ch Output latch (Pmn) N-ch Note Address Input signal of alternate function 1 Note There are no hysteresis characteristics in the port mode.
Page 109 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type E00-SUT P-ch PUmn PFCmn PMCmn PMmn Output signal of alternate function 2 Output signal of alternate function 1 PORT Output latch (Pmn) Address Alternate-function input signal in port mode User’s Manual U16896EJ2V0UD...
Page 110 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type E10-SUL P-ch PUmn PFCmn PMCmn PMmn PORT Output signal of alternate function 2 Output latch (Pmn) Note Address Input signal of alternate function 1 Note There are no hysteresis characteristics in the port mode. User’s Manual U16896EJ2V0UD...
Page 111 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type E10-SULT P-ch PUmn PFCmn PMCmn PMmn Output signal of alternate function 2 PORT Output latch (Pmn) Address Input signal of alternate function 1 Alternate-function input signal in port mode User’s Manual U16896EJ2V0UD...
Page 112 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type Ex0-SUT P-ch PUmn PFCmn PMCmn PMmn Output signal of alternate function 2 PORT Output latch (Pmn) Address Alternate-function input signal in port mode User’s Manual U16896EJ2V0UD...
Page 113 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type Ex0-UF PUmn P-ch PFmn PFCmn PMCmn PMmn Output signal of alternate function 2 PORT P-ch Output latch (Pmn) N-ch Address User’s Manual U16896EJ2V0UD...
Page 114 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type Ex1-SUHT P-ch PUmn PFCmn PMCmn PMmn PORT Output latch (Pmn) Address Input signal of alternate function 2 Alternate-function input signal in port mode User’s Manual U16896EJ2V0UD...
Page 115 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type Ex1-SUIL PUmn P-ch INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn PORT Output latch (Pmn) Note 2 Address Noise elimination Input signal of Edge detection alternate function 2 Notes 1.
Page 116 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type Ex1-SUL PUmn P-ch PFCmn PMCmn PMmn PORT Output latch (Pmn) Address Input signal of alternate function 2 User’s Manual U16896EJ2V0UD...
Page 117 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type Ex2-SUFL PUmn P-ch PFmn Output enable signal of alternate function 2 PFCmn PMCmn PMmn Output signal of alternate function 2 PORT P-ch Output latch (Pmn) N-ch Note Address Input signal of alternate function 2 Note There are no hysteresis characteristics in the port mode.
Page 118 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of Type Gxx10-SUL PUmn P-ch PFCE PFCEmn PFCmn PMCmn PMmn Output signal of alternate function 4 PORT Output latch (Pmn) Note Address Input signal of alternate function 3 Note There are no hysteresis characteristics in the port mode. User’s Manual U16896EJ2V0UD...
Page 119: Port Register Setting When Alternate Function Is Used
CHAPTER 4 PORT FUNCTIONS 4.5 Port Register Setting When Alternate Function Is Used Table 4-12 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to description of each pin. User’s Manual U16896EJ2V0UD...
Page 120 Table 4-12. Settings When Port Pins Are Used for Alternate Functions (1/3) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCEnx Bit of PFCnx Bit of PFCn Other Bits (Registers) PMCn Register PFCEn Register Register Function Name...
Page 121 Table 4-12. Settings When Port Pins Are Used for Alternate Functions (2/3) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Function Name PMCn Register PFCn Register Note –...
Page 122 Table 4-12. Settings When Port Pins Are Used for Alternate Functions (3/3) Pin Name Alternate Function Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) Function Name PMCn Register PFCn Register ANI0 Input P70 = Setting not required...
Page 123: Cautions
CHAPTER 4 PORT FUNCTIONS 4.6 Cautions 4.6.1 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
Page 124: Hysteresis Characteristics
CHAPTER 4 PORT FUNCTIONS 4.6.2 Hysteresis characteristics In port mode, the following ports do not have hysteresis characteristics. P02 to P06 P31 to P35, P38, P39 P40, P42 P97, P99, P913 to P915 User’s Manual U16896EJ2V0UD...
Page 125: Chapter 5 Clock Generation Function
CHAPTER 5 CLOCK GENERATION FUNCTION 5.1 Overview The following clock generation functions are available. Main clock oscillator <R> <In PLL (×4) mode> • f = 8 to 20 MHz: 4.5 V ≤ V ≤ 5.5 V) = 2 to 5 MHz (f •...
Page 126: Configuration
CHAPTER 5 CLOCK GENERATION FUNCTION 5.2 Configuration Figure 5-1. Clock Generator <R> FRC bit Watch timer clock, Subclock watchdog timer 2 clock oscillator INTBRG /2 to f Interval timer Watch timer clock IDLE mode IDLE control MFRC IDLE mode PLLON bit CK2 to CK0 bits CLS bit, CK3 bit Main clock stop...
Page 127 CHAPTER 5 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main clock oscillator oscillates the following frequencies (f • f = 2 to 5 MHz (V = 4.5 to 5.5 V, in PLL mode) • f = 2 to 4 MHz (V = 4.0 to 5.5 V, in PLL mode) <R>...
Page 128: Registers
CHAPTER 5 CLOCK GENERATION FUNCTION 5.3 Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H.
Page 129 CHAPTER 5 CLOCK GENERATION FUNCTION (2/2) Clock selection (f /8 (default value) × Setting prohibited × × × Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being output. 2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits.
Page 130 CHAPTER 5 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started.
Page 131 CHAPTER 5 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3>...
Page 132 CHAPTER 5 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution The settings of the RCM register differ for a mask ROM version and flash memory version.
Page 133: Operation
CHAPTER 5 CLOCK GENERATION FUNCTION 5.4 Operation 5.4.1 Operation of each clock The following table shows the operation status of each clock. Table 5-1. Operation Status of Each Clock Register Setting and PCC Register Operation Status CLS bit = 0, CLS bit = 1, CLS bit = 1, MCK bit = 0...
Page 134: Pll Function
CHAPTER 5 CLOCK GENERATION FUNCTION 5.5 PLL Function 5.5.1 Overview The PLL function is used to output the operating clock of the CPU and on-chip peripheral function at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. When PLL function is used: Input clock = 2 to 5 MHz (f : 8 to 20 MHz) Clock-through mode:...
Page 135: Usage
CHAPTER 5 CLOCK GENERATION FUNCTION 5.5.3 Usage (1) When PLL is used • After reset has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1). •...
Page 136: Chapter 6 16-Bit Timer/Event Counter P (Tmp)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850ES/KE1+ incorporates TMP0. 6.1 Overview An outline of TMP0 is shown below. • Clock selection: 8 ways • Capture trigger input pins: 2 • External event count input pins: 1 •...
Page 137: Configuration
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.3 Configuration TMP0 includes the following hardware. Table 6-1. Configuration of TMP0 Item Configuration Timer register 16-bit counter Registers TMP0 capture/compare registers 0, 1 (TP0CCR0, TP0CCR1) TMP0 counter read buffer register (TP0CNT) CCR0, CCR1 buffer registers Note Timer inputs 2 (TIP00...
Page 138 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TP0CNT register. When the TP0CTL0.TP0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TP0CNT register is read at this time, 0000H is read.
Page 139: Registers
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.4 Registers (1) TMP0 control register 0 (TP0CTL0) The TP0CTL0 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 140 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) TMP0 control register 1 (TP0CTL1) The TP0CTL1 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF5A1H <6>...
Page 141 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMP0 I/O control register 0 (TP0IOC0) The TP0IOC0 register is an 8-bit register that controls the timer output (TOP00, TOP01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 142 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMP0 I/O control register 1 (TP0IOC1) The TP0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIP00, TIP01 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 143 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMP0 I/O control register 2 (TP0IOC2) The TP0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIP00 pin) and external trigger input signal (TIP00 pin). This register can be read or written in 8-bit or 1-bit units.
Page 144 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMP0 option register 0 (TP0OPT0) The TP0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 145 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMP0 capture/compare register 0 (TP0CCR0) The TP0CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS0 bit.
Page 146 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TP0CCR0 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTP0CC0) is generated.
Page 147 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMP0 capture/compare register 1 (TP0CCR1) The TP0CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS1 bit.
Page 148 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TP0CCR1 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTP0CC1) is generated.
Page 149 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMP0 counter read buffer register (TP0CNT) The TP0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TP0CTL0.TP0CE bit = 1, the count value of the 16-bit counter can be read. This register is read-only, in 16-bit units.
Page 150: Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5 Operation TMP0 can perform the following operations. TP0CTL1.TP0EST Bit TIP00 Pin Capture/Compare Compare Register Operation (Software Trigger Bit) (External Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write Note 1 External event count mode Invalid...
Page 151: Interval Timer Mode (Tp0Md2 To Tp0Md0 Bits = 000)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5.1 Interval timer mode (TP0MD2 to TP0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTP0CC0) is generated at the specified interval if the TP0CTL0.TP0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOP00 pin.
Page 152 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOP00 pin is inverted. Additionally, the set value of the TP0CCR0 register is transferred to the CCR0 buffer register.
Page 153 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TMP0 I/O control register 0 (TP0IOC0) TP0OL1 TP0OE1 TP0OL0 TP0OE0 TP0IOC0 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of output level with operation of TOP00 pin disabled 0: Low level 1: High level...
Page 154 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 6-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed Register initial setting...
Page 155 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Interval timer mode operation timing (a) Operation if TP0CCR0 register is cleared to 0000H If the TP0CCR0 register is cleared to 0000H, the INTTP0CC0 signal is generated at each count clock, and the output of the TOP00 pin is inverted.
Page 156 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TP0CCR0 register is set to FFFFH If the TP0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTP0CC0 signal is generated and the output of the TOP00 pin is inverted.
Page 157 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TP0CCR0 register To change the value of the TP0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TP0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 158 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TP0CCR1 register Figure 6-6. Configuration of TP0CCR1 Register TP0CCR1 register Output TOP01 pin CCR1 buffer register controller Match signal INTTP0CC1 signal Clear Count clock Output 16-bit counter TOP00 pin selection controller Match signal INTTP0CC0 signal...
Page 159 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TP0CCR1 register is less than the set value of the TP0CCR0 register, the INTTP0CC1 signal is generated once per cycle. At the same time, the output of the TOP01 pin is inverted. The TOP01 pin outputs a square wave with the same cycle as that output by the TOP00 pin.
Page 160 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TP0CCR1 register is greater than the set value of the TP0CCR0 register, the count value of the 16-bit counter does not match the value of the TP0CCR1 register. Consequently, the INTTP0CC1 signal is not generated, nor is the output of the TOP01 pin changed.
Page 161: External Event Count Mode (Tp0Md2 To Tp0Md0 Bits = 001)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5.2 External event count mode (TP0MD2 to TP0MD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TP0CTL0.TP0CE bit is set to 1, and an interrupt request signal (INTTP0CC0) is generated each time the specified number of edges have been counted.
Page 162 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TP0CCR0 register is transferred to the CCR0 buffer register.
Page 163 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TMP0 counter read buffer register (TP0CNT) The count value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare register 0 (TP0CCR0) If D is set to the TP0CCR0 register, the counter is cleared and a compare match interrupt request...
Page 164 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 6-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers...
Page 165 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TP0CCR0 and TP0CCR1 registers to <R> 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer <R>...
Page 166 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TP0CCR0 register To change the value of the TP0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TP0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 167 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TP0CCR1 register Figure 6-13. Configuration of TP0CCR1 Register TP0CCR1 register CCR1 buffer register Match signal INTTP0CC1 signal Clear Edge TIP00 pin 16-bit counter detector Match signal INTTP0CC0 signal TP0CE bit CCR0 buffer register TP0CCR0 register If the set value of the TP0CCR1 register is smaller than the set value of the TP0CCR0 register, the...
Page 168 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TP0CCR1 register is greater than the set value of the TP0CCR0 register, the INTTP0CC1 signal is not generated because the count value of the 16-bit counter and the value of the TP0CCR1 register do not match.
Page 169: External Trigger Pulse Output Mode (Tp0Md2 To Tp0Md0 Bits = 010)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5.3 External trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TP0CTL0.TP0CE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOP01 pin.
Page 170 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-17. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output <R> (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Wait...
Page 171 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-18. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1.
Page 172 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-18. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 Select valid edge of external trigger input Select valid edge of external event count input (e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register.
Page 173 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 6-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register CCR0 buffer register INTTP0CC0 signal...
Page 174 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TP0CCR0, TP0CCR1 register setting change flow Only writing of the TP0CCR1 START register must be performed when the set duty factor is changed.
Page 175 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TP0CCR1 register last. Rewrite the TP0CCRa register after writing the TP0CCR1 register after the INTTP0CC0 signal is detected. FFFFH 16-bit counter 0000H...
Page 176 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TP0CCRa register to the CCRa buffer register, the TP0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TP0CCR0 register and then set the active level width to the TP0CCR1 register.
Page 177 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, clear the TP0CCR1 register to 0000H. If the set value of the TP0CCR0 register is FFFFH, the INTTP0CC1 signal is generated periodically. Count clock −...
Page 178 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with TP0CCR1 register If the trigger is detected immediately after the INTTP0CC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOP01 pin is asserted, and the counter continues counting.
Page 179 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with TP0CCR0 register If the trigger is detected immediately after the INTTP0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOP01 pin is extended by time from generation of the INTTP0CC0 signal to trigger detection.
Page 180 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTP0CC1) The timing of generation of the INTTP0CC1 signal in the external trigger pulse output mode differs from the timing of other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register.
Page 181: One-Shot Pulse Output Mode (Tp0Md2 To Tp0Md0 Bits = 011)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5.4 One-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TP0CTL0.TP0CE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOP01 pin.
Page 182 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-21. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Delay Active...
Page 183 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-22. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE...
Page 184 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-22. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 Select valid edge of external trigger input Select valid edge of external event count input (e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register.
Page 185 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode Figure 6-23. Software Processing Flow in One-Shot Pulse Output Mode <R> FFFFH 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TP0CCR1 register INTTP0CC1 signal...
Page 186 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TP0CCRa register To change the set value of the TP0CCRa register to a smaller value, stop counting once, and then change the set value.
Page 187 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTP0CC1) The generation timing of the INTTP0CC1 signal in the one-shot pulse output mode is different from other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register.
Page 188: Pwm Output Mode (Tp0Md2 To Tp0Md0 Bits = 100)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5.5 PWM output mode (TP0MD2 to TP0MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOP01 pin when the TP0CTL0.TP0CE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOP00 pin. Figure 6-24.
Page 189 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-25. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output Active period Cycle Inactive period...
Page 190 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-26. Register Setting in PWM Output Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE...
Page 191 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-26. Register Setting in PWM Output Mode (2/2) (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 Select valid edge of external event count input. (e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register.
Page 192 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 6-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output TP0CCR1 register CCR1 buffer register INTTP0CC1 signal...
Page 193 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TP0CCR0, TP0CCR1 register setting change flow Only writing of the TP0CCR1 START register must be performed when the set duty factor is changed.
Page 194 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TP0CCR1 register last. Rewrite the TP0CCRa register after writing the TP0CCR1 register after the INTTP0CC1 signal is detected. FFFFH 16-bit counter 0000H...
Page 195 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TP0CCR1 register to 0000H. If the set value of the TP0CCR0 register is FFFFH, the INTTP0CC1 signal is generated periodically. Count clock −...
Page 196 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTP0CC1) The timing of generation of the INTTP0CC1 signal in the PWM output mode differs from the timing of other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register.
Page 197: Free-Running Timer Mode (Tp0Md2 To Tp0Md0 Bits = 101)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5.6 Free-running timer mode (TP0MD2 to TP0MD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit is set to 1. At this time, the TP0CCRa register can be used as a compare register or a capture register, depending on the setting of the TP0OPT0.TP0CCS0 and TP0OPT0.TP0CCS1 bits.
Page 198 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOP00 and TOP01 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TP0CCRa register, a compare match interrupt request signal (INTTP0CCa) is generated, and the output signal of the TOP0a pin is inverted.
Page 199 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIP0a pin is detected, the count value of the 16-bit counter is stored in the TP0CCRa register, and a capture interrupt request signal (INTTP0CCa) is generated.
Page 200 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-31. Register Setting in Free-Running Timer Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE...
Page 201 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-31. Register Setting in Free-Running Timer Mode (2/2) (d) TMP0 I/O control register 1 (TP0IOC1) TP0IS3 TP0IS2 TP0IS1 TP0IS0 TP0IOC1 Select valid edge of TIP00 pin input Select valid edge of TIP01 pin input (e) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0...
Page 202 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 6-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TOP00 pin output...
Page 203 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TP0CTL0 register is performed before setting the (TP0CKS0 to TP0CKS2 bits) TP0CE bit to 1.
Page 204 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 6-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TP0CE bit TIP00 pin input TP0CCR0 register 0000 0000 INTTP0CC0 signal TIP01 pin input 0000...
Page 205 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TP0CTL0 register is performed before setting the (TP0CKS0 to TP0CKS2 bits) TP0CE bit to 1.
Page 206 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TP0CCRa register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTP0CCa signal has been detected.
Page 207 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TP0CCRa register used as a capture register, software processing is necessary for reading the capture register each time the INTTP0CCa signal has been detected and for calculating an interval.
Page 208 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter...
Page 209 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TP0CE bit INTTP0OV signal TP0OVF bit Note TP0OVF0 flag TIP00 pin input TP0CCR0 register Note TP0OVF1 flag TIP01 pin input TP0CCR1 register <1>...
Page 210 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TP0CE bit INTTP0OV signal TP0OVF bit Note TP0OVF0 flag TIP00 pin input TP0CCR0 register Note TP0OVF1 flag TIP01 pin input TP0CCR1 register <1>...
Page 211 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 212 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TP0CE bit TIP0a pin input TP0CCRa register INTTP0OV signal TP0OVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 213 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TP0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TP0OPT0 register. To accurately detect an overflow, read the TP0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Page 214: Pulse Width Measurement Mode (Tp0Md2 To Tp0Md0 Bits = 110)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5.7 Pulse width measurement mode (TP0MD2 to TP0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit is set to 1. Each time the valid edge input to the TIP0a pin has been detected, the count value of the 16-bit counter is stored in the TP0CCRa register, and the 16-bit counter is cleared to 0000H.
Page 215 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TP0CE bit TIP0a pin input 0000H TP0CCRa register INTTP0CCa signal INTTP0OV signal Cleared to 0 by TP0OVF bit CLR instruction Remark a = 0, 1 When the TP0CE bit is set to 1, the 16-bit counter starts counting.
Page 216 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note Setting is invalid when the TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE...
Page 217 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 6-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMP0 option register 0 (TP0OPT0) TP0CCS1 TP0CCS0 TP0OVF TP0OPT0 Overflow flag (f) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (g) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIP0a pin is detected.
Page 218 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 6-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TP0CE bit TIP00 pin input 0000H 0000H TP0CCR0 register INTTP0CC0 signal <1>...
Page 219 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TP0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TP0OPT0 register.
Page 220: Timer Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.5.8 Timer output operations The following table shows the operations and output levels of the TOP00 and TOP01 pins. Table 6-4. Timer Output Control in Each Mode Operation Mode TOP01 Pin TOP00 Pin Interval timer mode Square wave output −...
Page 221: Eliminating Noise On Capture Trigger Input Pin (Tip0A)
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6 Eliminating Noise on Capture Trigger Input Pin (TIP0a) The TIP0a pin has a digital noise eliminator. However, this circuit is valid only when the pin is used as a capture trigger input pin; it is invalid when the pin is used as an external event count input pin or external trigger input pin.
Page 222 CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) <Setting procedure> <1> Select the number of times of sampling and the sampling clock by using the PaNFC register. <2> Select the alternate function (of the TIP0a pin) by using the PMC3, PFC3, and PFCE3 registers. <3>...
Page 223: Cautions
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.7 Cautions (1) Capture operation When the capture operation is used and f /8, f /16, f /32, f /64, f /128, or the external event counter (TP0CTL1.TP0EEE bit = 1) is selected as the count clock, FFFFH, not 0000H, may be captured in the TP0CCRn register if the capture trigger is input immediately after the TP0CE bit is set to 1.
Page 224: Chapter 7 16-Bit Timer/Event Counter 0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 <R> In the V850ES/KE1+, one channel of 16-bit timer/event counter 0 is provided. 7.1 Functions 16-bit timer/event counter 01 has the following functions. (1) Interval timer 16-bit timer/event counter 01 generates an interrupt request at the preset time interval. (2) Square-wave output 16-bit timer/event counter 01 can output a square wave with any selected frequency.
Page 225: Configuration
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.2 Configuration 16-bit timer/event counter 01 includes the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counter 01 Item Configuration Time/counter 16-bit timer counter 01 (TM01) 16-bit timer capture/compare registers: 16-bit × 2 (CR010, CR011) Register Timer input 2 (TI010, TI011 pins)
Page 226 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (1) 16-bit timer counter 01 (TM01) The TM01 register is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. After reset: 0000H Address: FFFFF610H TM01 The count value of the TM01 register can be read by reading the TM01 register when the values of the...
Page 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (2) 16-bit timer capture/compare register 010 (CR010), 16-bit timer capture/compare register 011 (CR011) The CR010 and CR011 registers are 16-bit registers that are used with a capture function or comparison function selected by using the CRC01 register. Change of the value of the CR010 register while the timer is operating (TMC01.TMC013 and TMC01.TMC012 bits = other than 00) is prohibited.
Page 228 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (b) 16-bit timer capture/compare register 011 (CR011) After reset: 0000H Address: FFFFF614H CR011 When using the CR011 register as a compare register The value set to the CR011 register and the count value of the TM01 register are always compared and when these values match, an interrupt request signal (INTTM011) is generated.
Page 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (c) Setting range when used as compare register When the CR010 or CR011 register is used as a compare register, set it as shown below. Operation CR010 Register CR011 Register 0000H < N ≤ FFFFH ≤...
Page 230 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Table 7-2. Capture Operation of CR010 and CR011 Registers External Input Signal TI010 Pin Input TI011 Pin Input Capture Operation Capture operation of CRC011 bit = 1 Set values of ES101 and CRC011 bit = 0 Set values of ES111 and CR010 register TI010 pin input...
Page 231: Registers
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.3 Registers Registers used to control 16-bit timer/event counter 01 are shown below. • 16-bit timer mode control register 01 (TMC01) • Capture/compare control register 01 (CRC01) • 16-bit timer output control register 01 (TOC01) •...
Page 232 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 After reset: 00H Address: FFFFF616H <0> TMC01 TMC013 TMC012 TMC011 OVF01 TMC013 TMC012 Enable operation of 16-bit timer/event counter 01 Disables TM01 operation. Stops supplying operating clock. Clears 16-bit timer counter (TM01). Free-running timer mode Note 1 Clear &...
Page 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (2) Capture/compare control register 01 (CRC01) The CRC01 register is the register that controls the operation of the CR010 and CR011 registers. Changing the value of the CRC01 register is prohibited during operation (when the TMC01.TMC013 and TMC01.TMC012 bits = other than 00).
Page 234 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (3) 16-bit timer output control register 01 (TOC01) The TOC01 register is an 8-bit register that controls the TO01 pin output. The TOC01 register can be rewritten while only the OSPT01 bit is operating (when the TMC01.TMC013 and TMC01.TMC012 bits = other than 00).
Page 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (2/2) LVS01 LVR01 Setting of TO01 pin output status No change Initial value of TO01 pin output is low level (TO01 pin output is cleared to 0). Initial value of TO01 pin output is high level (TO01 pin output is set to 1). Setting prohibited •...
Page 236 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (4) Prescaler mode register 01 (PRM01) The PRM01 register is the register that sets the TM01 register count clock and TI010 and TI011 pin input valid edges. The PRM011 and PRM010 bits are set in combination with the SELCNT1.ISEL11 bit. Refer to 7.3 (6) Count clock setting for 16-bit timer/event counter 01 for details.
Page 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (5) Selector operation control register 1 (SELCNT1) The SELCNT1 register sets the count clock of 16-bit timer/event counter 01. The SELCNT1 register is set in combination with the PRM01.PRM101 and PRM01.PRM100 bits. Refer to 7.3 (6) Count clock setting for 16-bit timer/event counter 01 for details.
Page 238: Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.4 Operation 7.4.1 Interval timer operation If the TMC01.TMC013 and TMC01.TMC012 bits are set to 11 (clear & start mode entered upon a match between the TM01 register and the CR010 register), the count operation is started in synchronization with the count clock. When the value of the TM01 register later matches the value of the CR010 register, the TM01 register is cleared to 0000H and a match interrupt signal (INTTM010) is generated.
Page 239 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-4. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 01 (TMC01) TMC013 TMC012 TMC011 OVF01 Clears and starts on match between TM01 and CR010. (b) Capture/compare control register 01 (CRC01) CRC012 CRC011 CRC010 CR010 used as compare register...
Page 240 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-5. Example of Software Processing for Interval Timer Function TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) Compare match interrupt (INTTM010) <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before PRM01 register, setting the TMC013 and TMC012 bits to 11.
Page 241: Square Wave Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.4.2 Square wave output operation When 16-bit timer/event counter 01 operates as an interval timer (refer to 7.4.1), a square wave can be output from the TO01 pin by setting the TOC01 register to 03H. When the TMC01.TMC013 and TMC01.TMC012 bits are set to 11 (count clear &...
Page 242 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-8. Example of Register Settings for Square Wave Output Operation (a) 16-bit timer mode control register 01 (TMC01) TMC013 TMC012 TMC011 OVF01 Clears and starts on match between TM01 and CR010. (b) Capture/compare control register 01 (CRC01) CRC012 CRC011 CRC010 CR010 used as compare register...
Page 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-9. Example of Software Processing for Square Wave Output Function TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) TO01 pin output Compare match interrupt (INTTM010) TO01 output control bit (TOC011, TOE01) <1>...
Page 244: External Event Counter Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.4.3 External event counter operation When the PRM01.PRM011 and PRM01.PRM010 bits are set to 11 (for counting up with the valid edge of the TI010 pin) and the TMC01.TMC013 and TMC01.TMC012 bits are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between the TM01 register and the CR010 register (INTTM010) is generated.
Page 245 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-11. Example of Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 01 (TMC01) TMC013 TMC012 TMC011 OVF01 Clears and starts on match between TM01 and CR010. (b) Capture/compare control register 01 (CRC01) CRC012 CRC011 CRC010 CR010 used as compare register...
Page 246 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-12. Example of Software Processing in External Event Counter Mode TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) TO01 pin output Compare match interrupt (INTTM010) TO01 output control bit (TOC014, TOC011, TOE01) <1>...
Page 247: Operation In Clear & Start Mode Entered By Ti010 Pin Valid Edge Input
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.4.4 Operation in clear & start mode entered by TI010 pin valid edge input When the TMC01.TMC013 and TMC01.TMC012 bits are set to 10 (clear & start mode entered by the TI010 pin valid edge input) and the count clock (set by the PRM01, SELCNT1 registers) is supplied to the timer/event counter, the TM01 register starts counting up.
Page 248 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (1) Operation in clear & start mode entered by TI010 pin valid edge input (CR010 register: compare register, CR011 register: compare register) Figure 7-13. Block Diagram of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 register: Compare Register, CR011 register: Compare Register) Edge TI010 pin...
Page 249 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-14. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Compare Register, CR011 Register: Compare Register) (a) TOC01 = 13H, PRM01 = 10H, CRC01 = 00H, TMC01 = 08H TM01 register 0000H Operable bits...
Page 250 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (2) Operation in clear & start mode entered by TI010 pin valid edge input (CR010 register: compare register, CR011 register: capture register) Figure 7-15. Block Diagram of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Compare Register, CR011 Register: Capture Register) Edge TI010 pin...
Page 251 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-16. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Compare Register, CR011 Register: Capture Register) (1/2) (a) TOC01 = 13H, PRM01 = 10H, CRC01, = 04H, TMC01 = 08H, CR010 = 0000H TM01 register 0000H Operable bits...
Page 252 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-16. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Compare Register, CR011 Register: Capture Register) (2/2) (b) TOC01 = 13H, PRM01 = 10H, CRC01 = 04H, TMC01 = 0AH, CR010 = 0003H TM01 register 0003H 0000H...
Page 253 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (3) Operation in clear & start mode entered by TI010 pin valid edge input (CR010 register: capture register, CR011 register: compare register) Figure 7-17. Block Diagram of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Compare Register) Edge TI010 pin...
Page 254 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-18. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Compare Register) (1/2) (a) TOC01 = 13H, PRM01 = 10H, CRC01 = 03H, TMC01 = 08H, CR011 = 0000H TM01 register 0000H Operable bits...
Page 255 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-18. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Compare Register) (2/2) (b) TOC01 = 13H, PRM01 = 10H, CRC01 = 03H, TMC01 = 0AH, CR011 = 0003H TM01 register 0003H 0000H...
Page 256 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (4) Operation in clear & start mode entered by TI010 pin valid edge input (CR010 register: capture register, CR011 register: capture register) Figure 7-19. Block Diagram of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Capture Register) Operable bits TMC013, TMC012...
Page 257 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-20. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Capture Register) (2/3) (b) TOC01 = 13H, PRM01 = C0H, CRC01 = 05H, TMC01 = 0AH FFFFH TM01 register 0000H...
Page 258 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-20. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input (CR010 Register: Capture Register, CR011 Register: Capture Register) (3/3) (c) TOC01 = 13H, PRM01 = 00H, CRC01 = 07H, TMC01 = 0AH TM01 register 0000H Operable bits...
Page 259 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-21. Example of Register Settings in Clear & Start Mode Entered by TI010 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 01 (TMC01) TMC013 TMC012 TMC011 OVF01 0: Inverts TO01 output on match between CR010 and CR011.
Page 260 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-21. Example of Register Settings in Clear & Start Mode Entered by TI010 Pin Valid Edge Input (2/2) (d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1) ES111 ES110 ES101 ES100 PRM011 PRM010 ISEL11...
Page 261 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-22. Example of Software Processing in Clear & Start Mode Entered by TI010 Pin Valid Edge Input TM01 register 0000H Operable bits (TMC013, TMC012) Count clear input (TI010 pin input) Compare register (CR010) Compare match interrupt (INTTM010) Compare register...
Page 262: Free-Running Timer Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.4.5 Free-running timer operation When the TMC01.TMC013 and TMC01.TMC012 bits are set to 01 (free-running timer mode), 16-bit timer/event counter 01 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (TMC01.OVF01 bit) is set to 1 at the next clock, and the TM01 register is cleared (to 0000H) and continues counting.
Page 263 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-24. Timing Example of Free-Running Timer Mode (CR010 Register: Compare Register, CR011 Register: Compare Register) • TOC01 = 13H, PRM01 = 00H, CRC01 = 00H, TMC01 = 04H FFFFH TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010)
Page 264 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-26. Timing Example of Free-Running Timer Mode (CR010 Register: Compare Register, CR011 Register: Capture Register) • TOC01 = 13H, PRM01 = 10H, CRC01 = 04H, TMC01 = 04H FFFFH TM01 register 0000H Operable bits (TMC013, TMC012) Capture trigger input (TI010)
Page 265 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (3) Free-running timer mode operation (CR010 register: capture register, CR011 register: capture register) Figure 7-27. Block Diagram of Free-Running Timer Mode (CR010 Register: Capture Register, CR011 Register: Capture Register) Operable bits TMC013, TMC012 16-bit counter Count clock (TM01) Capture register...
Page 266 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-28. Timing Example of Free-Running Timer Mode (CR010 Register: Capture Register, CR011 Register: Capture Register) (1/2) (a) TOC01 = 13H, PRM01 = 0 to 50H, CRC01 = 05H, TMC01 = 04H FFFFH TM01 register 0000H Operable bits (TMC013, TMC012)
Page 267 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-28. Timing Example of Free-Running Timer Mode (CR010 Register: Capture Register, CR011 Register: Capture Register) (2/2) (b) TOC01 = 13H, PRM01 = C0H, CRC01 = 05H, TMC01 = 04H FFFFH TM01 register 0000H Operable bits (TMC013, TMC012) Capture trigger input...
Page 268 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-29. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 01 (TMC01) TMC013 TMC012 TMC011 OVF01 0: Inverts TO01 pin output on match between CR010 and CR011. 1: Inverts TO01 pin output on match between CR010 and CR011 and valid edge of TI010 pin.
Page 269 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-29. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 01 (PRM01), selector operation control register 1 (SELCNT1) ES111 ES110 ES101 ES100 PRM011 PRM010 ISEL11 PRM01 SELCNT1 Count clock selection (setting TI010 valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection...
Page 270 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-30. Example of Software Processing in Free-Running Timer Mode FFFFH TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) Timer output control bits (TOE01, TOC014, TOC011) TO01 pin output <1>...
Page 271: Ppg Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.4.6 PPG output operation A rectangular wave having a pulse width set in advance by the CR011 register is output from the TO01 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by the CR010 register when the TMC01.TMC013 and TMC01.TMC012 bits are set to 11 (clear &...
Page 272 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-32. Example of Register Settings for PPG Output Operation (a) 16-bit timer mode control register 01 (TMC01) TMC013 TMC012 TMC011 OVF01 Clears and starts on match between TM01 and CR010. (b) Capture/compare control register 01 (CRC01) CRC012 CRC011 CRC010 CR010 used as compare register...
Page 273 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-33. Example of Software Processing for PPG Output Operation TM01 register 0000H Operable bits (TMC013, TMC012) Compare register (CR010) Compare match interrupt (INTTM010) Compare register (CR011) Compare match interrupt (INTTM011) Timer output control bits (TOE01, TOC014, TOC011) TO01 pin output N + 1...
Page 274: One-Shot Pulse Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.4.7 One-shot pulse output operation A one-shot pulse can be output by setting the TMC01.TMC013 and TMC01.TMC012 bits to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI010 pin valid edge) and setting the TOC01.OSPE01 bit to 1. When the TOC01.OSPT01 is set to 1 or when the valid edge is input to the TI010 pin during timer operation, clearing &...
Page 275 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-35. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 01 (TMC01) TMC013 TMC012 TMC011 OVF01 01: Free running timer mode 10: Clear and start mode by valid edge of TI010 pin.
Page 276 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-35. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) This register is used as a compare register when a one-shot pulse is output.
Page 277 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-36. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH TM01 register 0000H Operable bits 01 or 10 (TMC013, TMC012) One-shot pulse enable bit (OSPE1) One-shot pulse trigger bit (OSPT1) One-shot pulse trigger input (TI010 pin) Overflow plug (OVF01)
Page 278 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-36. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM01 register, before setting the TMC013 and TMC012 bits. SELCNT1 register, CRC01 register, Note...
Page 279: Pulse Width Measurement Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.4.8 Pulse width measurement operation The TM01 register can be used to measure the pulse width of the signal input to the TI010 and TI011 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 01 in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI010 pin.
Page 280 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 A pulse width can be measured in the following three ways. • Measuring the pulse width by using two input signals of the TI010 and TI011 pins (free-running timer mode) • Measuring the pulse width by using one input signal of the TI010 pin (free-running timer mode) •...
Page 281 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (2) Measuring the pulse width by using one input signal of the TI010 pin (free-running timer mode) Set the free-running timer mode (the TMC01.TMC013 and TMC01.TMC012 bits = 01). The count value of the TM01 register is captured to the CR010 register in the phase reverse to the valid edge detected on the TI010 pin.
Page 282 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (3) Measuring the pulse width by using one input signal of the TI010 pin (clear & start mode entered by the TI010 pin valid edge input) Set the clear & start mode entered by the TI010 pin valid edge (the TMC01.TMC013 and TMC01.TMC012 bits = 10).
Page 283 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-42. Example of Register Settings for Pulse Width Measurement Operation (1/2) (a) 16-bit timer mode control register 01 (TMC01) TMC013 TMC012 TMC011 OVF01 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI010 pin.
Page 284 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-42. Example of Register Settings for Pulse Width Measurement Operation (2/2) (e) 16-bit timer counter 01 (TM01) By reading the TM01 register, the count value can be read. (f) 16-bit capture/compare register 010 (CR010) This register is used as a capture register.
Page 285 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-43. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode FFFFH TM01 register 0000H Operable bits (TMC013, TMC012) Capture trigger input (TI010) Capture register 0000H (CR011) Capture interrupt (INTTM011) Capture trigger input (TI011)
Page 286 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 Figure 7-43. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM01 register, before setting the TMC013 and TMC012 bits. SELCNT1 register, CRC01 register, port setting...
Page 287: Special Use Of Tm01
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.5 Special Use of TM01 7.5.1 Rewriting CR011 register during TM01 operation In principle, rewriting the CR010 and CR011 registers of the V850ES/KE1+ when they are used as compare registers is prohibited while the TM01 register is operating (TMC01.TMC013 and TMC01.TMC012 bits = other than 00).
Page 288 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (2) Setting the LVS01 and LVR01 bits Set the LVS01 and LVR01 bits using the following procedure. Figure 7-44. Example of Flow for Setting LVS01 and LVR01 Bits Setting TOC01.OSPE01, TOC014, TOC011 bits <1> Setting of timer output operation Setting TOC01.TOE01 Setting...
Page 289: Cautions
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 7.6 Cautions (1) Alternate functions of TI010/TO01 pins Channel Alternate function Remarks TM01 TI010 P35/TO01 Shares the pin with TO01. − TI011 P50/KR0/RTP00 TO01 P32/ASCK0/ADTRG Assigned to two pins, P32 and P35. P35/TI010 • To perform the one-shot pulse output with detecting the valid edge of the TI010 pin as a trigger, use the output of the TO01 pin that functions alternately as P32.
Page 290 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (4) Data hold timing of capture register (a) If the valid edge of the TI011/TI010 pin is input while the CR010/CR011 register is read, the CR010/CR011 register performs capture operation, but the read value at this time is not guaranteed. However, the interrupt request signal (INTTM010/INTTM011) is generated as a result of detection of the valid edge.
Page 291 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (7) Operation of OVF01 flag (a) Setting of OVF01 flag The TMC01.OVF01 flag is set to 1 in the following case in addition to when the TM01 register overflows. Select the mode in which clear & start occurs upon match between the TM01 register and the CR010 register.
Page 292 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0 (9) Capture operation (a) If valid edge of TI010 pin is specified for count clock If the valid edge of the TI010 pin is specified for the count clock, the capture register that specified the TI010 pin as the trigger does not operate normally.
Page 293: Chapter 8 8-Bit Timer/Event Counter 5
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 In the V850ES/KE1+, two channels of 8-bit timer/event counter 5 are provided. 8.1 Functions 8-bit timer/event counter 5n has the following two modes (n = 0, 1). • Mode using 8-bit timer/event counter alone (individual mode) •...
Page 294: Configuration
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.2 Configuration 8-bit timer/event counter 5n consists of the following hardware. Table 8-1. Configuration of 8-Bit Timer/Event Counter 5n Item Configuration Timer registers 8-bit timer counters 50, 51 (TM50, TM51) 16-bit timer counter 5 (TM5): Only when using cascade connection Registers 8-bit timer compare registers 50, 51 (CR50, CR51) 16-bit timer compare register 5 (CR5): Only when using cascade connection...
Page 295 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 (1) 8-bit timer counter 5n (TM5n) The TM5n register is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. Through cascade connection, the TM5n registers can be used as a 16-bit timer. When using the TM50 register and the TM51 register in cascade as a 16-bit timer, these registers can be read only in 16-bit units.
Page 296 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 (2) 8-bit timer compare register 5n (CR5n) The CR5n register can be read and written in 8-bit units. In a mode other than the PWM mode, the value set to the CR5n register is always compared to the count value of the TM5n register, and if the two values match, an interrupt request signal (INTTM5n) is generated.
Page 297: Registers
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.3 Registers The following two registers are used to control 8-bit timer/event counter 5n. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) Remark To use the functions of the TI5n and TO5n pins, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions.
Page 298 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 (2) 8-bit timer mode control register 5n (TMC5n) The TMC5n register performs the following six settings. • Controls counting by the TM5n register • Selects the operation mode of the TM5n register • Selects the individual mode or cascade connection mode •...
Page 299 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 After reset: 00H Address: TMC50 FFFFF5C6H, TMC51 FFFFF5C7H <7> <0> Note TMC5n TCE5n TMC5n6 TMC514 LVS5n LVR5n TMC5n1 TOE5n (n = 0, 1) TCE5n Control of count operation of 8-bit timer/event counter 5n Counting is disabled after the counter is cleared to 0 (counter disabled) Start count operation TMC5n6 Selection of operation mode of 8-bit timer/event counter 5n...
Page 300: Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.4 Operation 8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that repeatedly generates interrupts at the interval of the count value preset in the CR5n register. If the count value in the TM5n register matches the value set in the CR5n register, the value of the TM5n register is cleared to 00H and counting is continued, and at the same time, an interrupt request signal (INTTM5n) is generated.
Page 301 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 Figure 8-2. Timing of Interval Timer Operation (2/2) When CR5n register = 00H Count clock TM5n count value CR5n TCE5n INTTM5n Interval time Remark n = 0, 1 When CR5n register = FFH Count clock TM5n count value FEH FFH FEH FFH...
Page 302: Operation As External Event Counter
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.4.2 Operation as external event counter The external event counter counts the number of clock pulses input to the TI5n pin from an external source by using the TM5n register. Each time the valid edge specified by the TCL5n register is input to the TI5n pin, the TM5n register is incremented. Either the rising edge or the falling edge can be specified as the valid edge.
Page 303: Square-Wave Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.4.3 Square-wave output operation A square wave with any frequency can be output at an interval determined by the value preset in the CR5n register. By setting the TMC5n.TOE5n bit to 1, the output status of the TO5n pin is inverted at an interval determined by the count value preset in the CR5n register.
Page 304 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 Figure 8-4. Timing of Square-Wave Output Operation Count clock TM5n count value Count start Clear Clear CR5n TCE5n INTTM5n Interrupt Interrupt acknowledgment acknowledgment Note TO5n Interval time Interval time Note The initial value of the TO5n pin output can be set using the TMC5n.LVS5n and TMC5n.LVR5n bits.
Page 305: 8-Bit Pwm Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.4.4 8-bit PWM output operation By setting the TMC5n.TMC5n6 bit to 1, 8-bit timer/event counter 5n performs PWM output. Pulses with a duty factor determined by the value set in the CR5n register are output from the TO5n pin. Set the width of the active level of the PWM pulse in the CR5n register.
Page 306 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 (a) Basic operation of PWM output Figure 8-5. Timing of PWM Output Operation Basic operation (active level = H) Count clock TM5n count value N + 1 CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level When CR5n register = 00H Count clock...
Page 307 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 (b) Operation based on CR5n register transitions Figure 8-6. Timing of Operation Based on CR5n Register Transitions When the value of the CR5n register changes from N to M before the rising edge of the FFH clock →...
Page 308: Operation As Interval Timer (16 Bits)
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.4.5 Operation as interval timer (16 bits) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. 8-bit timer/event counter 5n operates as an interval timer by repeatedly generating interrupts using the count value preset in 16-bit timer compare register 5 (CR5) as the interval.
Page 309 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 Figure 8-7 shows a timing example of the cascade connection mode with 16-bit resolution. Figure 8-7. Cascade Connection Mode with 16-Bit Resolution Count clock N + 1 TM50 count value M − 1 TM51 count value CR50 CR51 TCE50...
Page 310: Operation As External Event Counter (16 Bits)
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.4.6 Operation as external event counter (16 bits) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. The external event counter counts the number of clock pulses input to the TI50 pin from an external source using 16-bit timer counter 5 (TM5).
Page 311: Square-Wave Output Operation (16-Bit Resolution)
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.4.7 Square-wave output operation (16-bit resolution) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (CR5).
Page 312: Cautions
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5 8.4.8 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because the TM5n register is started asynchronously to the count pulse. Figure 8-8.
Page 313: Chapter 9 8-Bit Timer H
CHAPTER 9 8-BIT TIMER H In the V850ES/KE1+, two channels of 8-bit timer H are provided. 9.1 Functions 8-bit timer Hn has the following functions. • Interval timer • Square wave output • PWM output • Carrier generator Remark n = 0, 1 9.2 Configuration 8-bit timer Hn consists of the following hardware.
Page 314 CHAPTER 9 8-BIT TIMER H The block diagram of 8-bit timer Hn is shown below. Figure 9-1. Block Diagram of 8-Bit Timer Hn Internal bus 8-bit timer H mode 8-bit timer H carrier control register n (TMHMDn) register n (TMCYCn) 8-bit timer H compare 8-bit timer H compare RMCn NRZBn...
Page 315 CHAPTER 9 8-BIT TIMER H (2) 8-bit timer H compare register n1 (CMPn1) <R> The CMPn1 register can be read or written in 8-bit units. This register is used in the PWM output mode and carrier generator mode. In the PWM output mode, this register constantly compares the value set to the CMPn1 register with the count value of 8-bit timer counter Hn and, when the two values match, inverts the output level of the TOHn pin.
Page 316: Registers
CHAPTER 9 8-BIT TIMER H 9.3 Registers The registers that control 8-bit timer Hn are as follows. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register n (TMCYCn) Remarks 1. To use the TOHn pin function, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions.
Page 317 CHAPTER 9 8-BIT TIMER H (a) 8-bit timer H mode register 0 (TMHMD0) After reset: 00H Address: FFFFF580H <7> <1> <0> TMHMD0 TMHE0 CKSH02 CKSH01 CKSH00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 8-bit timer H0 operation enable Stop timer count operation (8-bit timer counter H0 = 00H) Enable timer count operation (Counting starts when clock is input) CKSH02 CKSH01...
Page 318 CHAPTER 9 8-BIT TIMER H (b) 8-bit timer H mode register 1 (TMHMD1) After reset: 00H Address: FFFFF590H <7> <1> <0> TMHMD1 TMHE1 CKSH12 CKSH11 CKSH10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 8-bit timer H1 operation enable Stop timer count operation (8-bit timer counter H1 = 00H) Enable timer count operation (Counting starts when clock is input) CKSH12 CKSH11...
Page 319 CHAPTER 9 8-BIT TIMER H (2) 8-bit timer H carrier control register n (TMCYCn) This register controls the 8-bit timer Hn remote control output and carrier pulse output status. The TMCYCn register can be read or written in 8-bit or 1-bit units. The NRZn bit is a read-only bit. Reset sets this register to 00H.
Page 320: Operation
CHAPTER 9 8-BIT TIMER H 9.4 Operation 9.4.1 Operation as interval timer/square wave output When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. The CMPn1 register cannot be used in the interval timer mode.
Page 321 CHAPTER 9 8-BIT TIMER H Figure 9-3. Timing of Interval Timer/Square Wave Output Operation (1/2) Basic operation (operation when 01H ≤ CMPn0 ≤ FEH) Count clock Count start 8-bit timer counter 01H 00H Hn count value Clear Clear CMPn0 TMHEn INTTMHn Interval time TOHn...
Page 322 CHAPTER 9 8-BIT TIMER H Figure 9-3. Timing of Interval Timer/Square Wave Output Operation (2/2) Operation when CMPn0 register = FFH Count clock Count start 8-bit timer counter Hn count value Clear Clear CMPn0 TMHEn Interval time INTTMHn TOHn Operation when CMPn0 register = 00H Count clock Count start 8-bit timer counter...
Page 323: Pwm Output Mode Operation
CHAPTER 9 8-BIT TIMER H 9.4.2 PWM output mode operation In the PWM output mode, a pulse of any duty and cycle can be output. The CMPn0 register controls the timer output (TOHn) cycle. Rewriting the CMPn0 register during timer operation is prohibited.
Page 324 CHAPTER 9 8-BIT TIMER H <3> After the count operation is enabled, the first compare register to be compared is the CMPn0 register. When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and the TOHn output level is inverted.
Page 325 CHAPTER 9 8-BIT TIMER H Figure 9-5. Operation Timing in PWM Output Mode (1/4) Basic operation Count clock 8-bit timer counter 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H Hn count value CMPn0 CMPn1 TMHEn INTTMHn TOHn (TOLEVn = 0) <3>...
Page 326 CHAPTER 9 8-BIT TIMER H Figure 9-5. Operation Timing in PWM Output Mode (2/4) Operation when CMPn0 register = FFH, CMPn1 register = 00H Count clock 8-bit timer counter 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H Hn count value CMPn0 CMPn1...
Page 327 CHAPTER 9 8-BIT TIMER H Figure 9-5. Operation Timing in PWM Output Mode (3/4) Operation when CMPn0 register = 01H, CMPn1 register = 00H Count clock 8-bit timer counter 01H 00H 01H 00H 00H 01H 00H 01H Hn count value CMPn0 CMPn1 TMHEn...
Page 328 CHAPTER 9 8-BIT TIMER H Figure 9-5. Operation Timing in PWM Output Mode (4/4) <R> Operation based on CMPn1 register transitions (CMPn1 register = 02H → 03H, CMPn0 register = A5H) Count clock 8-bit timer 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H counter Hn...
Page 329: Carrier Generator Mode Operation
CHAPTER 9 8-BIT TIMER H 9.4.3 Carrier generator mode operation The carrier clock generated by 8-bit timer Hn is output using the cycle set with 8-bit timer/event counter 5n. In the carrier generator mode, 8-bit timer/event counter 5n is used to control the extent to which the carrier pulse of 8-bit timer Hn is output, and the carrier pulse is output from the TOHn output.
Page 330 CHAPTER 9 8-BIT TIMER H To control carrier pulse output during count operation, the TMCYCn.NRZn and TMCYCn.NRZBn bits have a master and slave bit configuration. The NRZn bit is read-only while the NRZBn bit can be read and written. The INTTM5n signal is synchronized with the 8-bit timer Hn clock and output as the INTTM5Hn signal. The INTTM5Hn signal becomes the data transfer signal of the NRZn bit and the value of the NRZBn bit is transferred to the NRZn bit.
Page 331 CHAPTER 9 8-BIT TIMER H Setting <1> Set each register. Figure 9-7. Register Settings in Carrier Generator Mode • 8-bit timer H mode register n (TMHMDn) TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn TOENn TMHMDn Enables timer output Sets timer output default level Selects carrier generator mode Selects count clock (f Stops count operation...
Page 332 CHAPTER 9 8-BIT TIMER H Designating the set value of the CMPn0 register as (N), the set value of the CMPn1 register as (M), and the count clock frequency as f , the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/f Duty = High level width: Carrier clock output width = (M + 1) : (N + M + 2) Cautions 1.
Page 333 CHAPTER 9 8-BIT TIMER H Figure 9-8. Carrier Generator Mode (1/3) Operation when CMPn0 register = N, CMPn1 register = N is set 8-bit timer Hn count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H Hn count value CMPn0 CMPn1...
Page 334 CHAPTER 9 8-BIT TIMER H Figure 9-8. Carrier Generator Mode (2/3) Operation when CMPn0 register = N, CMPn1 register = M is set 8-bit timer Hn count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H Hn count value CMPn0 CMPn1...
Page 335 CHAPTER 9 8-BIT TIMER H Figure 9-8. Carrier Generator Mode (3/3) Operation based on CMPn1 register transitions 8-bit timer Hn count clock 8-bit timer counter 00H 01H 00H 01H Hn count value CMPn0 <3> <3>’ <R> CMPn1 M (L) TMHEn INTTMHn <4>...
Page 336: Chapter 10 Interval Timer, Watch Timer
CHAPTER 10 INTERVAL TIMER, WATCH TIMER The V850ES/KE1+ includes interval timer BRG and a watch timer. Interval timer BRG can also be used as the source clock of the watch timer. The watch timer can also be used as interval timer WT. Two interval timer channels and one watch timer channel can be used at the same time.
Page 337 CHAPTER 10 INTERVAL TIMER, WATCH TIMER (1) Clock control The clock control controls supply/stop of the operation clock (f ) of interval timer BRG. (2) 3-bit prescaler The 3-bit prescaler divides f to generate f /2, f /4, and f (3) Selector The selector selects the count clock (f ) for interval timer BRG from f...
Page 338: Registers
CHAPTER 10 INTERVAL TIMER, WATCH TIMER 10.1.3 Registers Interval timer BRG includes the following registers. (1) Interval timer BRG mode register (PRSM) PRSM controls the operation of interval timer BRG, selection of count clock, and clock supply to the watch timer.
Page 339 CHAPTER 10 INTERVAL TIMER, WATCH TIMER (2) Interval timer BRG compare register (PRSCM) PRSCM is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF8B1H PRSCM PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0...
Page 340: Operation
CHAPTER 10 INTERVAL TIMER, WATCH TIMER 10.1.4 Operation (1) Operation of interval timer BRG Set the count clock by using the PRSM.BGCS1 and PRSM.BGCS0 bits and the 8-bit compare value by using the PRSCM register. When the PRSM.BGCE bit is set (1), interval timer BRG starts operating. Each time the count value of the 8-bit counter and the set value in the PRSCM register match, an interrupt request signal (INTBRG) is generated.
Page 341: Watch Timer
CHAPTER 10 INTERVAL TIMER, WATCH TIMER 10.2 Watch Timer 10.2.1 Functions The watch timer has the following functions. • Watch timer: An interrupt request signal (INTWT) is generated at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. •...
Page 342: Register
CHAPTER 10 INTERVAL TIMER, WATCH TIMER (1) 11-bit prescaler The 11-bit prescaler generates a clock of f to f by dividing f (2) 5-bit counter The 5-bit counter generates the watch timer interrupt request signal (INTWT) at intervals of 2 or 2 by counting f or f...
Page 343 CHAPTER 10 INTERVAL TIMER, WATCH TIMER After reset: 00H Address: FFFFF680H < > < > WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 WTM7 WTM6 WTM5 WTM4 Selection of interval timer interrupt (INTWTI) time μ (488 s: f μ (977 s: f (1.95 ms: f (3.91 ms: f (7.81 ms: f...
Page 344: Operation
CHAPTER 10 INTERVAL TIMER, WATCH TIMER 10.2.4 Operation (1) Operation as watch timer The watch timer generates an interrupt request at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz). The count operation starts when the WTM.WTM0 and WTM.WTM1 bits are set to 11.
Page 345 CHAPTER 10 INTERVAL TIMER, WATCH TIMER Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T)
Page 346: Cautions
CHAPTER 10 INTERVAL TIMER, WATCH TIMER 10.3 Cautions (1) Operation as watch timer Some time is required before the first watch timer interrupt request signal (INTWT) is generated after operation is enabled (WTM.WTM1 and WTM.WTM0 bits = 11). Figure 10-4. Example of Generation of Watch Timer Interrupt Request Signal (INTWT) (When Interrupt Period = 0.5 s) ×...
Page 347: Chapter 11 Watchdog Timer Functions
CHAPTER 11 WATCHDOG TIMER FUNCTIONS 11.1 Watchdog Timer 1 11.1.1 Functions Watchdog timer 1 has the following operation modes. • Watchdog timer • Interval timer The following functions are realized from the above-listed operation modes. • Generation of non-maskable interrupt request signal (INTWDT1) upon overflow of watchdog timer 1 Note •...
Page 348 CHAPTER 11 WATCHDOG TIMER FUNCTIONS Figure 11-1. Block Diagram of Watchdog Timer 1 Internal bus Watchdog timer clock Watchdog timer mode selection register (WDCS) register 1 (WDTM1) RUN1 WDTM14 WDTM13 WDCS2 WDCS1 WDCS0 Clear Prescaler INTWDTM1 Output INTWDT1 controller WDTRES1 Remark INTWDTM1: Request signal for maskable interrupt through watchdog timer 1 overflow INTWDT1: Request signal for non-maskable interrupt through watchdog timer 1 overflow...
Page 349: Configuration
CHAPTER 11 WATCHDOG TIMER FUNCTIONS 11.1.2 Configuration Watchdog timer 1 consists of the following hardware. Table 11-1. Configuration of Watchdog Timer 1 Item Configuration Control registers Watchdog timer clock selection register (WDCS) Watchdog timer mode register 1 (WDTM1) 11.1.3 Registers The registers that control watchdog timer 1 are as follows.
Page 350 CHAPTER 11 WATCHDOG TIMER FUNCTIONS (2) Watchdog timer mode register 1 (WDTM1) This register sets the watchdog timer 1 operation mode and enables/disables count operations. This register is a special register that can be written only in a special sequence (refer to 3.4.7 Special registers).
Page 351: Operation
CHAPTER 11 WATCHDOG TIMER FUNCTIONS 11.1.4 Operation (1) Operation as watchdog timer 1 Watchdog timer 1 operation to detect a program loop is selected by setting the WDTM1.WDTM14 bit to 1. The count clock (program loop detection time interval) of watchdog timer 1 can be selected using the WDCS.WDCS0 to WDCS.WDCS2 bits.
Page 352 CHAPTER 11 WATCHDOG TIMER FUNCTIONS (2) Operation as interval timer Watchdog timer 1 can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by clearing the WDTM1.WDTM14 bit to 0. When watchdog timer 1 operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification flags (WDTPR0 to WDTPR2) of the WDTIC register are valid and maskable interrupt request signals (INTWDTM1) can be generated.
Page 353: Watchdog Timer 2
CHAPTER 11 WATCHDOG TIMER FUNCTIONS 11.2 Watchdog Timer 2 11.2.1 Functions Watchdog timer 2 has the following functions. • Default start watchdog timer Note 1 → Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDTRES2 signal) →...
Page 354: Configuration
CHAPTER 11 WATCHDOG TIMER FUNCTIONS 11.2.2 Configuration Watchdog timer 2 consists of the following hardware. Table 11-4. Configuration of Watchdog Timer 2 Item Configuration Control registers Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE) 11.2.3 Registers (1) Watchdog timer mode register 2 (WDTM2) This register sets the overflow time and operation clock of watchdog timer 2.
Page 355 CHAPTER 11 WATCHDOG TIMER FUNCTIONS Table 11-5. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected Clock Program Loop Detection Time Note 17.1 ms (f = 240 kHz (TYP.)) Note 34.1 ms (f = 240 kHz (TYP.)) Note 68.2 ms (f = 240 kHz (TYP.)) Note...
Page 356: Operation
CHAPTER 11 WATCHDOG TIMER FUNCTIONS 11.2.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset through byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using 8-bit memory manipulation instructions. After this is done, the operation of watchdog timer 2 cannot be stopped.
Page 357: Chapter 12 Real-Time Output Function (Rto)
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.1 Function The real-time output function (RTO) transfers preset data to the RTBL0 and RTBH0 registers, and then transfers this data with hardware to an external device via the real-time output latches, upon occurrence of a timer interrupt. The pins through which the data is output to an external device constitute a port called a real-time output port.
Page 358: Configuration
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.2 Configuration RTO consists of the following hardware. Table 12-1. Configuration of RTO Item Configuration Registers Real-time output buffer register 0 (RTBL0, RTBH0) Control registers Real-time output port mode register 0 (RTPM0) Real-time output port control register 0 (RTPC0) (1) Real-time output buffer register 0 (RTBL0, RTBH0) RTBL0 and RTBH0 are 4-bit registers that hold output data in advance.
Page 359: Registers
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.3 Registers RTO is controlled using the following two types of registers. • Real-time output port mode register 0 (RTPM0) • Real-time output port control register 0 (RTPC0) (1) Real-time output port mode register 0 (RTPM0) This register selects the real-time output port mode or port mode in 1-bit units.
Page 360 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register 0 (RTPC0) This register sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Table 12-3.
Page 361: Operation
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.4 Operation If the real-time output operation is enabled by setting the RTPC0.RTPOE0 bit to 1, the data of the RTBH0 and RTBL0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPC0.EXTR0 and RTPC0.BYTE0 bits).
Page 362: Usage
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.5 Usage (1) Disable real-time output. Clear the RTPC0.RTPOE0 bit to 0. (2) Perform initialization as follows. • Specify the real-time output port mode or port mode in 1-bit units. Set the RTPM0 register. •...
Page 363: Security Function
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.7 Security Function A circuit that sets the pin outputs to high impedance as a security function for when malfunctions of a stepping motor controlled by RTO occur is provided on chip. It forcibly resets the pins allocated to RTP00 to RTP05 via external interrupt INTP0 pin edge detection, placing them in the high-impedance state.
Page 364 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the RTO security function and PLL. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H. After reset: 01H Address: FFFFF806H <...
Page 365: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Overview The A/D converter converts analog input signals into digital values and has an 8-channel (ANI0 to ANI7) configuration. The A/D converter has the following functions. ○ Operating voltage (AV ): 2.7 to 5.5 V REF0 ○...
Page 366: Configuration
CHAPTER 13 A/D CONVERTER 13.3 Configuration The A/D converter consists of the following hardware. Figure 13-1. Block Diagram of A/D Converter REF0 ADCS bit ANI0 ANI1 Sample & hold circuit ANI2 Voltage comparator ANI3 ANI4 ANI5 SAR register ANI6 ANI7 INTAD INTTM010 Controller...
Page 367 CHAPTER 13 A/D CONVERTER (1) ANI0 to ANI7 pins These are analog input pins for the 8 channels of the A/D converter. They are used to input analog signals to be converted into digital signals. Pins other than those selected as analog input by the ADS register can be used as input ports.
Page 368: Registers
CHAPTER 13 A/D CONVERTER (10) A/D converter mode register (ADM) This register sets the conversion time of the analog input to be converted to a digital signal and the conversion operation start/stop. (11) Analog input channel specification register (ADS) This register specifies the input port for the analog voltage to be converted to a digital signal. (12) Power fail comparison mode register (PFM) This register sets the power fail detection mode.
Page 369 CHAPTER 13 A/D CONVERTER After reset: 00H Address: FFFFF200H < > < > Note 1 Note 1 Note 1 Note 1 Note 1 ADCS ADMD ADHS1 ADHS0 ADCS2 ADCS Control of A/D conversion operation Conversion operation stopped Conversion operation enabled ADMD Control of operation mode Select mode...
Page 370 CHAPTER 13 A/D CONVERTER Table 13-2. A/D Conversion Time μ ADHS1 ADHS0 FR2 A/D Conversion Time ( Conversion Time Mode 20 MHz@ 16 MHz@ 8 MHz@ 8 MHz@ ≥ 4.5 V ≥ 4.0 V ≥ 2.85 V ≥ 2.7 V REF0 REF0 REF0...
Page 371 CHAPTER 13 A/D CONVERTER (a) Controlling reference voltage generator for boosting μ When the ADCS2 bit = 0, power to the A/D converter drops. The converter requires a setup time of 1 μ (high-speed mode) or 14 s (normal mode) or more after the ADCS2 bit has been set to 1. Therefore, the result of A/D conversion becomes valid from the first result by setting the ADCS bit to 1 at μ...
Page 372 CHAPTER 13 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the analog voltage input port for A/D conversion. The ADS register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF201H Note 1...
Page 373 CHAPTER 13 A/D CONVERTER (3) A/D conversion result register, A/D conversion result register H (ADCR, ADCRH) The ADCR and ADCRH registers store the A/D conversion results. These registers are read-only in 16-bit or 8-bit units. However, specify the ADCR register for 16-bit access, and the ADCRH register for 8-bit access.
Page 374 CHAPTER 13 A/D CONVERTER The following shows the relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and A/D conversion results (ADCR register). × 1024 + 0.5) SAR = INT ( REF0 = SAR × 64 Note ADCR REF0...
Page 375 CHAPTER 13 A/D CONVERTER (4) Power fail comparison mode register (PFM) This register sets the power fail detection mode. The PFM register compares the value in the PFT register with the value of the ADCRH register. The PFM register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 376 CHAPTER 13 A/D CONVERTER (5) Power fail comparison threshold register (PFT) The PFT register sets the comparison value in the power fail detection mode. The 8-bit data set in the PFT register is compared with the value of the ADCRH register. The PFT register can be read or written in 8-bit units.
Page 377: Operation
CHAPTER 13 A/D CONVERTER 13.5 Operation 13.5.1 Basic operation <1> Select the channel whose analog signal is to be converted into a digital signal using the ADS register. Set the ADM.ADHS1 or ADM.ADHS0 bit. μ μ <2> Set the ADM.ADCS2 bit to 1 and wait 1 s (high-speed mode) or 14 s (normal mode) or longer.
Page 378: Trigger Modes
CHAPTER 13 A/D CONVERTER 13.5.2 Trigger modes The V850ES/KE1+ has the following three trigger modes that set the A/D conversion start timing. These trigger modes are set by the ADS register. • Software trigger mode • External trigger mode (hardware trigger mode) •...
Page 379: Operation Modes
CHAPTER 13 A/D CONVERTER 13.5.3 Operation modes The following two operation modes are available. These operation modes are set by the ADM register. • Select mode • Scan mode (1) Select mode One input analog signal specified by the ADS register while the ADM.ADMD bit = 0 is converted. When conversion is complete, the result of conversion is stored in the ADCR register.
Page 380 CHAPTER 13 A/D CONVERTER (2) Scan mode In this mode, the analog signals specified by the ADS register and input from the ANI0 pin while the ADM.ADMD bit = 1 are sequentially selected and converted. When conversion of one analog input signal is complete, the conversion result is stored in the ADCR register and, at the same time, the A/D conversion end interrupt request signal (INTAD) is generated.
Page 381 CHAPTER 13 A/D CONVERTER Figure 13-5. Example of Scan Mode Operation Timing (ADS.ADS2 to ADS.ADS0 Bits = 0011B) (a) Timing example ANI0 Data 5 Data 1 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1 Data 2 Data 3 Data 4...
Page 382: Power Fail Detection Function
CHAPTER 13 A/D CONVERTER 13.5.4 Power fail detection function The conversion end interrupt request signal (INTAD) can be controlled as follows using the PFM and PFT registers. • If the PFM.PFEN bit = 0, the INTAD signal is generated each time conversion ends. •...
Page 383: Setting Method
CHAPTER 13 A/D CONVERTER 13.5.5 Setting method The following describes how to set registers. (1) When using the A/D converter for A/D conversion <1> Set (1) the ADM.ADCS2 bit. <2> Select the channel and conversion time by setting the ADS.ADS2 to ADS.ADS0 bits and the ADM.ADHS1, ADM.ADHS0, and ADM.FR2 to ADM.FR0 bits.
Page 384 CHAPTER 13 A/D CONVERTER (2) When using the A/D converter for the power fail detection function <1> Set (1) the PFM.PFEN bit. <2> Set the power fail comparison conditions by using the PFM.PFCM bit. <3> Set (1) the ADM.ADCS2 bit. <4>...
Page 385: Cautions
CHAPTER 13 A/D CONVERTER 13.6 Cautions (1) Power consumption in standby mode The operation of the A/D converter stops in the standby mode. At this time, the power consumption can be reduced by stopping the conversion operation (the ADM.ADCS bit = 0) and stopping the reference voltage circuit (ADM.ADCS2 bit = 0).
Page 386 CHAPTER 13 A/D CONVERTER (4) Measures against noise To keep a resolution of 10 bits, be aware of noise on the AV and ANI0 to ANI7 pins. The higher the output REF0 impedance of the analog input source, the greater the effect of noise. Therefore, it is recommended to connect external capacitors as shown in Figure 13-8 to reduce noise.
Page 387 CHAPTER 13 A/D CONVERTER (7) Interrupt request flag (ADIC.ADIF bit) Even when the ADS register is changed, the ADIF bit is not cleared (0). Therefore, if the analog input pin is changed during A/D conversion, the ADIF bit may be set (1) because A/D conversion of the previous analog input pin ends immediately before the ADS register is rewritten.
Page 388 CHAPTER 13 A/D CONVERTER (10) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the ADM register. A delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 13-10 and Table 13-4.
Page 389 CHAPTER 13 A/D CONVERTER Table 13-4. A/D Converter Conversion Time ADHS1 ADHS0 Conversion Time Sampling Time Register Write Trigger Response Note Note Response Time Time MIN. MAX. MIN. MAX. 288/f 176/f 11/f 12/f 240/f 176/f 11/f 12/f 192/f 132/f 10/f 11/f 144/f 88/f...
Page 390 CHAPTER 13 A/D CONVERTER (11) Internal equivalent circuit The following shows the equivalent circuit of the analog input block. Figure 13-11. Internal Equivalent Circuit of ANIn Pin ANIn REF0 4.5 V 3 kΩ 8 pF 15 pF 2.7 V 60 kΩ 8 pF 15 pF Remarks 1.
Page 391: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.7 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1 LSB (Least Significant Bit).
Page 392 CHAPTER 13 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a ±1/2 LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2 LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 393 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full scale − 3/2 LSB) when the digital output changes from 1……110 to 1……111. Figure 13-15. Full-Scale Error Full-scale error –3 –2...
Page 394 CHAPTER 13 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
Page 395: Chapter 14 Asynchronous Serial Interface (Uart)
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) In the V850ES/KE1+, two channels of asynchronous serial interface (UART) are provided. Of these channels, UART0 supports LIN-bus. 14.1 Features • Maximum transfer speed: 312.5 kbps • Full-duplex communications On-chip RXBn register On-chip TXBn register •...
Page 396: Configuration
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.2 Configuration Table 14-1. Configuration of UARTn Item Configuration Registers Receive buffer register n (RXBn) Transmit buffer register n (TXBn) Receive shift register Transmit shift register Asynchronous serial interface mode register n (ASIMn) Asynchronous serial interface status register n (ASISn) Asynchronous serial interface transmit status register n (ASIFn) LIN operation control register 0 (ASICL0) Other...
Page 397 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (7) Receive buffer register n (RXBn) The RXBn register is an 8-bit buffer register for holding receive data. When 7 characters are received, 0 is stored in the MSB. During a reception enabled state, receive data is transferred from the receive shift register to the RXBn register, synchronized with the end of the shift-in processing of one frame.
Page 398: Registers
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.3 Registers (1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register that controls the UARTn transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 01H.
Page 399 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (2/2) RXEn Reception enable/disable Note Disable reception Enable reception • Set the RXEn bit to 1 after setting the UARTEn bit to 1 at startup. Clear the UARTEn bit to 0 after clearing the RXEn bit to 0 to stop.
Page 400 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Asynchronous serial interface status register n (ASISn) The ASISn register, which consists of 3 error flag bits (PEn, FEn, and OVEn), indicates the error status when UARTn reception is complete. The ASISn register is cleared to 00H by a read operation. When a reception error occurs, the RXBn register should be read and the error flag should be cleared after the ASISn register is read.
Page 401 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (3) Asynchronous serial interface transmit status register n (ASIFn) The ASIFn register, which consists of 2 status flag bits, indicates the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmit shift register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 402 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (4) Receive buffer register n (RXBn) The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the receive shift register. When reception is enabled (ASIMn.RXEn bit = 1), receive data is transferred from the receive shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame.
Page 403 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (5) Transmit buffer register n (TXBn) The TXBn register is an 8-bit buffer register for setting transmit data. When transmission is enabled (ASIMn.TXEn bit = 1), the transmit operation is started by writing data to TXBn register.
Page 404 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (6) LIN operation control register 0 (ASICL0) The ASICL0 register is an 8-bit register that controls the output format for SBF transmission/reception and transmission. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 16H.
Page 405 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (2/2) SBL02 SBL01 SBL00 SBF transmission output width control SBF is output with 13-bit length (default) SBF is output with 14-bit length SBF is output with 15-bit length SBF is output with 16-bit length SBF is output with 17-bit length SBF is output with 18-bit length SBF is output with 19-bit length...
Page 406 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (7) Selector operation control register 0 (SELCNT0) The SELCNT0 register is an 8-bit register that selects the TM01 capture trigger. If SELCNT0.ISEL00 is set to 1 (RXD0 pin is selected) when LIN is used, the transfer rate for calculating the baud rate error can be checked using TM01.
Page 407: Interrupt Request Signals
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.4 Interrupt Request Signals The following three types of interrupt request signals are generated from UARTn. • Reception error interrupt request signal (INTSREn) • Reception completion interrupt request signal (INTSRn) • Transmission completion interrupt request signal (INTSTn) The default priorities among these three types of interrupt request signals are, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt.
Page 408: Operation
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.5 Operation 14.5.1 Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 14-2. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to the ASIMn register.
Page 409: Transmit Operation
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.5.2 Transmit operation When the ASIMn.UARTEn bit is set to 1, a high level is output from the TXDn pin. Then, when the ASIMn.TXEn bit is set to 1, transmission is enabled, and the transmit operation is started by writing transmit data to the TXBn register.
Page 410 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 14-3. UARTn Transmission Completion Interrupt Timing (a) Stop bit length: 1 Start TXDn (output) Parity Stop INTSTn (output) (b) Stop bit length: 2 Stop Parity TXDn (output) Start INTSTn (output) User’s Manual U16896EJ2V0UD...
Page 411: Continuous Transmission Operation
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.5.3 Continuous transmission operation UARTn can write the next transmit data to the TXBn register at the timing that the transmit shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the transmission completion interrupt service after the transmission of one data frame.
Page 412 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 14-4. Continuous Transmission Processing Flow Set registers Write transmit data to TXBn register When reading ASIFn register, TXBFn = 0? Write second byte transmit data to TXBn register Interrupt occurrence Required number of transfers performed? When reading When reading...
Page 413 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (1) Starting procedure The procedure to start continuous transmission is shown below. Figure 14-5. Continuous Transmission Starting Procedure Start Start Stop Stop TXDn (output) Data (1) Data (2) <1> <2> <3> <4> <5> INTSTn (output) TXBn register Data (1) Data (2)
Page 414 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Ending procedure The procedure for ending continuous transmission is shown below. Figure 14-6. Continuous Transmission End Procedure Start Start Stop Stop TXDn (output) Data (m − 1) Data (m) <6> <7> <8> <9> <10>...
Page 415: Receive Operation
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.5.4 Receive operation The awaiting reception state is set by setting the ASIMn.UARTEn bit to 1 and then setting the ASIMn.RXEn bit to 1. To start the receive operation, start sampling at the falling edge when the falling of the RXDn pin is detected. If the RXDn pin is low level at a start bit sampling point, the start bit is recognized.
Page 416 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 14-7. UARTn Reception Completion Interrupt Timing RXDn (input) Start Parity Stop INTSRn (output) RXBn register Cautions 1. Be sure to read the RXBn register even when a reception error occurs. If the RXBn register is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely.
Page 417: Reception Error
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.5.5 Reception error The three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. As a result of data reception, the various flags of the ASISn register are set (1), and a reception error interrupt request signal (INTSREn) or a reception completion interrupt request signal (INTSRn) is generated at the same time.
Page 418: Parity Types And Corresponding Operation
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.5.6 Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used on the transmission and reception sides. (1) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 419: Receive Data Noise Filter
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.5.7 Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output base clock (f ). If the same sampling UCLK value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to Figure 14-11).
Page 420: Sbf Transmission/Reception (Uart0 Only)
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.5.8 SBF transmission/reception (UART0 only) The UART0 of the V850ES/KE1+ has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network.
Page 421 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 14-13. LIN Reception Manipulation Outline Wakeup Sync Sync Data Data Checksum Ident signal frame break field field field field field field LIN bus <2> Data Data <5> SF reception ID reception 13 bits transmission transmission Data transmission...
Page 422 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) SBF transmission <R> When the device is incorporated in LIN, the SBF (Sync Break Field) transmission control function is used for transmission. For the transmission operation of LIN, refer to Figure 14-12 LIN Transmission Manipulation Outline.
Page 423 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (3) SBF reception The reception enabled status is achieved by setting the ASIM0.UARTE0 bit to 1 and then setting the ASIM0.RXE0 bit to 1. The SBF reception wait status is set by setting the SBF reception trigger (ASICL0.SBRT0 bit) to 1. In the SBF reception wait status, similarly to the UART reception wait status, the RXD0 pin is monitored and start bit detection is performed.
Page 424: Dedicated Baud Rate Generator N (Brgn)
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.6 Dedicated Baud Rate Generator n (BRGn) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by UARTn. The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 425: Serial Clock Generation
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.6.2 Serial clock generation A serial clock can be generated according to the settings of the CKSRn and BRGCn registers. The base clock to the 8-bit counter is selected by the CKSRn.TPSn3 to CKSRn.TPSn0 bits. The 8-bit counter divisor value can be set by the BRGCn.MDLn7 to BRGCn.MDLn0 bits.
Page 426 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Baud rate generator control register n (BRGCn) The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. This register can be read or written in 8-bit units. Reset sets this register to FFH.
Page 427 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) (3) Baud rate The baud rate is the value obtained by the following formula. UCLK Baud rate [bps] = 2 × k = Frequency [Hz] of base clock selected by CKSRn.TPSn3 to CKSRn.TPSn0 bits. UCLK k = Value set by BRGCn.MDLn7 to BRGCn.MDLn0 bits (k = 8, 9, 10, ..., 255) (4) Baud rate error...
Page 428: Baud Rate Setting Example
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.6.3 Baud rate setting example Table 14-4. Baud Rate Generator Setting Data = 20 MHz = 16 MHz = 10 MHz Baud Rate (bps) UCLK UCLK UCLK /512 41H (65) 0.16 /1024 1AH (26) 0.16 /256 41H (65)
Page 429: Allowable Baud Rate Range During Reception
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.6.4 Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 430 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) Therefore, the transfer destination’s maximum receivable baud rate (BRmax) is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. − × ×...
Page 431: Transfer Rate During Continuous Transmission
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART) 14.6.5 Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 432: Chapter 15 Clocked Serial Interface 0 (Csi0)
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) In the V850ES/KE1+, two channels of clocked serial interface 0 (CSI0) are provided. 15.1 Features • Maximum transfer speed: 5 Mbps • Master mode/slave mode selectable • Transmission data length: 8 bits or 16 bits can be set •...
Page 433: Configuration
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) 15.2 Configuration CSI0n is controlled via the CSIM0n register. (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register is an 8-bit register that specifies the operation of CSI0n. (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n serial transfer operation.
Page 434 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (12) Clocked serial interface initial transmit buffer register nL (SOTBFnL) The SOTBFnL register is an 8-bit buffer register that stores initial transmit data in the continuous transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock controller Controls the serial clock supply to the shift register.
Page 435 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 15-1. Block Diagram of Clocked Serial Interface Serial clock controller SCK0n Clock start/stop control Selector & clock phase control Interrupt INTCSI0n controller TO5n SCK0n Transmission control Transmission data control Control signal Initial transmit SO selection SO0n buffer register...
Page 436: Registers
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) 15.3 Registers (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register controls the CSI0n operation. This register can be read or written in 8-bit or 1-bit units (however, CSOTn bit is read-only). Reset sets this register to 00H.
Page 437 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) After reset: 00H Address: CSIM00 FFFFFD00H, CSIM01 FFFFFD10H <7> <6> <4> <0> CSIM0n CSI0En TRMDn CCLn DIRn CSITn AUTOn CSOTn (n = 0, 1) CSI0En CSI0n operation enable/disable Disable CSI0n operation. Enable CSI0n operation. Note The internal CSI0n circuit can be reset asynchronously by clearing the CSI0En bit to 0.
Page 438 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 439 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (3) Clocked serial interface receive buffer registers n, nL (SIRBn, SIRBnL) The SIRBn register is a 16-bit buffer register that stores receive data. When the receive-only mode is set (CSIM0n.TRMDn bit = 0), the reception operation is started by reading data from the SIRBn register.
Page 440 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (4) Clocked serial interface read-only receive buffer registers n, nL (SIRBEn, SIRBEnL) The SIRBEn register is a 16-bit buffer register that stores receive data. The SIRBEn register is the same as the SIRBn register. Even if the SIRBEn register is read, the next operation will not start.
Page 441 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (5) Clocked serial interface transmit buffer registers n, nL (SOTBn, SOTBnL) The SOTBn register is a 16-bit buffer register that stores transmit data. When the transmission/reception mode is set (CSIM0n.TRMDn bit = 1), the transmission operation is started by writing data to the SOTBn register.
Page 442 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (6) Clocked serial interface initial transmit buffer registers n, nL (SOTBFn, SOTBFnL) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the continuous transfer mode. The transmission operation is not started even if data is written to the SOTBFn register. This register can be read or written in 16-bit units.
Page 443 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (7) Serial I/O shift registers n, nL (SIO0n, SIO0nL) The SIO0n register is a 16-bit shift register that converts parallel data into serial data. The transfer operation is not started even if the SIO0n register is read. This register is read-only in 16-bit units.
Page 444 Table 15-1. Use of Each Buffer Register Note 1 Register Single Transfer Continuous Transfer Name Transmission/Reception Mode Receive-Only Mode Transmission/Reception Mode Receive-Only Mode • Reading starts reception Storing up to the (N − 1)th received data • Reading starts reception Note 2 SIRBn Read...
Page 445: Operation
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) 15.4 Operation 15.4.1 Transmission/reception completion interrupt request signal (INTCSI0n) The INTCSI0n signal is set (1) upon completion of data transmission/reception. Writing to the CSIM0n register clears (0) the INTCSI0n signal. Caution The delay mode (CSIM0n.CSITn bit = 1) is valid only in the master mode (CSICn.CKS0n2 to CSICn.CKS0n0 bits are not 111B).
Page 446 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 15-2. Timing Chart of INTCSI0n Signal Output in Delay Mode (a) Transmit/receive type 1 Input clock SCK0n (I/O) SI0n (input) SO0n (output) Reg_R/W INTCSI0n signal CSOTn bit Delay (b) Transmit/receive type 4 Input clock SCK0n (I/O) SI0n (input)
Page 447: Single Transfer Mode
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) 15.4.2 Single transfer mode (1) Usage In the receive-only mode (CSIM0n.TRMDn bit = 0), communication is started by reading the SIRBn/SIRBnL register. In the transmission/reception mode (TRMDn bit = 1), communication is started by writing to the SOTBn/SOTBnL register.
Page 448 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 15-3. Timing Chart in Single Transfer Mode (1/2) (a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, when AAH is received and 55H is transmitted, transmit/receive type 1 SCK0n (I/O) (55H) SO0n (output)
Page 449 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 15-3. Timing Chart in Single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, when AAH is received and 55H is transmitted, transmit/receive type 2 SCK0n (I/O) SO0n (output) (55H)
Page 450: Continuous Transfer Mode
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) 15.4.3 Continuous transfer mode (1) Usage (receive-only: 8-bit data length) <1> Set the continuous transfer mode (CSIM0n.AUTOn bit = 1) and the receive-only mode (CSIM0n.TRMDn bit = 0). <2> Read the SIRBnL register (start transfer with dummy read). <3>...
Page 451 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 15-4. Continuous Transfer (Receive-Only) Timing Chart • Transmit/receive type 1, 8-bit data length SCK0n (I/O) din-1 din-2 din-3 din-4 din-5 SI0n (input) SIO0nL din-5 register SIRBnL din-1 din-2 din-3 din-4 register SIRBEn (d4) Reg_RD SIRBn (d1) SIRBn (d2)
Page 452 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (2) Usage (transmission/reception: 8-bit data length) <1> Set the continuous transfer mode (CSIM0n.AUTOn bit = 1) and the transmission/reception mode (CSIM0n.TRMDn bit = 1). <2> Write the first data to the SOTBFnL register. <3>...
Page 453 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 15-5. Continuous Transfer (Transmission/Reception) Timing Chart • Transmit/receive type 1, 8-bit data length SCK0n (I/O) SO0n (output) dout-1 dout-2 dout-3 dout-4 dout-5 SI0n (input) din-1 din-2 din-3 din-4 din-5 SOTBFnL dout-1 register SOTBnL dout-2 dout-3...
Page 454 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (3) Next transfer reservation period In the continuous transfer mode, the next transfer must be prepared with the period shown in Figure 15-6. Figure 15-6. Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length: 8 bits, transmit/receive type 1 SCK0n (I/O)
Page 455 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 15-6. Timing Chart of Next Transfer Reservation Period (2/2) (c) When data length: 8 bits, transmit/receive type 2 SCK0n (I/O) INTCSI0n signal Reservation period: 6.5 SCK0n cycles (d) When data length: 16 bits, transmit/receive type 2 SCK0n (I/O) INTCSI0n...
Page 456 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (4) Cautions To continue continuous transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs.
Page 457 CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) (ii) In case of conflict between transmission/reception completion interrupt request signal (INTCSI0n) generation and register access Since continuous transfer has stopped once, executed as a new continuous transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 15-8). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent.
Page 458: Output Pins
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0) 15.5 Output Pins The following describes the output pins. For the setting of each pin, refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions. (1) SCK0n pin When the CSI0n operation is disabled (CSIM0n.CSI0En bit = 0), the SCK0n pin output status is as follows. Table 15-2.
Page 459: Chapter 16 I C Bus
CHAPTER 16 I C BUS To use the I C bus function, use the P38/SDA0 and P39/SCL0 pins as the serial transmit/receive data I/O pin (SDA0) and the serial clock I/O pin (SCL0), respectively. In the V850ES/KE1+, one channel of I C bus is provided.
Page 460 CHAPTER 16 I C BUS Figure 16-1. Block Diagram of I <R> Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Start Slave address Clear...
Page 461 CHAPTER 16 I C BUS A serial bus configuration example is shown below. Figure 16-2. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC...
Page 462: Configuration
CHAPTER 16 I C BUS 16.2 Configuration C0 includes the following hardware. Table 16-1. Configuration of I Item Configuration Registers IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers IIC control register 0 (IICC0) IIC status register 0 (IICS0) IIC flag register 0 (IICCF0) IIC clock selection register 0 (IICCL0) IIC function expansion register 0 (IICX0)
Page 463 CHAPTER 16 I C BUS (8) Serial clock controller In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits are used to generate and detect various statuses.
Page 464: Registers
CHAPTER 16 I C BUS 16.3 Registers C0 is controlled by the following registers. • IIC control register 0 (IICC0) • IIC status register 0 (IICS0) • IIC flag register 0 (IICF0) • IIC clock selection register 0 (IICCL0) • IIC function expansion register 0 (IICX0) The following registers are also used.
Page 465 CHAPTER 16 I C BUS (1/4) After reset: 00H Address: FFFFFD82H <7> <6> <5> <4> <3> <2> <1> <0> IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0 C0 operation enable/disable specification Note 1 Stop operation. Reset the IICS0 register .
Page 466 CHAPTER 16 I C BUS (2/4) Note SPIE0 Enable/disable generation of interrupt request when stop condition is detected Disable Enable Condition for clearing (SPIE0 bit = 0) Condition for setting (SPIE0 bit = 1) • Cleared by instruction • Set by instruction •...
Page 467 CHAPTER 16 I C BUS (3/4) STT0 Start condition trigger Do not generate a start condition. When bus is released (in STOP mode): Generate a start condition (for starting as master). The SDA0 line is changed from high level to low level while the SCL0 line is high level and then the start condition is generated.
Page 468 CHAPTER 16 I C BUS (4/4) SPT0 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until the SCL0 pin goes to high level.
Page 469 CHAPTER 16 I C BUS (2) IIC status register 0 (IICS0) The IICS0 register indicates the status of the I C0 bus. The IICS0 register is read-only, in 8-bit or 1-bit units. However, the IICS0 register can only be read when the IICC0.STT0 bit is 1 or during the wait period. <R>...
Page 470 CHAPTER 16 I C BUS (2/3) EXC0 Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXC0 bit = 0) Condition for setting (EXC0 bit = 1) • When a start condition is detected •...
Page 471 CHAPTER 16 I C BUS (3/3) ACKD0 Detection of ACK ACK was not detected. ACK was detected. Condition for clearing (ACKD0 bit = 0) Condition for setting (ACKD0 bit = 1) • When a stop condition is detected • After the SDA0 pin is set to low level at the rising edge of •...
Page 472 CHAPTER 16 I C BUS (3) IIC flag register 0 (IICF0) IICF0 is a register that sets the operation mode of I C0 and indicates the status of the I C bus. This register can be read or written in 8-bit or 1-bit units. However, the STCF0 and IICBSY0 bits are read-only. The IICRSV0 bit can be used to enable/disable the communication reservation function (refer to 16.13 Communication Reservation).
Page 473 CHAPTER 16 I C BUS Note After reset: 00H Address: IICF0 FFFFFD8AH <7> <6> <1> <0> IICF0 STCF0 IICBSY0 STCEN0 IICRSV0 STCF0 STT0 clear flag Generate start condition Start condition generation unsuccessful: clear STT0 flag Condition for clearing (STCF0 bit = 0) Condition for setting (STCF0 bit = 1) •...
Page 474 CHAPTER 16 I C BUS (4) IIC clock selection register 0 (IICCL0) The IICCL0 register is used to set the transfer clock for I The IICCL0 register can be read or written in 8-bit or 1-bit units. However, the CLD0 and DAD0 bits are read- only.
Page 475 CHAPTER 16 I C BUS (5) IIC function expansion register 0 (IICX0) This register sets the function expansion of I C0 (valid only in high-speed mode). This register can be read or written in 8-bit or 1-bit units. The CLX0 bit is set in combination with the IICCL0.SMC0, IICCL0.CL01, and IICCL0.CL00 bits (refer to 16.3 (6) I C0 transfer clock setting method).
Page 476 CHAPTER 16 I C BUS Table 16-2. Selection Clock Setting IICX0 IICCL0 Selection Clock Transfer Clock Settable Internal System Operation Mode Clock Frequency (f Bit 0 Bit 3 Bit 1 Bit 0 Range CLX0 SMC0 CL01 CL00 4.0 MHz to 8.38 MHz Normal mode (SMC0 bit = 0) /172...
Page 477: Functions
CHAPTER 16 I C BUS 16.4 Functions 16.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. SCL0 ....This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDA0 ....
Page 478: I C Bus Definitions And Control Methods
CHAPTER 16 I C BUS 16.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the status generated by the I bus. The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition”...
Page 479: Addresses
CHAPTER 16 I C BUS 16.5.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines.
Page 480: Ack
CHAPTER 16 I C BUS <R> 16.5.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues.
Page 481: Stop Condition
CHAPTER 16 I C BUS 16.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is generated when serial transfer from the master device to the slave device has been completed. Stop conditions can be detected when the device is used as a slave.
Page 482: Wait State
CHAPTER 16 I C BUS 16.5.6 Wait state The wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin.
Page 483 CHAPTER 16 I C BUS Figure 16-10. Wait State (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKE0 bit = 1) Master Master and slave both wait after output of ninth clock. IIC0 data write (cancel wait) IIC0 SCL0...
Page 484: Wait State Cancellation Method
CHAPTER 16 I C BUS 16.5.7 Wait state cancellation method <R> In the case of I C0, wait state can be canceled normally in the following ways. • By writing data to the IIC0 register • By setting the IICC0.WREL0 bit (wait state cancellation) •...
Page 485: C Interrupt Request Signals (Intiic0)
CHAPTER 16 I C BUS 16.6 I C Interrupt Request Signals (INTIIC0) <R> The following shows the value of the IICS0 register at the INTIIC0 interrupt request signal generation timing and at the INTIIC0 signal timing. Remark Start condition AD6 to AD0: Address R/W: Transfer direction specification ACK:...
Page 486: Master Device Operation
CHAPTER 16 I C BUS 16.6.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When IICC0.WTIM0 bit = 0 IICC0.SPT0 bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 Δ5 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X000B...
Page 487 CHAPTER 16 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIM0 bit = 0 IICC0.STT0 bit = 1 SPT0 bit = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ7...
Page 488 CHAPTER 16 I C BUS (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIM0 bit = 0 SPT0 bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 Δ5 1: IICS0 register = 1010X110B 2: IICS0 register = 1010X000B Note 3: IICS0 register = 1010X000B (WTIM0 bit = 1...
Page 489: Slave Device Operation (When Receiving Slave Address (Match With Address))
CHAPTER 16 I C BUS 16.6.2 Slave device operation (when receiving slave address (match with address)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICC0.WTIM0 bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X000B...
Page 490 CHAPTER 16 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICS0 register = 0001X110B 2: IICS0 register = 0001X000B...
Page 491 CHAPTER 16 I C BUS (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, address mismatch (extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICS0 register = 0001X110B...
Page 492 CHAPTER 16 I C BUS (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ4 1: IICS0 register = 0001X110B...
Page 493: Slave Device Operation (When Receiving Extension Code)
CHAPTER 16 I C BUS 16.6.3 Slave device operation (when receiving extension code) Always under communication when receiving the extension code. (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICC0.WTIM0 bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4...
Page 494 CHAPTER 16 I C BUS (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICS0 register = 0010X010B 2: IICS0 register = 0010X000B...
Page 495 CHAPTER 16 I C BUS (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICS0 register = 0010X010B 2: IICS0 register = 0010X000B...
Page 496 CHAPTER 16 I C BUS (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIM0 bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ4 1: IICS0 register = 0010X010B...
Page 497: Operation Without Communication
CHAPTER 16 I C BUS 16.6.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 Δ1 Δ 1: IICS0 register = 00000001B Δ: Generated only when IICC0.SPIE0 bit = 1 Remark 16.6.5 Arbitration loss operation (operation as slave after arbitration loss) When used as master in the multi-master system, check the arbitration result by reading the IICS0.MSTS0 bit for...
Page 498 CHAPTER 16 I C BUS (2) When arbitration loss occurs during transmission of extension code <1> When WTIM0 bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICS0 register = 0110X010B 2: IICS0 register = 0010X000B 3: IICS0 register = 0010X000B Δ...
Page 499: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)
CHAPTER 16 I C BUS 16.6.6 Operation when arbitration loss occurs (no communication after arbitration loss) When used as master in the multi-master system, check the arbitration result by reading the IICS0.MSTS0 bit for checking arbitration result by each INTIIC0 interrupt occurrence. (1) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0...
Page 500 CHAPTER 16 I C BUS (3) When arbitration loss occurs during data transfer <1> When IICC0.WTIM0 bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ3 1: IICS0 register = 10001110B 2: IICS0 register = 01000000B Δ 3: IICS0 register = 00000001B Remark : Always generated Δ: Generated only when SPIE0 bit = 1...
Page 501 CHAPTER 16 I C BUS (4) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 Δ3 1: IICS0 register = 1000X110B 2: IICS0 register = 01000110B Δ...
Page 502 CHAPTER 16 I C BUS (5) When loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn Δ2 1: IICS0 register = 1000X110B Δ 2: IICS0 register = 01000001B Remarks 1. : Always generated Δ: Generated only when SPIE0 bit = 1 X: don’t care 2.
Page 503 CHAPTER 16 I C BUS (6) When arbitration loss occurs due to low-level data when attempting to generate a restart condition <1> When WTIM0 bit = 0 IICC0.STT0 bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 Δ5 1: IICS0 register = 1000X110B...
Page 504 CHAPTER 16 I C BUS (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIM0 bit = 0 STT0 bit = 1 ↓ AD6 to AD0 D7 to D0 Δ4 1: IICS0 register = 1000X110B 2: IICS0 register = 1000X000B (WTIM0 bit = 1) 3: IICS0 register = 1000XX00B...
Page 505 CHAPTER 16 I C BUS (8) When arbitration loss occurs due to low-level data when attempting to generate a stop condition <1> When WTIM0 bit = 0 IICC0.SPT0 bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 Δ5 1: IICS0 register = 1000X110B...
Page 506: Interrupt Request Signal (Intiic0) Generation Timing And Wait Control
CHAPTER 16 I C BUS 16.7 Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control The setting of the IICC0.WTIM0 bit determines the timing by which the INTIIC0 signal is generated and the corresponding wait control, as shown below. Table 16-3. INTIIC0 Signal Generation Timing and Wait Control WTIM0 Bit During Slave Device Operation During Master Device Operation...
Page 507: Address Match Detection Method
CHAPTER 16 I C BUS (4) Wait cancellation method The four wait cancellation methods are as follows. • By writing data to the IIC0 register • By setting the IICC0.WREL0 bit (canceling wait state) • By setting the IICC0.STT0 bit (generating start condition) Note •...
Page 508: Extension Code
CHAPTER 16 I C BUS 16.10 Extension Code When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXC0) is set for extension code reception and an interrupt request signal (INTIIC0) is issued at the falling edge of the eighth clock. The local address stored in the SVA0 register is not affected.
Page 509: Arbitration
CHAPTER 16 I C BUS 16.11 Arbitration When several master devices simultaneously generate a start condition (when the IICC0.STT0 bit is set to 1 before the IICS0.STD0 bit is set to 1), communication among the master devices is performed as the number of clocks is adjusted until the data differs.
Page 510: Wakeup Function
CHAPTER 16 I C BUS Table 16-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...
Page 511: Communication Reservation
CHAPTER 16 I C BUS 16.13 Communication Reservation 16.13.1 When communication reservation function is enabled (IICF0.IICRSV0 bit = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
Page 512 CHAPTER 16 I C BUS The communication reservation timing is shown below. Figure 16-12. Communication Reservation Timing <R> Write STT0=1 Program processing to IIC0 Communication Hardware processing SPD0 and reservation STD0 INTIIC0 SCL0 SDA0 Generated by master with bus access IIC0: IIC shift register 0 STT0:...
Page 513 CHAPTER 16 I C BUS The communication reservation flowchart is illustrated below. Figure 16-14. Communication Reservation Flowchart STT0 = 1 ; Sets STT0 flag (communication reservation). Define communication ; Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM). ;...
Page 514: When Communication Reservation Function Is Disabled (Iicf0.Iicrsv0 Bit = 1)
CHAPTER 16 I C BUS 16.13.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1) When the IICC0.STT0 bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used.
Page 515: Cautions
CHAPTER 16 I C BUS 16.14 Cautions (1) When IICF0.STCEN0 bit = 0 Immediately after I C0 operation is enabled, the bus communication status (IICF0.IICBSY0 bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication.
Page 516: Communication Operations
CHAPTER 16 I C BUS 16.15 Communication Operations <R> The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the V850ES/KE1+ as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing.
Page 517: Master Operation In Single Master System
CHAPTER 16 I C BUS 16.15.1 Master operation in single master system Figure 16-15. Master Operation in Single Master System START Note Initialize I C bus Refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions Set ports to set the I C mode before this function is used.
Page 518: Master Operation In Multimaster System
CHAPTER 16 I C BUS 16.15.2 Master operation in multimaster system Figure 16-16. Master Operation in Multimaster System (1/3) START Refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions Set ports to set the I C mode before this function is used. IICX0 ←...
Page 519 CHAPTER 16 I C BUS Figure 16-16. Master Operation in Multimaster System (2/3) Communication reservation enabled Communication start preparation STT0 = 1 (start condition generation) Securing wait time by software Wait (refer to Table 16-6) MSTS0 = 1? INTIIC0 interrupt occurred? Waiting for bus release (communication reserved) EXC0 = 1 or COI0 =1?
Page 520 CHAPTER 16 I C BUS Figure 16-16. Master Operation in Multimaster System (3/3) Communication start Write IIC0 (address, transfer direction specification) INTIIC0 interrupt occurred? Waiting for ACK detection MSTS0 = 1? ACKD0 = 1? TRC0 = 1? ACKE0 = 1 WTIM0 = 0 WTIM0 = 1 WREL0 = 1...
Page 521: Slave Operation
CHAPTER 16 I C BUS 16.15.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIIC0 interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary.
Page 522 CHAPTER 16 I C BUS For reception, receive the required number of data and do not return ACK for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition. This causes exit from communications.
Page 523 CHAPTER 16 I C BUS The following shows an example of the processing of the slave device by an INTIIC0 interrupt (it is assumed that no extension codes are used here). During an INTIIC0 interrupt, the status is confirmed and the following steps are executed.
Page 524: Timing Of Data Communication
CHAPTER 16 I C BUS 16.16 Timing of Data Communication When using I C bus mode, the master device generates an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICS0.TRC0 bit that specifies the data transfer direction and then starts serial communication with the slave device.
Page 525 CHAPTER 16 I C BUS Figure 16-20. Example of Master to Slave Communication <R> (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IIC0 IIC0 address IIC0 data ACKD0 STD0...
Page 526 CHAPTER 16 I C BUS Figure 16-20. Example of Master to Slave Communication <R> (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IIC0 data IIC0 data IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0...
Page 527 CHAPTER 16 I C BUS Figure 16-20. Example of Master to Slave Communication <R> (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IIC0 IIC0 data IIC0 address ACKD0 STD0 SPD0 WTIM0...
Page 528 CHAPTER 16 I C BUS Figure 16-21. Example of Slave to Master Communication <R> (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (1/3) (a) Start condition ~ address Processing by master device ← ← IIC0 IIC0 address IIC0 FFH Note...
Page 529 CHAPTER 16 I C BUS Figure 16-21. Example of Slave to Master Communication <R> (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (2/3) (b) Data Processing by master device ← ← IIC0 IIC0 FFH Note IIC0 FFH Note ACKD0 STD0...
Page 530 CHAPTER 16 I C BUS Figure 16-21. Example of Slave to Master Communication <R> (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (3/3) (c) Stop condition Processing by master device ← IIC0 address ← IIC0 IIC0 FFH Note ACKD0 STD0...
Page 531: Chapter 17 Interrupt/Exception Processing Function
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.1 Overview The V850ES/KE1+ is provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize an interrupt function that can service interrupt requests from a total of 35 or 36 sources. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 532 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 17-1. Interrupt Source List (1/2) Type Classification Default Name Trigger Interrupt Exception Handler Restored Interrupt Priority Source Code Address Control Register Reset Interrupt – RESET RESET pin input 0000H 00000000H Undefined – Internal reset input from WDT1 WDT1, WDT2 WDT2...
Page 533 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 17-1. Interrupt Source List (2/2) Type Classification Default Name Trigger Interrupt Exception Handler Restored Interrupt Priority Source Code Address Control Register Maskable Interrupt INTTMH0 TMH0 and CMP00/CMP01 TMH0 01E0H 000001E0H nextPC TMHIC0 match INTTMH1 TMH1 and CMP10/CMP11 TMH1 01F0H...
Page 534: Non-Maskable Interrupts
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.2 Non-Maskable Interrupts Non-maskable interrupt request signals are acknowledged unconditionally, even when interrupts are disabled (DI state). Non-maskable interrupts (NMI) are not subject to priority control and take precedence over all other interrupt request signals. The following three types of non-maskable interrupt request signals are available in the V850ES/KE1+.
Page 535 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-1. Acknowledging Non-Maskable Interrupt Request Signals (1/2) (a) If two or more NMI request signals are simultaneously generated · NMI and INTWDT1 requests simultaneously generated · NMI and INTWDT2 requests simultaneously generated Main routine Main routine INTWDT1 INTWDT2...
Page 536 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-1. Acknowledging Non-Maskable Interrupt Request Signals (2/2) (b) If a new non-maskable interrupt request signal is generated during a non-maskable interrupt servicing Non-maskable Non-maskable interrupt request newly generated during non-maskable interrupt servicing interrupt currently INTWDT1 INTWDT2 being serviced...
Page 537: Operation
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.2.1 Operation Upon generation of a non-maskable interrupt request signal, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 538: Restore
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. (1) In case of NMI Restore from NMI processing is done with the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC.
Page 539: Np Flag
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is in progress. This flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts.
Page 540: Maskable Interrupts
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/KE1+ has 33 maskable interrupt sources (refer to 17.1.1 Features). If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority.
Page 541 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-4. Maskable Interrupt Servicing INT input Interrupt mask released? Priority higher than INTC acknowledged that of interrupt currently being serviced? Priority higher than that of other interrupt requests? Highest default priority of interrupt requests with the same priority? Maskable interrupt request Interrupt request pending...
Page 542: Restore
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.2 Restore Execution is restored from maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. (1) Loads the values of the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit and the PSW.NP bit are both 0.
Page 543: Priorities Of Maskable Interrupts
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.3 Priorities of maskable interrupts INTC provides a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxICn.xxPRn bit).
Page 544 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-6. Example of Interrupt Nesting (1/2) Main routine Servicing of a Servicing of b Interrupt request a Interrupt request b Interrupt request b is acknowledged (level 3) (level 2) because the priority of b is higher than that of a and interrupts are enabled.
Page 545 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-6. Example of Interrupt Nesting (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i.
Page 546 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-7. Example of Servicing Simultaneously Generated Interrupt Request Signals Main routine Interrupt request a (level 2) Note 1 Interrupt request b (level 1) ·Interrupt requests b and c are Servicing of interrupt Note 2 Interrupt request c (level 1) acknowledged first according to their request b...
Page 547: Interrupt Control Register (Xxlcn)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.4 Interrupt control register (xxlCn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control registers can be read or written in 8-bit or 1-bit units. Reset sets this register to 47H.
Page 548 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 17-2. Interrupt Control Registers (xxlCn) Address Register Bits <7> <6> FFFFF110H WDT1IC WDT1IF WDT1MK WDT1PR2 WDT1PR1 WDT1PR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2 PPR22 PPR21...
Page 549: Interrupt Mask Registers 0, 1, 3 (Imr0, Imr1, Imr3)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.5 Interrupt mask registers 0, 1, 3 (IMR0, IMR1, IMR3) These registers set the interrupt mask status for maskable interrupts. The xxMKn bit of the IMR0, IMR1, and IMR3 registers and the xxMKn bit of the xxlCn register are respectively linked. The IMRm register can be read or written in 16-bit units (m = 0, 1, 3).
Page 550: In-Service Priority Register (Ispr)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently being acknowledged. When the interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set (1) and remains set while the interrupt is being serviced.
Page 551: Id Flag
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.7 ID flag The interrupt disable flag (ID) is allocated to the PSW and controls the maskable interrupt’s operating state, and stores control information regarding enabling/disabling reception of interrupt request signals. Reset sets this flag to 00000020H. After reset: 00000020H NP EP ID SAT CY OV...
Page 552: Watchdog Timer Mode Register 1 (Wdtm1)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.3.8 Watchdog timer mode register 1 (WDTM1) This register is a special register that can be written to only in a special sequence. To generate a maskable interrupt (INTWDT1), clear the WDTM14 bit to 0. This register can be read or written in 8-bit or 1-bit units (for details, refer to CHAPTER 11 WATCHDOG TIMER FUNCTIONS).
Page 553: External Interrupt Request Input Pins (Nmi, Intp0 To Intp7)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP7) 17.4.1 Noise elimination (1) Noise elimination for NMI pin The NMI pin includes a noise eliminator that operates using analog delay. Therefore, a signal input to the NMI pin is not detected as an edge unless it maintains its input level for a certain period.
Page 554 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION (a) Digital noise elimination control register (NFC) The NFC register controls elimination of noise on the INTP3 pin. If f is used as the noise elimination clock, the external interrupt function of the INTP3 pin can be used even in the IDLE/STOP mode. This register can be read or written in 8-bit or 1-bit units.
Page 555: Edge Detection
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION <Noise elimination width> The digital noise elimination width (t ) is as follows, where T is the sampling clock period and M is the WIT3 number of samplings. • t < (M − 1)T: Accurately eliminated as noise WIT3 •...
Page 556 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt rising and falling edge specification registers 0 (INTR0, INTF0) These are 8-bit registers that specify detection of the rising and falling edges of the NMI and INTP0 to INTP3 pins. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
Page 557 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt rising and falling edge specification registers 3 (INTR3, INTF3) These are 8-bit registers that specify detection of the rising and falling edges of the INTP7 pin. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
Page 558 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt rising and falling edge specification registers 9H (INTR9H, INTF9H) These are 8-bit registers that specify detection of the rising edge of the INTP4 to INTP6 pins. These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
Page 559: Software Exceptions
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.5 Software Exceptions A software exception is generated when the CPU executes the TRAP instruction. Software exceptions can always be acknowledged. 17.5.1 Operation If a software exception occurs, the CPU performs the following processing and transfers control to a handler routine.
Page 560: Restore
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.5.2 Restore Execution is restored from software exception processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1>...
Page 561: Ep Flag
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.5.3 EP flag The EP flag, which is bit 6 of the PSW, is a status flag that indicates that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H NP EP ID SAT CY OV Exception processing status...
Page 562: Exception Trap
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.6 Exception Trap The exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/KE1+, an illegal opcode trap (ILGOP) is considered as an exception trap. 17.6.1 Illegal opcode An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26 to 23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B.
Page 563 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 17-10. Exception Trap Processing Exception trap (ILGOP) occurs DBPC Restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing (2) Restore Execution is restored from exception trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored <1>...
Page 564: Debug Trap
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.6.2 Debug trap A debug trap is an exception that occurs upon execution of the DBTRAP instruction and that can be acknowledged at all times. When a debug trap occurs, the CPU performs the following processing. (1) Operation <1>...
Page 565 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Execution is restored from debug trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1>...
Page 566: Multiple Interrupt Servicing Control
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.7 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a function that stops an interrupt service routine currently in progress if a higher priority interrupt request signal is generated, and processes the acknowledgment operation of the higher priority interrupt request signal.
Page 567 CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) To generate exception in service program Service program for maskable interrupt or exception … … • EIPC saved to memory or register • EIPSW saved to memory or register … • TRAP instruction ←Acknowledges exceptions such as TRAP instruction. …...
Page 568: Interrupt Response Time
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.8 Interrupt Response Time Except in the following cases, the CPU interrupt response time is a minimum of 4 clocks. If inputting consecutive interrupt request signals, at least 4 clocks must be placed between each interrupt request signal. •...
Page 569: Periods In Which Interrupts Are Not Acknowledged By Cpu
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION 17.9 Periods in Which Interrupts Are Not Acknowledged by CPU Interrupts are acknowledged by the CPU while an instruction is being executed. However, no interrupt is acknowledged between an interrupt request non-sample instruction and the next instruction (interrupts are held pending).
Page 570: Chapter 18 Key Interrupt Function
CHAPTER 18 KEY INTERRUPT FUNCTION 18.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register. Caution If any of the KR0 to KR7 pins is at low level, the INTKR signal is not generated even if a falling edge is input to another pin.
Page 571: Register
CHAPTER 18 KEY INTERRUPT FUNCTION 18.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 572: Chapter 19 Standby Function
CHAPTER 19 STANDBY FUNCTION 19.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 19-1. Table 19-1.
Page 573 CHAPTER 19 STANDBY FUNCTION Figure 19-1. Status Transition (1/2) STOP mode IDLE mode HALT mode Note 3 Reset Interrupt Note 4 request Note 1 Note 1 Reset Reset Wait for stabilization of oscillation Note 2 Interrupt request Wait for stabilization Wait for stabilization Setting of IDLE mode...
Page 574 CHAPTER 19 STANDBY FUNCTION Figure 19-1. Status Transition (2/2) Notes 1. RESET pin input, WDTRES2, POCRES, LVIRES, or CLMRES signal. In the case of the WDTRES1 signal, the oscillation stabilization time is not secured. 2. Non-maskable interrupt request signal or unmasked maskable interrupt request signal. 3.
Page 575: Registers
CHAPTER 19 STANDBY FUNCTION 19.2 Registers (1) Power save control register (PSC) This is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the standby mode. The PSC register is a special register that can be written to only in a special sequence (refer to 3.4.7 Special registers).
Page 576 CHAPTER 19 STANDBY FUNCTION (2) Power save mode register (PSMR) This is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 577 CHAPTER 19 STANDBY FUNCTION (3) Oscillation stabilization time selection register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released is controlled by the OSTS register. The OSTS register can be read or written in 8-bit units. Reset sets this register to 01H.
Page 578: Halt Mode
CHAPTER 19 STANDBY FUNCTION 19.3 HALT Mode 19.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues.
Page 579 CHAPTER 19 STANDBY FUNCTION Table 19-3. Operation Status in HALT Mode Setting of HALT Mode When CPU Is Operating with Main Clock Item When Subclock Is Not Used When Subclock Is Used Stops operation ROM correction Stops operation Main clock oscillator Oscillation enabled −...
Page 580: Idle Mode
CHAPTER 19 STANDBY FUNCTION 19.4 IDLE Mode 19.4.1 Setting and operation status The IDLE mode is set by clearing the PSMR.PSM bit to 0 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral functions stops.
Page 581 CHAPTER 19 STANDBY FUNCTION (2) Releasing IDLE mode by reset The same operation as the normal reset operation is performed. Table 19-5. Operation Status in IDLE Mode Setting of IDLE Mode When CPU Is Operating with Main Clock Item When Subclock Is Not Used When Subclock Is Used Stops operation ROM correction...
Page 582: Stop Mode
CHAPTER 19 STANDBY FUNCTION 19.5 STOP Mode 19.5.1 Setting and operation status The STOP mode is set when the PSMR.PSM bit is set to 1 and the PSC.STP bit is set to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped.
Page 583 CHAPTER 19 STANDBY FUNCTION (2) Releasing STOP mode by reset The same operation as the normal reset operation is performed. Table 19-7. Operation Status in STOP Mode Setting of STOP Mode When CPU Is Operating with Main Clock Item When Subclock Is Not Used When Subclock Is Used Stops operation ROM correction...
Page 584: Securing Oscillation Stabilization Time When Stop Mode Is Released
CHAPTER 19 STANDBY FUNCTION 19.5.3 Securing oscillation stabilization time when STOP mode is released When the STOP mode is released, only the oscillation stabilization time set by the OSTS register elapses. If the Note STOP mode has been released by reset, however, the reset value of the OSTS register elapses.
Page 585: Subclock Operation Mode
CHAPTER 19 STANDBY FUNCTION 19.6 Subclock Operation Mode 19.6.1 Setting and operation status The subclock operation mode is set when the PCC.CK3 bit is set to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped.
Page 586 CHAPTER 19 STANDBY FUNCTION Table 19-8. Operation Status in Subclock Operation Mode Setting of Subclock Operation Status Operation Mode When Main Clock Is Oscillating When Main Clock Is Stopped Item Operable ROM correction Operable Subclock oscillator Oscillation enabled Internal oscillator (f Operable Interrupt controller Operable...
Page 587: Sub-Idle Mode
CHAPTER 19 STANDBY FUNCTION 19.7 Sub-IDLE Mode 19.7.1 Setting and operation status The sub-IDLE mode is set when the PSMR.PSM bit is cleared to 0 and the PSC.STP bit is set to 1 in the subclock operation mode. In this mode, the clock oscillator continues operation but clock supply to the CPU and the other on-chip peripheral functions is stopped.
Page 588 CHAPTER 19 STANDBY FUNCTION (2) Releasing sub-IDLE mode by reset The same operation as the normal reset operation is performed. Table 19-10. Operation Status in Sub-IDLE Mode Setting of Sub-IDLE Operation Status Mode When Main Clock Is Oscillating When Main Clock Is Stopped Item Stops operation ROM correction...
Page 589: Chapter 20 Reset Function
CHAPTER 20 RESET FUNCTION 20.1 Overview The following reset functions are available. • Reset by RESET pin input • Reset by watchdog timer 1 overflow (WDTRES1) • Reset by watchdog timer 2 overflow (WDTRES2) • System reset by low-voltage detector (LVI) (LVIRES) •...
Page 590: Register To Check Reset Source
CHAPTER 20 RESET FUNCTION 20.3 Register to Check Reset Source (1) Reset source flag register (RESF) The RESF register is a special register that can be written only by a combination of specific sequences (refer to 3.4.7 Special registers). The RESF register indicates the source from which a reset signal is generated. This register can be read or written in 8-bit or 1-bit units (however, only “0”...
Page 591: Reset Sources
CHAPTER 20 RESET FUNCTION 20.4 Reset Sources The following six reset sources are available. • Reset by RESET pin input • Reset by watchdog timer 1 overflow (WDTRES1) • Reset by watchdog timer 2 overflow (WDTRES2) • System reset by low-voltage detector (LVI) (LVIRES) •...
Page 592 CHAPTER 20 RESET FUNCTION Figure 20-2. Hardware Status on RESET Pin Input Initialized to f /8 operation RESET Eliminated as noise Detected Analog delay Analog as reset (eliminated delay as noise) Internal system reset signal (active low) Oscillation stabilization time count Overflow of oscillation stabilization time counter Figure 20-3.
Page 593 CHAPTER 20 RESET FUNCTION (1) Elimination of digital noise on RESET pin For the RESET pin of the V850ES/KE1+, an analog/digital + analog noise eliminator can be selected. The digital noise eliminator is selected when the RNZC.RNZSEL bit = 1. The digital noise is sampled using the main clock (f ), and the number of samplings can be selected from 10 or 20 by the RNZC.SMPSEL bit.
Page 594 CHAPTER 20 RESET FUNCTION Figure 20-4. Sampling Operation Timing (20 Times) RESET signal 19 20 Oscillation stabilization time count Internal reset signal (active low) Digital noise Analog Analog Period set by OSTS register elimination delay delay <1> Digital noise is eliminated when the RNZC.RNZSEL bit = 1. <2>...
Page 595: Reset Operation By Wdtres1 Signal
CHAPTER 20 RESET FUNCTION 20.4.2 Reset operation by WDTRES1 signal If a reset operation mode in which reset is effected when watchdog timer 1 overflows is set, the system is reset when watchdog timer 1 overflows (when the WDTRES1 signal is generated), and each hardware unit is initialized to a specific status.
Page 596: Reset Operation By Wdtres2 Signal
CHAPTER 20 RESET FUNCTION 20.4.3 Reset operation by WDTRES2 signal If a reset operation mode in which reset is effected when watchdog timer 2 overflows is set, the system is reset when watchdog timer 2 overflows (when the WDTRES2 signal is generated), and each hardware unit is initialized to a specific status.
Page 597: Power-On-Clear Reset Operation
CHAPTER 20 RESET FUNCTION 20.4.4 Power-on-clear reset operation The supply voltage (V ) and detection voltage (V ) are compared. When V < V , the system is reset and each hardware unit is initialized to a specific status. ) is 2.6 V ±0.1 V. The detection voltage (V ≥...
Page 598 CHAPTER 20 RESET FUNCTION Figure 20-7. Reset Timing by Power-on-Clear Circuit Initialized to f /8 operation POCRES signal (active low) Internal system reset signal (active low) Response time Response time Oscillation stabilization time count Overflow of oscillation stabilization time counter User’s Manual U16896EJ2V0UD...
Page 599 CHAPTER 20 RESET FUNCTION Figure 20-8. Reset Timing on Power Application Initialized to f /8 operation POCRES signal (active low) Internal system Oscillation stabilization reset signal time count (active low) Response time Overflow of oscillation stabilization time counter User’s Manual U16896EJ2V0UD...
Page 600: Reset Operation By Low-Voltage Detector
CHAPTER 20 RESET FUNCTION 20.4.5 Reset operation by low-voltage detector If a mode in which the internal reset signal (LVIRES) is to be generated by the low-voltage detector is set, the supply voltage (V ) and detection voltage (V ) are compared. When V <...
Page 601: Reset Operation By Clock Monitor
CHAPTER 20 RESET FUNCTION 20.4.6 Reset operation by clock monitor If the main clock is monitored using the sampling clock (internal oscillation clock: f ) and if it is detected that the main clock has stopped when the clock monitor operation is enabled, the system is reset and each hardware unit is initialized to a specific status.
Page 602: Reset Output Function
CHAPTER 20 RESET FUNCTION 20.5 Reset Output Function The P00/TOH0 pin of the V850ES/KE1+ can be used as a dummy reset output pin. The P00 pin is set in the output port mode (PM0.PM00 bit = 0) and outputs a low level (P0.P00 bit = 0) when the reset signal is generated.
Page 603: Chapter 21 Clock Monitor
CHAPTER 21 CLOCK MONITOR 21.1 Function The clock monitor samples the main clock by using the internal oscillation clock and generates a reset signal (CLMRES) when oscillation of the main clock is stopped. After reset is released, the CPU operates on internal oscillation clock. Once the operation of the clock monitor has been enabled by the CLM.CLME bit, it can be stopped only by reset.
Page 604 CHAPTER 21 CLOCK MONITOR (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register 00H. After reset: Address: FFFFF80CH...
Page 605: Operation
CHAPTER 21 CLOCK MONITOR 21.3 Operation The clock monitor start and stop conditions are as follows. <Monitor start condition> Set the CLM.CLME bit to 1 <Monitor stop conditions> • When the oscillation stabilization time is counted after the STOP mode has been released •...
Page 606 CHAPTER 21 CLOCK MONITOR (a) Operation when main clock oscillation is stopped If oscillation of the main clock is stopped when the CLME bit = 1, the CLMRES signal is generated as shown in Figure 21-1. Figure 21-1. When Oscillation of Main Clock Is Stopped 4 internal oscillation clocks Main clock Internal oscillation...
Page 607 CHAPTER 21 CLOCK MONITOR (c) Operation when main clock is stopped (arbitrary) If the main clock is stopped by setting the PCC.MCK bit to 1 while the subclock is operating (PCC.CLS bit = 1), the monitor operation is stopped until the main clock operates (CLS bit = 0). The monitor operation is automatically started when the main clock starts operating.
Page 608: Internal Oscillation Clock Operation Mode
CHAPTER 21 CLOCK MONITOR 21.4 Internal Oscillation Clock Operation Mode 21.4.1 Setting and operation status <R> If watchdog timer 2 overflows during the oscillation stabilization time securing period after a reset is released or after the STOP mode is released (overflow of the counter by setting the OSTS register), the internal oscillation clock operation mode is set.
Page 609 CHAPTER 21 CLOCK MONITOR Figure 21-4. Reset Timing of Clock Monitor Oscillation stabilization time secured (count operation stops) Main clock operation stopped operation Program fetch started CLMRES signal (active low) Main clock stop detected CLME bit CLMRF bit WDT2 count Count operation or count stopped Stopped Count operation...
Page 610 CHAPTER 21 CLOCK MONITOR Table 21-3. Operation Status in Internal Oscillation Clock Operation Mode Setting of Internal Oscillation Clock Operation Status Operation Mode When Subclock Is Not Used When Subclock Is Used Item ROM correction Operable Interrupt controller Operable 16-bit timer (TMP0) Stops operation 16-bit timer (TM01) Stops operation...
Page 611: Internal Oscillation Halt Mode
CHAPTER 21 CLOCK MONITOR 21.5 Internal Oscillation HALT Mode 21.5.1 Setting and operation status The internal oscillation HALT mode is set when a dedicated instruction (HALT instruction) is executed in the internal oscillation clock operation mode. In the internal oscillation HALT mode, the internal oscillator continues operating. Only clock supply to the CPU is stopped;...
Page 612 CHAPTER 21 CLOCK MONITOR (2) Releasing internal oscillation HALT mode by reset The same operation as the normal reset operation is performed. Table 21-5. Operation Status in Internal Oscillation HALT Mode Setting of Internal Oscillation Operation Status HALT Mode When Subclock Is Not Used When Subclock Is Used Item Stops operation...
Page 613: Chapter 22 Low-Voltage Detector
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.1 Function The low-voltage detector (LVI) has the following functions. • Compares the supply voltage (V ) and detection voltage (V ), and generates an interrupt request signal (INTLVI) or reset signal (LVIRES) when V < V •...
Page 614: Registers
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.3 Registers The low-voltage detector is controlled by the following two registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) (1) Low-voltage detection register (LVIM) The LVIM register is an 8-bit register that sets the operation mode of the low-voltage detector. The LVIM register is a special register that can be written only by a combination of specific sequences (refer to 3.4.7 Special registers).
Page 615 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) The LVIS register is an 8-bit register that selects the low-voltage detection level. The LVIS register can be read or written in 8-bit units. If the LVIM.LVION and LVIM.LVIMD bits = 11, however, the LVIS register cannot be rewritten until the reset signal (LVIRES) is generated.
Page 616: Operation
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4 Operation The low-voltage detector can be used in the following two modes. • Reset operation (LVIRES): Compares the supply voltage (V ) and detection voltage (V ), and generates a reset signal (LVIRES) when V <...
Page 617 CHAPTER 22 LOW-VOLTAGE DETECTOR (2) Interrupt operation (INTLVI) <When starting operation> <1> Mask the INTLVI interrupt (LVIMK bit = 1). <2> Set the detection voltage (V ) using the LVIS.LVIS2 to LVIS.LVIS0 bits. <3> Set the LVIM.LVION bit to 1 (enables low-voltage detector operation). <4>...
Page 618: Chapter 23 Power-On-Clear Circuit
CHAPTER 23 POWER-ON-CLEAR CIRCUIT 23.1 Function The power-on-clear (POC) circuit has the following functions. • Generates a reset signal (POCRES) upon power application. • Compares the supply voltage (V ) and detection voltage (V ), and generates a reset signal (POCRES) when = 2.6 V ±0.1 V).
Page 619: Operation
CHAPTER 23 POWER-ON-CLEAR CIRCUIT 23.3 Operation The power-on-clear circuit compares the supply voltage (V ) and detection voltage (V ), and generates a reset signal (POCRES) when V < V Figure 23-2. Operation of Power-on-Clear Circuit Supply voltage Power-on-clear circuit detection voltage 2.5 V POCRES...
Page 620: Chapter 24 Rom Correction Function
CHAPTER 24 ROM CORRECTION FUNCTION 24.1 Overview The ROM correction function is used to replace part of the program in the internal ROM with the program of an external memory or the internal RAM. By using this function, program bugs found in the internal ROM can be corrected. Up to four addresses can be specified for correction.
Page 621: Control Registers
CHAPTER 24 ROM CORRECTION FUNCTION 24.2 Control Registers 24.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3) These registers are used to set the first address of the program to be corrected. The program can be corrected at up to four places because four CORADn registers are provided. The CORADn register can be read or written in 32-bit units.
Page 622: Correction Control Register (Corcn)
CHAPTER 24 ROM CORRECTION FUNCTION 24.2.2 Correction control register (CORCN) This register disables or enables the correction operation at the address specified by the CORADn register. Each channel can be enabled or disabled by this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register 00H.
Page 623 CHAPTER 24 ROM CORRECTION FUNCTION Figure 24-2. ROM Correction Operation and Program Flow Reset & start Initialize microcontroller Set CORADn register Read data for setting ROM Load program for judgment correction from external memory of ROM correction and correction codes Set CORCN register CORENn bit = 1? Execute fetch code...
Page 624: Chapter 25 Mask Option/Option Byte
CHAPTER 25 MASK OPTION/OPTION BYTE 25.1 Mask Option (Mask ROM Versions) μ The mask ROM versions ( PD703302 and 703302Y) have the following mask options. • Connection of pull-up resistor to P38 and P39 pins • Enabling/disabling stopping internal oscillator by software •...
Page 625: Option Byte (Flash Memory Versions)
CHAPTER 25 MASK OPTION/OPTION BYTE (3) Shortening oscillation stabilization time of main clock oscillation after release of reset OSTS0 Option to Shorten Oscillation Stabilization Time of Main Clock Oscillation After Release of Reset (Default Value of OSTS Register) Oscillation Stabilization Time Shorten oscillation stabilization time.
Page 626: Chapter 26 Flash Memory
CHAPTER 26 FLASH MEMORY The following products are the flash memory versions of the V850ES/KE1+. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing and application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation for the commercial samples (not engineering samples) of the mask ROM version.
Page 627: Memory Configuration
CHAPTER 26 FLASH MEMORY 26.2 Memory Configuration The 128 KB internal flash memory area is divided into 64 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. When the boot swap function is used, the physical memory (blocks 0 to 3) located at the addresses of boot area 0 is replaced by the physical memory (blocks 4 to 7) located at the addresses of boot area 1.
Page 628: Functional Outline
CHAPTER 26 FLASH MEMORY 26.3 Functional Outline The internal flash memory of the V850ES/KE1+ can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850ES/KE1+ has already been mounted on the target system or not (on- board/off-board programming).
Page 629 CHAPTER 26 FLASH MEMORY Table 26-2. Basic Functions Support ( : Supported, ×: Not supported) Function Functional Outline On-Board/Off-Board Self Programming Programming Block erasure The contents of specified memory blocks are erased. × Chip erasure The contents of the entire memory area are erased all at once.
Page 630 CHAPTER 26 FLASH MEMORY Table 26-4. Security Setting <R> Function Erase/Writing/Reading When Each Security Is Set Cautions on Security Setting (√: Executable, ×: Not Executable, −: Not Support) On-Board/Off-Board Self Programming On-Board/ Self Programming Off-Board Programming Programming Block erase command: × Block erase (FlashBlockErase): √...
Page 631 CHAPTER 26 FLASH MEMORY (1) Security setting with PG-FP4 (security flag settings) <R> When disabling the read command (Disable Read), to raise the security level, it is recommended to also disable the block erase command (Disable Block Erase) and program command (Disable Program). Furthermore, similar to the mask ROM products, when program rewriting is not necessary, additionally disable the chip erase command (Disable Chip Erase).
Page 632: Rewriting By Dedicated Flash Programmer
CHAPTER 26 FLASH MEMORY 26.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/KE1+ is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series).
Page 633: Communication Mode
CHAPTER 26 FLASH MEMORY 26.4.2 Communication mode Communication between the dedicated flash programmer and the V850ES/KE1+ is performed by serial communication using the UART0 or CSI00 interfaces of the V850ES/KE1+. (1) UART0 Transfer rate: 9,600 to 153,600 bps Figure 26-3. Communication with Dedicated Flash Programmer (UART0) FLMD0 FLMD0 FLMD1...
Page 634 CHAPTER 26 FLASH MEMORY (3) CSI00 + HS Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 26-5. Communication with Dedicated Flash Programmer (CSI00 + HS) FLMD0 FLMD0 FLMD1 FLMD1 Axxxx Bxxxxx Cxxxxxx RESET RESET STATVE PG-FP4 SO00 Dedicated flash V850ES/KE1+ SI00 programmer...
Page 635 CHAPTER 26 FLASH MEMORY μ Table 26-6. Wiring Between PD70F3302, 70F3302Y and PG-FP4 Pin Configuration of Flash Programmer (PG-FP4) Pin Name on With CSI00-HS With CSI00 With UART0 FA Board Signal Name Pin Function Pin Name Pin No. Pin Name Pin No.
Page 636 CHAPTER 26 FLASH MEMORY Figure 26-6. Wiring Example of V850ES/KE1+ Flash Writing Adapter (FA-64GK-9ET-A, FA-64GB-8EU-A) (1/2) <R> Note 1 μ PD70F3302, μ PD70F3302Y Note 3 Connect to GND. Connect to VDD. Note 2 VDD2 CLKIN X2 /RESET VPP RESERVE/HS RFU-3 RFU-2 RFU-1 FLMD1 FLMD0...
Page 637 CHAPTER 26 FLASH MEMORY Figure 26-6. Wiring Example of V850ES/KE1+ Flash Writing Adapter (FA-64GK-9ET-A, FA-64GB-8EU-A) (2/2) <R> Notes 1. Wire the FLMD1 pin as shown in the figure, or connect it to GND on board via a pull-down resistor. 2. The above figure shows an example of wiring when the clock is supplied from the PG-FP4. Be sure to set and connect as follows when the clock is supplied from the PG-FP4.
Page 638: Flash Memory Control
CHAPTER 26 FLASH MEMORY 26.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 26-7. Procedure for Manipulating Flash Memory Start Switch to flash memory Supplies FLMD0 pulse programming mode Select communication system Manipulate flash memory End? User’s Manual U16896EJ2V0UD...
Page 639: Selection Of Communication Mode
CHAPTER 26 FLASH MEMORY 26.4.4 Selection of communication mode In the V850ES/KE1+, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
Page 640: Communication Commands
CHAPTER 26 FLASH MEMORY 26.4.5 Communication commands The V850ES/KE1+ communicates with the dedicated flash programmer by means of commands. The signals sent from the dedicated flash programmer to the V850ES/KE1+ are called “commands”. The response signals sent from the V850ES/KE1+ to the dedicated flash programmer are called “response commands”. Figure 26-9.
Page 641: Pin Connection
CHAPTER 26 FLASH MEMORY 26.4.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode.
Page 642 CHAPTER 26 FLASH MEMORY (2) FLMD1 pin When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When V is supplied to the FLMD0 pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin.
Page 643 CHAPTER 26 FLASH MEMORY (3) Serial interface pin The following shows the pins used by each serial interface. Table 26-9. Pins Used by Serial Interfaces Serial Interface Pins Used UART0 TXD0, RXD0 CSI00 SO00, SI00, SCK00 CSI00 + HS SO00, SI00, SCK00, PCM0 When connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device.
Page 644 CHAPTER 26 FLASH MEMORY (b) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction.
Page 645 CHAPTER 26 FLASH MEMORY (4) RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 646: Rewriting By Self Programming
CHAPTER 26 FLASH MEMORY 26.5 Rewriting by Self Programming 26.5.1 Overview The V850ES/KE1+ supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory.
Page 647: Features
CHAPTER 26 FLASH MEMORY 26.5.2 Features (1) Secure self programming (boot swap function) The V850ES/KE1+ supports a boot swap function that can exchange the physical memory (blocks 0 to 3) of boot area 0 with the physical memory (blocks 4 to 7) of boot area 1. By writing the start program to be rewritten to boot area 1 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in boot area 0.
Page 648: Standard Self Programming Flow
CHAPTER 26 FLASH MEMORY 26.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 26-17. Standard Self Programming Flow <R> (a) Rewriting at once (b) Rewriting in block units Flash memory manipulation Flash memory manipulation Flash environment...
Page 649: Flash Functions
Remark For details, refer to the V850 Series Flash Memory Self Programming (Single Power Supply Flash Memory) User’s Manual. Contact an NEC Electronics sales representative for the above manual. 26.5.5 Pin processing (1) FLMD0 pin The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from being written during self rewriting.
Page 650: Internal Resources Used
When using TM50 and TM51 after self programming, set them again. Remark For details, refer to the V850 Series Flash Memory Self Programming (Single Power Supply Flash Memory) User’s Manual. Contact an NEC Electronics sales representative for the above manual. User’s Manual U16896EJ2V0UD...
Page 651: Chapter 27 On-Chip Debug Function
CHAPTER 27 ON-CHIP DEBUG FUNCTION <R> The V850ES/KE1+ is not provided with an on-chip debug function. However, a pseudo on-chip debug function can ® be realized by using the on-chip debug emulator (MINICUBE ) and debug adapter (QB-V850ESKX1H-DA). For the connection example, refer to A.4.2 When using MINICUBE QB-V850MINI. 27.1 ROM Security Function 27.1.1 Security ID The flash memory versions of the V850ES/KE1+ perform authentication using a 10-byte ID code to prevent the...
Page 652: Setting
CHAPTER 27 ON-CHIP DEBUG FUNCTION 27.1.2 Setting The following shows how to set the ID code as shown in Table 27-1. When the ID code is set as shown in Table 27-1, the ID code input in the configuration dialog box of the ID850QB is “123456789ABCDEF123D4”.
Page 653: Cautions
CHAPTER 27 ON-CHIP DEBUG FUNCTION [Program example (when using CA850 Ver. 2.60 or later)] #------------------------------------------------------------------------------ SECURITYID #------------------------------------------------------------------------------ .section "SECURITY_ID" --Interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xF1DEBC9A --4-7 byte code .hword 0xD423 --8-9 byte code Remark Add the above program example to the startup files. 27.2 Cautions (1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN (program execution), the break function may malfunction.
Page 654: Chapter 28 Electrical Specifications
CHAPTER 28 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage = EV = AV REF0 −0.3 to +6.5 = EV = AV REF0 REF0 −0.3 to +6.5 = EV = AV REF0 −0.3 to +0.3...
Page 655 CHAPTER 28 ELECTRICAL SPECIFICATIONS Capacitance (T = 25°C, V = EV = AV = EV = AV = 0 V) REF0 Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance = 1 MHz P70 to P77 Unmeasured pins I/O capacitance Note returned to 0 V P38, P39...
Page 656 CHAPTER 28 ELECTRICAL SPECIFICATIONS Operating Conditions for EEPROM Emulation <R> = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V, C = 50 pF) REF0 Parameter Symbol Conditions MIN.
Page 657 CHAPTER 28 ELECTRICAL SPECIFICATIONS Main Clock Oscillator Characteristics = −40 to +85°C, V (1) Crystal resonator, ceramic resonator (T = 2.7 to 5.5 V, V = 0 V) Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillation PLL mode = 4.5 to 5.5 V Note 1 frequency (f = 4.0 to 5.5 V...
Page 658 CHAPTER 28 ELECTRICAL SPECIFICATIONS Subclock Oscillator Characteristics = −40 to +85°C, V (1) Crystal resonator (T = 2.7 to 5.5 V, V = 0 V) Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillation 32.768 Note 1 frequency (f Oscillation stabilization Note 2 time...
Page 659 CHAPTER 28 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V) (1/4) REF0 Parameter Symbol Conditions MIN. TYP. MAX. Unit −5.0 Output current, high Per pin for P00 to P06, P30 to P35, P40 to P42, P50 to P55, P90, P91, P96 to P99, P913 to P915, PCM0, PCM1, PDL0 to PDL7...
Page 660 CHAPTER 28 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V) (2/4) REF0 Parameter Symbol Conditions MIN. TYP. MAX. Unit = −2.0 mA, −...
Page 661 CHAPTER 28 ELECTRICAL SPECIFICATIONS <R> DC Characteristics = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V) (3/4) REF0 Note 2 Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Supply current Normal operation mode (all peripheral functions operating)
Page 662 CHAPTER 28 ELECTRICAL SPECIFICATIONS <R> DC Characteristics = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V) (4/4) REF0 Note 2 Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Supply current Normal operation mode (all peripheral functions operating)
Page 663 CHAPTER 28 ELECTRICAL SPECIFICATIONS Data Retention Characteristics = −40 to +85°C) STOP Mode (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage STOP mode DDDR μ STOP release signal input time DREL Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range.
Page 664 CHAPTER 28 ELECTRICAL SPECIFICATIONS AC Characteristics AC Test Input Measurement Points , AV , EV REF0 Measurement points , AV , EV AC Test Output Measurement Points Measurement points Load Conditions (Device under measurement) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 665 CHAPTER 28 ELECTRICAL SPECIFICATIONS CLKOUT Output Timing = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V, C = 50 pF) REF0 Parameter Symbol Conditions MIN. MAX. Unit <1>...
Page 666 CHAPTER 28 ELECTRICAL SPECIFICATIONS Basic Operation (1) Reset/external interrupt timing = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V, C = 50 pF) REF0 Parameter Symbol Conditions MIN.
Page 667 CHAPTER 28 ELECTRICAL SPECIFICATIONS Timer Timing = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V, C = 50 pF) REF0 Parameter Symbol Conditions MIN. MAX. Unit Note 1 <R>...
Page 668 CHAPTER 28 ELECTRICAL SPECIFICATIONS CSI0 Timing (1) Master mode = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V, C = 50 pF) REF0 Parameter Symbol Conditions MIN. MAX.
Page 669 CHAPTER 28 ELECTRICAL SPECIFICATIONS CSI0 Timing <R> (a) CSICn.CKPn, CSICn.DAPn bits = 00 or 11 <101> <102> <102> SCK0n (I/O) <103> <104> Hi-Z Hi-Z SI0n (input) Input data <105> Output data SO0n (output) (b) CSICn.CKPn, CSICn.DAPn bits = 01 or 10 <101>...
Page 670 CHAPTER 28 ELECTRICAL SPECIFICATIONS μ C Bus Mode ( PD703302Y, 70F3302Y Only) = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V, C = 50 pF) REF0 Parameter Symbol Normal Mode High-Speed Mode...
Page 671 CHAPTER 28 ELECTRICAL SPECIFICATIONS μ C Bus Mode ( PD703302Y, 70F3302Y Only) <113> <114> SCL0 (I/O) <115> <119> <118> <116> <117> <120> <112> <121> <112> SDA0 (I/O) <111> <118> <119> Stop Start Restart Stop condition condition condition condition User’s Manual U16896EJ2V0UD...
Page 672 CHAPTER 28 ELECTRICAL SPECIFICATIONS A/D Converter = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V) REF0 Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 4.0 ≤ AV ≤...
Page 673 CHAPTER 28 ELECTRICAL SPECIFICATIONS Power-on-Clear Circuit Characteristics = −40 to +85°C, V , 2.7 V ≤ V = EV = AV = EV = AV = 0 V, C = 50 pF) <R> REF0 Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage μ...
Page 674 CHAPTER 28 ELECTRICAL SPECIFICATIONS Low-Voltage Detector Characteristics = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V, C = 50 pF) <R> REF0 Parameter Symbol Conditions MIN. TYP. MAX.
Page 675 CHAPTER 28 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics = −40 to +85°C, V = EV = AV = 2.7 to 5.5 V, V = EV = AV = 0 V) REF0 (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Programming operation = 4.5 to 5.5 V...
Page 676: Chapter 29 Package Drawings
CHAPTER 29 PACKAGE DRAWINGS 64-PIN PLASTIC TQFP (12x12) detail of lead end ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.125 1.125 0.32 +0.06 −0.10 0.13 0.65 (T.P.) 1.0±0.2 NOTE 0.17 +0.03 −0.07 Each lead centerline is located within 0.13 mm of 0.10 its true position (T.P.) at maximum material condition.
Page 677 CHAPTER 29 PACKAGE DRAWINGS 64-PIN PLASTIC LQFP (10x10) detail of lead end ITEM MILLIMETERS 12.0±0.2 10.0±0.2 10.0±0.2 12.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.) NOTE 1.0±0.2 Each lead centerline is located within 0.08 mm of 0.17 +0.03 its true position (T.P.) at maximum material condition. −0.07 0.08 0.1±0.05...
Page 678: Chapter 30 Recommended Soldering Conditions
Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with -A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative.
Page 679 Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with -A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative.
Page 680: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the V850ES/KE1+. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 681 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) ® (1) When using IECUBE (QB-V850ESKX1H) Software package Language processing software Debugging software • C compiler package • Integrated debugger • Device file • System simulator Control software • Project manager Embedded software Note 1 •...
Page 682 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) <R> (2) When using MINICUBE (QB-V850MINI) Software package Debugging software Language processing software • C compiler package • Integrated debugger • Device file • System simulator Control software • Project manager Embedded software Note 1 •...
Page 683: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 Development tools (software) common to the V850 Series are combined in this package. V850 Series software package μ Part number: S××××SP850 Remark ×××× in the part number differs depending on the host machine and OS used. μ...
Page 684: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS <R> A.4 Debugging Tools (Hardware) A.4.1 When using IECUBE QB-V850ESKX1H The system configuration when connecting the QB-V850ESKX1H to the host machine (PC-9821 series, PC/AT compatible) is shown below. If no option products are prepared, connection is possible. Figure A-2.
Page 685 APPENDIX A DEVELOPMENT TOOLS Figure A-2. System Configuration (QB-V850ESKX1H Used) (2/2) Notes 1. Obtain the device file from the NEC Electronics website. http://www.necel.com/micro/ods/eng/index.html Under development Depending on the ordering number, supplied with the device. • When QB-V850ESKX1H-ZZZ is ordered The exchange adapter and the target connector are not supplied.
Page 686: When Using Minicube Qb-V850Mini
APPENDIX A DEVELOPMENT TOOLS A.4.2 When using MINICUBE QB-V850MINI (1) Debug emulation by using MINICUBE and QB-V850ESKX1H-DA The system configuration when connecting the MINICUBE and the debug adapter QB-V850ESKX1H-DA to the host machine (PC-9821 series, PC/AT compatible) is shown below. If no option products are prepared, connection is possible.
Page 687 QB-64GB-MA-01S (option) • QB-64GB-MA-01S: 64-pin plastic LQFP (GB-8EU type) Mount adapter Note Obtain the device file from the NEC Electronics website. http://www.necel.com/micro/ods/eng/index.html Remark The numbers in the square brackets correspond to the numbers in Figures A-3 and A-4. User’s Manual U16896EJ2V0UD...
Page 688: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) ID850QB This debugger supports the in-circuit emulators for the V850 Series. The ID850QB is Integrated debugger Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.
Page 689: Embedded Software
APPENDIX A DEVELOPMENT TOOLS A.6 Embedded Software μ RX850, RX850 Pro The RX850 and RX850 Pro are real-time OSs conforming to ITRON 3.0 specifications. Real-time OS A tool (configurator) for generating multiple information tables is supplied. RX850 Pro has more functions than RX850. μ...
Page 690: Appendix B Instruction Set List
APPENDIX B INSTRUCTION SET LIST B.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results.
Page 691 APPENDIX B INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 692 APPENDIX B INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (6) Condition codes Condition Code Condition Formula Explanation (cccc) 0000...
Page 693: Instruction Set (In Alphabetical Order)
APPENDIX B INSTRUCTION SET LIST B.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 11 0 RRRRR GR[reg2]←GR[reg2]+GR[reg1] × × ×...
Page 694 APPENDIX B INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT DBTRAP 1111100001000000 DBPC←PC+2 (restored PC) DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H 0000011111100000 PSW.ID←1 0000000101100000 DISPOSE imm5,list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2) LLLLLLLLLLL00000 GR[reg in list12]←Load-memory(sp,Word)
Page 695 APPENDIX B INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) Note ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword)) Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]←GR[reg2] Other than regID = PSW 0000000000100000 × × × ×...
Page 696 APPENDIX B INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] × × imm16,reg1,reg2 r r rr r1 10 10 0 RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16) i i i i i i i i i i i i i i i i PREPARE...
Page 697 APPENDIX B INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) × reg2,[reg1] r r rr r1 11 11 1 RRRRR adr←GR[reg1] Z flag←Not(Load-memory-bit(adr,reg2)) 0000000011100000...
Page 698 APPENDIX B INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] × × × × SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2] SWITCH reg1 00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
Page 699 APPENDIX B INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. r r r r r = regID specification RRRRR = reg2 specification...
Page 700: Appendix C Register Index
APPENDIX C REGISTER INDEX (1/6) Symbol Name Unit Page ADCR A/D conversion result register ADCRH A/D conversion result register H ADIC Interrupt control register INTC A/D converter mode register Analog input channel specification register ASICL0 LIN operation control register 0 UART ASIF0 Asynchronous serial interface transmit status register 0...
Page 701 APPENDIX C REGISTER INDEX (2/6) Symbol Name Unit Page CSI0IC0 Interrupt control register INTC CSI0IC1 Interrupt control register INTC CSIC0 Clocked serial interface clock selection register 0 CSI0 CSIC1 Clocked serial interface clock selection register 1 CSI0 CSIM00 Clocked serial interface mode register 00 CSI0 CSIM01 Clocked serial interface mode register 01...
Page 702 APPENDIX C REGISTER INDEX (3/6) Symbol Name Unit Page OSTS Oscillation stabilization time selection register Standby Port 0 register Port P0NFC TIP00 noise elimination control register P1NFC TIP01 noise elimination control register Port 3 register Port Port 3 register H Port Port 3 register L Port...
Page 703 APPENDIX C REGISTER INDEX (4/6) Symbol Name Unit Page PM9H Port 9 mode register H Port PM9L Port 9 mode register L Port PMC0 Port 0 mode control register Port PMC3 Port 3 mode control register Port PMC3H Port 3 mode control register H Port PMC3L Port 3 mode control register L...
Page 704 APPENDIX C REGISTER INDEX (5/6) Symbol Name Unit Page SIO01 Serial I/O shift register 1 CSI0 SIO01L Serial I/O shift register 1L CSI0 SIRB0 Clocked serial interface receive buffer register 0 CSI0 SIRB0L Clocked serial interface receive buffer register 0L CSI0 SIRB1 Clocked serial interface receive buffer register 1...
Page 705 APPENDIX C REGISTER INDEX (6/6) Symbol Name Unit Page TMHMD1 8-bit timer H mode register 1 TOC01 16-bit timer output control register 01 TP0CCIC0 Interrupt control register INTC TP0CCIC1 Interrupt control register INTC TP0CCR0 TMP0 capture/compare register 0 TP0CCR1 TMP0 capture/compare register 1 TP0CNT TMP0 counter read buffer register TP0CTL0...
Page 706: Appendix D Revision History
APPENDIX D REVISION HISTORY <R> D.1 Major Revisions in This Edition (1/3) Page Description Throughout Modification of oscillation frequency p. 24 Modification of 1.4 Ordering Information pp. 36, 37 Modification of 2.2 Pin I/O Circuits and Recommended Connection of Unused Pins p.
Page 707 APPENDIX D REVISION HISTORY (2/3) Page Description p. 354 Modification of Caution and addition of Caution 4 to 11.2.3 (1) Watchdog timer mode register 2 (WDTM2) p. 355 Addition of Caution 4 to 11.2.3 (2) Watchdog timer enable register (WDTE) p.
Page 708 APPENDIX D REVISION HISTORY (3/3) Page Description p. 523 Modification of Figure 16-19 Slave Operation Flowchart (2) pp. 525 to 527 Modification of Figure 16-20 Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) pp.
Page 709 Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd. Arcadiastrasse 10 District, Beijing 100083, P.R.China Santa Clara, CA 95050-2554, U.S.A.

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NEC V850ES/KE1+ User Manual

Chapter 1 Introduction

K1 Series Product Lineup

Features

Applications

Ordering Information

Pin Configuration (Top View)

Function Block Configuration

Overview of Functions

Chapter 2 Pin Functions

List of Pin Functions

Pin I/O Circuits and Recommended Connection of Unused Pins

Pin I/O Circuits

Chapter 3 Cpu Functions

Features

CPU Register Set

Operating Modes

Address Space

Chapter 4 Port Functions

Features

Basic Port Configuration

Port Configuration

Block Diagrams

Port Register Setting When Alternate Function Is Used

Cautions

Chapter 5 Clock Generation Function

Overview

Configuration

Registers

Operation

PLL Function

Chapter 6 16-Bit Timer/Event Counter P (Tmp)

Overview

Functions

Configuration

Registers

Operation

Eliminating Noise on Capture Trigger Input Pin (Tip0A)

Cautions

Chapter 7 16-Bit Timer/Event Counter 0

Functions

Configuration

Registers

Operation

Special Use of TM01

Cautions

Chapter 8 8-Bit Timer/Event Counter 5

Functions

Configuration

Registers

Operation

Chapter 9 8-Bit Timer H

Functions

Configuration

Registers

Operation

Chapter 10 Interval Timer, Watch Timer

Interval Timer BRG

Watch Timer

Cautions

Chapter 11 Watchdog Timer Functions

Watchdog Timer 1

Watchdog Timer 2

Chapter 12 Real-Time Output Function (Rto)

Function

Configuration

Registers

Operation

Usage

Cautions

Security Function

Chapter 13 A/D Converter

Overview

Functions

Configuration

Registers

Operation

Cautions

How to Read A/D Converter Characteristics Table

Chapter 14 Asynchronous Serial Interface (Uart)