Page 1 User’s Manual V850E/MA1 32-Bit Single-Chip Microcontroller Hardware µ µ µ µ PD703103A µ µ µ µ PD703105A µ µ µ µ PD703106A µ µ µ µ PD703106A(A) µ µ µ µ PD703107A µ µ µ µ PD703107A(A) µ µ µ µ PD70F3107A µ...
Page 2 [MEMO] User’s Manual U14359EJ4V0UM...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. V850 Series and V850E/MA1 are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
Page 4 NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition (1/3) Page Description • Deletion of the following products: Throughout µ PD703103, 703105, 703106, 703107, and 70F3107 • Addition of the following product names: µ PD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A), 70F3107A, and 70F3107A(A) p.30 Change of description in 1.4 Ordering Information Change of pin configuration in 1.5 Pin Configuration (Top View) 161-pin plastic FBGA (13 ×...
Page 7 Major Revisions in This Edition (2/3) Page Description Addition of Caution to and deletion of reserved word < > of device file from 7.3.5 Interrupt mask registers p.282 0 to 3 (IMR0 to IMR3) Addition of Caution to 7.3.9 (1) External interrupt mode registers 1 to 4 (INTM1 to INTM4) p.284 p.286 Addition of Caution to 7.3.9 (2) Valid edge select registers C0 to C3 (SESC0 to SESC3)
Page 8 Addition of Caution to 14.3.10 (2) (b) Port DL mode control register (PMCDL) p.510 Addition of Caution to 16.2 Writing with Flash Programmer p.511 Addition of Table 16-1 Wiring of Adapter for V850E/MA1 Flash Memory Programming (FA-144GJ- UEN) p.512 Addition of Figure 16-2 Wiring Example of Adapter (FA-161F1-EN4) for V850E/MA1 Flash Memory Programming p.513...
Page 9 The purpose of this manual is for users to gain an understanding of the hardware functions of the V850E/MA1. Organization The V850E/MA1 User’s Manual is divided into two parts: Hardware (this manual) and Architecture (V850E1 User’s Manual Architecture). The organization of each manual is as follows:...
Page 10 • To understand the details of an instruction function →Refer to the V850E1 User’s Manual Architecture. • To understand the overall functions of the V850E/MA1 →Read this manual according to the CONTENTS. • How to interpret the register format →For a bit whose bit number is enclosed in brackets, its bit name is defined as a reserved word in the device file.
Page 11 Document related to development tools (User’s Manuals) Document Name Document No. IE-V850E-MC, IE-V850E-MC-A (In-circuit emulator) U14487E IE-703107-MC-EM1 (In-circuit emulator option board) U14481E CA850 (Ver.2.30 or later) Operation U14568E (C compiler package) C Language U14566E Project Manager U14569E Assembly Language U14567E CA850 (Ver.2.40 or later) (C compiler package) Operation U15024E...
Page 12: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION ....................... 27 Outline............................27 Features ............................. 28 Applications ..........................30 Ordering Information........................ 30 Pin Configuration (Top View) ....................31 Function Blocks ........................35 1.6.1 Internal block diagram ........................35 1.6.2 On-chip units ..........................36 Differences Among Products ....................38 CHAPTER 2 PIN FUNCTIONS.......................
Page 13 4.5.1 Number of access clocks ......................103 4.5.2 Bus sizing function ........................104 4.5.3 Endian control function ......................105 4.5.4 Big endian method usage restrictions in NEC development tools..........106 4.5.5 Bus width ...........................108 Wait Function.......................... 119 4.6.1 Programmable wait function ......................119 4.6.2 External wait function.........................124 4.6.3...
Page 14 5.3.4 DRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6) ........162 5.3.5 DRAM access ..........................165 5.3.6 Refresh control function ......................170 5.3.7 Self-refresh control function .......................175 DRAM Controller (SDRAM) ....................177 5.4.1 Features .............................177 5.4.2 SDRAM connection........................177 5.4.3 Address multiplex function ......................178 5.4.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6)........180 5.4.5...
Page 15 6.13 Forcible Termination ......................260 6.14 Times Related to DMA Transfer .................... 261 6.15 Maximum Response Time for DMA Transfer Request ............261 6.16 One-Time Transfer During Single Transfer via DMARQ0 to DMARQ3 Signals....262 6.17 Cautions ..........................263 6.17.1 Interrupt factors..........................263 6.18 DMA Transfer End ........................
Page 16 9.3.2 PLL mode...........................302 9.3.3 Peripheral command register (PHCMD)..................302 9.3.4 Clock control register (CKC).......................303 9.3.5 Peripheral status register (PHS)....................305 PLL Lockup ..........................306 Power-Save Control........................ 307 9.5.1 Overview ............................307 9.5.2 Control registers.........................309 9.5.3 HALT mode ..........................312 9.5.4 IDLE mode ..........................314 9.5.5 Software STOP mode ........................317 Securing Oscillation Stabilization Time ................
Page 17 11.3 Clocked Serial Interfaces 0 to 2 (CSI0 to CSI2) ..............390 11.3.1 Features.............................390 11.3.2 Configuration ..........................390 11.3.3 Control registers.........................392 11.3.4 Operation ...........................399 11.3.5 Output pins ..........................402 11.3.6 System configuration example....................403 CHAPTER 12 A/D CONVERTER......................404 12.1 Features........................... 404 12.2 Configuration .......................... 404 12.3 Control Registers ........................
Page 18 14.3.1 Port 0 ............................466 14.3.2 Port 1 ............................469 14.3.3 Port 2 ............................471 14.3.4 Port 3 ............................475 14.3.5 Port 4 ............................478 14.3.6 Port 5 ............................481 14.3.7 Port 7 ............................483 14.3.8 Port AL ............................484 14.3.9 Port AH............................486 14.3.10 Port DL ............................488 14.3.11 Port CS............................490 14.3.12 Port CT............................494 14.3.13 Port CM ............................496 14.3.14 Port CD ............................499...
Page 19 16.7.5 Software environment ........................525 16.7.6 Self-programming function number....................526 16.7.7 Calling parameters........................527 16.7.8 Contents of RAM parameters ....................528 16.7.9 Errors during self-programming ....................529 16.7.10 Flash information ........................529 16.7.11 Area number ..........................530 16.7.12 Flash programming mode control register (FLPMC) ..............531 16.7.13 Calling device internal processing....................533 16.7.14 Erasing flash memory flow......................536 16.7.15 Successive writing flow ......................537 16.7.16 Internal verify flow ........................538...
Page 20 LIST OF FIGURES (1/5) Figure No. Title Page CPU Address Space............................72 Images on Address Space..........................73 Memory Map ( µ PD703103A, 703105A)......................75 Memory Map ( µ PD703106A, 703107A, 70F3107A) ..................76 Internal ROM Area in Single-Chip Mode 1......................79 Recommended Memory Map..........................84 Example When CSC0 Register Is Set to 0703H ...................100 Big Endian Addresses Within Word ......................106 Little Endian Addresses Within Word......................106 Timing Example of Access to SRAM, External ROM, and External I/O (Read →...
Page 21 LIST OF FIGURES (2/5) Figure No. Title Page Single Transfer Example 3 ...........................225 Single Transfer Example 4 ...........................225 Single-Step Transfer Example 1........................226 Single-Step Transfer Example 2........................226 Block Transfer Example ..........................227 Timing of Access to SRAM, External ROM, and External I/O During 2-Cycle DMA Transfer.......229 Timing of 2-Cycle DMA Transfer (External I/O →...
Page 22 LIST OF FIGURES (3/5) Figure No. Title Page Power-Save Mode State Transition Diagram....................308 10-1 Basic Operation of Timer C...........................334 10-2 Operation After Overflow (When OSTn = 1) ....................335 10-3 Capture Operation Example .........................336 10-4 TMC1 Capture Operation Example (When Both Edges Are Specified) ............337 10-5 Compare Operation Example ........................338 10-6...
Page 23 LIST OF FIGURES (4/5) Figure No. Title Page 12-3 Select Mode Operation Timing: 1-Buffer Mode (ANI1) .................416 12-4 Select Mode Operation Timing: 4-Buffer Mode (ANI6) .................417 12-5 Scan Mode Operation Timing: 4-Channel Scan (ANI0 to ANI3) ..............418 12-6 Example of 1-Buffer Mode Operation (A/D Trigger Select: 1 Buffer) ............419 12-7 Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers) ............420 12-8...
Page 24 14-13 Block Diagram of Type M..........................463 14-14 Block Diagram of Type N ..........................464 14-15 Block Diagram of Type O..........................465 16-1 Wiring Example of Adapter (FA-144GJ-UEN) for V850E/MA1 Flash Memory Programming .......510 16-2 Wiring Example of Adapter (FA-161F1-EN4) for V850E/MA1 Flash Memory Programming ......512 16-3 Outline of Self-Programming.........................521...
Page 25 LIST OF TABLES (1/2) Table No. Title Page Program Registers............................67 System Register Numbers..........................68 Interrupt/Exception Table ..........................78 Bus Cycles in Which Wait Function Is Valid ....................125 Bus Priority Order ............................139 Example of DRAM and Address Multiplex Width..................161 Interval Factor Setting Examples........................172 Example of Interval Factor Settings......................198 Relationship Between Transfer Type and Transfer Object ................255 External Bus Cycles During DMA Transfer....................256...
Page 26 LIST OF TABLES (2/2) Table No. Title Page 16-1 Wiring of Adapter for V850E/MA1 Flash Memory Programming (FA-144GJ-UEN) ........511 16-2 Wiring of Adapter for V850E/MA1 Flash Memory Programming (FA-161F1-EN4) ........513 16-3 List of Communication Modes........................519 16-4 Function List ..............................522 16-5 Software Environmental Conditions......................525...
Page 27: Chapter 1 Introduction
The on-chip flash memory version ( µ PD70F3107A) has on-chip flash memory, which is capable of high- speed access, and since it is possible to rewrite a program with the V850E/MA1 mounted as is in the application system, system development time can be reduced and system maintainability after shipping can be markedly improved.
Page 28: Features
CHAPTER 1 INTRODUCTION 1.2 Features Number of instructions: Minimum instruction execution time: 20 ns (at internal 50 MHz operation) 32 bits × 32 General-purpose registers: Instruction set: V850E1 CPU Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits): 1 to 2 clocks Saturated operation instructions (with overflow/underflow detection function)
Page 29 CHAPTER 1 INTRODUCTION DMA controller: 4 channels Transfer unit: 8 bits/16 bits Maximum transfer count: 65,536 (2 Transfer type: Flyby (1-cycle)/2-cycle Transfer mode: Single/Single step/Block Transfer target: Memory ↔ memory, memory ↔ I/O Transfer request: External request/On-chip peripheral I/O/ Software DMA transfer terminate (terminal count) output signal Next address setting function I/O lines:...
Page 30: Applications
The µ PD703106A, 703107A, and 70F3107A do not differ from the µ PD703106A(A), 703107A(A), and 70F3107A(A) except the quality grade. Please refer to Quality Grades on NEC Semiconductor Devices (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Page 31: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) • 144-pin plastic LQFP (fine pitch) (20 × 20) µ PD703103AGJ-UEN µ PD703106AGJ(A)-×××-UEN µ PD703105AGJ-×××-UEN µ PD703107AGJ(A)-×××-UEN µ PD703106AGJ-×××-UEN µ PD70F3107AGJ(A)-UEN µ PD703107AGJ-×××-UEN µ PD70F3107AGJ-UEN D14/PDL14 PCD3/UBE/SDRAS D13/PDL13 PCS0/CS0 D12/PDL12 PCS1/CS1/RAS1 D11/PDL11 PCS2/CS2/IOWR D10/PDL10 PCS3/CS3/RAS3...
Page 32 CHAPTER 1 INTRODUCTION • 161-pin plastic FBGA (13 × 13) µ PD703106AF1-×××-EN4 µ PD703107AF1-×××-EN4 µ PD70F3107AF1-EN4 Top View Bottom View A B C D E F G H J K L M N P P N M L K J H G F E D C B A Index mark Index mark (1/2)
Page 33 CHAPTER 1 INTRODUCTION (2/2) Pin Name Pin Name Pin Name Number Number Number – TI030/INTP030/P50 SCK1/P45 CS6/RAS6/PCS6 SELFREF/PCM5 TXD0/SO0/P40 CS4/RAS4/PCS4 INTP031/P51 ANI6/P76 CS7/PCS7 PWM0/P00 ANI5/P75 – D2/PDL2 DMAAK1/PBD1 – D3/PDL3 DMAAK3/PBD3 PWM1/P10 D4/PDL4 ANI1/P71 TC3/INTP113/P27 ANI0/P70 TC0/INTP110/P24 RD/PCT4 NMI/P20 ADTRG/INTP123/P37 LCAS/LWR/LDQM/PCT0 –...
Page 34 CHAPTER 1 INTRODUCTION Pin Identification A0 to A25: Address bus P70 to P77: Port 7 ADTRG: A/D trigger input PAH0 to PAH9: Port AH ANI0 to ANI7: Analog input PAL0 to PAL15: Port AL Analog power supply PBD0 to PBD3: Port BD Analog reference voltage PCD0 to PCD3:...
Page 35: Function Blocks
CHAPTER 1 INTRODUCTION 1.6 Function Blocks 1.6.1 Internal block diagram HLDRQ MEMC HLDAK INTP100 to INTP103, INTC CS0, CS7 INTP110 to INTP113, CS1/RAS1, CS3/RAS3 INTP120 to INTP123, Instruction CS4/RAS4, CS6/RAS6 DRAMC INTP130 to INTP133 queue CS2/IORD CS5/IOWR INTP000 to INTP001, Note 1 SELFREF INTP010 to INTP011,...
Page 36: On-Chip Units
CHAPTER 1 INTRODUCTION 1.6.2 On-chip units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits) and a barrel shifter (32 bits), help accelerate processing of complex instructions.
Page 37 CHAPTER 1 INTRODUCTION (3) ROM The µ PD703105A and 703106A have 128 KB of on-chip mask ROM, the µ PD703107A has 256 KB of on-chip mask ROM and the µ PD70F3107A has 256 KB of on-chip flash memory. The µ PD703103A does not include on-chip ROM.
Page 38: Differences Among Products
CHAPTER 1 INTRODUCTION (11) Ports As shown below, the following ports have general port functions and control pin functions. Port Port Function Control Function Port 0 8-bit I/O Real-time pulse unit I/O, external interrupt input, PWM output, DMA controller input Port 1 4-bit I/O Real-time pulse unit I/O, external interrupt input, PWM output...
Page 39: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The names and functions of the pins in the V850E/MA1 are listed below. These pins can be divided into port pins and non-port pins according to their functions. 2.1 List of Pin Functions (1) Port pins...
Page 40 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Function Alternate Function TXD0/SO0 Port 4 6-bit I/O port RXD0/SI0 Input/output can be specified in 1-bit units. SCK0 TXD1/SO1 RXD1/SI1 SCK1 Port 5 INTP030/TI030 3-bit I/O port INTP031 Input/output can be specified in 1-bit units. TO03 P70 to P77 Input...
Page 41 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Function Alternate Function PAH0 to PAH9 A16 to A25 Port AH 8-/10-bit I/O port Input/output can be specified in 1-bit units. PAL0 to PAL15 Port AL A0 to A15 8-/16-bit I/O port Input/output can be specified in 1-bit units. PDL0 to PDL15 Port DL D0 to D15...
Page 42 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/4) Pin Name Function Alternate Function TO00 Output Pulse signal output of timer C0 to C3 TO01 TO02 TO03 TI000 Input External count clock input of timer C0 to C3 P01/INTP000 TI010 P11/INTP010 TI020 P21/INTP020 TI030...
Page 43 DMA transfer end (terminal count) signal output P24/INTP110 P25/INTP111 P26/INTP112 P27/INTP113 Input Non-maskable interrupt request signal input − MODE0 Input V850E/MA1 operating mode specification − MODE1 MODE2 Input Flash memory programming power-supply application pin MODE2 ( µ PD70F3107A only) WAIT Input...
Page 44 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name Function Alternate Function LCAS Output Column address strobe signal output for DRAM lower data PCT0/LWR/LDQM UCAS Output Column address strobe signal output for DRAM higher data PCT1/UWR/UDQM Output External data lower byte write strobe signal output PCT0/LCAS/LDQM Output External data higher byte write strobe signal output...
Page 45 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name Function Alternate Function − CKSEL Input Input specifying the clock generator's operating mode Input Reference voltage applied to A/D converter − Positive power supply for A/D converter − − Ground potential for A/D converter −...
Page 46: Pin Status
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The status of each pin after reset, in power-save mode (software STOP, IDLE, HALT modes), and during DMA transfer, refresh, and bus hold (TH) is shown below. Operating Status Bus Hold Reset Reset IDLE Mode/Software HALT Mode/During (TH)
Page 47: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (Port 0) ··· 3-state I/O P00 to P07 function as an 8-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the real-time pulse unit (RPU), external interrupt request inputs, a PWM output, and DMA request inputs.
Page 48 CHAPTER 2 PIN FUNCTIONS (2) P10 to P13 (Port 1) ··· 3-state I/O P10 to P13 function as a 4-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the real-time pulse unit (RPU), external interrupt request inputs, and a PWM output.
Page 49 CHAPTER 2 PIN FUNCTIONS (3) P20 to P27 (Port 2) ··· 3-state I/O P20 is an input-only pin. P21 to P27 function as a 7-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the real-time pulse unit (RPU), external interrupt request inputs, and DMA transfer termination outputs (terminal count).
Page 50 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) ··· 3-state I/O P30 to P37 function as an 8-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the serial interfaces (CSI2, UART2), external interrupt request inputs, and the A/D converter external trigger input.
Page 51 CHAPTER 2 PIN FUNCTIONS (5) P40 to P45 (Port 4) ··· 3-state I/O P40 to P45 function as a 6-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the serial interfaces (UART0/CSI0, UART1/CSI1).
Page 52 CHAPTER 2 PIN FUNCTIONS (6) P50 to P52 (Port 5) ··· 3-state I/O P50 to P52 function as a 3-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the real-time pulse unit (RPU) and external interrupt request inputs.
Page 53 CHAPTER 2 PIN FUNCTIONS (8) PBD0 to PBD3 (Port BD) ··· 3-state I/O PBD0 to PBD3 function as a 4-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in the control mode, these pins operate as DMA acknowledge outputs. The operation mode can be set to port or control in 1-bit units, specified by the port BD mode control register (PMCBD).
Page 54 (v) HLDRQ (Hold request) ··· input In this mode, this pin is the input pin through which an external device requests the V850E/MA1 to release the address bus, data bus, and control bus. The HLDRQ signal can be input asynchronously to the CLKOUT signal.
Page 55 CHAPTER 2 PIN FUNCTIONS (10) PCT0, PCT1, PCT4 to PCT7 (Port CT) ··· 3-state I/O PCT0, PCT1, PCT4 to PCT7 function as a 6-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when memory is expanded externally.
Page 56 CHAPTER 2 PIN FUNCTIONS (vii) RD (Read strobe) ··· 3-state output This strobe signal shows that the bus cycle currently being executed is a read cycle for the SRAM, external ROM, external peripheral I/O, or page ROM area. In the idle state (TI), it becomes inactive. (viii) WE (Write enable) ···...
Page 57 CHAPTER 2 PIN FUNCTIONS (11) PCS0 to PCS7 (Port CS) ··· 3-state I/O PCS0 to PCS7 function as an 8-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when memory and peripheral I/O are expanded externally.
Page 58 CHAPTER 2 PIN FUNCTIONS (12) PCD0 to PCD3 (Port CD) ··· 3-state I/O PCD0 to PCD3 function as a 4-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as a port, in control mode, these pins operate as control signal outputs for when the memory and peripheral I/O are expanded externally.
Page 59 CHAPTER 2 PIN FUNCTIONS (13) PAH0 to PAH9 (Port AH) ··· 3-state I/O PAH0 to PAH9 function as an 8- or 10-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these pins operate as an address bus (A16 to A25) for when the memory is expanded externally.
Page 60 CHAPTER 2 PIN FUNCTIONS (15) PDL0 to PDL15 (Port DL) ··· 3-state I/O PDL0 to PDL15 function as an 8- or 16-bit I/O port that can be set to input or output in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these pins operate as a data bus (D0 to D15) for when the memory is expanded externally.
Page 61 CHAPTER 2 PIN FUNCTIONS (24) AV (Analog power supply) This is the analog positive power supply pin for the A/D converter. (25) AV (Analog ground) This is the ground pin for the A/D converter. (26) AV (Analog reference voltage) ··· input This is the reference voltage supply pin for the A/D converter.
Page 62: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins It is recommended that 1 to 10 kΩ resistors be used when connecting to V or V via resistors. (1/2) Pin Name I/O Circuit Type Recommended Connection P00/PWM0 Input: Independently connect to V or V...
Page 63 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name I/O Circuit Type Recommended Connection PCM2/HLDAK Input: Independently connect to V or V via a resistor Output: Leave open PCM3/HLDRQ Input: Independently connect to V via a resistor PCM4/REFRQ Input: Independently connect to V or V via a resistor Output: Leave open...
Page 64: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type 1 Type 5-AC Data P-ch IN/OUT P-ch Output N-ch disable N-ch Input enable Type 2 Type 9 P-ch Comparator N-ch (threshold voltage) Schmitt-triggered input with hysteresis characteristics Input enable Type 5 Data P-ch IN/OUT...
Page 65: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850E/MA1 is based on RISC architecture and executes almost all the instructions in one clock cycle using 5-stage pipeline control. 3.1 Features • Minimum instruction cycle: 20 ns (@ 50 MHz internal operation) •...
Page 66: Cpu Register Set
CPU FUNCTION 3.2 CPU Register Set The registers of the V850E/MA1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have a 32-bit width. For details, refer to V850E1 User’s Manual Architecture.
Page 67: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 68: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, specify a system register number indicated below using the system register load/store instruction (LDSR or STSR instruction). Table 3-2.
Page 69 CHAPTER 3 CPU FUNCTION (2) Program status word (PSW) After reset 00000020H Bit position Flag Function 31 to 8 Reserved field (fixed to 0). Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set when an NMI is acknowledged, and disables multiple interrupts. 0: NMI servicing not under execution.
Page 70: Operating Modes
CPU FUNCTION 3.3 Operating Modes 3.3.1 Operating modes The V850E/MA1 has the following operating modes. Mode specification is carried out using the MODE0 to MODE2 pins. (1) Normal operation mode (a) Single-chip modes 0, 1 Access to the internal ROM is enabled.
Page 71: Operating Mode Specification
CHAPTER 3 CPU FUNCTION 3.3.2 Operating mode specification The operating mode is specified according to the status of the MODE0 to MODE2 pins. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation.
Page 72: Address Space
CPU address space The CPU of the V850E/MA1 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported.
Page 73: Image
CHAPTER 3 CPU FUNCTION 3.4.2 Image A 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits 31 to 28 of the CPU address. Figure 3-2 shows the image of the virtual addressing space.
Page 74: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of a branch address calculation, the higher 6 bits ignore the carry or borrow.
Page 75: Memory Map
CPU FUNCTION 3.4.4 Memory map The V850E/MA1 reserves areas as shown in Figures 3-3 and 3-4. The mode is specified by the MODE0 to MODE2 pins. Figure 3-3. Memory Map ( µ µ µ µ PD703103A, 703105A) Single-chip mode 0...
Page 76 CHAPTER 3 CPU FUNCTION Figure 3-4. Memory Map ( µ µ µ µ PD703106A, 703107A, 70F3107A) Single-chip mode 0 Single-chip mode 1 ROMless mode 0, 1 xFFFFFFFH Internal peripheral Internal peripheral Internal peripheral 4 KB I/O area I/O area I/O area xFFFF000H xFFFEFFFH xFFFE800H...
Page 77: Area
• In single-chip mode 1: Addresses 100000H to 13FFFFH (b) Interrupt/exception table The V850E/MA1 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area.
Page 78 CHAPTER 3 CPU FUNCTION Table 3-3. Interrupt/Exception Table (1/2) Start Address of Interrupt/Exception Table Interrupt/Exception Source 00000000H RESET 00000010H 00000040H TRAP0n (n = 0 to F) 00000050H TRAP1n (n = 0 to F) 00000060H ILGOP/DBG0 00000080H INTOV00 00000090H INTOV01 000000A0H INTOV02 000000B0H INTOV03...
Page 79 CHAPTER 3 CPU FUNCTION Table 3-3. Interrupt/Exception Table (2/2) Start Address of Interrupt/Exception Table Interrupt/Exception Source 00000280H INTDMA0 00000290H INTDMA1 000002A0H INTDMA2 000002B0H INTDMA3 000002C0H INTCSI0 000002D0H INTSER0 000002E0H INTSR0 000002F0H INTST0 00000300H INTCSI1 00000310H INTSER1 00000320H INTSR1 00000330H INTST1 00000340H INTCSI2 00000350H...
Page 80 CHAPTER 3 CPU FUNCTION (2) Internal RAM area The 12 KB area of addresses FFFC000H to FFFEFFFH are reserved for the internal RAM area. The 12 KB area of 3FFC000H to 3FFEFFFH can be seen as an image of FFFC000H to FFFEFFFH. In the µ...
Page 81 I/O are all memory-mapped to the internal peripheral I/O area. Program fetches cannot be executed from this area. Cautions 1. In the V850E/MA1, no registers exist which are capable of word access, but if a register is word accessed, halfword access is performed twice in the order of lower address, then higher address of the word area, disregarding the lower 2 bits of the address.
Page 82: External Memory Expansion
CHAPTER 3 CPU FUNCTION 3.4.6 External memory expansion By setting the port n mode control register (PMCn) to control mode, an external memory device can be connected to the external memory space using each pin of ports AL, AH, DL, CS, CT, CM, and CD. Each register is set by selecting control mode for each pin of these ports using PMCn (n = AL, AH, DL, CS, CT, CM, CD).
Page 83: Recommended Use Of Address Space
(2) Data space With the V850E/MA1, a 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. The highest bit (bit 25) of this 26-bit address is assigned as an address sign-extended to 32 bits.
Page 84 CHAPTER 3 CPU FUNCTION Figure 3-6. Recommended Memory Map Program space Data space FFFFFFFFH On-chip peripheral I/O FFFFFC14H FFFFFC13H FFFFF000H FFFFEFFFH Internal RAM xFFFFFFFH On-chip peripheral I/O xFFFFC14H FFFFC000H xFFFFC13H FFFFBFFFH xFFFF000H xFFFEFFFH Internal RAM xFFFD000H xFFFCFFFH xFFFC000H 04000000H xFFFFBFFFH 03FFFFFFH On-chip Note...
Page 85: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.8 Peripheral I/O registers (1/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFFFF000H Port AL Undefined FFFFF000H Port ALL PALL Undefined FFFFF001H Port ALH PALH Undefined FFFFF002H Port AH Undefined...
Page 86 CHAPTER 3 CPU FUNCTION (2/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFFFF044H Port DL mode control register PMCDL 0000H/FFFFH FFFFF044H Port DL mode control register L PMCDLL 00H/FFH FFFFF045H Port DL mode control register H PMCDLH 00H/FFH...
Page 87 CHAPTER 3 CPU FUNCTION (3/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFFFF0D2H DMA addressing control register 1 DADC1 0000H FFFFF0D4H DMA addressing control register 2 DADC2 0000H FFFFF0D6H DMA addressing control register 3 DADC3 0000H FFFFF0E0H...
Page 88 CHAPTER 3 CPU FUNCTION (4/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFFFF130H Interrupt control register P11IC0 FFFFF132H Interrupt control register P11IC1 FFFFF134H Interrupt control register P11IC2 FFFFF136H Interrupt control register P11IC3 FFFFF138H Interrupt control register...
Page 89 CHAPTER 3 CPU FUNCTION (5/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFFFF201H A/D converter mode register 1 ADM1 FFFFF202H A/D converter mode register 2 ADM2 FFFFF210H A/D conversion result register 0 (10 bits) ADCR0 0000H FFFFF212H...
Page 90 CHAPTER 3 CPU FUNCTION (6/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFFFF460H Port 0 function control register PFC0 FFFFF464H Port 2 function control register PFC2 FFFFF466H Port 3 function control register PFC3 FFFFF468H Port 4 function control register...
Page 91 CHAPTER 3 CPU FUNCTION (7/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFFFF564H Timer mode control register D2 TMCD2 FFFFF570H Timer D3 TMD3 0000H FFFFF572H Compare register D3 CMD3 0000H FFFFF574H Timer mode control register D3 TMCD3...
Page 92 CHAPTER 3 CPU FUNCTION (8/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFFFF880H External interrupt mode register 0 INTM0 FFFFF882H External interrupt mode register 1 INTM1 FFFFF884H External interrupt mode register 2 INTM2 FFFFF886H External interrupt mode register 3...
Page 93 CHAPTER 3 CPU FUNCTION (9/9) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FFFFFA20H Aynchronous serial interface mode register 2 ASIM2 FFFFFA22H Receive buffer register 2 RXB2 FFFFFA23H Asynchronous serial interface status register 2 ASIS2 FFFFFA24H Transmit buffer register 2...
Page 94: Specific Registers
I/O registers. Access to on-chip peripheral I/O registers is made in 3 clocks (without wait), however, in the V850E/MA1 waits may be required depending on the operation frequency. Set the values described in the table below to the VSWC in accordance with the operation frequency used.
Page 95: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V850E/MA1 is provided with an external bus interface function by which external I/O and memories, such as ROM and RAM, can be connected. 4.1 Features • 16-bit/8-bit data bus sizing function • 8-space chip select function •...
Page 96: Pin Status During Internal Rom, Internal Ram, And Peripheral I/O Access
CHAPTER 4 BUS CONTROL FUNCTION 4.2.1 Pin status during internal ROM, internal RAM, and peripheral I/O access While accessing internal ROM and RAM, the address bus becomes undefined, and the data bus control signals are not output and enter the high-impedance state. The external bus control signals become inactive. While accessing peripheral I/O, the address bus outputs the address data of the on-chip peripheral I/O currently being accessed, and the data bus control signals are not output and enter the high-impedance state.
Page 97: Memory Block Function
CHAPTER 4 BUS CONTROL FUNCTION 4.3 Memory Block Function The 256 MB memory space is divided into memory blocks of 2 MB and 64 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for each block. The area that can be used as program area is the 64 MB space of addresses 0000000H to 3FFFFFFH.
Page 98: Chip Select Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.3.1 Chip select control function Of the 256 MB memory area, the lower 8 MB (0000000H to 07FFFFFH) and the higher 8 MB (F800000H to FFFFFFFH) can be divided into 2 MB memory blocks by chip area select control registers 0 and 1 (CSC0, CSC1) to control the chip select signal.
Page 99 CHAPTER 4 BUS CONTROL FUNCTION Address After reset CSC0 CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00 FFFFF060H 2C11H Address After reset CSC1 CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60...
Page 100 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-1. Example When CSC0 Register Is Set to 0703H 3FFFFFFH CS1 is output. 58 MB 0800000H 07FFFFFH Block 3 (2 MB) 0600000H 05FFFFFH Block 2 2 MB CS2 is output. (2 MB) 0400000H 03FFFFFH Block 1 (2 MB) 0200000H...
Page 101: Bus Cycle Type Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.4 Bus Cycle Type Control Function In the V850E/MA1, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O • Page ROM • EDO DRAM • SDRAM Connected external devices are specified by bus cycle type configuration registers 0 and 1 (BCT0 and BCT1).
Page 102: Bus Cycle Type Configuration Registers 0, 1 (Bct0, Bct1)
CHAPTER 4 BUS CONTROL FUNCTION 4.4.1 Bus cycle type configuration registers 0, 1 (BCT0, BCT1) (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) These registers can be read/written in 16-bit units. Be sure to set bits 14, 10, 9, 6, 2, and 1 to 0. If they are set to 1, the operation is not guaranteed. Caution Write to the BCT0 and BCT1 registers after reset, and then do not change the set value.
Page 103: Bus Access
CHAPTER 4 BUS CONTROL FUNCTION 4.5 Bus Access 4.5.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Bus Cycle Configuration Instruction Fetch Operand Data Access Resource (Bus Width) Note 1 Internal ROM (32 bits) Note 2 Internal RAM (32 bits) Notes 1.
Page 104: Bus Sizing Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 Bus sizing function The bus sizing function controls the data bus width for each CS space. The data bus width is specified by using the bus size configuration register (BSC). (1) Bus size configuration register (BSC) This register can be read/written in 16-bit units.
Page 105: Endian Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.3 Endian control function The endian control function can be used to set processing of word data in memory using either the big endian method or the little endian method for each CS space selected with the chip select signals (CS0 to CS7). Switching of the endian method is specified using the endian configuration register (BEC).
Page 106: Big Endian Method Usage Restrictions In Nec Development Tools
0003H 0002H 0001H 0000H 4.5.4 Big endian method usage restrictions in NEC development tools (1) When using a debugger (ID850) The big endian method is supported only in the memory window display. (2) When using a compiler (CA850) (a) Restrictions in C language (i) There are restrictions for variables allocated to/located in the big endian space, as shown below.
Page 107 CHAPTER 4 BUS CONTROL FUNCTION [Related global optimization part] • 1-bit set using bit or int i; i ^=1; • 1-bit clear using bit and i &= ~1; • 1-bit not using bit xor i ^= 1; • 1-bit test using bit and if(i &...
Page 108: Bus Width
BUS CONTROL FUNCTION 4.5.5 Bus width The V850E/MA1 accesses peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. All data is accessed in order starting from the lower order side.
Page 109 CHAPTER 4 BUS CONTROL FUNCTION (d) When the data bus width is 8 bits (big endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 2n + 1 Byte data External Byte data External data bus data bus...
Page 110 CHAPTER 4 BUS CONTROL FUNCTION (c) When the data bus width is 16 bits (big endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1st access 2nd access Address Address Address 2n + 2 2n + 1 2n + 1 Halfword...
Page 111 CHAPTER 4 BUS CONTROL FUNCTION (3) Word access (32 bits) (a) When the bus width is 16 bits (little endian) (1/2) <1> Access to address (4n) 1st access 2nd access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data...
Page 112 CHAPTER 4 BUS CONTROL FUNCTION (a) When the bus width is 16 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 2nd access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data...
Page 113 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (1/2) <1> Access to address (4n) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External...
Page 114 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data...
Page 115 CHAPTER 4 BUS CONTROL FUNCTION (c) When the data bus width is 16 bits (big endian) (1/2) <1> Access to address (4n) 1st access 2nd access Address Address 4n + 2 4n + 1 4n + 3 Word data External Word data External data bus...
Page 116 CHAPTER 4 BUS CONTROL FUNCTION (c) When the data bus width is 16 bits (big endian) (2/2) <3> Access to address (4n + 2) 1st access 2nd access Address Address 4n + 2 4n + 4 4n + 3 4n + 5 Word data External Word data...
Page 117 CHAPTER 4 BUS CONTROL FUNCTION (d) When the data bus width is 8 bits (big endian) (1/2) <1> Access to address (4n) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 3 4n + 1 4n + 2 Word data External...
Page 118 CHAPTER 4 BUS CONTROL FUNCTION (d) When the data bus width is 8 bits (big endian) (2/2) <3> Access to address (4n + 2) 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 5 4n + 2 4n + 3 4n + 4 Word data...
Page 119: Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6 Wait Function 4.6.1 Programmable wait function (1) Data wait control registers 0, 1 (DWC0, DWC1) To facilitate interfacing with low-speed memory and I/Os, it is possible to insert up to 7 data wait states in the starting bus cycle for each CS space.
Page 120 CHAPTER 4 BUS CONTROL FUNCTION Address After reset DWC0 0 DW32 DW31 DW30 0 DW22 DW21 DW20 0 DW12 DW11 DW10 0 DW02 DW01 DW00 FFFFF484H 7777H CSn signal Address After reset DWC1 0 DW72 DW71 DW70 0 DW62 DW61 DW60 0 DW52 DW51 DW50 0 DW42 DW41 DW40 FFFFF486H 7777H CSn signal...
Page 121 BUS CONTROL FUNCTION (2) Address setup wait control register (ASC) The V850E/MA1 allows insertion of address setup wait states before the SRAM/page ROM cycle (the setting of the ASC register in the EDO DRAM/SDRAM cycle is invalid). The number of address setup wait states can be set with the ASC register for each CS space.
Page 122 (3) Bus cycle period control register (BCP) In the V850E/MA1, the bus cycle period can be doubled during SRAM, external ROM, and external I/O access. The bus cycle period is controlled using the BCP register. When the BCP bit of the BCP register is set to 1, the external bus operates at one half the frequency of the internal system clock.
Page 123 CHAPTER 4 BUS CONTROL FUNCTION Figure 4-4. Timing Example of Access to SRAM, External ROM, and External I/O (Read → → → → Write) Internal system clock BUSCLK (output) Address Address A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output)
Page 124: External Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (WAIT) for synchronization with the external device. Just as with programmable waits, accessing internal ROM, internal RAM, and on-chip peripheral I/O areas cannot be controlled by external waits.
Page 125: Bus Cycles In Which Wait Function Is Valid
4.6.4 Bus cycles in which wait function is valid In the V850E/MA1, the number of waits can be specified according to the memory type specified for each memory block. The following shows the bus cycles in which the wait function is valid and the registers used for wait setting.
Page 126: Idle State Insertion Function
CHAPTER 4 BUS CONTROL FUNCTION 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the current bus cycle after the T2 state to meet the data output float delay time (t ) on memory read access for each CS space.
Page 127: Bus Hold Function
If the HLDRQ pin becomes inactive (high level) and the bus mastership request is canceled, driving of these pins begins again. During the bus hold period, the internal operations of the V850E/MA1 continue until the external memory is accessed.
Page 128: Bus Hold Procedure
CHAPTER 4 BUS CONTROL FUNCTION 4.8.2 Bus hold procedure The procedure of the bus hold function is illustrated below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests held pending Normal state <3> End of current bus cycle <4>...
Page 129: Bus Hold Timing (Sram)
CHAPTER 4 BUS CONTROL FUNCTION 4.8.4 Bus hold timing (SRAM) (1) SRAM (when read, no idle states inserted) Note 1 Note 1 CLKOUT (input) HLDRQ (input) HLDAK (output) Address Undefined A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output)
Page 130 CHAPTER 4 BUS CONTROL FUNCTION (2) SRAM (when written, three idle states inserted) Note 1 Note 1 Note 1 Note 2 Note 2 CLKOUT (input) HLDRQ (input) HLDAK (output) Address Undefined A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output)
Page 131: Bus Hold Timing (Edo Dram)
CHAPTER 4 BUS CONTROL FUNCTION 4.8.5 Bus hold timing (EDO DRAM) (1) EDO DRAM (when read, no idle states inserted) Note 1 Note 3 TRPW CLKOUT (input) HLDRQ (input) HLDAK (output) Column Undefined A0 to A25 (output) address address BCYST (output) CSn/RASm (output) Note 2 RD (output)
Page 132 CHAPTER 4 BUS CONTROL FUNCTION (2) EDO DRAM (when read, three idle states inserted) Note 1 Note 3 Note 4 TRPW CLKOUT (input) HLDRQ (input) HLDAK (output) Column Undefined A0 to A25 (output) address address BCYST (output) CSn/RASm (output) Note 2 RD (output) OE (output) WE (output)
Page 133 CHAPTER 4 BUS CONTROL FUNCTION (3) EDO DRAM (when written) Note 1 Note 3 TRPW CLKOUT (input) HLDRQ (input) HLDAK (output) Column Undefined A0 to A25 (output) address address BCYST (output) CSn/RASm (output) Note 2 RD (output) OE (output) WE (output) UWR/UCAS (output) LWR/LCAS (output) IORD (output)
Page 134 CHAPTER 4 BUS CONTROL FUNCTION (4) EDO DRAM (when written, when bus hold request acknowledged during on-page access) Off-page cycle Note 1 Note 1 Note 2 Note 2 Note 1 TRPW TCPW TRPW CLKOUT (input) HLDRQ (input) HLDAK (output) Column Column Undefined A0 to A25 (output)
Page 135: Bus Hold Timing (Sdram)
CHAPTER 4 BUS CONTROL FUNCTION 4.8.6 Bus hold timing (SDRAM) (1) SDRAM (when read, latency = 2, no idle states inserted) Note 1 Note 1 Note 2 TACT TBCW TREAD TLATE TLATE TPRE SDCLK (output) HLDRQ (input) HLDAK (output) Note 3 (output) Address Undefined Bank...
Page 136 CHAPTER 4 BUS CONTROL FUNCTION (2) SDRAM (when read, latency = 2, three idle states inserted) Note 1 Note 1 Note 1 Note 2 Note 2 Note 3 TACT TBCW TREAD TLATE TLATE TPRE SDCLK (output) HLDRQ (input) HLDAK (output) Note 4 (output) Address Undefined...
Page 137 CHAPTER 4 BUS CONTROL FUNCTION (3) SDRAM (when written) Note 1 Note 1 Note 2 TACT TBCW TWR TWPRE TWE TPRE SDCLK (output) HLDRQ (input) HLDAK (output) Address Note 3 (output) Undefined Bank Undefined Bank address (output) Address address A10 (output) Undefined Address address...
Page 138 CHAPTER 4 BUS CONTROL FUNCTION (4) SDRAM (when written, when bus hold request acknowledged during on-page access) Note 1 Note 1 Note 2 TACT TBCW TWR TWR TWPRE TWE TPRE SDCLK (output) HLDRQ (input) HLDAK (output) Address Address Note 3 (output) Undefined Bank Undefined...
Page 139: Bus Priority Order
CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority Order There are five external bus cycles: bus hold, instruction fetch, operand data access, DMA cycle, and refresh cycle. In order of priority, bus hold is the highest, followed by the refresh cycle, DMA cycle, operand data access, and instruction fetch, in that order.
Page 140: Boundary Operation Conditions
4.10.2 Data space The V850E/MA1 is provided with an address misalign function. Through this function, regardless of the data format (word or halfword), data can be allocated to all addresses.
Page 141: Chapter 5 Memory Access Control Function
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features • SRAM is accessed in a minimum of 2 states. • Up to 7 states of programmable data waits can be inserted by setting the DWC0 and DWC1 registers. •...
Page 142: Sram Connection
(128 Kwords × 8 bits) A0 to A16 D8 to D15 D1 to D8 1 Mb SRAM V850E/MA1 (128 Kwords × 8 bits) (b) When data bus width is 16 bits A1 to A17 A0 to A16 D0 to D15...
Page 143 SDCAS/LBE SDCLK SDCKE 64 Mb SDRAM V850E/MA1 (1 Mword × 16 bits × 4 banks) Note The address signals used depend on the SDRAM model. Remark n = 0 to 7, m = 1, 3, 4, 6 (n ≠ m)
Page 144: Sram, External Rom, External I/O Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1.3 SRAM, external ROM, external I/O access Figure 5-2. SRAM, External ROM, External I/O Access Timing (1/6) (a) When read CLKOUT (output) Address Address A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output)
Page 145 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (2/6) (b) When read (address setup wait, idle state insertion) TASW CLKOUT (output) Address A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output) LWR/LCAS (output)
Page 146 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (3/6) (c) When written CLKOUT (output) Address Address A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output) LWR/LCAS (output) IORD (output) Note IOWR (output)
Page 147 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (4/6) (d) When written (address setup wait, idle state insertion) TASW CLKOUT (output) Address A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output) LWR/LCAS (output)
Page 148 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (5/6) (e) For read → → → → write operation CLKOUT (output) Address Address A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output) LWR/LCAS (output)
Page 149 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (6/6) (f) For write → → → → read operation CLKOUT (output) A0 to A25 (output) Address Address BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output) LWR/LCAS (output)
Page 150: Page Rom Controller (Romc)
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2 Page ROM Controller (ROMC) The page ROM controller (ROMC) is provided for accessing ROM (page ROM) with a page access function. Addresses are compared with the immediately preceding bus cycle and wait control for normal access (off-page) and page access (on-page) is executed.
Page 151: Page Rom Connection
(a) When data bus width is 16 bits A1 to A20 A0 to A19 D0 to D15 O1 to O16 V850E/MA1 16 Mb page ROM (1 Mword × 16 bits) (b) When data bus width is 8 bits A1 to A21...
Page 152: On-Page/Off
(a) In case of 16 Mb (1 M × × × × 16 bits) page ROM (4-word page access) Internal address latch (immediately preceding address) PRC register setting Comparison V850E/MA1 address output Page ROM address Off-page address On-page address Continuous reading possible: 16-bit data bus width × 4 words...
Page 153 (b) In case of 16 Mb (1 M × × × × 16 bits) page ROM (8-word page access) Internal address latch (immediately preceding address) PRC register setting Comparison V850E/MA1 address output Page ROM address Off-page address On-page address Continuous reading possible: 16-bit data bus width ×...
Page 154: Page Rom Configuration Register (Prc)
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2.4 Page ROM configuration register (PRC) This register specifies whether page ROM cycle on-page access is enabled or disabled. If on-page access is enabled, the masking address (no comparison is made) out of the addresses (A3 to A6) corresponding to the configuration of the connected page ROM and the number of bits that can be read continuously, as well as the number of waits corresponding to the internal system clock, are set.
Page 155: Page Rom Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2.5 Page ROM access Figure 5-5. Page ROM Access Timing (1/4) (a) When read (halfword/word access with 8-bit bus width or word access with 16-bit bus width) CLKOUT (output) Off-page address On-page address A0 to A25 (output) BCYST (output) CSn/RASm (output) Note...
Page 156 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-5. Page ROM Access Timing (2/4) (b) When read (byte access with 8-bit bus width or byte/half- word access with 16-bit bus width) CLKOUT (output) Off-page address On-page address A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output)
Page 157 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-5. Page ROM Access Timing (3/4) (c) When read (address setup wait, idle state insertion) (halfword/word access with 8-bit bus width or word access with 16-bit bus width) TASW TASW CLKOUT (output) Off-page address On-page address A0 to A25 (output) BCYST (output)
Page 158 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-5. Page ROM Access Timing (4/4) (d) When read (address setup wait, idle state insertion) (byte access with 8-bit bus width or byte/halfword access with 16-bit bus width) TASW TASW CLKOUT (output) Off-page address On-page address A0 to A25 (output) BCYST (output)
Page 159: Dram Controller (Edo Dram)
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3 DRAM Controller (EDO DRAM) 5.3.1 Features • Generates the RAS, LCAS, and UCAS signals • Can be connected directly to EDO DRAM. • Supports the RAS hold mode. • 4 types of DRAM can be assigned to 4 memory block spaces. •...
Page 160: Dram Connection
I/O1 to I/O16 RASn LCAS LCAS UCAS UCAS V850E/MA1 64 Mb DRAM (4 Mwords × 16 bits) (b) When DRAM is 16 Mb (2 M × × × × 8 bits) A1 to A12 A0 to A11 D0 to D7...
Page 161: Address Multiplex Function
DRAM cycle are multiplexed as shown in Figure 5-7 (n = 1, 3, 4, 6). In Figure 5-7, a0 to a25 show the addresses output from the CPU and A0 to A25 show the address pins of the V850E/MA1.
Page 162: Dram Configuration Registers 1, 3, 4, 6 (Scr1, Scr3, Scr4, Scr6)
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.4 DRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6) These registers are used to set the type of DRAM to be connected. SCRn corresponds to CSn (n = 1, 3, 4, 6). For example, to connect DRAM to CS1, set SCR1.
Page 163 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (2/3) Bit position Bit name Function 11, 10 RHC1n, Row Address Hold Wait Control RHC0n Specifies the number of wait states inserted as row address hold time. (n = 1, 3, 4, 6) RHC1n RHC0n Number of wait states inserted 9, 8...
Page 164 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (3/3) Bit position Bit name Function 3, 2 ASO1n, Address Shift Width On-page Control ASO0n This sets the address shift width during on-page judgment. (n = 1, 3, When the external data bus width is 8 bits: Set ASO1n, ASO0n = 00B 4, 6 When the external data bus width is 16 bits: Set ASO1n, ASO0n = 01B ASO1n...
Page 165: Dram Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.5 DRAM access Figure 5-8. EDO DRAM Access Timing (1/5) (a) Read timing (when no waits are inserted) Note 1 TRPW CLKOUT (output) Row address Column address Column address Column address A0 to A25 (output) BCYST (output) Note 2 CSn/RASm (output)
Page 166 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-8. EDO DRAM Access Timing (2/5) (b) Read timing (when TRHW and TW are inserted) Note 1 TRPW TRHW CLKOUT (output) Column address Column address A0 to A25 (output) Row address BCYST (output) Note 2 CSn/RASm (output) RD (output)
Page 167 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-8. EDO DRAM Access Timing (3/5) (c) Read timing (when two idle states are inserted) Note Note TRPW TRHW TCPW CLKOUT (output) Row address Column address Column address A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output)
Page 168 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-8. EDO DRAM Access Timing (4/5) (d) Write timing (when no waits are inserted) Note 1 Note 1 Note 1 TRPW TCPW TCPW CLKOUT (output) Row address Column address Column address Column address A0 to A25 (output) BCYST (output) Note 2...
Page 169 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-8. EDO DRAM Access Timing (5/5) (e) Write timing (when TRHW and TW are inserted) TRPW Note 1 TRHW TCPW Note 1 CLKOUT (output) A0 to A25 (output) Row address Column address Column address BCYST (output) Note 2 CSn/RASm (output)
Page 170: Refresh Control Function
5.3.6 Refresh control function The V850E/MA1 can generate the CBR (CAS-before-RAS) refresh cycle. The refresh cycle is set with refresh control registers 1, 3, 4, and 6 (RFS1, RFS3, RFS4, RFS6). RFSn corresponds to CSn (n = 1, 3, 4, 6). For example, to connect DRAM to CS1, set RFS1.
Page 171 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Address After reset RFS1 REN1 RCC11 RCC01 RIN51 RIN41 RIN31 RIN21 RIN11 RIN01 FFFFF4A6H 0000H RFS3 REN3 0 RCC13 RCC03 0 0 RIN53 RIN43 RIN33 RIN23 RIN13 RIN03 FFFFF4AEH 0000H RFS4 REN4 0 RCC14 RCC04 0 0 RIN54 RIN44 RIN34 RIN24 RIN14 RIN04 FFFFF4B2H 0000H...
Page 172 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Table 5-2. Interval Factor Setting Examples Notes 1, 2 Interval Factor Value Specified Refresh Interval Refresh Count Clock (T Value ( µ s) = 20 MHz = 33 MHz = 50 MHz 32/f 4 (6.4) 8 (7.8) 12 (7.7) 128/f...
Page 173 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Address After reset RRW1 RRW0 RCW2 RCW1 RCW0 SRW2 SRW1 SRW0 FFFFF49EH Bit position Bit name Function 7, 6 RRW1, Refresh RAS Wait Control RRW0 Specifies the number of wait states inserted as hold time for the RASm signal's high level width during CBR refresh (m = 1, 3, 4, 6).
Page 174 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (3) Refresh timing Figure 5-9. CBR Refresh Timing Note 1 Note 2 Note 2 TRRW TRCW TRCW CLKOUT (output) REFRQ (output) A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output) LWR/LCAS (output) IORD (output)
Page 175: Self-Refresh Control Function
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.7 Self-refresh control function When transferring to the IDLE or software STOP mode, or if the SELFREF signal becomes active, the DRAM controller generates the CBR self-refresh cycle. Note that the RASn pulse width of DRAM must meet the specifications for DRAM to enable the self-refresh operation (n = 1, 3, 4, 6).
Page 176 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-10. Self-Refresh Timing (DRAM) TRCW TRRW TSRW TSRW Note 2 Note 1 CLKOUT (output) REFRQ (output) A0 to A25 (output) BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output) UWR/UCAS (output) LWR/LCAS (output) IORD (output) IOWR (output) D0 to D15 (I/O)
Page 177: Dram Controller (Sdram)
SDCAS LDQM LDQM UDQM UDQM V850E/MA1 64 Mb SDRAM (1 Mword × 16 bits × 4 banks) Note The address signals to be used differ depending on the SDRAM product. Remark n = 1, 3, 4, 6 User’s Manual U14359EJ4V0UM...
Page 178: Address Multiplex Function
Figure 5-12 (b) (n = 1, 3, 4, 6). In Figures 5-12 (a) and (b), a0 to a25 indicate the addresses output from the CPU, and A0 to A25 indicate the address pins of the V850E/MA1. Figure 5-12. Row Address/Column Address Output (1/2)
Page 179 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-12. Row Address/Column Address Output (2/2) (d) Column address output (using read/write command) Address pin A25 to A18 Column address a25 to a18 (SSO1n, SSO0n = 00) Column address a25 to a18 a17 a16 a15 a14 a13 a10 a9 (SSO1n, SSO0n = 01)
Page 180: Sdram Configuration Registers 1, 3, 4, 6 (Scr1, Scr3, Scr4, Scr6)
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.4.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6) These registers specify the number of waits and the address multiplex width. SCRn corresponds to CSn (n = 1, 3, 4, 6). For example, to connect SDRAM to CS1, set SCR1. These registers can be read/written in 16-bit units.
Page 181 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (2/2) Bit position Bit name Function 5, 4 SSO1n, SDRAM Shift Width On-Page Control SSO0n Specifies the address shift width during on-page judgment. (n = 1 3, When the external data bus width is 8 bits: Set SSO1n, SSO0n = 00B 4, 6) When the external data bus width is 16 bits: Set SSO1n, SSO0n = 01B SSO1n SSO0n...
Page 182: Sdram Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.4.5 SDRAM access During power-on or a refresh operation, the all bank precharge command is always issued for SDRAM. When accessing SDRAM after that, therefore, the active command and read/write command are issued in that order (see <1>...
Page 183 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (1) SDRAM single read cycle The SDRAM single read cycle is a cycle for reading from SDRAM by executing a load instruction (LD) for the SDRAM area, by fetching an instruction, or by 2-cycle DMA transfer. In the SDRAM single read cycle, the active command (ACT) and read command (RD) are issued for SDRAM in that order.
Page 184 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-14. SDRAM Single Read Cycle (1/3) (a) During off-page access (when latency = 2) Off-page TACT TREAD TLATE TLATE SDCLK (output) Command BCYST (output) SDCKE (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) LDQM (output) UDQM (output) Note (output)
Page 185 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-14. SDRAM Single Read Cycle (2/3) (b) During off-page access (when latency = 2, page change) Off-page TPREC TACT TREAD TLATE TLATE SDCLK (output) Command BCYST (output) SDCKE (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) LDQM (output)
Page 186 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-14. SDRAM Single Read Cycle (3/3) (c) During on-page access (when latency = 2) On-page TREAD TLATE TLATE SDCLK (output) Command BCYST (output) SDCKE (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) LDQM (output) UDQM (output) Note (output)
Page 187 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (2) SDRAM single write cycle The SDRAM single write cycle is a cycle for writing to SDRAM by executing a write instruction (ST) for the SDRAM area or by 2-cycle DMA transfer. In the SDRAM single write cycle, the active command (ACT) and write command (WR) are issued for SDRAM in that order.
Page 188 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-15. SDRAM Single Write Cycle (1/3) (a) During off-page access Off-page TACT TWPRE SDCLK (output) Command BCYST (output) SDCKE (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) LDQM (output) UDQM (output) Note (output) Address Address Bank...
Page 189 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-15. SDRAM Single Write Cycle (2/3) (b) During off-page access (page change) Off-page TPREC TACT TWR1 TWR2 TWR3 SDCLK (output) Command BCYST (output) SDCKE (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) LDQM (output) UDQM (output) Address...
Page 190 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-15. SDRAM Single Write Cycle (3/3) (c) During on-page access On-page TWPRE SDCLK (output) Command BCYST (output) SDCKE (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) LDQM (output) UDQM (output) Address Address Note (output) Bank address (output) Address...
Page 191 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (3) SDRAM access timing control The SDRAM access timing can be controlled by SDRAM configuration register n (SCRn) (n = 1, 3, 4, 6). For details, see 5.4.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6). Caution Wait control by the WAIT pin is not available during SDRAM access.
Page 192 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-16. SDRAM Access Timing (1/4) (a) Read timing (16-bit bus width word access, page change, BCW = 2, latency = 2) TACT TBCW TREAD TREAD TLATE TLATE TW TPREC TBCW TACT TBCW TREAD TREAD TLATE TLATE SDCLK (output) Note (output) Add.
Page 193 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-16. SDRAM Access Timing (2/4) (b) Read timing (8-bit bus width word access, page change, BCW = 2, latency = 2) TACT TBCW TREAD TREAD TREAD TREAD TLATE TLATE TPREC TBCW TACT TBCW TREAD TREAD TREAD TREAD TLATE TLATE SDCLK (output) Note (output) Add.
Page 194 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-16. SDRAM Access Timing (3/4) (c) Write timing (16-bit bus width word access, bank change, BCW = 1, latency = 2) Bank A write Bank B write Bank B write TW TACT TWR TWR TWPRE TACT TWR TWR TWPRE TWE...
Page 195 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-16. SDRAM Access Timing (4/4) (d) Write timing (8-bit bus width word access, bank change, BCW = 1, latency = 2) Bank A write Bank B write Bank A read TW TACT TWR TWR TWR TWR TWPRE TWE TW TACT TWR TWR TWR TWR...
Page 196: Refresh Control Function
5.4.6 Refresh control function The V850E/MA1 can generate a refresh cycle. The refresh cycle is set with SDRAM refresh control registers 1, 3, 4, and 6 (RFS1, RFS3, RFS4, RFS6). RFSn corresponds to CSn (n = 1, 3, 4, 6). For example, to connect SDRAM to CS1, set RFS1.
Page 197 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Address After reset RFS1 REN1 RCC11 RCC01 RIN51 RIN41 RIN31 RIN21 RIN11 RIN01 FFFFF4A6H 0000H RFS3 REN3 RCC13 RCC03 0 RIN53 RIN43 RIN33 RIN23 RIN13 RIN03 FFFFF4AEH 0000H RFS4 REN4 RCC14 RCC04 0 RIN54 RIN44 RIN34 RIN24 RIN14 RIN04 FFFFF4B2H 0000H RFS6...
Page 198 2. The values in parentheses are the calculated values for the refresh interval ( µ s). Refresh interval ( µ s) = Refresh count clock (T ) × Interval factor Remark : Internal system clock The V850E/MA1 can automatically generate an auto-refresh cycle and a self-refresh cycle. User’s Manual U14359EJ4V0UM...
Page 199 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (2) Auto-refresh cycle In the auto-refresh cycle, the auto-refresh command (REF) is issued four clocks after the precharge command for all banks (PALL) is issued. Figure 5-17. Auto-Refresh Cycle Auto-refresh cycle TABPW TREFW TREFW TREFW TREF SDCLK (output) PALL...
Page 200 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (3) Refresh timing Figure 5-18. CBR Refresh Timing (SDRAM) × 4clk ALLPRE TW TREF TBCW TBCW TBCW TBCW TBCW TBCW TBCW TBCW SDCLK (output) A10 (output) A0 to A9, A11 to A23 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output)
Page 201: Self-Refresh Control Function
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.4.7 Self-refresh control function In the case of transition to the IDLE or software STOP mode, or if the SELFREF signal becomes active, the DRAM controller generates the CBR self-refresh cycle (the system enters a state in which not only SDRAM, but also all DRAM is self-refreshed).
Page 202 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-19. Self-Refresh Timing (SDRAM) BCW × 4clk TW NOP TREF TDCW TDCW TDCW TDCW SDCLK (output) Note A10 (output) A0 to A9, A11 to A23 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) RD (output) OE (output) WE (output)
Page 203: Sdram Initialization Sequence
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.4.8 SDRAM initialization sequence Be sure to initialize SDRAM when applying power. (1) Set the registers of SDRAM (other than SDRAM configuration register n (SCRn)) • Bus cycle type configuration registers 0 and 1 (BCT0 and BCT1) •...
Page 204 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-20. SDRAM Mode Register Setting Cycle Mode register setting cycle TABPW TREFW TREFW TREFW TREF SDCLK (output) Command PALL BCYST (output) SDCKE (output) CSn (output) SDRAS (output) SDCAS (output) WE (output) LDQM (output) UDQM (output) Address (output) A10 (output)
Page 205 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-21. SDRAM Register Write Operation Timing ALPRE TW TW TREF TW TW TREF TW TW REGW TW SDCLK (output) Note (output) Bank address (output) A10 (output) A0 to A9 (output) BCYST (output) CSn (output) SDRAS (output) SDCAS (output) RD (output)
Page 206: Chapter 6 Dma Functions (Dma Controller)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The V850E/MA1 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, or among memories, based on DMA requests issued by the on-chip peripheral I/O (serial interface, real-time pulse unit, and A/D converter), DMARQ0 to DMARQ3 pins, or software triggers (memory refers to internal RAM or external memory).
Page 207: Configuration
DMA addressing control DMAAKn Channel register (DADCn) control DMA disable status register (DDIS) DMA restart register (DRST) DMA trigger factor register (DTFRn) DMAC Bus interface External bus V850E/MA1 External External External I/O Remark n = 0 to 3 User’s Manual U14359EJ4V0UM...
Page 208: Control Registers
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3 Control Registers 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA source address (28 bits) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAnH and DSAnL.
Page 209 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA source address registers 0L to 3L (DSA0L to DSA3L) These registers can be read/written in 16-bit units. Address After reset DSA0L SA15 SA14 SA13 SA12 SA11 SA10 FFFFF080H Undefined DSA1L SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF088H Undefined DSA2L...
Page 210: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA destination address (28 bits) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL.
Page 211 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA destination address registers 0L to 3L (DDA0L to DDA3L) These registers can be read/written in 16-bit units. Address After reset DDA0L DA15 DA14 DA13 DA12 DA11 DA10 FFFFF084H Undefined DDA1L DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF08CH Undefined DDA2L...
Page 212: Dma Byte Count Registers 0 To 3 (Dbc0 To Dbc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the byte transfer count for DMA channel n (n = 0 to 3). They store the remaining transfer count during DMA transfer.
Page 213: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers cannot be accessed during DMA operation. They can be read/written in 16-bit units.
Page 214 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit position Bit name Function 3, 2 TM1, TM0 Transfer Mode Sets the transfer mode during DMA transfer. Transfer mode Single transfer mode Single-step transfer mode Setting prohibited Block transfer mode TTYP Transfer Type Sets the DMA transfer type.
Page 215: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only.
Page 216: Dma Disable Status Register (Ddis)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.6 DMA disable status register (DDIS) This register holds the contents of the Enn bit of the DCHCn register during NMI input (n = 0 to 3). This register is read-only in 8-bit units. Address After reset DDIS...
Page 217: Dma Terminal Count Output Control Register (Dtoc)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.8 DMA terminal count output control register (DTOC) The DMA terminal count output control register (DTOC) is an 8-bit register that controls the terminal count output from each DMA channel. Terminal count signals from each DMA channel can be brought together and output from the TC0 pin.
Page 218: Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.9 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from on-chip peripheral I/O. The interrupt requests set by these registers serve as DMA transfer startup factors. These registers can be read/written in 8-bit units.
Page 219 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit position Bit name Function 5 to 0 IFCn5 to IFCn0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt source INTP030/INTM030 INTP031/INTM031 INTP100 INTP101 INTP102 INTP103 INTP110 INTP111 INTP112 INTP113 INTP120 INTP121 INTP122 INTP123 INTP130 INTP131 INTP132...
Page 220 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The relationship between the DMARQn signal and the interrupt source that serves as a DMA transfer trigger is as follows (n = 0 to 3). DMARQn Internal DMA request signal Interrupt source IFCn0 to IFCn5 Remark If an interrupt request is specified as the DMA transfer start factor, an interrupt request will be generated if DMA transfer starts.
Page 221: Dma Bus States
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4 DMA Bus States 6.4.1 Types of bus states The DMAC bus states consist of the following 13 states. (1) TI state The TI state is an idle state, during which no access request is issued. The DMARQ0 to DMARQ3 signals are sampled at the rising edge of the CLKOUT signal.
Page 222 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (10) T1FH state The basic flyby transfer state, this state corresponds to the transfer execution cycle. After entering the T1FH state, the bus enters the T2FH state. (11) T1FHI state The T1FHI state corresponds to the last state of a flyby transfer, during which the end of transfer is waited for.
Page 223: Dmac Bus Cycle State Transition
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.2 DMAC bus cycle state transition Except for the block transfer mode, each time the processing for a DMA transfer is completed, the bus mastership is released. Figure 6-1. DMAC Bus Cycle State Transition (a) 2-cycle transfer (b) Flyby transfer T1RI...
Page 224: Transfer Modes
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.5 Transfer Modes 6.5.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request takes precedence.
Page 225 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-4 is an example of single transfer where a DMA transfer request with the lower priority is issued one clock after single transfer has been completed. DMA channels 0 and 3 are used for single transfer. If two DMA transfer request signals are asserted active at the same time, two DMA transfer operations are alternately executed.
Page 226: Single-Step Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.5.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request signal (DMARQ0 to DMARQ3), transfer is performed again. This operation continues until a terminal count occurs.
Page 227: Block Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.5.3 Block transfer mode In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer. After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowledged.
Page 228: Transfer Types
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6 Transfer Types 6.6.1 2-cycle transfer In 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle (DMAC to destination). In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the second cycle, the destination address is output and writing is performed from the DMAC to the destination.
Page 229 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-9. Timing of Access to SRAM, External ROM, and External I/O During 2-Cycle DMA Transfer (1/2) (a) SRAM → → → → External I/O (BCC register setting for SRAM: BCn1, BCn0 = 00B) (BCC register setting for external I/O: BCn1, BCn0 = 00B) Note CLKOUT (output)
Page 230 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-9. Timing of Access to SRAM, External ROM, and External I/O During 2-Cycle DMA Transfer (2/2) (b) SRAM → → → → External I/O (BCC register setting for SRAM: BCn1, BCn0 = 11B) (BCC register setting for external I/O: BCn1, BCn0 = 00B) Note 1 Note 1...
Page 231 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-10. Timing of 2-Cycle DMA Transfer (External I/O → → → → SRAM) (a) Single-step transfer mode Note 1 Note 1 CLKOUT (output) DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) Address Address Address...
Page 232 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-11. Timing of 2-Cycle DMA Transfer (SRAM → → → → EDO DRAM) (1/3) (a) Single transfer mode Note 2 Note 2 TRPW TCPW Note 1 Note 1 T1W T2W T2W CLKOUT (output) DMARQx (input) Internal DMA request signal...
Page 233 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-11. Timing of 2-Cycle DMA Transfer (SRAM → → → → EDO DRAM) (2/3) (b) Single-step transfer mode Note 2 Note 2 TRPW TCPW Note 1 Note 1 T1W T2W T2W CLKOUT (output) DMARQx (input) Internal DMA request singal...
Page 234 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-11. Timing of 2-Cycle DMA Transfer (SRAM → → → → EDO DRAM) (3/3) (c) Block transfer mode Note 2 Note 2 TRPW TCPW Note 1 Note 1 T1W T2W T2W CLKOUT (output) DMARQx (input) Internal DMA request signal...
Page 235 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-12. Timing of 2-Cycle DMA Transfer (EDO DRAM → → → → SRAM) (1/3) (a) Single transfer mode Note 1 TRPW T2R T2R CLKOUT (output) DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) Col.
Page 236 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-12. Timing of 2-Cycle DMA Transfer (EDO DRAM → → → → SRAM) (2/3) (b) Single-step transfer mode Note 1 TRPW T2R T2R CLKOUT (output) DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) Col.
Page 237 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-12. Timing of 2-Cycle DMA Transfer (EDO DRAM → → → → SRAM) (3/3) (c) Block transfer mode Note 1 TRPW Note 2 T2R T2R CLKOUT (output) DMARQx (input) Input DMA request signal DMAAKx (output) TCx (output) Col.
Page 238 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-13. Timing of 2-Cycle DMA Transfer (SRAM → → → → SDRAM) (1/3) (a) Single transfer mode TACT TWR TWPRE TWPRE Note Note T1W T2W T2W T2W T2W T2W T2W SDCLK (output) DMARQx (input) Internal DMA output signal DMAAKx (output)
Page 239 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-13. Timing of 2-Cycle DMA Transfer (SRAM → → → → SDRAM) (2/3) (b) Single-step transfer mode TACT TWR TWPRE TWPRE Note Note T1W T2W T2W T2W T2W T2W T2W SDCLK (output) DMARQx (input) Internal DMA request signal DMAAKx (output)
Page 240 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-13. Timing of 2-Cycle DMA Transfer (SRAM → → → → SDRAM) (3/3) (c) Block transfer mode TACT TWR TWPRE TWPRE Note Note Note T1W T2W T2W T2W T2W T2W T2W SDCLK (output) DMARQx (input) Internal DMA request signal...
Page 241 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-14. Timing of 2-Cycle DMA Transfer (SDRAM → → → → SRAM) (1/3) (a) Single transfer mode TACT TREAD TLATE TLATE TREAD TLATE TLATE Note Note SDCLK (output) DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) Address (output)
Page 242 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-14. Timing of 2-Cycle DMA Transfer (SDRAM → → → → SRAM) (2/3) (b) Single-step transfer mode TACT TREAD TLATE TLATE TREAD TLATE TLATE Note Note SDCLK (output) DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) Col.
Page 243 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-14. Timing of 2-Cycle DMA Transfer (SDRAM → → → → SRAM) (3/3) (c) Block transfer mode TACT TREAD TLATE TLATE TREAD TLATE TLATE Note Note Note SDCLK (output) DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output)
Page 244: Flyby Transfer
D0 to D7 SRAM Ax to Axx D8 to D15 SRAM D0 to D15 IORD IOWR DMAAKx V850E/MA1 External I/O Remark n = 0 to 7, m = 0 to 7 (n ≠ m) x = 0 to 3 User’s Manual U14359EJ4V0UM...
Page 245 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-16. Timing of Flyby Transfer (DRAM → → → → External I/O) (1/3) (a) Block transfer mode Note TRPW T1FH T2FH T1FH T1FH T1FH CLKOUT (output) DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) A0 to A25 (output) Col.
Page 246 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-16. Timing of Flyby Transfer (DRAM → → → → External I/O) (2/3) (b) Single transfer mode Note Note TRPW TRPW T1FH T2FH T1FH T1FH T2FH T2FH CLKOUT (output) DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output)
Page 247 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-16. Timing of Flyby Transfer (DRAM → → → → External I/O) (3/3) (c) Single-step transfer mode Note TRPW T1FH T2FH T1FH T1FH CLKOUT (output) DMARQx (input) Internal DMA request signal DMAAKx (output) TCx (output) Col.
Page 248 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-17. Timing of Access to SRAM, External ROM, and External I/O During DMA Flyby Transfer (1/2) (a) SRAM → → → → external I/O When TASW and TI are inserted TASW CLKOUT (output) Address Address A0 to A25 (output)
Page 249 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-17. Timing of Access to SRAM, External ROM, and External I/O During DMA Flyby Transfer (2/2) (b) External I/O → → → → SRAM When TASW is inserted TASW CLKOUT (output) Address Address A0 to A25 (output) BCYST (output) CSn/RASm (output)
Page 250 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-18. Page ROM Access Timing During DMA Flyby Transfer (a) Page ROM → → → → external I/O When TI is inserted CLKOUT (output) A0 to A25 (output) Address Address BCYST (output) CSn/RASm (output) RD (output) OE (output) WE (output)
Page 251 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-19. DRAM Access Timing During DMA Flyby Transfer (1/4) (a) DRAM → → → → external I/O (when no wait is inserted) Note 1 TRPW CLKOUT (output) Row address Column address Column address A0 to A25 (output) BCYST (output) Note 3...
Page 252 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-19. DRAM Access Timing During DMA Flyby Transfer (2/4) (b) DRAM → → → → External I/O (when TRHW and TW are inserted) Note 1 Note 1 TRPW TRHW TCPW CLKOUT (output) A0 to A25 (output) Row address Column address Column address...
Page 253 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-19. DRAM Access Timing During DMA Flyby Transfer (3/4) (c) External I/O → → → → DRAM (when no waits are inserted) Note 1 Note 1 TRPW TCPW CLKOUT (output) Row address Column address Column address A0 to A25 (output) BCYST (output)
Page 254 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-19. DRAM Access Timing During DMA Flyby Transfer (4/4) (d) External I/O → → → → DRAM (when TRHW and TW are inserted) Note 1 Note 1 TRPW TRHW TCPW CLKOUT (output) Row address Column address Column address A0 to A25 (output)
Page 255: Transfer Object
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.7 Transfer Object 6.7.1 Transfer type and transfer object Table 6-1 lists the relationships between transfer type and transfer object. The mark “√” means “transfer possible”, and the mark “−” means “transfer impossible”. Table 6-1. Relationship Between Transfer Type and Transfer Object Destination 2-Cycle Transfer Flyby Transfer...
Page 256: External Bus Cycles During Dma Transfer
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.7.2 External bus cycles during DMA transfer The external bus cycles during DMA transfer are shown below. Table 6-2. External Bus Cycles During DMA Transfer Transfer Type Transfer Object External Bus Cycle Note 2-cycle transfer On-chip peripheral I/O, internal RAM None –...
Page 257: Next Address Setting Function
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.9 Next Address Setting Function The DMA source address registers (DSAnH, DSAnL), DMA destination address registers (DDAnH, DDAnL), and DMA transfer count register (DBCn) are buffer registers with a 2-stage FIFO configuration (n = 0 to 3). When the terminal count is issued, these registers are automatically rewritten with the value that was set immediately before.
Page 258: Dma Transfer Start Factors
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.10 DMA Transfer Start Factors There are 3 types of DMA transfer start factors, as shown below. (1) Request from an external pin (DMARQn) Requests from the DMARQn pin are sampled each time the CLKOUT signal rises (n = 0 to 3). Hold the request from DMARQn pin until the corresponding DMAAKn signal becomes active.
Page 259: Terminal Count Output Upon Dma Transfer End
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.11 Terminal Count Output upon DMA Transfer End The terminal count signal (TCn) becomes active for one clock during the last DMA transfer cycle (n = 3 to 0). The TCn signal becomes active in the clock following the clock in which the BCYST signal becomes active during the last DMA transfer cycle.
Page 260: Forcible Termination
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.13 Forcible Termination DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register, in addition to the forcible interruption operation by means of NMI input (n = 0 to 3). An example of forcible termination by the INITn bit of the DCHCn register is illustrated below (n = 0 to 3).
Page 261: Times Related To Dma Transfer
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.14 Times Related to DMA Transfer The overhead before and after DMA transfer and minimum execution clock for DMA transfer are shown below. In the case of external memory access, the time depends on the type of external memory connected. Table 6-3.
Page 262: One-Time Transfer During Single Transfer Via Dmarq0 To Dmarq3 Signals
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (3) Condition 3 Condition Instruction fetch from an external memory in 8-bit data bus width Execution of a bit manipulation instruction (SET1, CLR1, or NOT1) Tinst × 4 + Tdata × 2 + Tref Response time DMARQn (input) DMAAKn (output)
Page 263: Cautions
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.17 Cautions (1) Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA objects (external memory, internal RAM, or peripheral I/O) during DMA transfer. (2) Transfer of misaligned data DMA transfer of 16-bit bus width misaligned data is not supported.
Page 264: Chapter 7 Interrupt/Exception Processing Function
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850E/MA1 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 50 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 265 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (1/2) Type Classification Interrupt/Exception Source Default Exception Handler Restored PC Priority Code Address Name Controlling Generating Source Generating Register Unit − − − Reset Interrupt RESET Reset input 0000H 00000000H Undefined −...
Page 266 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (2/2) Type Classification Interrupt/Exception Source Default Exception Handler Restored PC Priority Code Address Name Controlling Generating Source Generating Register Unit Maskable Interrupt INTCMD2 CMICD2 CMD2 match signal 0260H 00000260H nextPC Interrupt INTCMD3 CMICD3...
Page 267: Non-Maskable Interrupts
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts. A non-maskable interrupt request is input from the NMI pin.
Page 268: Operation
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 269 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Figure 7-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service program is being executed Main routine (PSW.NP = 1) NMI request is held pending regardless NMI request NMI request of the value of the NP bit of PSW.
Page 270: Restore
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.2.2 Restore Execution is restored from the non-maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 271: Non-Maskable Interrupt Status Flag (Np)
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 272: Maskable Interrupts
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850E/MA1 has 49 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 273 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Figure 7-4. Maskable Interrupt Servicing INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 274: Restore
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. <1>...
Page 275: Priorities Of Maskable Interrupts
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850E/MA1 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 276 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 277 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 278 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Servicing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are NMI request Interrupt request c (level 1) acknowledged first according to their priorities.
Page 279: Interrupt Control Register (Xxicn)
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. <7>...
Page 280 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION (1/2) Address Register <7> <6> FFFFF110H OVIC00 OVIF0 OVMK0 OVPR02 OVPR01 OVPR00 FFFFF112H OVIC01 OVIF1 OVMK1 OVPR12 OVPR11 OVPR10 FFFFF114H OVIC02 OVIF2 OVMK2 OVPR22 OVPR21 OVPR20 FFFFF116H OVIC03 OVIF3 OVMK3 OVPR32 OVPR31 OVPR30 FFFFF118H P00IC0 P00IF0 P00MK0 P00PR02...
Page 281 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION (2/2) Address Register <7> <6> FFFFF15AH SEIC0 SEIF0 SEMK0 SEPR02 SEPR01 SEPR00 FFFFF15CH SRIC0 SRIF0 SRMK0 SRPR02 SRPR01 SRPR00 FFFFF15EH STIC0 STIF0 STMK0 STPR02 STPR01 STPR00 FFFFF160H CSIIC1 CSIIF1 CSIMK1 CSIPR12 CSIPR11 CSIPR10 FFFFF162H SEIC1 SEIF1 SEMK1 SEPR12...
Page 282: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn bit of the xxICn register. The IMRm register (m = 0 to 3) can be read/written in 16-bit units.
Page 283: In-Service Priority Register (Ispr)
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 284: Noise Elimination
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.3.8 Noise elimination The noise of the INTPn, INTPm, and TI000 to TI030 pins is eliminated with analog delay (n = 000, 001, 010, 011, 020, 021, 030, 031, m = 103 to 100, 113 to 110, 123 to 120, and 133 to 130). The delay time is about 60 to 220 ns. A signal input that changes within the delay time is not internally acknowledged.
Page 285 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Address After reset INTM1 ES1031 ES1030 ES1021 ES1020 ES1011 ES1010 ES1001 ES1000 FFFFF882H INTP103 INTP102 INTP101 INTP100 Address After reset INTM2 ES1131 ES1130 ES1121 ES1120 ES1111 ES1110 ES1101 ES1100 FFFFF884H INTP113 INTP112 INTP111 INTP110 Address After reset INTM3 ES1231 ES1230...
Page 286 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION (2) Valid edge select registers C0 to C3 (SESC0 to SESC3) These registers specify the valid edge for external interrupt requests (INTP000, INTP001, INTP010, INTP011, INTP020, INTP021, INTP030, INTP031, TI000 to TI030), input via external pins. correspondence between each register and the external interrupt requests that register controls is shown below.
Page 287 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Address After reset SESC0 TES01 TES00 IES0011 IES0010 ES0001 IES0000 FFFFF609H TI000 INTP001 INTP000 Address After reset SESC1 TES11 TES10 IES0111 IES0110 IES0101 IES0100 FFFFF619H TI010 INTP011 INTP010 Address After reset SESC2 TES21 TES20 IES0211 IES0210 IES0201 IES0200 FFFFF629H TI020 INTP021...
Page 288: Software Exception
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: <1>...
Page 289: Restore
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. <2>...
Page 290: Exception Status Flag (Ep)
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.4.3 Exception status flag (EP) The EP flag is bit 6 of the PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset 00000020H Bit Position...
Page 291: Exception Trap
7.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850E/MA1, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 7.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B.
Page 292 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION Figure 7-10. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC Restored PC DBPSW PSW.NP PSW.EP PSW.ID 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 293: Debug Trap
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.5.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. (1) Operation <1>...
Page 294 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION (2) Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2>...
Page 295: Multiple Interrupt Servicing Control
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.6 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is acknowledged and serviced first.
Page 296 CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION (2) Generation of exception in service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • TRAP instruction ← Exception such as TRAP instruction acknowledged. •...
Page 297: Interrupt Latency Time
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.7 Interrupt Latency Time V850E/MA1 interrupt latency time (from interrupt request generation to start of interrupt servicing) is described below. Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgement (Outline) 4 system clocks Internal clock Interrupt request...
Page 298: Periods In Which Interrupts Are Not Acknowledged
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION 7.8 Periods in Which Interrupts Are Not Acknowledged An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows.
Page 299: Chapter 8 Prescaler Unit (Prs)
CHAPTER 8 PRESCALER UNIT (PRS) The prescaler divides the internal system clock and supplies the divided clock to internal peripheral units. The divided clock differs depending on the unit. For the timer units and A/D converter, a 2-division clock is input. For other units, the input clock is selected using that unit’s control register.
Page 300: Chapter 9 Clock Generation Function
CHAPTER 9 CLOCK GENERATION FUNCTION The clock generator (CG) generates and controls the internal system clock (f ) that is supplied to each internal unit, such as the CPU. 9.1 Features • Multiplication function using phase locked loop (PLL) synthesizer •...
Page 301: Input Clock Selection
In direct mode, an external clock with twice the frequency of the internal system clock is input. The maximum frequency that can be input in direct mode is 50 MHz. The V850E/MA1 is mainly used in application systems in which it is operated at relatively low frequencies.
Page 302 , or 1 × × × × f is used, a frequency of 4 to 6.6 MHz can be used. Remark If the V850E/MA1 does not need to be operated at high frequency, when PLL mode is selected a = 5 ×...
Page 303 CHAPTER 9 CLOCK GENERATION FUNCTION 9.3.4 Clock control register (CKC) The clock control register is an 8-bit register that controls the internal system clock (f ) in PLL mode. It can be written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to an inadvertent program loop.
Page 304 CHAPTER 9 CLOCK GENERATION FUNCTION Set data in the clock control register (CKC) in the following sequence. <1> Disable interrupts (set the NP bit of PSW to 1) <2> Prepare data in any one of the general-purpose registers to set in the specific register. <3>...
Page 305 CHAPTER 9 CLOCK GENERATION FUNCTION 9.3.5 Peripheral status register (PHS) If a write operation to the protection-targeted internal registers is not performed in the correct sequence, including access to the command register, writing is not performed and a protection error is generated, setting the status flag (PRERR) to 1.
Page 306 CHAPTER 9 CLOCK GENERATION FUNCTION 9.4 PLL Lockup The lockup time (frequency stabilization time) is the time from when the power is turned on or software STOP mode is released until the phase locks at the prescribed frequency. The state until this stabilization occurs is called the unlocked state, and the stabilized state is called the locked state.
Page 307 CHAPTER 9 CLOCK GENERATION FUNCTION 9.5 Power-Save Control 9.5.1 Overview The power-save function has the following three modes. (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU’s operation clock stops. Since the supply of clocks to on-chip peripheral functions other than the CPU continues, operation continues.
Page 308 CHAPTER 9 CLOCK GENERATION FUNCTION Figure 9-1 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, and software STOP mode. An effective low power consumption system can be realized by combining these modes and switching modes according to the required use.
Page 309 CHAPTER 9 CLOCK GENERATION FUNCTION 9.5.2 Control registers (1) Power-save mode register (PSMR) This is an 8-bit register that controls power-save mode. It is effective only when the STB bit of the PSC register is set to 1. Writing to the PSMR register is executed by the store instruction (ST/SST instruction) and a bit manipulation instruction (SET1/CLR1/NOT1 instruction).
Page 310 CHAPTER 9 CLOCK GENERATION FUNCTION (3) Power-save control register (PSC) This is an 8-bit register that controls the power-save function. This register, which is one of the specific registers, is valid only when accessed in a specific sequence during a write operation. This register can be read or written in 8-bit or 1-bit units.
Page 311 CHAPTER 9 CLOCK GENERATION FUNCTION Sample coding <1> ST.B ; Set PSMR register r11, PSMR [r0] <2> MOV 0x02, r10 <3> ST.B ; Write PRCMD register r10, PRCMD [r0] <4> ST.B ; Set PSC register r10, PSC [r0] <5> NOP ;...
Page 312 CHAPTER 9 CLOCK GENERATION FUNCTION 9.5.3 HALT mode (1) Setting and operation status In HALT mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the operation clock of the CPU is stopped. Since the supply of clocks to on-chip peripheral I/O units other than the CPU continues, operation continues.
Page 313 CHAPTER 9 CLOCK GENERATION FUNCTION (2) Release of HALT mode HALT mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, or RESET pin input. (a) Release according to a non-maskable interrupt request or an unmasked maskable interrupt request HALT mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority.
Page 314 CHAPTER 9 CLOCK GENERATION FUNCTION 9.5.4 IDLE mode (1) Setting and operation status In IDLE mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of internal system clocks is stopped which causes the overall system to stop. When IDLE mode is released, the system can be switched to normal operation mode quickly because the oscillator's oscillation stabilization time or the PLL lockup time does not need to be secured.
Page 315 CHAPTER 9 CLOCK GENERATION FUNCTION Table 9-4. Operation Status in IDLE Mode Function Operation Status Clock generator Operating Internal system clock Stopped Stopped Ports Maintained On-chip peripheral I/O (excluding ports) Stopped Internal data All internal data such as CPU registers, statuses, data, and the contents of internal RAM are maintained in the state they were in immediately before IDLE mode began.
Page 316 CHAPTER 9 CLOCK GENERATION FUNCTION (2) Release of IDLE mode IDLE mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (INTP1nn), or RESET pin input. (a) Release according to a non-maskable interrupt request or an unmasked maskable interrupt request IDLE mode can be released by an interrupt request only when it has been set with the INTM and NMIM bits of the PSC register cleared to 0.
Page 317 CHAPTER 9 CLOCK GENERATION FUNCTION 9.5.5 Software STOP mode (1) Setting and operation status In software STOP mode, the clock generator (oscillator and PLL synthesizer) is stopped. The overall system is stopped, and ultra-low power consumption is achieved in which only leakage current is lost. The system is switched to software STOP mode by using a store instruction (ST or SST instruction) or bit manipulation instruction (SET1, CLR1, or NOT1 instruction) to set the PSC and PSMR registers (see 9.5.2 Control registers).
Page 318 CHAPTER 9 CLOCK GENERATION FUNCTION Table 9-6. Operation Status in Software STOP Mode Function Operation Status Clock generator Stopped Internal system clock Stopped Stopped Note Ports Maintained On-chip peripheral I/O (excluding ports) Stopped Internal data All internal data such as CPU registers, statuses, data, and the contents of internal RAM are maintained in the state they were in immediately before software STOP mode began.
Page 319 CHAPTER 9 CLOCK GENERATION FUNCTION (2) Release of software STOP mode Software STOP mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (INTP1nn), or RESET pin input. Also, to release software STOP mode when PLL mode (CKSEL pin = low level) and resonator connection mode (CESEL bit of CKC register = 0) are used, the oscillator’s oscillation stabilization time must be secured (n = 0 to 3).
Page 320 CHAPTER 9 CLOCK GENERATION FUNCTION 9.6 Securing Oscillation Stabilization Time 9.6.1 Oscillation stabilization time security specification Two specification methods can be used to secure the time from when software STOP mode is released until the stopped oscillator stabilizes. (1) Securing the time using an on-chip time base counter Software STOP mode is released when a valid edge is input to the NMI pin or a maskable interrupt request is input (INTP1nn).
Page 321 CHAPTER 9 CLOCK GENERATION FUNCTION (2) Securing the time according to the signal level width (RESET pin input) Software STOP mode is released due to falling edge input to the RESET pin. The time until the clock output from the oscillator stabilizes is secured according to the low-level width of the signal that is input to the pin.
Page 322 CHAPTER 9 CLOCK GENERATION FUNCTION 9.6.2 Time base counter (TBC) The time base counter (TBC) is used to secure the oscillator's oscillation stabilization time when software STOP mode is released. When an external clock is connected (CESEL bit of CKC register = 1) or a resonator is connected (PLL mode and CESEL bit of CKC register = 0), the TBC counts the oscillation stabilization time after software STOP mode is released, and program execution begins after the count is completed.
Page 323 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.1 Timer C 10.1.1 Features (timer C) Timer C is a 16-bit timer/counter that can perform the following operations. • Interval timer function • PWM output • External signal cycle measurement 10.1.2 Function overview (timer C) •...
Page 324 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.1.3 Basic configuration of timer C Table 10-1. Timer C Configuration Generated Capture Timer Output Timer Count Clock Register Read/Write Other Functions Interrupt Signal Trigger Timer C /4, f TMC0 Read INTOV00 – –...
Page 325 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.1.4 Timer C (1) Timers C0 to C3 (TMC0 to TMC3) TMCn functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being mainly used for cycle measurement, TMCn can be used as pulse output (n = 0 to 3). TMCn is read-only in 16-bit units.
Page 326 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (b) Selection of the internal count clock TMCn operates as a free-running timer. When an internal clock is specified as the count clock by timer mode control register Cn1 (TMCCn1), TMCn is counted up for each input clock cycle specified by the CSn0 to CSn2 bits of the TMCCn0 register (n = 0 to 3).
Page 327 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Capture/compare registers Cn0 and Cn1 (CCCn0 and CCCn1) (n = 0 to 3) These capture/compare registers (Cn0 and Cn1) are 16-bit registers. They can be used as capture registers or compare registers according to the CMSn0 and CMSn1 bit specifications of timer mode control register Cn1 (TMCCn1) (n = 0 to 3).
Page 328 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (b) Setting these registers as compare registers (CMSn0 and CMSn1 of TMCCn1 = 1) When these registers are set as compare registers, the TMCn and register values are compared for each count clock, and an interrupt is generated by a match. If the CCLRn bit of timer mode control register Cn1 (TMCCn1) is set (1), the TMCn value is cleared (0) at the same time as a match with the CCCn0 register (it is not cleared (0) by a match with the CCCn1 register) (n = 0 to 3).
Page 329 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.1.5 Timer C control registers (1) Timer mode control registers C00 to C30 (TMCC00 to TMCC30) The TMCCn0 registers control the operation of TMCn (n = 0 to 3). These registers can be read or written in 8-bit or 1-bit units.
Page 330 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit position Bit name Function 6 to 4 CSn2 to CSn0 Count Enable Select (n = 0 to 3) Selects the TMCn internal count clock (n = 0 to 3). CSn2 CSn1 CSn0 Count cycle /128...
Page 331 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Timer mode control registers C01 to C31 (TMCC01 to TMCC31) The TMCCn1 registers control the operation of TMCn (n = 0 to 3). These registers can be read or written in 8-bit units. Be sure to set bit 2 to 0.
Page 332 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit position Bit name Function Active Level ACTLVn Specifies the active level for external pulse output (TO0n) (n = 0 to 3). (n = 0 to 3) 0: Active level is low level 1: Active level is high level Caution The initial value of the ACTLVn bit is 1.
Page 333 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Valid edge select registers C0 to C3 (SESC0 to SESC3) These registers specify the valid edge of an external interrupt request (INTP000, INTP001, INTP010, INTP011, INTP020, INTP021, INTP030, INTP031, and TI000 to TI030) from an external pin. The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin.
Page 334 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.1.6 Timer C operation (1) Count operation Timer C can function as a 16-bit free-running timer or as an external signal event counter. The setting for the type of operation is specified by timer mode control registers Cn0 and Cn1 (TMCCn0 and TMCCn1) (n = 0 to When it operates as a free-running timer, if the CCCn0 or CCCn1 register and the TMCn count value match, an interrupt signal is generated and the timer output signal (TO0n) can be set or reset.
Page 335 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Overflow When the TMCn register has counted the count clock from FFFFH to 0000H, the OVFn bit of the TMCCn0 register is set (1), and an overflow interrupt (INTOV0n) is generated at the same time (n = 0 to 3). However, if the CCCn0 register is set to compare mode (CMSn0 bit = 1) and to the value FFFFH when match clearing is enabled (CCLRn bit = 1), then the TMCn register is considered to be cleared and the OVFn bit is not set (1) when the TMCn register changes from FFFFH to 0000H.
Page 336 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Capture operation The TMCn register has two capture/compare registers. These are the CCCn0 register and the CCCn1 register. A capture operation or a compare operation is performed according to the settings of both the CMSn1 and CMSn0 bits of the TMCCn1 register.
Page 337 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 10-4. TMC1 Capture Operation Example (When Both Edges Are Specified) (TMC1 count values) TMC1 ∆ ∆ Count start Overflow TMCCE1←1 OVF1←1 Interrupt request (INTP011) Capture register (CCC11) Remark D0 to D2: TMC1 count values User’s Manual U14359EJ4V0UM...
Page 338 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Compare operation The TMCn register has two capture/compare registers. These are the CCCn0 register and the CCCn1 register. A capture operation or a compare operation is performed according to the settings of both the CMSn1 and CMSn0 bits of the TMCCn1 register.
Page 339 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 10-5. Compare Operation Example (2/2) (b) When CCLR0 = 1 and CCC00 is 0000H Count-up TMC0 FFFFH 0000H 0000H 0001H Compare register 0000H (CCC00) INTOV00 Match detection (INTM000) Remark The match is detected immediately after the count-up, and the match detection signal is generated.
Page 340 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) External pulse output Timer C has four timer output pins (TO0n). An external pulse output (TO0n) is generated when a match of the two compare registers (CCCn0 and CCCn1) and the TMCn register is detected. If a match is detected when the TMCn count value and the CCCn0 value are compared, the output level of the TO0n pin is set.
Page 341 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.1.7 Application examples (timer C) (1) Interval timer By setting the TMCCn0 and TMCCn1 registers as shown in Figure 10-7, timer C operates as an interval timer that repeatedly generates interrupt requests with the value that was preset in the CCCn0 register as the interval.
Page 342 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 10-8. Interval Timer Operation Timing Example Count clock TMCn register 0000H 0001H 0000H 0001H 0000H 0001H Clear Clear Count start CCCn0 register INTM0n0 interrupt Interval time Interval time Interval time Remarks 1. p: Setting value of CCCn0 register (0000H to FFFFH) t: Count clock cycle Interval time = (p + 1) ×...
Page 343 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) PWM output By setting the TMCCn0 and TMCCn1 registers as shown in Figure 10-9, timer C can output a PWM signal, whose frequency is determined according to the setting of the CSn2 to CSn0 bits of the TMCCn0 register, with the values that were preset in the CCCn0 and CCCn1 registers determining the intervals.
Page 344 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 10-10. PWM Output Timing Example Count clock TMCn 0000H 0001H FFFFH 0000H 0001H register Count start Clear CCCn0 register CCCn1 register INTM0n0 interrupt INTM0n1 interrupt TO0n (output) Remarks 1. p: Setting value of CCCn0 register (0000H to FFFFH) q: Setting value of CCCn1 register (0000H to FFFFH) p ≠...
Page 345 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Cycle measurement By setting the TMCCn0 and TMCCn1 registers as shown in Figure 10-11, timer C can measure the cycle of signals input to the INTP0n0 or INTP0n1 pin. The valid edge of the INTP0n0 pin is selected according to the IES0n01 and IES0n00 bits of the SESCn register, and the valid edge of the INTP0n1 pin is selected according to the IES0n11 and IES0n10 bits of the SESCn register.
Page 346 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 10-11. Contents of Register Settings When Timer C Is Used for Cycle Measurement OVFn CSn2 CSn1 CSn0 TMCCEn TMCCAEn TMCCn0 Supply input clocks to internal units Enable count operation OSTn ENTn1 ACTLVn ETIn CCLRn CMSn1 CMSn0 TMCCn1 Use CCCn0 register as capture register...
Page 347 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 10-12. Cycle Measurement Operation Timing Example Count clock TMCn 0000H 0001H FFFFH 0000H 0001H register Count start Clear INTP0n0 (input) CCCn0 register INTM0n0 interrupt INTOV0n interrupt (D1 − D0) × t {(10000H − D1) + D2} × t (D3 −...
Page 348 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.1.8 Cautions (timer C) Various cautions concerning timer C are shown below. (1) If a conflict occurs between the reading of the CCCn0 register and a capture operation when the CCCn0 register is used in capture mode, an external trigger (INTP0n0) valid edge is detected and an external interrupt request signal (INTM0n0) is generated, however, the timer value is not stored in the CCCn0 register.
Page 349 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.2 Timer D 10.2.1 Features (timer D) Timer D functions as a 16-bit interval timer. 10.2.2 Function overview (timer D) • 16-bit interval timer • Compare registers: 4 • Interrupt request sources: 4 sources •...
Page 350 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.2.4 Timer D (1) Timers D0 to D3 (TMD0 to TMD3) TMDn is a 16-bit timer. It is mainly used as an interval timer for software (n = 0 to 3). Starting and stopping TMDn is controlled by the TMDCEn bit of the timer mode control register Dn (TMCDn) (n = 0 to 3).
Page 351 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Compare registers D0 to D3 (CMD0 to CMD3) CMDn and the TMDn register count value are compared, and an interrupt request signal (INTCMDn) is generated when a match occurs. TMDn is cleared, in synchronization with this match. If the TMDCAEn bit of the TMCDn register is set to 0, a reset is performed asynchronously, and the registers are initialized (n = 0 to The CMDn registers are configured with a master/slave configuration.
Page 352 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 10-13. Example of Timing During TMDn Operation (a) When TMDn < < < < CMDn TMDn TMDCAEn TMDCEn CMDn INTCMDn Remark M = TMDn value when overwritten N = CMDn value when overwritten M <...
Page 353 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.2.5 Timer D control registers (1) Timer mode control registers D0 to D3 (TMCD0 to TMCD3) The TMCDn registers control the operation of timer Dn (n = 0 to 3). These registers can be read or written in 8-bit or 1-bit units. Caution The TMDCAEn and other bits cannot be set at the same time.
Page 354 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2/2) Bit position Bit name Function TMDCAEn Clock Action Enable (n = 0 to 3) Controls the internal count clock (n = 0 to 3). 0: The entire TMDn unit is reset asynchronously. The supply of input clocks to the TMDn unit stops.
Page 355 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.2.6 Timer D operation (1) Compare operation TMDn can be used for a compare operation in which the value that was set in a compare register (CMDn) is compared with the TMDn count value (n = 0 to 3). If a match is detected by the compare operation, an interrupt (INTCMDn) is generated.
Page 356 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 10-14. TMD0 Compare Operation Example (2/2) (b) When CMD0 is set to 0 Count clock Count up TMD0 clear Clear FFFFH TMD0 CMD0 Match detected (INTCMD0) Overflow Interval time = (FFFFH + 2) × (Count clock cycle) Remark User’s Manual U14359EJ4V0UM...
Page 357 CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 10.2.7 Application examples (timer D) (1) Interval timer This section explains an example in which timer D is used as an interval timer with 16-bit precision. Interrupt requests (INTCMDn) are output at equal intervals (see Figure 10-14 TMD0 Compare Operation Example).
Page 358 11.1.1 Switching between UART and CSI modes In the V850E/MA1, since UART0 and CSI0 pin and the UART1 and CSI1 pin are alternate function pins, they cannot be used at the same time. The PMC4 and PFC4 registers must be set in advance (see 14.3.5 Port 4).
Page 359 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2 Asynchronous Serial Interfaces 0 to 2 (UART0 to UART2) 11.2.1 Features • Transfer rate: 300 bps to 1,562.5 Kbps (using a dedicated baud rate generator and an internal system clock of 50 MHz) • Full-duplex communications On-chip receive buffer (RXBn) On-chip transmit buffer (TXBn) •...
Page 360 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2.2 Configuration UARTn is controlled by the asynchronous serial interface mode register (ASIMn), asynchronous serial interface status register (ASISn), and asynchronous serial interface transmission status register (ASIFn) (n = 0 to 2). Receive data is held in the receive buffer (RXBn), and transmit data is written to the transmit buffer (TXBn). Figure 11-1 shows the configuration of the asynchronous serial interface.
Page 361 CHAPTER 11 SERIAL INTERFACE FUNCTION (8) Transmit buffer (TXBn) TXBn is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXBn. The transmission completion interrupt request (INTSTn) is generated in synchronization with the completion of transmission of one frame.
Page 362 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2.3 Control registers (1) Asynchronous serial interface mode registers 0 to 2 (ASIM0 to ASIM2) These are 8-bit registers for controlling the transfer operations of UART0 to UART2. These registers can be read or written in 8-bit or 1-bit units. Caution When using UARTn, set the external pins related to the UARTn function in the control mode, set clock select register n (CKSRn) and baud rate generator control register n (BRGCn).
Page 363 CHAPTER 11 SERIAL INTERFACE FUNCTION (2/3) Bit position Bit name Function RXEn Receive Enable (n = 0 to 2) Specifies whether reception is enabled or disabled. 0: Reception is disabled 1: Reception is enabled Cautions 1. On startup, set UARTCAEn to 1 and then set RXEn to 1. To stop transmission, clear RXEn to 0 and then UARTCAEn to 0.
Page 364 CHAPTER 11 SERIAL INTERFACE FUNCTION (3/3) Bit position Bit name Function Character Length (n = 0 to 2) Specifies the character length of the transmit/receive data. 0: 7 bits 1: 8 bits Caution To overwrite the CLn bit, first clear (0) the TXEn and RXEn bits. Stop Bit Length (n = 0 to 2) Specifies the stop bit length of the transmit data.
Page 365 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status registers 0 to 2 (ASIS0 to ASIS2) These registers, which consist of 3-bit error flags (PEn, FEn, and OVEn), indicate the error status when UARTn reception is completed (n = 0 to 2). The status flag, which indicates a reception error, always indicates the status of the error that occurred most recently.
Page 366 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface transmission status registers 0 to 2 (ASIF0 to ASIF2) These registers, which consist of 2-bit status flags, indicate the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the TXSn register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 367 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Receive buffer registers 0 to 2 (RXB0 to RXB2) These are 8-bit buffer registers for storing parallel data that had been converted by the receive shift register. When reception is enabled (RXEn = 1 in the ASIMn register), receive data is transferred from the receive shift register to the receive buffer, in synchronization with the completion of the shift-in processing of one frame.
Page 368 CHAPTER 11 SERIAL INTERFACE FUNCTION (5) Transmit buffer registers 0 to 2 (TXB0 to TXB2) These are 8-bit buffer registers for setting transmit data. When transmission is enabled (TXEn = 1 in the ASIMn register), the transmit operation is started by writing data to TXBn.
Page 369 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2.4 Interrupt requests The following three types of interrupt requests are generated from UARTn (n = 0 to 2). • Reception error interrupt (INTSERn) • Reception completion interrupt (INTSRn) • Transmission completion interrupt (INTSTn) The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt.
Page 370 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2.5 Operation (1) Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 11-2. The character bit length within one data frame, the type of parity, and the stop bit length are specified by the asynchronous serial interface mode register n (ASIMn) (n = 0 to 2).
Page 371 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Transmit operation When UARTCAEn is set to 1 in the ASIMn register, a high level is output to the TXDn pin. Then, when TXEn is set to 1 in the ASIMn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmit buffer register n (TXBn) (n = 0 to 2).
Page 372 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-3. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 Stop TXDn (output) Start Parity INTSTn (output) (b) Stop bit length: 2 Stop Parity TXDn (output) Start INTSTn (output) Remark n = 0 to 2 User’s Manual U14359EJ4V0UM...
Page 373 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Continuous transmission operation UARTn can write the next data to the TXBn register at the time that the TXSn register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during interrupt servicing after the transmission of one data frame (n = 0 to 2).
Page 374 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-4. Continuous Transmission Processing Flow Set registers. Write transmit data to TXBn register. TXBFn = 0 when ASIFn register is read? Interrupt occurs. Transfer executed necessary number of times? TXSFn = 1 TXSFn = 0 when ASIFn register when ASIFn register is read?
Page 375 CHAPTER 11 SERIAL INTERFACE FUNCTION (a) Starting procedure The procedure for starting continuous transmission is shown below. Figure 11-5. Continuous Transmission Starting Procedure Start Start Stop Stop TXDn (output) Data (1) Data (2) <1> <2> <3> <4> <5> INTSTn (output) TXBn register Data (1) Data (2)
Page 376 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Ending procedure The procedure for ending continuous transmission is shown below. Figure 11-6. Continuous Transmission Ending Procedure Start Start Stop Stop TXDn (output) Data (m – 1) Data (m) <6> <7> <8> <9> <10> <11>...
Page 377 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Receive operation The awaiting reception state is set by setting UARTCAEn to 1 in the ASIMn register and then setting RXEn to 1 in the ASIMn register. RXDn pin sampling begins and a start bit is detected. When the start bit is detected, the receive operation begins, and data is stored sequentially in the receive shift register according to the baud rate that was set.
Page 378 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-7. Asynchronous Serial Interface Reception Completion Interrupt Timing RXDn (input) Start Parity Stop INTSRn (output) RXBn register Cautions 1. Be sure to read the receive buffer (RXBn) when a reception error occurs. Unless RXBn is read, an overrun error occurs when the next data is received, causing the reception error status to persist.
Page 379 CHAPTER 11 SERIAL INTERFACE FUNCTION (a) Separation of reception error interrupt A reception error interrupt can be separated from the INTSRn interrupt and generated as an INTSERn interrupt by clearing the ISRMn bit of the ASIMn register (n = 0 to 2) to 0. Figure 11-8.
Page 380 CHAPTER 11 SERIAL INTERFACE FUNCTION (6) Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (a) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 381 CHAPTER 11 SERIAL INTERFACE FUNCTION (7) Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output clock. If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 11- 11).
Page 382 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.2.6 Dedicated baud rate generators 0 to 2 (BRG0 to BRG2) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception in UARTn. The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 383 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Serial clock generation A serial clock can be generated according to the settings of the CKSRn and BRGCn registers (n = 0 to 2). The clock input to the 8-bit counter is selected according to the TPSn3 to TPSn0 bits of the CKSRn register. The 8-bit counter divisor value can be selected according to the BRGn7 to BRGn0 bits of the BRGCn register.
Page 384 CHAPTER 11 SERIAL INTERFACE FUNCTION (b) Baud rate generator control registers 0 to 2 (BRGC0 to BRGC2) The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. These registers can be read or written in 8-bit units. Caution If the BRGn7 to BRGn0 bits are to be overwritten, TXEn and RXEn should be set to 0 in the ASIMn register first (n = 0 to 2).
Page 385 CHAPTER 11 SERIAL INTERFACE FUNCTION (c) Baud rate The baud rate is the value obtained according to the following formula. XCLK Baud rate [bps] × = Frequency of basic clock selected according to TPSn3 to TPSn0 bits of CKSRn register. XCLK k = Value set according to BRGn7 to BRGn0 bits of BRGCn register (k = 8, 9, 10, ..., 255) (d) Baud rate error...
Page 386 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Baud rate setting example Table 11-3. Baud Rate Generator Setting Data Baud Rate = 50 MHz = 40 MHz = 33 MHz = 10 MHz (bps) XCLK XCLK XCLK XCLK −0.07 0.15 0.16 0.16 −0.07 0.15 0.16...
Page 387 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 388 CHAPTER 11 SERIAL INTERFACE FUNCTION Therefore, the maximum baud rate that can be received at the transfer destination is as follows. − BRmax (FLmin/11) Brate Similarly, the maximum allowable transfer rate can be obtained as follows. − × × − ×...
Page 389 CHAPTER 11 SERIAL INTERFACE FUNCTION (5) Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 390 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3 Clocked Serial Interfaces 0 to 2 (CSI0 to CSI2) 11.3.1 Features • Transfer rate: Master mode: Maximum 3.125 Mbps (when internal system clock operates at 50 MHz) Slave mode: Maximum 5 Mbps • Half-duplex communications •...
Page 391 CHAPTER 11 SERIAL INTERFACE FUNCTION (7) Serial clock counter The serial clock counter counts serial clocks that are output or input during transmit and receive operations and checks that 8-bit data has been transmitted or received. (8) Interrupt controller The interrupt controller controls whether or not an interrupt request is generated when the serial clock counter has counted eight serial clocks.
Page 392 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.3 Control registers (1) Clocked serial interface mode registers 0 to 2 (CSIM0 to CSIM2) The CSIMn register controls the operation of CSIn (n = 0 to 2). These registers can be read or written in 8-bit or 1-bit units. Be sure to set bits 5, 3, 2, and 1 to 0.
Page 393 CHAPTER 11 SERIAL INTERFACE FUNCTION <7> <6> <4> <0> Address After reset CSIM0 CSICAE0 TRMD0 DIR0 CSOT0 FFFFF900H CSIM1 CSICAE1 TRMD1 DIR1 CSOT1 FFFFF910H CSIM2 CSICAE2 TRMD2 DIR2 CSOT2 FFFFF920H Bit position Bit name Function CSICAEn CSI Operation Permission/Prohibition (n = 0 to 2) Specifies whether CSIn operation is enabled or disabled (n = 0 to 2).
Page 394 CHAPTER 11 SERIAL INTERFACE FUNCTION (2) Clocked serial interface clock selection registers 0 to 2 (CSIC0 to CSIC2) The CSICn register is an 8-bit register that controls the transmit operation of CSIn. These registers can be read or written in 8-bit units. Caution The CSIC2 to CSIC0 registers can be overwritten when CSICAEn = 0 in the CSIMn register.
Page 395 CHAPTER 11 SERIAL INTERFACE FUNCTION (2/2) Bit position Bit name Function 2 to 0 CKSn2 to Input Clock Selection CKSn0 Specifies the input clock. (n = 0 to 2) CKSn2 CKSn1 CKSn0 Input clock Mode Master mode Master mode Master mode Master mode Master mode Master mode...
Page 396 CHAPTER 11 SERIAL INTERFACE FUNCTION (3) Serial I/O shift registers 0 to 2 (SIO0 to SIO2) The SIOn register is an 8-bit shift register that converts parallel data to serial data. If TRMDn = 0 in the CSIMn register, the transfer is started by reading SIOn. Except when a reset is input, the SIOn register becomes 00H even when the CSICAEn bit of the CSIMn register is cleared (0).
Page 397 CHAPTER 11 SERIAL INTERFACE FUNCTION (4) Receive-only serial I/O shift registers 0 to 2 (SIOE0 to SIOE2) The SIOEn register is an 8-bit shift register that converts parallel data into serial data. A receive operation does not start even if the SIOEn register is read while the TRMD bit of the CSIMn register is 0. Therefore this register is used to read the value of the SIOn register (receive data) without starting a receive operation.
Page 398 CHAPTER 11 SERIAL INTERFACE FUNCTION (5) Clocked serial interface transmit buffer registers 0 to 2 (SOTB0 to SOTB2) The SOTBn register is an 8-bit buffer register for storing transmit data. If transmission/reception mode is set (TRMDn = 1 in the CSIMn register), a transmit operation is started by writing data to the SOTBn register.
Page 399 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.4 Operation (1) Transfer mode CSIn transmits and receives data in three lines: 1 clock line and 2 data lines. In reception-only mode (TRMDn = 0 in the CSIMn register), the transfer is started by reading the SIOn register (n = 0 to 2).
Page 400 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-16. Transfer Timing (a) When TRMDn = 1, DIRn = 0, CKPn = 0, and DAPn = 0 SCKn Reg-R/W (Write 55H to SOTBn) SOTBn 55H (transmission data) SIOn CSOTn bit INTCSIn interrupt (AAH) (55H) Remark n = 0 to 2...
Page 401 CHAPTER 11 SERIAL INTERFACE FUNCTION Figure 11-17. Clock Timing (a) When CKPn = 0 and DAPn = 0 SCKn SIn capture SIOn Reg-R/W INTCSIn interrupt CSOTn bit (b) When CKPn = 1 and DAPn = 0 SCKn SIn capture SIOn Reg-R/W INTCSIn interrupt CSOTn bit...
Page 402 CHAPTER 11 SERIAL INTERFACE FUNCTION 11.3.5 Output pins (1) SCKn pin When CSIn operation is disabled (CSICAEn = 0), the SCKn pin output state is as follows. CKPn SCKn Pin Output Fixed at high level Fixed at low level Remarks 1. When the CKPn bit is overwritten, the SCKn pin output changes. 2.
Page 403 (SOn). This is effective when connecting peripheral I/O that incorporate a conventional clocked serial interface, or a display controller to the V850E/MA1 (n = 2 to 0). When connecting the V850E/MA1 to several devices, lines for handshake are required.
Page 404 • Successive approximation method 12.2 Configuration The A/D converter of the V850E/MA1 adopts the successive approximation method, and uses A/D converter mode registers 0, 1, 2 (ADM0, ADM1, ADM2), and the A/D conversion result register (ADCR0 to ADCR7) to perform A/D conversion operations.
Page 405 This is the pin for inputting the reference voltage of the A/D converter. It converts signals input to the ANIn pin to digital signals based on the voltage applied between AV and AV In the V850E/MA1, the AV pin functions alternately as the AV pin. It is therefore impossible to set...
Page 406 CHAPTER 12 A/D CONVERTER Figure 12-1. Block Diagram of A/D Converter Series resistor string ANI0 Sample & hold circuit ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 Voltage comparator ANI7 SAR (10) INTAD ADCR0 INTM000 ADCR1 INTM001 Controller INTM010 ADCR2 INTM011 ADCR3 Edge ADTRG ADCR4...
Page 407 CHAPTER 12 A/D CONVERTER 12.3 Control Registers (1) A/D converter mode register 0 (ADM0) The ADM0 register is an 8-bit register that selects the analog input pin, specifies the operation mode, and executes conversion operations. This register can be read/written in 8-bit or 1-bit units. However, when data is written to the ADM0 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning.
Page 408 CHAPTER 12 A/D CONVERTER <7> <6> Address After reset ADM0 ADCE ADCS ANIS2 ANIS1 ANIS0 FFFFF200H Bit position Bit name Function ADCE Convert Enable Enables or disables A/D conversion operation. 0: Disabled 1: Enabled ADCS Converter Status Indicates the status of A/D converter. This bit is read only. 0: Stopped 1: Operating Buffer Select...
Page 409 CHAPTER 12 A/D CONVERTER (2) A/D converter mode register 1 (ADM1) The ADM1 register is an 8-bit register that specifies the conversion operation time and trigger mode. This register can be read/written in 8-bit units. However, when data is written to the ADM1 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning.
Page 410 CHAPTER 12 A/D CONVERTER (3) A/D converter mode register 2 (ADM2) The ADM2 register is an 8-bit register that controls the reset and clock of the A/D converter. This register can be read/written in 8-bit or 1-bit units. Caution Because ADCAE = 0 after reset release, the A/D converter enters the reset state. When operating the A/D converter, be sure to write to the ADM0 and ADM1 registers after setting the ADCAE bit of the ADM2 register to 1 (it is impossible to write to the ADM0 and ADM1 registers when ADCAE = 0).
Page 411 CHAPTER 12 A/D CONVERTER (4) A/D conversion result registers (ADCR0 to ADCR7, ADCR0H to ADCR7H) The ADCRn register is a 10-bit register holding the A/D conversion results. There are eight 10-bit registers. These registers are read-only in 16-bit or 8-bit units. During 16-bit access, the ADCRn register is specified, and during higher 8-bit access, the ADCRnH register is specified (n = 0 to 7).
Page 412 CHAPTER 12 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (of the A/D conversion result register (ADCRn)) is as follows: × ADCR 1,024 0.5) − × ≤...
Page 413 CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Operation 12.4.1 Basic operation of A/D converter A/D conversion is executed by the following procedure. (1) The ADCAE bit of the ADM2 register is set (1). (2) The selection of the analog input and specification of the operation mode, trigger mode, etc. should be Note 1 specified using the ADM0 and ADM1 registers When the ADCE bit of the ADM0 register is set (1), A/D conversion starts in the A/D trigger mode.
Page 414 CHAPTER 12 A/D CONVERTER 12.4.2 Operation mode and trigger mode Various conversion operations can be specified for the A/D converter by specifying the operation mode and trigger mode. The operation mode and trigger mode are set by the ADM0 and ADM1 registers. The following shows the relationship between the operation mode and trigger mode.
Page 415 CHAPTER 12 A/D CONVERTER (c) External trigger mode A mode that specifies the conversion timing of the analog input to the ANI0 to ANI3 pins using the ADTRG pin. This mode can be specified only with the ANI0 to ANI3 pins. (2) Operation mode There are two operation modes that set the ANI0 to ANI7 pins: select mode and scan mode.
Page 416 CHAPTER 12 A/D CONVERTER Figure 12-3. Select Mode Operation Timing: 1-Buffer Mode (ANI1) ANI1 Data 4 Data 5 (input) Data 1 Data 2 Data 3 Data 6 Data 7 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 conversion (ANI1)
Page 417 CHAPTER 12 A/D CONVERTER • 4-buffer mode In this mode, one analog input is A/D converted four times and the results are stored in the ADCR0 to ADCR3 registers. The A/D conversion end interrupt (INTAD) is generated when the four A/D conversions end.
Page 418 CHAPTER 12 A/D CONVERTER (b) Scan mode In this mode, the analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to 7).
Page 419 CHAPTER 12 A/D CONVERTER 12.5 Operation in A/D Trigger Mode When the ADCE bit of the ADM0 register is set to 1, A/D conversion is started. 12.5.1 Select mode operation In this mode, the analog input specified by the ADM0 register is A/D converted. The conversion results are stored in the ADCRn register corresponding to the analog input.
Page 420 CHAPTER 12 A/D CONVERTER (2) 4-buffer mode (A/D trigger select: 4 buffers) In this mode, one analog input is A/D converted four times and the results are stored in the ADCR0 to ADCR3 registers. When the 4th A/D conversion ends, an A/D conversion end interrupt (INTAD) is generated and the A/D conversion is stopped.
Page 421 CHAPTER 12 A/D CONVERTER 12.5.2 Scan mode operations In this mode, the analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to 7).
Page 422 CHAPTER 12 A/D CONVERTER 12.6 Operation in Timer Trigger Mode Conversion timings for up to four-channel analog inputs (ANI0 to ANI3) can be set for the A/D converter using the interrupt signal output from the TMC compare register. Two 16-bit timers (TMC0, TMC1) and four capture/compare registers (CCC00, CCC01, CCC10, CC11) are used for the timer to specify the analog conversion trigger.
Page 423 CHAPTER 12 A/D CONVERTER 12.6.1 Select mode operation In this mode, an analog input (ANI0 to ANI3) specified by the ADM0 register is A/D converted. The conversion results are stored in the ADCRn register. In the select mode, the 1-buffer mode and 4-buffer mode are provided according to the storing method of the A/D conversion results (n = 0 to 3).
Page 424 CHAPTER 12 A/D CONVERTER (b) 4-trigger mode (timer trigger select: 1 buffer, 4 triggers) In this mode, one analog input is A/D converted four times using four match interrupt signals (INTM000, INTM001, INTM010, INTM011) as triggers and the results are stored in one ADCRn register. The A/D conversion end interrupt (INTAD) is generated with each A/D conversion, and the ADCS bit of the ADM0 register is reset (0).
Page 425 CHAPTER 12 A/D CONVERTER (2) 4-buffer mode operation (timer trigger select: 4 buffers) In this mode, A/D conversion of one analog input is executed four times, and the results are stored in the ADCR0 to ADCR3 registers. There are two 4-buffer modes: 1-trigger mode and 4-trigger mode, according to the number of triggers.
Page 426 CHAPTER 12 A/D CONVERTER (b) 4-trigger mode In this mode, one analog input is A/D converted four times using four match interrupt signals (INTM000, INTM001, INTM010, INTM011) as triggers and the results are stored in four ADCRn registers. The A/D conversion end interrupt (INTAD) is generated when the four A/D conversions end, the ADCS bit is reset (0), and A/D conversion is stopped.
Page 427 CHAPTER 12 A/D CONVERTER 12.6.2 Scan mode operation In this mode, the analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin and are A/D converted the specified number of times using the match interrupt signal as a trigger. In the conversion operation, first the analog input lower channels (ANI0 to ANI3) are A/D converted the specified number of times.
Page 428 CHAPTER 12 A/D CONVERTER Figure 12-13. Example of 1-Trigger Mode Operation (Timer Trigger Scan: 1 Trigger) (a) Setting when scanning ANI0 to ANI3 ANI0 ADCR0 ANI1 ADCR1 INTM000 ANI2 ADCR2 ANI3 ADCR3 A/D converter ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ANI7 ADCR7 The ADCE bit of ADM0 is set to 1 (enable)
Page 429 CHAPTER 12 A/D CONVERTER (2) 4-trigger mode In this mode, analog inputs are A/D converted for the number of times specified using the match interrupt signal (INTM000, INTM001, INTM010, INTM011) as a trigger. The analog input and ADCRn register correspond one to one. When all the specified A/D conversions have ended, the A/D conversion end interrupt (INTAD) is generated and A/D conversion is stopped.
Page 430 CHAPTER 12 A/D CONVERTER Figure 12-14. Example of 4-Trigger Mode Operation (Timer Trigger Scan: 4 Triggers) (a) Setting when scanning ANI0 to ANI3 random INTM000 ANI0 ADCR0 INTM001 ANI1 ADCR1 INTM010 ANI2 ADCR2 INTM011 ANI3 ADCR3 A/D converter ANI4 ADCR4 ANI5 ADCR5 ANI6...
Page 431 CHAPTER 12 A/D CONVERTER 12.7 Operation in External Trigger Mode In the external trigger mode, the analog inputs (ANI0 to ANI3) are A/D converted by the ADTRG pin input timing. The ADTRG pin has an alternate function as the P37 and INTP123 pins. To set the external trigger mode, set the PMC37 bit of the PMC3 register to 1 and bits TRG2 to TRG0 of the ADM1 register to 110.
Page 432 CHAPTER 12 A/D CONVERTER (2) 4-buffer mode (external trigger select: 4 buffers) In this mode, one analog input is A/D converted four times using the ADTRG signal as a trigger and the results are stored in the ADCR0 to ADCR3 registers. The A/D conversion end interrupt (INTAD) is generated and A/D conversion is stopped after the 4th A/D conversion.
Page 433 CHAPTER 12 A/D CONVERTER 12.7.2 Scan mode operation (external trigger scan) In this mode, the analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin using the ADTRG signal as a trigger, and A/D converted. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to 7).
Page 434 CHAPTER 12 A/D CONVERTER Figure 12-17. Example of Scan Mode Operation (External Trigger Scan) (a) Setting when scanning ANI0 to ANI3 ANI0 ADCR0 ANI1 ADCR1 ANI2 ADCR2 ADTRG ANI3 ADCR3 A/D converter ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ANI7 ADCR7 The ADCE bit of ADM0 is set to 1 (enable) The external trigger is generated The external trigger is generated...
Page 435 CHAPTER 12 A/D CONVERTER 12.8 Notes on Operation 12.8.1 Stopping conversion operation When the ADCE bit of the ADM0 register is set to 0 during a conversion operation, the conversion operation stops and the conversion results are not stored in the ADCRn register (n = 0 to 7). 12.8.2 External/timer trigger interval Set the interval (input time interval) of the trigger in the external or timer trigger mode longer than the conversion time specified by the FR2 to FR0 bits of the ADM1 register.
Page 436 CHAPTER 12 A/D CONVERTER 12.8.4 Compare match interrupt in timer trigger mode The compare register’s match interrupt becomes an A/D conversion start trigger and starts the conversion operation. When this happens, the compare register’s match interrupt also functions as a compare register match interrupt for the CPU.
Page 437 CHAPTER 12 A/D CONVERTER 12.9 How to Read A/D Converter’s Characteristic Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 438 CHAPTER 12 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, quantization error is unavoidable.
Page 439 CHAPTER 12 A/D CONVERTER (5) Full-scale error This is a difference between the actually measured analog input voltage and its theoretical value when digital output changes from 1…110 to 0…111 (full scale − 3/2 LSB). Figure 12-21. Full-Scale Error Full-scale errors 2 AV REF −...
Page 440 CHAPTER 12 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relations. It indicates the maximum value of difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 441 CHAPTER 13 PWM UNIT 13.1 Features • PWMn: 2 channels • PWMn: Output pulse active level can be selected • Operation clock can be selected from among f /2, f /4, f /8, f /16, f /32, f /64 (f is the internal system clock) •...
Page 442 CHAPTER 13 PWM UNIT 13.3 Control Register (1) PWM control registers 0, 1 (PWMC0, PWMC1) The PWMCn register is used to control the PWMn’s operations (n = 0, 1). The PWMCn register can be read/written in 8-bit or 1-bit units. Caution When PWMn is used, be sure to set external pins related to PWMn to control mode.
Page 443 CHAPTER 13 PWM UNIT <7> <6> Address After Reset FFFFFC00H, PWMCn PWMEn ALVn PRMn1 PRMn0 PWPn2 PWPn1 PWPn0 FFFFFC10H Bit position Bit name Description Note PWMEn PWM Enable (n = 0, 1) This bit is used to enable or disable PWMn operation. 0: PWM operation disabled 1: PWM operation enabled ALVn...
Page 444 CHAPTER 13 PWM UNIT (2) PWM buffer registers 0, 1 (PWMB0, PWMB1) The PWMBn register is a 12-bit buffer register that is used to set control data for the active signal width of PWMn output. Bits 15 to 12 are fixed to zero. Even if 1 is written in these bits, it is ignored. It is possible to directly read the values of bits 11 to 8 as written irrespective of the bit length setting made by the PWMCn register.
Page 445 CHAPTER 13 PWM UNIT Figure 13-1. PWM Basic Operation Timing PWMEn bit Start TMPn count Counter Overflow signal PWMBn register Reload CMPn register Comparator match signal Reset PWMn (Output) FEH count Full count Remark n = 0, 1 Figure 13-2. Timing for Write Operation to PWMBn Register PWMEn bit Start TMPn count Counter...
Page 446 CHAPTER 13 PWM UNIT Figure 13-3. Timing When PWMBn Register Is Set to 00H Counter FEH FFH FEH FFH Overflow signal PWMBn register CMPn register Comparator match signal PWMn (Output) Not set to active level Remark n = 0, 1 Figure 13-4.
Page 447 CHAPTER 13 PWM UNIT 13.4.2 Repetition frequency The repetition frequencies of PWMn are shown below (n = 0, 1). PWMn Operating Resolution Repetition Frequency Frequency 8 bits 9 bits 10 bits 12 bits 8 bits 9 bits 10 bits 12 bits 8 bits 9 bits 10 bits...
Page 448 CHAPTER 14 PORT FUNCTIONS 14.1 Features • Input-only ports: Input/output ports: 106 • Function alternately as other peripheral I/O pins. • It is possible to specify input and output in 1-bit units. User’s Manual U14359EJ4V0UM...
Page 449 CHAPTER 14 PORT FUNCTIONS 14.2 Port Configuration The V850E/MA1 incorporates a total of 115 input/output ports (including 9 input-only ports) labeled ports 0 through 5, and AL, AH, DL, CS, CT, CM, CD, and BD. The port configuration is shown below.
Page 450 CHAPTER 14 PORT FUNCTIONS (1) Function of each port The port functions of this product are shown below. 8-bit and 1-bit operations are possible on all ports, allowing various kinds of control to be performed. In addition to their port functions, these pins also function as internal peripheral I/O input/output pins in the control mode.
Page 451 CHAPTER 14 PORT FUNCTIONS (2) Function when each port’s pins are reset and registers that set the port/control mode (1/2) Port Name Pin Name Pin Function After Reset Register That Sets the Mode Single-Chip Mode 0 Single-Chip ROMless ROMless Mode 1 Mode 0 Mode 1 Port 0...
Page 452 CHAPTER 14 PORT FUNCTIONS (2/2) Port Name Pin Name Pin Function After Reset Register That Sets the Mode Single-Chip Mode 0 Single-Chip ROMless ROMless Mode 1 Mode 0 Mode 1 Port 5 P50/INTP030/TI030 P50 (input mode) PMC5 P51/INTP031 P51 (input mode) P52/TO03 P52 (input mode) Port 7...
Page 453 CHAPTER 14 PORT FUNCTIONS (3) Block diagram of port Figure 14-1. Block Diagram of Type A PMCmn PMmn Output signal in control PORT mode Address Remark m: Port number n: Bit number User’s Manual U14359EJ4V0UM...
Page 454 CHAPTER 14 PORT FUNCTIONS Figure 14-2. Block Diagram of Type B PMCmn PMmn PORT Address Input signal in Noise elimination control mode Edge detection Remark m: Port number Bit number Figure 14-3. Block Diagram of Type C ANIn Input signal in Sample &...
Page 455 CHAPTER 14 PORT FUNCTIONS Figure 14-4. Block Diagram of Type D MODE0 to MODE2 PMCCMn PMCMn PORT PCMn PCMn Address Input signal in control mode Remark n = 0, 3 User’s Manual U14359EJ4V0UM...
Page 456 CHAPTER 14 PORT FUNCTIONS Figure 14-5. Block Diagram of Type E MODE0 to MODE2 PMCCM5 PMCM5 PORT PCM5 PCM5 Address Input signal in control mode Figure 14-6. Block Diagram of Type F Noise elimination Address Edge detection User’s Manual U14359EJ4V0UM...
Page 457 CHAPTER 14 PORT FUNCTIONS Figure 14-7. Block Diagram of Type G PFC4n PMC4n PM4n Output signal in control mode PORT Address Remark n = 0, 3 User’s Manual U14359EJ4V0UM...
Page 458 CHAPTER 14 PORT FUNCTIONS Figure 14-8. Block Diagram of Type H PFCmn PMCmn PMmn PORT Address Input signal in control mode Edge detection Remark m: Port number Bit number User’s Manual U14359EJ4V0UM...
Page 459 CHAPTER 14 PORT FUNCTIONS Figure 14-9. Block Diagram of Type I PFC32 SCK2 output enable signal PMC32 PM32 Output signal in PORT control mode Address Input signal in control mode User’s Manual U14359EJ4V0UM...
Page 460 CHAPTER 14 PORT FUNCTIONS Figure 14-10. Block Diagram of Type J MODE0 to MODE2 PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U14359EJ4V0UM...
Page 461 CHAPTER 14 PORT FUNCTIONS Figure 14-11. Block Diagram of Type K MODE0 to MODE2 PFCmn PMCmn PMmn Output signal in control mode PORT Address Remark m: Port number n: Bit number User’s Manual U14359EJ4V0UM...
Page 462 CHAPTER 14 PORT FUNCTIONS Figure 14-12. Block Diagram of Type L PFC3n PMC3n PM3n Output signal in control mode PORT Address Input signal in control mode Remark n = 0, 3 User’s Manual U14359EJ4V0UM...
Page 463 CHAPTER 14 PORT FUNCTIONS Figure 14-13. Block Diagram of Type M SCKx output enable signal PMC4n PM4n Output signal in control mode PORT Address Input signal in control mode Remark n = 2, 5 x: 0 (when n = 2) 1 (when n = 5) User’s Manual U14359EJ4V0UM...
Page 464 CHAPTER 14 PORT FUNCTIONS Figure 14-14. Block Diagram of Type N PFC2n PMC2n PM2n Output signal in control mode PORT Address Input signal in control mode Remark m: Port number n: Bit number User’s Manual U14359EJ4V0UM...
Page 465 CHAPTER 14 PORT FUNCTIONS Figure 14-15. Block Diagram of Type O MODE0 to MODE2 I/O control PMCDLn PMDLn Output signal in control mode PORT PDLn PDLn Address Input signal in control mode I/O control Remark n = 0 to 15 User’s Manual U14359EJ4V0UM...
Page 466 CHAPTER 14 PORT FUNCTIONS 14.3 Port Pin Functions 14.3.1 Port 0 Port 0 is an 8-bit I/O port that can be set to the input or output mode in 1-bit units. Address After reset FFFFF400H Undefined Bit position Bit name Function 7 to 0 Port 0...
Page 467 CHAPTER 14 PORT FUNCTIONS (b) Port 0 mode control register (PMC0) This register can be read/written in 8-bit or 1-bit units. Address After reset PMC0 PMC07 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 FFFFF440H Bit position Bit name Function Port Mode Control 7 to 4 PMC0n Specifies operation mode of P0n pin in combination with the PFC0 register.
Page 468 CHAPTER 14 PORT FUNCTIONS (c) Port 0 function control register (PFC0) This register can be read/written in 8-bit or 1-bit units. Bits 3 to 0, however, are fixed to 0, so writing 1 to these bits is ignored. Caution When the port mode is specified by the port 0 mode control register (PMC0), the PFC0 setting becomes invalid.
Page 469 CHAPTER 14 PORT FUNCTIONS 14.3.2 Port 1 Port 1 is a 4-bit I/O port that can be set to the input or output mode in 1-bit units. Address After reset – – – – FFFFF402H Undefined Bit position Bit name Function Port 1 3 to 0...
Page 470 CHAPTER 14 PORT FUNCTIONS (b) Port 1 mode control register (PMC1) This register can be read/written in 8-bit or 1-bit units. Address After reset PMC1 PMC13 PMC12 PMC11 PMC10 FFFFF442H Bit position Bit name Function PMC13 Port Mode Control Specifies operation mode of P13 pin. 0: I/O port mode 1: TO01 output mode PMC12...
Page 471 CHAPTER 14 PORT FUNCTIONS 14.3.3 Port 2 Port 2 is an I/O port that can be set to the input or output mode in 1-bit units except for P20, which is an input-only pin. Caution P20 is fixed to NMI input. The level of the NMI input can be read regardless of the PM2 and PMC2 registers’...
Page 472 CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port 2 I/O mode setting is performed by the port 2 mode register (PM2), and the control mode setting is performed by the port 2 mode control register (PMC2) and the port 2 function control register (PFC2). (a) Port 2 mode register (PM2) This register can be read/written in 8-bit or 1-bit units.
Page 473 CHAPTER 14 PORT FUNCTIONS (b) Port 2 mode control register (PMC2) This register can be read/written in 8-bit or 1-bit units. Address After reset PMC2 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 FFFFF444H Bit position Bit name Function 7 to 4 PMC2n Port Mode Control (n = 7 to 4)
Page 474 CHAPTER 14 PORT FUNCTIONS (c) Port 2 function control register (PFC2) This register can be read/written in 8-bit or 1-bit units. Bits 3 to 0, however, are fixed to 0 by hardware, so writing 1 to these bits is ignored. Caution When the port mode is specified by the port 2 mode control register (PMC2), the PFC2 setting becomes invalid.
Page 475 CHAPTER 14 PORT FUNCTIONS 14.3.4 Port 3 Port 3 is an 8-bit I/O port that can be set to the input or output mode in 1-bit units. Address After reset FFFFF406H Undefined Bit position Bit name Function 7 to 0 Port 3 (n = 7 to 0) I/O port...
Page 476 CHAPTER 14 PORT FUNCTIONS (b) Port 3 mode control register (PMC3) This register can be read/written in 8-bit or 1-bit units. Address After reset PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF446H Bit position Bit name Function PMC37 Port Mode Control Specifies operation mode of P37 pin.
Page 477 CHAPTER 14 PORT FUNCTIONS (c) Port 3 function control register (PFC3) This register can be read/written in 8-bit or 1-bit units. Bits 5 to 7, however, are fixed to 0, so writing 1 to these bits is ignored. Caution When the port mode is specified by the port 3 mode control register (PMC3), the PFC3 setting becomes invalid.
Page 478 CHAPTER 14 PORT FUNCTIONS 14.3.5 Port 4 Port 4 is a 6-bit I/O port that can be set to the input or output mode in 1-bit units. Address After reset – – FFFFF408H Undefined Bit position Bit name Function 5 to 0 Port 4 (n = 5 to 0) I/O port...
Page 479 CHAPTER 14 PORT FUNCTIONS (b) Port 4 mode control register (PMC4) This register can be read/written in 8-bit or 1-bit units. Address After reset PMC4 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 FFFFF448H Bit position Bit name Function PMC45 Port Mode Control Specifies operation mode of P45 pin.
Page 480 CHAPTER 14 PORT FUNCTIONS (c) Port 4 function control register (PFC4) This register can be read/written in 8-bit or 1-bit units. Bits 7 to 5 and 2, however, are fixed to 0, so writing 1 to these bits is ignored. Caution When the port mode is specified by the port 4 mode control register (PMC4), the PFC4 register setting becomes invalid.
Page 481 CHAPTER 14 PORT FUNCTIONS 14.3.6 Port 5 Port 5 is a 3-bit I/O port that can be set to the input or output mode in 1-bit units. Address After reset – – – – – FFFFF40AH Undefined Bit position Bit name Function 2 to 0 Port 5...
Page 482 CHAPTER 14 PORT FUNCTIONS (b) Port 5 mode control register (PMC5) This register can be read/written in 8-bit or 1-bit units. Address After reset PMC5 PMC52 PMC51 PMC50 FFFFF44AH Bit position Bit name Function PMC52 Port Mode Control Specifies operation mode of P52 pin. 0: I/O port mode 1: TO03 output mode PMC51...
Page 483 CHAPTER 14 PORT FUNCTIONS 14.3.7 Port 7 Port 7 is an 8-bit input-only port whose pins are fixed to input. Address After reset FFFFF40EH Undefined Bit position Bit name Function 7 to 0 Port 7 (n = 7 to 0) Input-only port In addition to their function as port pins, the port 7 pins can also operate as the analog inputs to the A/D converter in the control mode.
Page 484 CHAPTER 14 PORT FUNCTIONS 14.3.8 Port AL Port AL (PAL) is a 16-bit I/O port that can be set to the input or output mode in 1-bit units. When the higher 8 bits of port AL are used as port ALH (PALH) and the lower 8 bits as port ALL (PALL), port AL becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
Page 485 CHAPTER 14 PORT FUNCTIONS (b) Port AL mode control register (PMCAL) The port AL mode control register (PMCAL) can be read/written in 16-bit units. If the higher 8 bits of PMCAL are used as port AL mode control register H (PMCALH), and the lower 8 bits as port AL mode control register L (PMCALL), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit units.
Page 486 CHAPTER 14 PORT FUNCTIONS 14.3.9 Port AH Port AH (PAH) is a 16-bit I/O port that can be set in the input or output mode in 1-bit units. When the higher 8 bits of port AH are used as port AHH (PAHH) and the lower 8 bits as port AHL (PAHL), port AH becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
Page 487 CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port AH I/O mode setting is performed by the port AH mode register (PMAH), and the control mode setting is performed by the port AH mode control register (PMCAH). (a) Port AH mode register (PMAH) The port AH mode register (PMAH) can be read/written in 16-bit units.
Page 488 CHAPTER 14 PORT FUNCTIONS 14.3.10 Port DL Port DL (PDL) is a 16-bit I/O port that can be set in the input or output mode in 1-bit units. When the higher 8 bits of port DL are used as port DLH (PDLH), and the lower 8 bits as port DLL (PDLL), port DL becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
Page 489 CHAPTER 14 PORT FUNCTIONS (b) Port DL mode control register (PMCDL) The port DL mode control register (PMCDL) can be read/written in 16-bit units. If the higher 8 bits of PMCDL are used as port DL mode control register H (PMCDLH), and the lower 8 bits as port DL mode control register L (PMCDLL), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit units.
Page 490 CHAPTER 14 PORT FUNCTIONS 14.3.11 Port CS Port CS is an 8-bit I/O port that can be set to the input or output mode in 1-bit units. Address After reset PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 FFFFF008H Undefined Bit position Bit name Function...
Page 491 CHAPTER 14 PORT FUNCTIONS (2) I/O mode/control mode setting The port CS I/O mode setting is performed by the port CS mode register (PMCS), and the control mode setting is performed by the port CS mode control register (PMCCS) and the port CS function control register (PFCCS).
Page 492 CHAPTER 14 PORT FUNCTIONS (b) Port CS mode control register (PMCCS) This register can be read/written in 8-bit or 1-bit units. Note Address After reset PMCCS PMCCS7 PMCCS6 PMCCS5 PMCCS4 PMCCS3 PMCCS2 PMCCS1 PMCCS0 FFFFF048H 00H/FFH Note In ROMless modes 0 and 1, and single-chip mode 1: In single-chip mode 0: Bit position Bit name...
Page 493 CHAPTER 14 PORT FUNCTIONS (c) Port CS function control register (PFCCS) This register can be read/written in 8-bit or 1-bit units. Bits 7, 6, 4, 3, 1, and 0, however, are fixed to 0, so writing 1 to these bits is ignored. Caution When the port mode is specified by the port CS mode control register (PMCCS), the PFCCS setting becomes invalid.
Page 494 CHAPTER 14 PORT FUNCTIONS 14.3.12 Port CT Port CT is a 6-bit I/O port that can be set to input or output mode in 1-bit units. Address After reset PCT7 PCT6 PCT5 PCT4 – – PCT1 PCT0 FFFFF00AH Undefined Bit position Bit name Function 7 to 4, 1, 0...
Page 495 CHAPTER 14 PORT FUNCTIONS (b) Port CT mode control register (PMCCT) This register can be read/written in 8-bit or 1-bit units. Note Address After reset PMCCT PMCCT7 PMCCT6 PMCCT5 PMCCT4 PMCCT1 PMCCT0 FFFFF04AH 00H/F3H Note In ROMless modes 0 and 1, and single-chip mode 1: In single-chip mode 0: Bit position Bit name...
Page 496 CHAPTER 14 PORT FUNCTIONS 14.3.13 Port CM Port CM is a 6-bit I/O port that can be set to the input or output mode in 1-bit units. Address After reset – – PCM5 PCM4 PCM3 PCM2 PCM1 PCM0 FFFFF00CH Undefined Bit position Bit name Function...
Page 497 CHAPTER 14 PORT FUNCTIONS (b) Port CM mode control register (PMCCM) This register can be read/written in 8-bit or 1-bit units. Caution If the mode of the PCM1/CLKOUT/BUSCLK pin is changed from the I/O port mode to the CLKOUT/BUSCLK mode, a glitch may be generated in the CLKOUT/BUSCLK output immediately after the change.
Page 498 CHAPTER 14 PORT FUNCTIONS (c) Port CM function control register (PFCCM) This register can be read/written in 8-bit or 1-bit units. Bits 7 to 2 and 0, however, are fixed to 0, so writing 1 to these bits is ignored. To output the half clock of the internal system clock from the BUSCLK pin, the BCP bit of the BCP register must be set to 1.
Page 499 CHAPTER 14 PORT FUNCTIONS 14.3.14 Port CD Port CD is a 4-bit I/O port that can be set to the input or output mode in 1-bit units. Address After reset – – – – PCD3 PCD2 PCD1 PCD0 FFFFF00EH Undefined Bit position Bit name Function...
Page 500 CHAPTER 14 PORT FUNCTIONS (b) Port CD mode control register (PMCCD) This register can be read/written in 8-bit or 1-bit units. Cautions 1. Do not perform the SDCLK and SDCKE output mode setting simultaneously. Be sure to perform the SDCLK output mode setting before the SDCKE output mode setting.
Page 501 CHAPTER 14 PORT FUNCTIONS (c) Port CD function control register (PFCCD) This register can be read/written in 8-bit or 1-bit units. Bits 7 to 4, 1, and 0, however, are fixed to 0, so writing 1 to these bits is ignored. Caution When the port mode is specified by the port CD mode control register (PMCCD), the PFCCD setting becomes invalid.
Page 502 CHAPTER 14 PORT FUNCTIONS 14.3.15 Port BD Port BD is a 4-bit I/O port that can be set to the input or output mode in 1-bit units. Address After reset – – – – PBD3 PBD2 PBD1 PBD0 FFFFF012H Undefined Bit position Bit name Function...
Page 503 CHAPTER 14 PORT FUNCTIONS (b) Port BD mode control register (PMCBD) This register can be read/written in 8-bit or 1-bit units. Address After reset PMCBD PMCBD3 PMCBD2 PMCBD1 PMCBD0 FFFFF052H Bit position Bit name Function 3 to 0 PMCBDn Port Mode Control (n = 3 to 0) Specifies operation mode of PBDn pin.
Page 504 CHAPTER 15 RESET FUNCTIONS When a low-level signal is input to the RESET pin, a system reset is effected and the hardware is initialized. When the RESET signal level changes from low to high, the reset state is released and CPU starts program execution.
Page 505 CHAPTER 15 RESET FUNCTIONS (1) Acknowledging the reset signal RESET (input) Analog Analog Analog delay delay delay Eliminated as noise Internal system Note reset signal ∆ ∆ Reset Reset acknowledgement release Note The internal system reset signal continues in the active state for at least 4 system clock cycles after reset clear timing by the RESET signal.
Page 506 CHAPTER 15 RESET FUNCTIONS 15.3 Initialization Initialize the contents of each register as necessary while programming. The initial values of the CPU, internal RAM, and on-chip peripheral I/O after a reset are shown in Table 15-2. Table 15-2. Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (1/3) Internal Hardware Register Name Initial Value After Reset...
Page 507 CHAPTER 15 RESET FUNCTIONS Table 15-2. Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (2/3) Internal Hardware Register Name Initial Value After Reset On-chip Serial interface Clocked serial interface mode register n (CSIMn) (n = 0 to 2) peripheral functions Clocked serial interface clock select register n (CSICn) (n = 0 to 2)
Page 508 CHAPTER 15 RESET FUNCTIONS Table 15-2. Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (3/3) Internal Hardware Register Name Initial Value After Reset On-chip DMA functions DMA addressing control register n (DADCn) (n = 0 to 3) 0000H peripheral DMA byte count register n (DBCn) (n = 0 to 3)
Page 509 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 The µ PD70F3107A is the flash memory version of the V850E/MA1 and it has an on-chip 256 KB flash memory configured as two 128 KB areas. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions.
Page 510 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 Figure 16-1. Wiring Example of Adapter (FA-144GJ-UEN) for V850E/MA1 Flash Memory Programming 99 98 82 81 µ PD70F3107A Connect to GND Connect to VDD /RESET RESERVE/HS Remarks 1. Pins whose connections are not indicated should be connected according to the recommended connections of unused pins (refer to 2.4 Pin I/O Circuits and Recommended Connection of...
Page 511 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 Table 16-1. Wiring of Adapter for V850E/MA1 Flash Memory Programming (FA-144GJ-UEN) Pin Configuration of Flash Programmer (PG-FP3) With CSI0 + HS With CSI0 Signal Name Input/Output Pin Function Pin Name Pin No.
Page 512 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 Figure 16-2. Wiring Example of Adapter (FA-161F1-EN4) for V850E/MA1 Flash Memory Programming P11 P13 E14 F12 µ PD70F3107A Connect to GND Connect to VDD Leave open B1 B3 C1 CLKOUT...
Page 513 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 Table 16-2. Wiring of Adapter for V850E/MA1 Flash Memory Programming (FA-161F1-EN4) Pin Configuration of Flash Programmer (PG-FP3) With CSI0 + HS With CSI0 Signal Name Input/Output Pin Function Pin Name Pin No.
Page 514 A host machine is required for controlling the dedicated flash programmer. CSI0 is used for the interface between the dedicated flash programmer and the V850E/MA1 to perform writing, erasing, etc. A dedicated program adapter (FA Series) is required for off-board writing.
Page 515 MODE2/V pin. The following shows an example of the connection of the MODE2/V pin. V850E/MA1 Dedicated flash programmer connection pin MODE2/V Pull-down resistor (R 16.5.2 Serial interface pin The following shows the pins used by each serial interface.
Page 516 Dedicated flash programmer connection pin Output pin Other device Input pin In the flash memory programming mode, if the signal the V850E/MA1 outputs affects the other device, isolate the signal on the other device side. V850E/MA1 Dedicated flash programmer connection pin Input pin...
Page 517 When the reset signal is input from the user system in flash memory programming mode, the programming operations will not be performed correctly. Therefore, do not input signals other than the reset signal from the dedicated flash programmer. V850E/MA1 Conflict of signals Dedicated flash programmer connection pin...
Page 518 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.6 Programming Method 16.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Start Supply RESET pulse Switch to flash memory programming mode Select communication mode Manipulate flash memory End? User’s Manual U14359EJ4V0UM...
Page 519 CHAPTER 16 16.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850E/MA1 in the flash memory programming mode. To switch to this mode, set the MODE0 to MODE1 and MODE2/V pins before releasing reset.
Page 520 The V850E/MA1 communicates with the dedicated flash programmer by means of commands. A command sent from the dedicated flash programmer to the V850E/MA1 is called the “command”. The response signal sent from the V850E/MA1 to the dedicated flash programmer is called the “response command”.
Page 521 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7 Flash Memory Programming by Self-Programming The µ PD70F3107A supports a self-programming function to rewrite the flash memory using a user program. By using this function, the flash memory can be rewritten with a user application. This self-programming function can be also used to upgrade the program in the field.
Page 522 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.2 Self-programming function The µ PD70F3107A provides self-programming functions, as shown below. By combining these functions, erasing/writing flash memory becomes possible. Table 16-4. Function List Type Function Name Function Erase Area erase Erases the specified area.
Page 523 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 The self-programming interface is outlined below. Figure 16-4. Outline of Self-Programming Interface Application program RAM parameter Entry program Self-programming interface Device internal processing Flash-memory manipulation Flash memory 16.7.4 Hardware environment To write or erase the flash memory, a high voltage must be applied to the V pin.
Page 524 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 The voltage applied to the V pin must satisfy the following conditions: • Hold the voltage applied to the V pin at 0 V in the normal operation mode and hold the V voltage only while the flash memory is being manipulated.
Page 525 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.5 Software environment The following conditions must be satisfied before using the entry program to call the device internal processing. Table 16-5. Software Environmental Conditions Item Description Location of entry Execute the entry program in memory other than the block 0 space and flash memory area.
Page 526 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.6 Self-programming function number To identify a self-programming function, the following numbers are assigned to the respective functions. These function numbers are used as parameters when the device internal processing is called. Table 16-6.
Page 527 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.7 Calling parameters The arguments used to call the self-programming function are shown in the table below. In addition to these arguments, parameters such as the write time and erase time are set to the RAM parameters indicated by ep (r30). Table 16-7.
Page 528 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.8 Contents of RAM parameters Reserve the following 48-byte area in the internal RAM or external RAM for the RAM parameters, and set the parameters to be input. Set the base addresses of these parameters to ep (r30). Table 16-8.
Page 529 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.9 Errors during self-programming The following errors related to manipulation of the flash memory may occur during self-programming. An error occurs if the return value (r10) of each function is not 0. Table 16-9.
Page 530 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.11 Area number The area numbers and memory map of the µ PD70F3107A are shown below. Figure 16-7. Area Configuration 0 x 3 F F F F (End address of area 1) Area 1 (128 KB) 0 x 2 0 0 0 0 (Start address of area 1)
Page 531 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.12 Flash programming mode control register (FLPMC) The flash memory mode control register (FLPMC) is a register used to enable/disable writing to flash memory and to specify the self-programming mode. This register can be read/written in 8-bit or 1-bit units (the VPP bit (bit 2) is read-only).
Page 532 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 Setting data to the flash programming mode control register (FLPMC) is performed in the following sequence. <1> Disable interrupts (set the NP bit and ID bit of the PSW to 1) <2>...
Page 533 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.13 Calling device internal processing This section explains the procedure to call the device internal processing from the entry program. Before calling the device internal processing, make sure that all the conditions of the hardware and software environments are satisfied and that the necessary arguments and RAM parameters have been set.
Page 534 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 (4) Program example An example of a program in which the entry program is executed as a subroutine is shown below. In this example, the return address is saved to the stack and then the device internal processing is called. This program must be located in memory other than the block 0 space and flash memory area.
Page 535 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 (5) Internal manipulation setup parameter If the self-programming mode is switched to the normal operation mode, the µ PD70F3107A must wait for 100 µ s before it accesses the flash memory. In the program example in (4) above, the elapse of this wait time is ensured by setting ISETUP to “130”...
Page 536 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.14 Erasing flash memory flow The procedure to erase the flash memory is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-8.
Page 537 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.15 Successive writing flow The procedure to write data all at once to the flash memory by using the function to successively write data in word units is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure.
Page 538 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.16 Internal verify flow The procedure of internal verification is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-10. Internal Verify Flow Internal verify Set RAM parameter.
Page 539 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.17 Acquiring flash information flow The procedure to acquire the flash information is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-11.
Page 540 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.7.18 Self-programming library V850 Series User’s Manual Flash Memory Self Programming Library is available for reference when executing self-programming. In this manual, the library uses the self-programming interface of the V850 Series and can be used in C as a utility and as part of the application program.
Page 541 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 The configuration of the self-programming library is outlined below. Figure 16-13. Outline of Self-Programming Library Configuration Application program C interface Self-programming library Entry program RAM parameter Self-programming interface Device internal processing Flash memory manipulation Flash memory User’s Manual U14359EJ4V0UM...
Page 542 FLASH MEMORY ( µ µ µ µ PD70F3107A) CHAPTER 16 16.8 How to Distinguish Flash Memory and Mask ROM Versions It is possible to distinguish a flash memory version ( µ PD70F3107A) and mask ROM versions ( µ PD703105A, 703106A, 703107A) by means of software, using the methods shown below. <1>...
Page 543 APPENDIX A REGISTER INDEX (1/8) Register Symbol Register Name Unit Page ADCR0 A/D conversion result register 0 (10 bits) ADCR0H A/D conversion result register 0H (8 bits) ADCR1 A/D conversion result register 1 (10 bits) ADCR1H A/D conversion result register 1H (8 bits) ADCR2 A/D conversion result register 2 (10 bits) ADCR2H...
Page 544 APPENDIX A REGISTER INDEX (2/8) Register Symbol Register Name Unit Page BRGC0 Baud rate generator control register 0 BRG0 BRGC1 Baud rate generator control register 1 BRG1 BRGC2 Baud rate generator control register 2 BRG2 Bus size configuration register CCC00 Capture/compare register C00 CCC01 Capture/compare register C01...
Page 545 APPENDIX A REGISTER INDEX (3/8) Register Symbol Register Name Unit Page DBC0 DMA byte count register 0 DMAC DBC1 DMA byte count register 1 DMAC DBC2 DMA byte count register 2 DMAC DBC3 DMA byte count register 3 DMAC DCHC0 DMA channel control register 0 DMAC DCHC1...
Page 546 APPENDIX A REGISTER INDEX (4/8) Register Symbol Register Name Unit Page IMR0 Interrupt mask register 0 INTC IMR1 Interrupt mask register 1 INTC IMR2 Interrupt mask register 2 INTC IMR3 Interrupt mask register 3 INTC INTM0 External interrupt mode register 0 INTC INTM1 External interrupt mode register 1...
Page 547 APPENDIX A REGISTER INDEX (5/8) Register Symbol Register Name Unit Page P13IC3 Interrupt control register INTC Port 2 Port Port 3 Port Port 4 Port Port 5 Port Port 7 Port Port AH Port Port AL Port Port BD Port Port CD Port Port CM...
Page 548 APPENDIX A REGISTER INDEX (6/8) Register Symbol Register Name Unit Page PMCAH Port AH mode control register Port PMCAL Port AL mode control register Port PMCBD Port BD mode control register Port PMCCD Port CD mode control register Port PMCCM Port CM mode control register Port PMCCS...
Page 549 APPENDIX A REGISTER INDEX (7/8) Register Symbol Register Name Unit Page SCR4 DRAM configuration register 4 MEMC SDRAM configuration register 4 MEMC SCR6 DRAM configuration register 6 MEMC SDRAM configuration register 6 MEMC SEIC0 Interrupt control register INTC SEIC1 Interrupt control register INTC SEIC2 Interrupt control register...
Page 550 APPENDIX A REGISTER INDEX (8/8) Register Symbol Register Name Unit Page TMCD0 Timer mode control register D0 TMCD1 Timer mode control register D1 TMCD2 Timer mode control register D2 TMCD3 Timer mode control register D3 TMD0 Timer D0 TMD1 Timer D1 TMD2 Timer D2 TMD3...
Page 551 APPENDIX B INSTRUCTION SET LIST B.1 Convention (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose register: Used as source register. reg2 General-purpose register: Used mainly as destination register. Also used as source register in some instructions. reg3 General-purpose register: Used mainly to store the remainders of division results and the higher 3 bits of...
Page 552 APPENDIX B INSTRUCTION SET LIST (3) Register symbols used in operation Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 553 APPENDIX B INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 × Set or cleared in accordance with the results. Previously saved values are restored. (6) Condition codes Condition Name Condition Code Condition Formula Explanation (cond)
Page 554 APPENDIX B INSTRUCTION SET LIST B.2 Instruction Set (In Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1, reg2 r r r r r 0 0 1 1 1 0 R R R R R GR[reg2]←GR[reg2]+GR[reg1] ×...
Page 555 APPENDIX B INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT DBTRAP 1111100001000000 DBPC←PC+2 (returned PC) DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H 0000011111100000 PSW.ID←1 0000000101100000 DISPOSE imm5, list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend (imm5 logically shift left by 2) LLLLLLLLLLL00000 GR[reg in list12]←Load-memory (sp, Word)
Page 556 APPENDIX B INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT LD.H disp16[reg1], reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend (disp16) Note ddddddddddddddd0 GR[reg2]←sign-extend (Load-memory (adr, Note 8 Halfword)) LDSR reg2, regID rrrrr111111RRRRR SR[regID]←GR[reg2] Other than regID = PSW 0000000000100000 ×...
Page 557 APPENDIX B INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × reg1, reg2 r r r r r 0 0 1 0 0 0 R R R R R GR[reg2]←GR[reg2]OR GR[reg1] ×...
Page 558 APPENDIX B INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × SET1 bit#3, disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend (disp16) dddddddddddddddd Z flag←Not (Load-memory-bit (adr, bit#3)) Note 3 Note 3 Note 3 Store-memory-bit (adr, bit#3, 1) ×...
Page 559 APPENDIX B INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1, reg2 r r r r r 0 0 1 1 0 1 R R R R R GR[reg2]←GR[reg2]–GR[reg1] ×...
Page 560 APPENDIX B INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. r r r r r = regID specification RRRRR = reg2 specification...
Page 561 APPENDIX C INDEX BCT0, BCT1 ............102 BCYST ..............56 A/D conversion result registers 0 to 7 ....411 BEC ................105 A/D conversion result registers 0H to 7H ....411 Block transfer mode ..........227 A/D converter mode register 0 ....... 407 Boundary operation conditions .......140 A/D converter mode register 1 .......
Page 562 APPENDIX C INDEX Clock control register ..........303 DMA restart register..........216 Clock select registers 0 to 2 ........383 DMA source address registers 0H to 3H ....208 Clocked serial interface clock selection DMA source address registers 0L to 3L....209 registers 0 to 2 ............
Page 563 APPENDIX C INDEX Maskable interrupts ..........272 Maximum response time for DMA transfer request 261 HALT mode............312 Memory block function..........97 HLDAK..............54 Memory map ............75 HLDRQ ..............54 MODE0 to MODE2 ...........60 How to distinguish flash memory and mask ROM Multiple interrupt processing control.......295 versions ..............
Page 564 APPENDIX C INDEX P20 to P27 ............... 49 PLL mode .............. 302 P3................475 PM0 ............... 466 P30 to P37 ............... 50 PM1 ............... 469 P4................478 PM2 ............... 472 P40 to P45 ............... 51 PM3 ............... 475 P5................481 PM4 ...............
Page 565 APPENDIX C INDEX Port 5 ..............481 PWM0...............47 Port 5 mode control register........482 PWM1...............48 Port 5 mode register ..........481 PWMB0, PWMB1 ...........444 Port 7 ..............483 PWMC0, PWMC1...........442 Port AH ..............486 Port AH mode control register........ 487 Quantization error...........438 Port AH mode register ...........
Page 566 APPENDIX C INDEX Self-programming function ........522 TMC0 to TMC3 ............325 SELFREF ..............54 TMCC00 to TMCC30 ..........329 Self-refresh control function (EDO DRAM)..... 175 TMCC01 to TMCC31 ..........331 Self-refresh control function (SDRAM) ....201 TMCD0 to TMCD3 ..........353 Serial I/O shift registers 0 to 2 ........
Page 567 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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NEC V850E/MA1 User Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Bus Control Function

Chapter 5 Memory Access Control Function

Chapter 6 Dma Functions (Dma Controller)

Chapter 7 Interrupt/Exception Processing Function

Chapter 8 Prescaler Unit (Prs)

Chapter 9 Clock Generation Function

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