Page 1 User’s Manual V850E/MS1 32-/16-Bit Single-Chip Microcontrollers Hardware µ µ µ µ PD703100 µ µ µ µ PD703100A µ µ µ µ PD703101 µ µ µ µ PD703101A µ µ µ µ PD703102 µ µ µ µ PD703102A µ µ µ µ PD70F3102 µ...
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Page 3 Reset operation must be executed immediately after power-on for devices having reset function. V850E/MS1 and V850 Family are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability •...
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Page 7 Major Revisions in This Edition Page Description Change of R/W and bit units for manipulation for PMX and PMCX in 3.4.8 Peripheral I/O registers p. 98 p. 108 Addition of Caution to 4.5.2 (1) Bus size configuration register (BSC) p. 151 Modification of WAIT signal in Figure 5-10 DRAM Access Timing During DMA Flyby Transfer p.
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Page 9 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the V850E/MS1 ( µ PD703100, 703100A, 703101, 703101A, 703102, 703102A, 70F3102, 70F3102A) to design application systems using the V850E/MS1. Purpose This manual is designed to help users understand the hardware functions of the V850E/MS1.
Page 10 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher address on the top and lower address on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 11 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Document related to device Document Name Document No. µ PD703100-33, 703100-40, 703101-33, 703102-33 Data Sheet U13995E µ PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Sheet U14168E µ...
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Page 13: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION......................... 27 Outline ............................27 Features............................28 Applications ..........................30 Ordering Information ......................... 30 Pin Configuration (Top View) ....................31 Function Block ........................... 35 1.6.1 Internal block diagram ........................35 1.6.2 Internal units ..........................36 CHAPTER 2 PIN FUNCTIONS......................... 39 List of Pin Functions........................
Page 14 4.5.2 Bus sizing function........................108 4.5.3 Bus width .............................109 Wait Function ..........................113 4.6.1 Programmable wait function ......................113 4.6.2 External wait function........................114 4.6.3 Relationship between programmable wait and external wait............114 4.6.4 Bus cycles in which the wait function is valid................115 Idle State Insertion Function ....................
Page 15 6.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) ............... 171 6.3.7 DMA disable status register (DDIS)..................... 173 6.3.8 DMA restart register (DRST) ....................... 173 6.3.9 Flyby transfer data wait control register (FDW) ................174 DMA Bus States........................175 6.4.1 Types of bus states ........................
Page 16 7.3.5 In-service priority register (ISPR)....................218 7.3.6 Maskable interrupt status flag (ID)....................218 7.3.7 Noise elimination .........................219 7.3.8 Edge detection function .......................220 Software Exception ........................222 7.4.1 Operation .............................222 7.4.2 Restore ............................223 7.4.3 Exception status flag (EP) ......................224 Exception Trap.......................... 225 7.5.1 Illegal op code definition ......................225 7.5.2 Operation .............................226...
Page 17 Timer 4 Operation........................271 9.5.1 Count operation ........................... 271 9.5.2 Count clock selection........................271 9.5.3 Overflow ............................271 9.5.4 Compare operation........................272 Application Example ........................ 274 Precaution ..........................281 CHAPTER 10 SERIAL INTERFACE FUNCTION ................283 10.1 Features............................. 283 10.2 Asynchronous Serial Interfaces 0, 1 (UART0, UART1) ............284 10.2.1 Features ............................
Page 18 11.8.2 External/timer trigger interval.......................345 11.8.3 Operation of standby mode ......................345 11.8.4 Compare match interrupt when in timer trigger mode..............345 11.8.5 Timer 1 functions when in external trigger mode .................346 CHAPTER 12 PORT FUNCTIONS......................347 12.1 Features............................. 347 12.2 Port Configuration ........................348 12.3 Port Pin Functions........................
Page 19 14.6.2 Flash memory programming mode....................419 14.6.3 Selection of communication mode....................419 14.6.4 Communication command ......................420 APPENDIX A REGISTER INDEX......................423 APPENDIX B INSTRUCTION SET LIST....................431 General Examples ........................431 Instruction Set (in Alphabetical Order) .................. 434 APPENDIX C INDEX ..........................441 User’s Manual U12688EJ4V0UM00...
Page 20 LIST OF FIGURES (1/4) Figure No. Title Page Program Counter (PC) ........................... 71 Interrupt Source Register (ECR)........................72 Program Status Word (PSW)......................... 73 CPU Address Space............................76 Image on Address Space ..........................77 Internal ROM Area in Single-Chip Mode 1..................... 84 Recommended Memory Map.........................
Page 21 LIST OF FIGURES (2/4) Figure No. Title Page 6-11 Example of Forcible Termination of DMA Transfer ..................193 Block Diagram of Interrupt Control Function ....................203 Processing Configuration of Non-Maskable Interrupt.................. 205 Acknowledging Non-Maskable Interrupt Request ..................206 RETI Instruction Processing ........................207 Maskable Interrupt Processing ........................
Page 22 LIST OF FIGURES (3/4) Figure No. Title Page 9-14 Example of Pulse Width Measurement Setting Procedure ................276 9-15 Example of Interrupt Request Processing Routine Which Calculates the Pulse Width....... 276 9-16 Example of PWM Output Timing........................277 9-17 Example of PWM Output Setting Procedure....................278 9-18 Example of Interrupt Request Processing Routine for Rewriting Compare Value........
Page 23 LIST OF FIGURES (4/4) Figure No. Title Page 11-13 Example of 1-Trigger Mode (Timer Trigger Scan 1-Trigger) Operation............338 11-14 Example of 4-Trigger Mode (Timer Trigger Scan 4-Trigger) Operation............340 11-15 Example of 1-Buffer Mode (External Trigger Select 1-Buffer) Operation ............ 341 11-16 Example of 4-Buffer Mode (External Trigger Select 4-Buffer) Operation ............
Page 24 LIST OF TABLES (1/2) Table No. Title Page Program Registers............................71 System Register Numbers..........................72 Interrupt/Exception Table..........................83 Bus Cycles in Which the Wait Function Is Valid ..................115 Bus Priority Order ............................122 Example of DRAM and Address Multiplex Width..................138 Example of DRAM Refresh Interval ......................
Page 25 LIST OF TABLES (2/2) Table No. Title Page 13-1 Operating State of Each Pin During Reset ....................409 13-2 Initial Values of CPU, Internal RAM, and Internal Peripheral I/O after Reset ..........411 14-1 List of Communication Modes ........................419 User’s Manual U12688EJ4V0UM00...
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Page 27: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850E/MS1 is one of NEC’s “V850 Family ” of single-chip microcontrollers. This chapter gives a simple outline of the V850E/MS1. 1.1 Outline The V850E/MS1 is a 32-/16-bit single-chip microcontroller which uses the V850 Family’s “V850E” CPU, and...
Page 28: Features
CHAPTER 1 INTRODUCTION 1.2 Features { Number of instructions: 25 ns (at internal 40 MHz) … µ PD703100-40, 703100A-40 { Minimum instruction execution time: 30 ns (at internal 33 MHz) … other than above 32 bits × 32 { General registers: { Instruction set: Upwardly compatible with V850 CPU Signed multiplication (16 bits ×...
Page 29 CHAPTER 1 INTRODUCTION { DMA controller: 4 channels Transfer units: 8 bits/16 bits Maximum transfer count: 65,536 (2 Transfer type: Flyby (1-cycle)/2-cycle Transfer mode: Single/Single step/Block DMA transfer terminate (terminal count) output signal { I/O lines: Input ports: I/O ports: { Real-time pulse unit: 16-bit timer/event counter: 6 channels 16-bit timers: 6...
Page 30: Applications
CHAPTER 1 INTRODUCTION 1.3 Applications • OA devices (printers, facsimiles, PPCs, etc.) • Multimedia devices (digital still cameras, video printers, etc.) • Consumer appliances (single lens reflex cameras, etc.) • Industrial devices (motor control, NC machine tools, etc.) 1.4 Ordering Information Part Number Package Maximum Operating...
Page 31: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) 157-pin plastic FBGA (14 × × × × 14 mm) • µ PD703100AF1-40-FA1 • µ PD703100AF1-33-FA1 • µ PD703101AF1-33-×××-FA1 • µ PD703102AF1-33-×××-FA1 • µ PD70F3102AF1-33-FA1 Top View Bottom View A B C D E F G H J K L M N P R T T R P N M L K J H G F E D C B A Index mark Index mark...
Page 32 CHAPTER 1 INTRODUCTION (2/2) Pin Name Pin Name Pin Name Number Number Number TI10/P03 TI12/P103 RESET INTP100/DMARQ0/P04 INTP120/TC0/P104 INTP151/P125 INTP121/TC1/P105 INTP150/P124 — HLDAK/P96 OE/P95 ANI0/P70 A21/P65 BCYST/P94 A20/P64 TO120/P100 SCK0/P24 TO101/P01 TO121/P101 SCK1/P27 TCLR10/P02 TCLR12/P102 INTP132/SI2/P36 TI13/P33 REFRQ/PX5 TO130/P30 A23/P67 HLDRQ/P97 INTP141/SO3/P115 A22/P66...
Page 33 CHAPTER 1 INTRODUCTION 144-pin plastic LQFP (fine pitch) (20 × × × × 20 mm) • µ PD703100GJ-40-8EU, 703100AGJ-40-8EU • µ PD703100GJ-33-8EU, 703100AGJ-33-8EU • µ PD703101GJ-33-×××-8EU, 703101AGJ-33-×××-8EU • µ PD703102GJ-33-×××-8EU, 703102AGJ-33-×××-8EU • µ PD70F3102GJ-33-8EU, 70F3102AGJ-33-8EU INTP103/DMARQ3/P07 A16/P60 INTP102/DMARQ2/P06 A17/P61 INTP101/DMARQ1/P05 A18/P62 INTP100/DMARQ0/P04 A19/P63...
Page 34 CHAPTER 1 INTRODUCTION Pin Name A0 to A23: Address Bus P60 to P67: Port 6 ADTRG: AD Trigger Input P70 to P77: Port 7 ANI0 to ANI7: Analog Input P80 to P87: Port 8 Analog Power Supply P90 to P97: Port 9 Analog Reference Voltage P100 to P107:...
Page 35: Function Block
CHAPTER 1 INTRODUCTION 1.6 Function Block 1.6.1 Internal block diagram HLDRQ HLDAK INTP100 to INTP103 INTC CS0 to CS7/RAS0 to RAS7 Instruction INTP110 to INTP113 IOWR queue DRAMC INTP120 to INTP123 Multiplier Note IORD INTP130 to INTP133 (32 × 32 → 64) REFRQ INTP140 to INTP143 BCYST...
Page 36: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits) and a barrel shifter (32 bits), help accelerate processing of complex instructions.
Page 37 CHAPTER 1 INTRODUCTION (5) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP100 to INTP103, INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143, INTP150 to INTP153) from internal peripheral I/O and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources.
Page 38 CHAPTER 1 INTRODUCTION (10) Ports As shown below, the following ports have general port functions and control pin functions. Port Port Function Control Function Port 0 8-bit I/O Real-time pulse unit input/output, external interrupt input, DMA controller input Port 1 8-bit I/O Real-time pulse unit input/output, external interrupt input, DMA controller output Port 2...
Page 39: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The names and functions of this product’s pins are listed below. These pins can be divided into port pins and non- port pins according to their functions. 2.1 List of Pin Functions (1) Port pins (1/4) Pin Name Function Alternate Function...
Page 40 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/4) Pin Name Function Alternate Function Port 3 TO130 8-bit input/output port TO131 Input/output mode can be specified in 1-bit units. TCLR13 TI13 INTP130 INTP131/SO2 INTP132/SI2 INTP133/SCK2 P40 to P47 Port 4 D0 to D7 8-bit input/output port Input/output mode can be specified in 1-bit units.
Page 41 CHAPTER 2 PIN FUNCTIONS (1) Port pins (3/4) Pin Name Function Alternate Function P100 Port 10 TO120 8-bit input/output port P101 TO121 Input/output mode can be specified in 1-bit units. P102 TCLR12 P103 TI12 P104 INTP120/TC0 P105 INTP121/TC1 P106 INTP122/TC2 P107 INTP123/TC3 P110...
Page 42 CHAPTER 2 PIN FUNCTIONS (1) Port pins (4/4) Pin Name Function Alternate Function Port B 8-bit input/out port Input/output mode can be specified in 1-bit units. Port X REFRQ 3-bit input/output port WAIT Input/output mode can be specified in 1-bit units. CLKOUT User’s Manual U12688EJ4V0UM00...
Page 43 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/4) Pin Name Function Alternate Function TO100 Output Pulse signal output of timers 10 to 15 TO101 TO110 TO111 TO120 P100 TO121 P101 TO130 TO131 TO140 P110 TO141 P111 TO150 P120 TO151 P121 TCLR10 Input External clear signal input of timers 10 to 15...
Page 44 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/4) Pin Name Function Alternate Function INTP130 Input External maskable interrupt request input, or timer 13 external capture trigger input INTP131 P35/SO2 INTP132 P36/SI2 INTP133 P37/SCK2 INTP140 Input External maskable interrupt request input, or timer 14 external P114 capture trigger input INTP141...
Page 45 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (3/4) Pin Name Function Alternate Function Output Write enable signal output for DRAM Output Output enable signal output for DRAM LCAS Output Column address strobe signal output for DRAM lower data P90/LWR UCAS Output Column address strobe signal output for DRAM higher data P91/UWR...
Page 46 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (4/4) Pin Name Function Alternate Function  RESET Input System reset input  Input Connects the system clock oscillator. In the case of an external source supplying the clock, it is input to X1. ...
Page 47: Pin Status
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The state of each pin after reset, in a power save mode (software STOP, IDLE, HALT), during bus hold (TH), and in the idle state (TI), is shown below. Operating State Reset Software IDLE Mode HALT Mode Bus Hold...
Page 48 CHAPTER 2 PIN FUNCTIONS Operating State Reset Software IDLE Mode HALT Mode Bus Hold Idle State STOP Mode (TH) (TI)    SI0 to SI3 Operating Operating Operating SO0 to SO3 Hi-Z Hold Hold Operating Operating Operating SCK0 to SCK3 Hi-Z Hold (output) Hold (output)
Page 49: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (Port 0) ··· 3-state I/O Port 0 is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode it operates as the input/output for the real-time pulse unit (RPU), the external interrupt request input and the DMA request input.
Page 50 CHAPTER 2 PIN FUNCTIONS (2) P10 to P17 (Port 1) ··· 3-state I/O Port 1 is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode it operates as the input/output for the real-time pulse unit (RPU), the external interrupt request input and the DMA request input.
Page 51 CHAPTER 2 PIN FUNCTIONS (3) P20 to P27 (Port 2) ··· 3-state I/O Port 2, except for P20, which is an input-only pin, is an input/output port which can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode it operates as the input/output for the serial interface (UART0/CSI0, UART1/CST1).
Page 52 CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) ··· 3-state I/O Port 3 is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode it operates as the input/output for the real-time pulse unit (RPU), the external request input and the serial interface (CSI2) input/output.
Page 53 CHAPTER 2 PIN FUNCTIONS (5) P40 to P47 (Port 4) ··· 3-state I/O Port 4 is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode (external expansion mode) it operates as a data bus (D0 to D7) when memory is externally expanded.
Page 54 CHAPTER 2 PIN FUNCTIONS (7) P60 to P67 (Port 6) ··· 3-state I/O Port 6 is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode (external expansion mode) it operates as an address bus (A16 to A23) when memory is externally expanded.
Page 55 CHAPTER 2 PIN FUNCTIONS (9) P80 to P87 (Port 8) ··· 3-state I/O Port 8 is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode it operates as a control signal output when memory and peripheral I/O are externally expanded.
Page 56 CHAPTER 2 PIN FUNCTIONS (iv) IOWR (I/O Write) ··· 3-state output This is the write strobe signal for external I/O during DMA flyby transfer. It indicates whether the bus cycle currently being executed is a write cycle for external I/O during flyby transfer, or a write cycle for the SRAM area.
Page 57 CHAPTER 2 PIN FUNCTIONS (v) RD (Read Strobe) ··· 3-state output This strobe signal shows that the bus cycle currently being executed is a read cycle for the SRAM, external ROM, external peripheral I/O, page ROM or synchronous flash memory area. In the idle state (TI), it becomes inactive.
Page 58 CHAPTER 2 PIN FUNCTIONS (11) P100 to P107 (Port 10) ··· 3-state I/O Port 10 is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode it operates as an input/output for real time pulse unit (RPU), external interrupt request input and DMA termination signal (terminal count) from DMA controller.
Page 59 CHAPTER 2 PIN FUNCTIONS (12) P110 to P117 (Port 11) ··· 3-state I/O Port 11 is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode it operates as an input/output for real-time pulse unit (RPU), external interrupt request, input and serial interface (CSI3) input/output.
Page 60 CHAPTER 2 PIN FUNCTIONS (13) P120 to P127 (Port 12) ··· 3-state I/O Port 12 is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode it operates as an input/output for real-time pulse unit (RPU), external interrupt request input and external trigger input to A/D converter.
Page 61 CHAPTER 2 PIN FUNCTIONS (14) PA0 to PA7 (Port A) ··· 3-state I/O Port A is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode (external expansion mode) it operates as an address bus (A0 to A7) when memory is externally expanded.
Page 62 CHAPTER 2 PIN FUNCTIONS (16) PX5 to PX7 (Port X) ··· 3-state I/O Port X is an 8-bit input/output port that can be set to input or output in 1-bit units. Besides functioning as a port, in the control mode it operates as a refresh request signal output for DRAM, wait insertion signal input and system clock output.
Page 63 CHAPTER 2 PIN FUNCTIONS (18) MODE0 to MODE3 (Mode) ··· input These are the input pins that specify the operation mode. Operation modes can be roughly divided into normal operation mode and flash memory programming mode. In the normal operation mode, there are single-chip modes 0 and 1, and ROM-less modes 0 and 1 (for details, refer to 3.3 Operation Modes).
Page 64 CHAPTER 2 PIN FUNCTIONS (19) RESET (Reset) ··· input RESET input is asynchronous input for a signal that has a constant low-level width regardless of the operating clock’s status. When this signal is input, a system reset is executed as the first priority ahead of all other operations.
Page 65: Pin Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Pin Input/Output Circuits and Recommended Connection of Unused Pins If connecting to V or V via resistors, it is recommended that 1 to 10 kΩ resistors be connected. Pin Name Input/Output Circuit Type Recommended Connection of Unused Pins P00/TO100, P01/TO101 Input: Independently connect to HV...
Page 66 CHAPTER 2 PIN FUNCTIONS Pin Name Input/Output Circuit Type Recommended Connection of Unused Pins P102/TCLR12, P103/TI12 Input: Independently connect to HV via a resistor. P104/INTP120/TC0 to Output: Leave open. P107/INTP123/TC3 P110/TO140, P111/TO141 P112/TCLR14, P113/TI14 P114/INTP140 P115/INTP141/SO3 P116/INTP142/SI3 P117/INTP143/SCK3 P120/TO150, P121/TO151 P122/TCLR15, P123/TI15 P124/INTP150 to P126/INTP152 P127/INTP153/ADTRG...
Page 67: Pin Input/Output Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pin Input/Output Circuits Type 1 Type 5-K Data P-ch IN/OUT P-ch Output N-ch disable N-ch Input enable Type 9 Type 2 P-ch Comparator – N-ch (threshold voltage) Schmitt-triggered input with hysteresis characteristics Input enable Type 5 Data P-ch IN/OUT...
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Page 69: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850E/MS1 is based on RISC architecture and executes almost all the instructions in one clock cycle, using 5-stage pipeline control. 3.1 Features • Minimum instruction execution time: 25 ns (at internal 40 MHz operation) … µ PD703100-40, 703100A-40 30 ns (at internal 33 MHz operation) …...
Page 70: Cpu Register Set
CHAPTER 3 CPU FUNCTION 3.2 CPU Register Set The registers of the V850E/MS1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. The size of the registers is 32 bits. For details, refer to V850E/MS1 User’s Manual Architecture. (1) Program register set (2) System register set Zero Register...
Page 71: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 72: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers System Register Name Usage Operation EIPC Status saving register during These registers save the PC and PSW when a software exception or interrupt occurs.
Page 73 CHAPTER 3 CPU FUNCTION Figure 3-3. Program Status Word (PSW) After reset 00000020H Bit Position Flag Function 31 to 8 Reserved field (fixed to 0). NMI Pending Indicates that NMI processing is in progress. This flag is set when an NMI is accepted, and disables multiple interrupts.
Page 74: Operation Modes
CHAPTER 3 CPU FUNCTION 3.3 Operation Modes 3.3.1 Operation modes The V850E/MS1 has the following operation modes. Mode specification is carried out by MODE0 to MODE3. (1) Normal operation mode (a) Single-chip modes 0, 1 Access to the internal ROM is enabled. In single-chip mode 0, after system reset is cancelled, each pin related to the bus interface enters the port mode, branches to the reset entry address of the internal ROM and starts instruction processing.
Page 75: Operation Mode Specification
CHAPTER 3 CPU FUNCTION 3.3.2 Operation mode specification The operation mode is specified according to the status of pins MODE0 to MODE3. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation. (a) µ...
Page 76: Address Space
CHAPTER 3 CPU FUNCTION 3.4 Address Space 3.4.1 CPU address space The CPU of the V850E/MS1 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported.
Page 77: Image
CHAPTER 3 CPU FUNCTION 3.4.2 Image The core CPU supports 4 GB of “virtual” addressing space, or 64 memory blocks, each containing 64 MB physical address space. In actuality, the same 64 MB physical address space is accessed regardless of the values of bits 31 to 26 of the CPU address.
Page 78: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are set to 0, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation, the higher 6 bits ignore the carry or borrow.
Page 79: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.4 Memory map The V850E/MS1 reserves areas as shown below. Each mode is specified by the MM register and the MODE0 to MODE3 pins. Note 1 Note 1 Single-chip mode 0 Single-chip mode 1 ROM-less mode 0, 1 x3FFFFFFH Internal peripheral Internal peripheral...
Page 80: Area
CHAPTER 3 CPU FUNCTION 3.4.5 Area (1) Internal ROM area ( µ µ µ µ PD703101, 703101A, 703102, 703102A, 70F3102, and 70F3102A only) (a) Memory map 1 MB of internal ROM area, addresses 00000H to FFFFFH, is reserved. <1> µ µ µ µ PD703101, 703101A 96 KB of memory, addresses 00000H to 17FFFH, is provided as physical internal ROM (mask ROM).
Page 81 CHAPTER 3 CPU FUNCTION <2> µ µ µ µ PD703102, 703102A 128 KB of memory, addresses 00000H to 1FFFFH, is provided as physical internal ROM (mask ROM). Also, in the remaining area (20000H to FFFFFH), the image of 00000H to 1FFFFH can be seen. x00FFFFFH Image x00E0000H...
Page 82 CHAPTER 3 CPU FUNCTION <3> µ µ µ µ PD70F3102, 70F3102A 128 KB of memory, addresses 00000H to 1FFFFH, is provided as physical internal ROM (flash memory). Also, in the remaining area (20000H to FFFFFH), the image of 00000H to 1FFFFH can be seen. x00FFFFFH Image x00E0000H...
Page 83 CHAPTER 3 CPU FUNCTION Table 3-3. Interrupt/Exception Table (1/2) Start Address of Interrupt/Exception Table Interrupt/Exception Source 00000000H RESET 00000010H 00000040H TRAP0n (n = 0 to FH) 00000050H TRAP1n (n = 0 to FH) 00000060H ILGOP 00000080H INTOV10 00000090H INTOV11 000000A0H INTOV12 000000B0H INTOV13...
Page 84 CHAPTER 3 CPU FUNCTION Table 3-3. Interrupt/Exception Table (2/2) Start Address of Interrupt/Exception Table Interrupt/Exception Source 00000290H INTCM41 000002A0H INTDMA0 000002B0H INTDMA1 000002C0H INTDMA2 000002D0H INTDMA3 00000300H INTCSI0 00000310H INTSER0 00000320H INTSR0 00000330H INTST0 00000340H INTCSI1 00000350H INTSER1 00000360H INTSR1 00000370H INTST1 00000380H...
Page 85 CHAPTER 3 CPU FUNCTION (2) Internal RAM area 4 KB of memory, addresses 3FFE000H to 3FFEFFFH, is provided as a physical internal RAM area. x3FFEFFFH Internal RAM x3FFE000H (3) Internal peripheral I/O area 4 KB of memory, addresses 3FFF000H to 3FFFFFFH, is provided as an internal peripheral I/O area. x3FFFFFFH Internal peripheral I/O x3FFF000H...
Page 86 CHAPTER 3 CPU FUNCTION (4) External memory area The following areas can be used as external memory area. However, the reserved area from x1000000H to x2FFFFFFH is excluded. (a) µ µ µ µ PD703101, 703101A, 703102, 703102A, 70F3102, 70F3102A When in single-chip mode 0: x0100000H to x3FFDFFFH When in single-chip mode 1: x0000000H to x00FFFFFH, x0200000H to x3FFDFFFH...
Page 87: External Expansion Mode
CHAPTER 3 CPU FUNCTION 3.4.6 External expansion mode The V850E/MS1 allows external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, A, and B. Setting the external expansion mode is carried out by selecting each pin of ports 4, 5, 6, A, and B in the control mode by means of the MM register.
Page 88 CHAPTER 3 CPU FUNCTION Address After reset FFFFF04CH Note Note When in ROM-less mode 0: 07H When in single-chip mode 0: 00H When in ROM-less mode 1: 0FH When in single-chip mode 1: 07H Bit Position Bit Name Function 3 to 0 MM3 to Memory Expansion Mode Set the function of ports 4, 5, 6, A, and B.
Page 89: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTION 3.4.7 Recommended use of address space The architecture of the V850E/MS1 requires that a register that serves as a pointer be secured for address generation when accessing the operand data in the data space. An instruction can be used to directly access operand data at the address in this pointer register ±32 KB.
Page 90 CHAPTER 3 CPU FUNCTION Example Application of wrap-around 0001FFFFH 00007FFFH Internal ROM area 32 Kbytes (R=) 00000000H Internal peripheral 4 Kbytes I/O area FFFFF000H Internal RAM area 4 Kbytes FFFFE000H External memory 24 Kbytes area FFFF8000H When R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, an addressing range of 00000000H ±32 KB can be referenced with the sign-extended, 16-bit displacement value.
Page 91 CHAPTER 3 CPU FUNCTION Figure 3-7. Recommended Memory Map Program space Data space FFFFFFFFH FFFFF5F7H FFFFF5F6H Internal peripheral I/O FFFFF000H FFFFEFFFH Internal RAM FFFFE000H FFFFDFFFH External x3FFFFFFH memory x3FFF5F7H x3FFF5F6H Internal FF000000H peripheral I/O x3FFF000H FEFFFFFFH x3FFEFFFH 04000000H Internal RAM 03FFFFFFH x3FFF000H Internal...
Page 92: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.8 Peripheral I/O registers (1/8) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits FFFFF000H Port 0 Undefined FFFFF002H Port 1 FFFFF004H Port 2 FFFFF006H Port 3 FFFFF008H Port 4 FFFFF00AH Port 5...
Page 93 CHAPTER 3 CPU FUNCTION (2/8) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits FFFFF050H Port 8 mode control register PMC8 00H/FFH FFFFF052H Port 9 mode control register PMC9 FFFFF054H Port 10 mode control register PMC10 FFFFF056H Port 11 mode control register...
Page 94 CHAPTER 3 CPU FUNCTION (3/8) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits FFFFF0D0H Asynchronous serial interface mode register 10 ASIM10 FFFFF0D2H Asynchronous serial interface mode register 11 ASIM11 FFFFF0D4H Asynchronous serial interface status register 1 ASIS1 FFFFF0D8H Receive buffer 1 (9 bits)
Page 95 CHAPTER 3 CPU FUNCTION (4/8) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits FFFFF138H Interrupt control register P15IC0 FFFFF13AH Interrupt control register P15IC1 FFFFF13CH Interrupt control register P15IC2 FFFFF13EH Interrupt control register P15IC3 FFFFF140H Interrupt control register...
Page 96 CHAPTER 3 CPU FUNCTION (5/8) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits FFFFF1B0H DMA source address register 2H DSA2H Undefined FFFFF1B2H DMA source address register 2L DSA2L FFFFF1B4H DMA destination address register 2H DDA2H FFFFF1B6H DMA destination address register 2L...
Page 97 CHAPTER 3 CPU FUNCTION (6/8) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits FFFFF260H Timer unit mode register 11 TUM11 0000H FFFFF262H Timer control register 11 TMC11 FFFFF264H Timer output control register 11 TOC11 FFFFF270H Timer 11...
Page 98 CHAPTER 3 CPU FUNCTION (7/8) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits FFFFF2F2H Capture/compare register 150 CC150 Undefined FFFFF2F4H Capture/compare register 151 CC151 FFFFF2F6H Capture/compare register 152 CC152 FFFFF2F8H Capture/compare register 153 CC153 FFFFF342H Timer control register 40...
Page 99 CHAPTER 3 CPU FUNCTION (8/8) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 bit 8 bits 16 bits FFFFF596H Port/control select register 11 PCS11 FFFFF5D0H DMA disable status register DDIS FFFFF5D2H DMA restart register DRST FFFFF5E0H DMA trigger factor register 0 DTFR0 FFFFF5E2H...
Page 100: Specific Registers
CHAPTER 3 CPU FUNCTION 3.4.9 Specific registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, the system status register (SYS) is notified.
Page 101 CHAPTER 3 CPU FUNCTION [Example of Description] ST reg_code, PRCMD ; PRCMD write (reg_code: Registration code) ST data, PSC ; Setting of the PSC register ; Dummy instruction (1 instruction) (next instruction) ; Execution routine after releasing the software STOP/IDLE mode The case where bit operation instructions are used in the PSC register settings is the same.
Page 102 CHAPTER 3 CPU FUNCTION (2) System status register (SYS) This register is assigned status flags showing the operating state of the entire system. This register can be read/written in 8- or 1-bit units. Address After reset PRERR UNLOCK FFFFF078H 0000000×B Bit Position Bit Name Function...
Page 103: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V850E/MS1 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 4.1 Features • 16-bit/8-bit data bus sizing function • 8-space chip select output function •...
Page 104: Memory Block Function
CHAPTER 4 BUS CONTROL FUNCTION 4.3 Memory Block Function The 64 MB memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for each individual memory block. 3FFFFFFH 3FFFFFFH Block 7...
Page 105: Bus Cycle Type Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.4 Bus Cycle Type Control Function In the V850E/MS1, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O • Page ROM • DRAM Connected external devices are specified by the bus cycle type configuration register (BCT). 4.4.1 Bus cycle type configuration register (BCT) This register can be read /written in 16-bit units.
Page 106 CHAPTER 4 BUS CONTROL FUNCTION The chip select signal (CS0/RAS0 to CS7/RAS7) is output as follows in correspondence with blocks 0 to 7. External Device SRAM, External ROM, External I/O DRAM Memory Block Page ROM Note 1 Block 0 RAS0 Block 1 RAS1 Block 2...
Page 107: Bus Access
CHAPTER 4 BUS CONTROL FUNCTION 4.5 Bus Access 4.5.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows. Bus Cycle Configuration Instruction Fetch Operand Data Access Normal Burst Access Normal Burst Resource (Bus Width) Access Access Access...
Page 108: Bus Sizing Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 Bus sizing function The V850E/MS1 is provided with a bus sizing function that is used to control the data bus width of each memory block. The data bus width is specified by using the bus size configuration register (BSC). (1) Bus size configuration register (BSC) This register can be read/written in 16-bit units.
Page 109: Bus Width
CHAPTER 4 BUS CONTROL FUNCTION 4.5.3 Bus width V850E/MS1 carries out peripheral I/O access and external memory access in 8, 16, or 32 bits. The following shows the operation for each access. All data is accessed in order from the lower side. (1) Byte access (8 bits) (a) When the data bus width is 16 bits <1>...
Page 110 CHAPTER 4 BUS CONTROL FUNCTION (2) Halfword access (16 bits) In halfword access to external memory, data is exchanged as is, or accessed in the order of lower byte, then higher byte. (a) When the data bus width is 16 bits <1>...
Page 111 CHAPTER 4 BUS CONTROL FUNCTION (a) When the data bus width is 16 bits <1> Access to address 4n First Second Address Address 4n + 1 4n + 3 4n + 2 Word External Word External data data bus data data bus <2>...
Page 112 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits <1> Access to address 4n First Second Third Fourth Address Address Address Address 4n + 1 4n + 2 4n + 3 Word External Word External Word External Word...
Page 113: Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6 Wait Function 4.6.1 Programmable wait function With the aim of realizing easy interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states with respect to the starting bus cycle for each memory block. The number of wait states can be set by data wait control registers 1 and 2 (DWC1, DWC2) and can be specified by program.
Page 114: External Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by the external wait pin (WAIT) to synchronize with the external device. Just as with programmable waits, access to internal ROM, internal RAM and internal peripheral I/O areas cannot be controlled by external waits.
Page 115: Bus Cycles In Which The Wait Function Is Valid
CHAPTER 4 BUS CONTROL FUNCTION 4.6.4 Bus cycles in which the wait function is valid In the V850E/MS1, the number of waits can be specified according to the type of memory specified for each memory block. The registers which set the bus cycles and waits in which the wait function is valid are as shown below. Table 4-1.
Page 116 CHAPTER 4 BUS CONTROL FUNCTION Table 4-1. Bus Cycles in Which the Wait Function Is Valid (2/2) Bus Cycle Type of Wait Programmable Wait Setting Wait by WAIT Pin Higher Order: Register Number Lower Order: Bit of Waits × CBR self-refresh cycle RAS pre-charge 0 to 3 RRW0, RRW1...
Page 117: Idle State Insertion Function
CHAPTER 4 BUS CONTROL FUNCTION 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the current bus cycle after the T2 state in order to meet the data output float delay time (t ) on memory read accesses for each memory block.
Page 118 CHAPTER 4 BUS CONTROL FUNCTION (2) Idle state insertion timing CLKOUT Address Address A0 to A23 BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR Data Data D0 to D15 WAIT Remarks 1. The circle indicates the sampling timing. 2. The broken lines indicate high impedance. 3.
Page 119: Bus Hold Function
CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Hold Function 4.8.1 Outline of function If pins P96 and P97 are specified in the control mode, the HLDAK and HLDRQ functions become valid. If it is determined that the HLDRQ pin has become active (low level) as a bus acquisition request from another bus master, the external address/data bus and each strobe pin are shifted to high impedance and released (bus hold state).
Page 120: Bus Hold Procedure
CHAPTER 4 BUS CONTROL FUNCTION 4.8.2 Bus hold procedure The procedure of the bus hold function is illustrated below. <1> HLDRQ = 0 accepted <2> All bus cycle start request pending Normal state <3> End of current bus cycle <4> Transition to bus idle state <5>...
Page 121: Bus Hold Timing
CHAPTER 4 BUS CONTROL FUNCTION 4.8.4 Bus hold timing CLKOUT HLDRQ Note Note HLDAK Column address Undefined A0 to A23 BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15 Data WAIT Note If HLDRQ signal is inactive (high level) at this sampling timing, bus hold state is not entered. Remarks 1.
Page 122: Bus Priority Order
CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority Order There are five external bus cycles: bus hold, instruction fetch, operand data access, DMA cycle and refresh cycle. Bus hold has the highest priority, then the refresh cycle, DMA cycle, instruction fetch and operand data access, in descending order.
Page 123: Data Space
CHAPTER 4 BUS CONTROL FUNCTION 4.10.2 Data space The V850E/MS1 incorporates an address misalign function. Through this function, regardless of the data format (word data, halfword data), data can be placed in all addresses. However, in the case of word data and halfword data, if data is not subject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop.
Page 124 [MEMO] User’s Manual U12688EJ4V0UM00...
Page 125: Chapter 5 Memory Access Control Function
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1 SRAM, External ROM, External I/O Interface 5.1.1 SRAM connections An example of connection to SRAM is shown below. Figure 5-1. Example of Connection to SRAM A1 to A17 A0 to A16 D0 to D7 I/O1 to I/O8 D8 to D15 1 Mbit (128 K ×...
Page 126: Sram, External Rom, External I/O Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1.2 SRAM, external ROM, external I/O access Figure 5-2. SRAM, External ROM, External I/O Access Timing (1/4) (a) During read CLKOUT Address Address A0 to A23 BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15 Data Data WAIT...
Page 127 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (2/4) (b) During write CLKOUT Address Address A0 to A23 BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15 Data Data WAIT Remarks 1. The circle indicates the sampling timing. 2.
Page 128 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (3/4) (c) During DMA flyby transfer (SRAM → → → → External I/O) CLKOUT Address Address Address A0 to A23 BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR Data D0 to D15...
Page 129 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-2. SRAM, External ROM, External I/O Access Timing (4/4) (d) During DMA flyby transfer (External I/O → → → → SRAM) CLKOUT Address Address Address A0 to A23 BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15 Data...
Page 130: Page Rom Controller (Romc)
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2 Page ROM Controller (ROMC) The page ROM controller (ROMC) is for access to ROM (page ROM) with a page access function. Comparison of addresses with the immediately previous bus cycle is carried out and wait control for normal access (off-page) and page access (on-page) is executed.
Page 131 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-3. Example of Page ROM Connections (2/2) (b) In the case of 16 Mbit (2 M × × × × 8) page ROM A1 to A20 A0 to A19 D0 to D7 O0 to O7 WORD/BYTE D8 to D15 16 Mbit page-ROM (2 M ×...
Page 132: On-Page/Off
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2.3 On-page/off-page judgment Whether a page ROM cycle is on-page or off-page is judged by latching the address of the previous cycle and comparing it with the address of the current cycle. Using the page ROM configuration register (PRC), one of the addresses (A3 to A5) is set as the masking address (no comparison is made) according to the configuration of the connected page ROM and the number of continuously readable bits.
Page 133 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-4. On-Page/Off-Page Judgment for Page ROM Connection (2/2) (b) In the case of 16 Mbit (2 M × × × × 8) page ROM (8-word page access) Internal address latch PRC register setting Comparison V850E/MS1 address output...
Page 134: Page Rom Configuration Register (Prc)
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2.4 Page ROM configuration register (PRC) This specifies whether page ROM on-page access is enabled or disabled. Also, if on-page access is enabled, the masked addresses (no comparison is made) out of the addresses (A3 to A5) corresponding to the configuration of the connected page ROM and the number of bits that can be read continuously, as well as the number of waits corresponding to the internal system clock, are set.
Page 135: Page Rom Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.2.5 Page ROM access Figure 5-5. Page ROM Access Timing CLKOUT   Off-page address   A0 to A23   On-page address On-page address  BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15 Data Data WAIT...
Page 136: Dram Controller
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3 DRAM Controller 5.3.1 Features { Generates the RAS, LCAS and UCAS signals. { Can be connected directly to high-speed page DRAM and EDO DRAM. { Supports the RAS hold mode. { 4 types of DRAM can be assigned to 8 memory block spaces. { Can handle 2CAS type DRAM { Can be switched between row and column address multiplex widths.
Page 137: Dram Connections
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.2 DRAM connections Examples of connections to DRAM are shown below. Figure 5-6. Examples of Connections to DRAM (a) In the case of 16 Mbit (1 M × × × × 16) DRAM A1 to A10 A0 to A9 D0 to D15 I/O1 to I/O16...
Page 138: Address Multiplex Function
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.3 Address multiplex function Depending on the value of the DAW0n and DAW1n bits in DRAM configuration register n (DRCn), the row address, column address output in the DRAM cycle is multiplexed as shown in Figure 5-7 (n = 0 to 3). In Figure 5-7, a0 to a23 show the addresses output from the CPU and A0 to A23 show the V850E/MS1’s address pins.
Page 139: Dram Configuration Registers 0 To 3 (Drc0 To Drc3)
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.4 DRAM configuration registers 0 to 3 (DRC0 to DRC3) This sets the type of DRAM to be connected. These registers can be read/written in 16-bit units. Caution If the object of access is a DRAM area, the wait set in registers DWC1 and DWC2 becomes invalid. In this case, waits are controlled by registers DRC0 to DRC3.
Page 140 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Bit Position Bit Name Function 11, 10 RHC1n, Row Address Hold Wait Control RHC0n Specifies the number of wait states inserted as row address hold time. RHC1n RHC0n Number of Wait States Inserted 9, 8 DAC1n, Data Access Programmable Wait Control DAC0n...
Page 141 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Bit Position Bit Name Function 1, 0 DAW1n, DRAM Address Multiplex Width Control DAW0n This sets the address multiplex width (refer to 5.3.3 Address multiplex function). DAW1n DAW0n Address Multiplex Width 8 bits 9 bits 10 bits 11 bits Caution Write to the DRCn register after reset, and then do not change the set value.
Page 142: Dram Type Configuration Register (Dtc)
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.5 DRAM type configuration register (DTC) This controls the relationship between DRAM configuration register n (DRCn) and memory block m (n = 0 to 3, m = 0 to 7). These registers can be read/written in 16-bit units. Address After reset FFFFF220H...
Page 143: Dram Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.6 DRAM access Figure 5-8. High-Speed Page DRAM Access Timing (1/4) (a) Read timing 1 CLKOUT Column address Column address Column address A0 to A23 address BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15 Data Data Data...
Page 144 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-8. High-Speed Page DRAM Access Timing (2/4) (b) Read timing 2 TRPW TRHW TDAW TCPW TO1 TDAW TO2 TCPW TO1 TDAW TO2 CLKOUT A0 to A23 Row address Column address Column address Column address BCYST CSn/RASn UWR/UCAS...
Page 145 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-8. High-Speed Page DRAM Access Timing (3/4) (c) Write timing 1 CLKOUT Column address Column address Column address A0 to A23 address BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15 Data Data Data WAIT Remarks 1.
Page 146 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-8. High-Speed Page DRAM Access Timing (4/4) (d) Write timing 2 TRPW TRHW TDAW TCPW TO1 TDAW TO2 TCPW TO1 TDAW TO2 CLKOUT A0 to A23 Row address Column address Column address Column address BCYST CSn/RASn UWR/UCAS...
Page 147 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-9. EDO DRAM Access Timing (1/4) (a) Read timing 1 CLKOUT Column Column Column address A0 to A23 address address address BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR Data Data Data D0 to D15 WAIT Optional Remarks 1.
Page 148 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-9. EDO DRAM Access Timing (2/4) (b) Read timing 2 TRPW TRHW TDAW TCPW TDAW TCPW TDAW CLKOUT Row address A0 to A23 Column address Column address Column address BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15...
Page 149 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-9. EDO DRAM Access Timing (3/4) (c) Write timing 1 CLKOUT Column Column Column address A0 to A23 address address address BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15 Data Data Data WAIT Optional Remarks 1.
Page 150 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-9. EDO DRAM Access Timing (4/4) (d) Write timing 2 TRPW TRHW TDAW TCPW TDAW TCPW TDAW CLKOUT A0 to A23 Row address Column address Column address Column address BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15...
Page 151: Dram Access During Dma Flyby Transfer
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.7 DRAM access during DMA flyby transfer Figure 5-10. DRAM Access Timing During DMA Flyby Transfer (1/2) (a) In the case of DRAM → → → → External I/O CLKOUT A0 to A23 Column address Column address Column address address...
Page 152 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-10. DRAM Access Timing During DMA Flyby Transfer (2/2) (b) In the case of external I/O → → → → DRAM Note TCPW TCPW CLKOUT A0 to A23 Column address Column address Column address address BCYST CSn/RASn...
Page 153: Refresh Control Function
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.8 Refresh control function V850E/MS1 can create a CBR (CAS-before-RAS) refresh cycle. The refresh cycle is set with the refresh control register (RFC). When another bus master occupies the external bus, the DRAM controller cannot occupy the external bus. In this case, the DRAM controller sends a refresh request to the bus master by changing the REFRQ signal to active (low level).
Page 154 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Bit Position Bit Name Function 9, 8 RCCn1, Refresh Count Clock RCCn0 Specifies the refresh count clock (T RCCn1 RCCn0 Refresh Count Clock (T 32/ φ 128/ φ 256/ φ Setting prohibited 5 to 0 RIn5 to Refresh Interval RIn0...
Page 155 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Example An example of the DRAM refresh interval and an example of setting the interval factor are shown below. Table 5-2. Example of DRAM Refresh Interval DRAM Capacity (bits) Refresh Cycle (Cycles/ms) Refresh Interval (µs) 256 K 256/4 15.6...
Page 156 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (2) Refresh wait control register (RWC) This specifies insertion of wait states during the refresh cycle. The register can be read/written in 8- or 1-bit units. Address After reset RRW1 RRW0 RCW2 RCW1 RCW0 SRW2 SRW1 SRW0...
Page 157 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION (3) Refresh timing Figure 5-11. CBR Refresh Timing Note TRRW TRCW TRCW CLKOUT REFRQ A0 to A23 BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15 WAIT Optional Note A minimum of 1 clock cycle is inserted for the TRCW cycle regardless of the RCW0 to RCW2 bit settings in the RWC register.
Page 158: Self-Refresh Functions
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.3.9 Self-refresh functions In the case of IDLE mode and software STOP mode, the DRAM controller generates a CBR self-refresh cycle. However, the RASn pulse width of DRAM should meet the specifications to enter a self-refresh operation mode (n = 0 to 7).
Page 159 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-12. CBR Self-Refresh Timing (1/2) (a) In the case of release according to the NMI input (in the IDLE Mode) TRRW TRCW TSRW TSRW CLKOUT REFRQ A0 to A23 BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR D0 to D15...
Page 160 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-12. CBR Self-Refresh Timing (2/2) (b) In the case of release according to the NMI input (in the software STOP Mode) TRRW TRCW TSRW TSRW CLKOUT REFRQ A0 to A23 BCYST CSn/RASn UWR/UCAS LWR/LCAS IORD IOWR...
Page 161: Chapter 6 Dma Functions (Dma Controller)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The V850E/MS1 includes a DMA (Direct Memory Access) controller (DMAC), which executes and controls DMA transfer. The DMAC (DMA controller) transfers data between memory and I/O, or within memory, based on DMA requests issued by the internal peripheral I/O (serial interface and real-time pulse unit), DMARQ0 to DMARQ3 pins, or software triggers.
Page 162: Configuration
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.2 Configuration Internal Internal RAM peripheral I/O Internal bus Internal peripheral I/O bus DMA source address Data Address register (DSAnH/DSAnL) control control DMA destination address register (DDAnH/DDAnL) DMA byte count register Count (DBCn) control DMA addressing control register (DADCn) DMA channel control...
Page 163: Control Registers
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3 Control Registers 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAnH and DSAnL.
Page 164 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA source address registers 0L to 3L (DSA0L to DSA3L) These registers can be read/written in 16-bit units. Address After reset DSA0L FFFFF1A2H Undefined DSA1L FFFFF1AAH Undefined DSA2L FFFFF1B2H Undefined FFFFF1BAH Undefined DSA3L Bit Position Bit Name Function...
Page 165: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA destination addresses (26 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL. During DMA transfer, the registers store the next DMA destination addresses.
Page 166 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA destination address registers 0L to 3L (DDA0L to DDA3L) These registers can be read/written in 16-bit units. Address After reset DDA0L FFFFF1A6H Undefined DDA1L FFFFF1AEH Undefined DDA2L FFFFF1B6H Undefined DDA3L FFFFF1BEH Undefined Bit Position Bit Name Function...
Page 167: Dma Byte Count Registers 0 To 3 (Dbc0 To Dbc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the byte transfer counts for DMA channel n (n = 0 to 3). They store the remaining transfer counts during DMA transfer. These registers are decremented by 1 for byte transfer and by two for 16-bit transfer.
Page 168: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer operation modes for DMA channel n (n = 0 to 3). These registers can be read/written in 16-bit units. Caution During DMA transfer, do not perform writing to these registers.
Page 169 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Bit Position Bit Name Function 5, 4 DAD1, Destination Address count Direction DAD0 Sets the count direction of the destination address for DMA channel n. DAD1 DAD0 Count Direction Increment Decrement Fixed Setting prohibited 3, 2 TM1, TM0 Transfer Mode...
Page 170: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operation mode for DMA channel n (n = 0 to 3). These registers can be read/written in 8-bit units. (However, bit 7 is read-only and bits 2 and 1 are write-only. When the DMA channel control registers are read, bits 2 and 1 are always 0.) Address After reset...
Page 171: Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from peripheral I/O. The interrupt requests that are set with these registers start DMA transfer. These registers can be read/written in 8- or 1-bit units.
Page 172 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Bit Position Bit Name Function 5 to 0 IFCn5 to IFCn0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source INTP120/INTCC120 INTP121/INTCC121 INTP122/INTCC122 INTP123/INTCC123 INTP130/INTCC130 INTP131/INTCC131 INTP132/INTCC132 INTP133/INTCC133 INTP140/INTCC140 INTP141/INTCC141 INTP142/INTCC142 INTP143/INTCC143 INTP150/INTCC150 INTP151/INTCC151 INTP152/INTCC151 intp153/intcc153 INTAD Other than above...
Page 173: Dma Disable Status Register (Ddis)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.7 DMA disable status register (DDIS) This register holds the contents of the ENn bit of the DCHCn register during NMI input (n = 0 to 3). It is read-only, in 8- or 1-bit units. Address After reset DDIS...
Page 174: Flyby Transfer Data Wait Control Register (Fdw)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.9 Flyby transfer data wait control register (FDW) To prevent illegal writing during flyby transfer, this register sets the insertion of wait states (TF) for securing the time from when the write signal (IOWR, UWR, LWR, WE) becomes inactive until the read signal (RD, IORD, OE) becomes inactive.
Page 175: Dma Bus States
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4 DMA Bus States 6.4.1 Types of bus states The DMAC bus cycle consists of the following 25 states: (1) TI state The TI state is idle state, during which no access request is issued. The DMARQ0 to DMARQ3 signals are sampled at the falling edge of the CLKOUT signal.
Page 176 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (11) T2F state The T2F state corresponds to the middle state of a flyby transfer from internal peripheral I/O to internal RAM. The write cycle to internal RAM is started. After entering the T2F state, the bus invariably enters the T3F state.
Page 177 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (21) T1FH state The T1FH state corresponds to the standard state of a flyby transfer between external memory and external I/O, and is the executing cycle of this transfer. After entering the T1FH state, the bus enters the T2FH state. (22) T1FHI state The T1FHI state corresponds to the last state of a flyby transfer between external memory and external I/O, and is a state in which the bus is waiting for end of DMA flyby transfer.
Page 178: Dmac State Transition
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.2 DMAC state transition Except block transfer mode, each time the processing for a DMA service is completed, the bus is released (the bus enters bus release mode). Figure 6-1. DMAC Bus Cycle State Transition Diagram (a) Two-cycle transfer (b) Flyby transfer T1FR...
Page 179: Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.5 Transfer Mode 6.5.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 180: Single-Step Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.5.2 Single-step transfer mode In single-step transfer mode, DMAC releases the bus at each byte/halfword transfer. Once a request signal (DMARQ0 to DMARQ3) is received, this operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 181: Transfer Types
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6 Transfer Types 6.6.1 Two-cycle transfer In two-cycle transfer, data transfer is performed in two-cycles, source to DMAC then DMAC to destination. In the first cycle, the source address is output to perform reading from the source to DMAC. In the second cycle, the destination address is output to perform writing from DMAC to the destination.
Page 182 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-7. Timing of Two-Cycle Transfer (2/4) (b) Single-step transfer mode (External I/O → → → → SRAM) BCU states DMAC states T2W TE T2W TE CLKOUT DMARQn Internal DMA request signal DMAAKn A0 to A23 Address Address Address...
Page 183 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-7. Timing of Two-Cycle Transfer (3/4) (c) Single transfer mode (Internal peripheral I/O → → → → DRAM) CPU states T1R T2R T2R DMAC states CLKOUT DMARQn Internal DMA request signal DMAAKn Column address A0 to A23 address D0 to D15...
Page 184 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-7. Timing of Two-Cycle Transfer (4/4) (d) Single transfer mode (DRAM → → → → Internal peripheral I/O) CPU states T2RI DMAC states CLKOUT DMARQn Internal DMA request signal DMAAKn Column address A0 to A23 address Data D0 to D15...
Page 185: Flyby Transfer
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6.2 Flyby transfer The V850E/MS1 supports flyby transfer between external memory and external I/O, and internal RAM and internal peripheral I/O. (1) Flyby transfer between external memory and external I/O This data transfer between memory and I/O is performed in one cycle. To achieve single-cycle transfer, the memory address is always output irrespective of whether it is that of the source or the destination, and the read/write strobe signals for the memory and I/O are made active at the same time.
Page 186 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-8. Timing of Flyby Transfer (DRAM → → → → External I/O) (2/3) (b) Single transfer mode CPU states DMAC states T1FH T1FHI T1FHI T1FH T1FHI T1FHI CLKOUT DMARQn Internal DMA request signal DMAAKn A0 to A23 Column address...
Page 187 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-8. Timing of Flyby Transfer (DRAM → → → → External I/O) (3/3) (c) Single-step transfer mode CPU states T1FH T1FHI T1FHI T1FH T1FHI T1FHI DMAC states CLKOUT DMARQn Internal DMA request signal DMAAKn A0 to A23 Column address...
Page 188 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) Flyby transfer between internal RAM and internal peripheral I/O Internal RAM and internal peripheral I/O are mapped on different address spaces. Therefore, different addresses are always output, and the read/write strobe signals for internal RAM and internal peripheral I/O are controlled at the same time.
Page 189: Transfer Objects
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.7 Transfer Objects 6.7.1 Transfer type and transfer objects Table 6-1 lists the relationship between transfer type and transfer object. Cautions 1. Among the transfer destinations and sources shown in Table 6-1, when an “× × × × ” is indicated for a combination, that operation is not guaranteed.
Page 190: Dma Channel Priorities
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.8 DMA Channel Priorities The DMA channel priorities are fixed, as follows: DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 These priorities are valid in the TI state only. In block transfer mode, the channel used for transfer is never switched.
Page 191: Dma Transfer Start Factors
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.10 DMA Transfer Start Factors There are 3 types of DMA transfer start factors, as shown below. (1) Request from an external pin (DMARQn) Although requests from the DMARQn pin are sampled each time the CLKOUT signal falls, sampling should be continued until the DMAAKn signal becomes active (n = 0 to 3).
Page 192: Interrupting Dma Transfer
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.11 Interrupting DMA Transfer 6.11.1 Interruption factors DMA transfer is interrupted if the following factors occur. • Bus hold • Refresh cycle If the factor that is interrupting DMA transfer disappears, DMA transfer promptly restarts. 6.11.2 Forcible interruption DMA transfer can be forcibly interrupted by an NMI input during DMA transfer.
Page 193: Forcible Termination
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12.3 Forcible termination In addition to forcible interruption of DMA transfer by NMI input, DMA transfer can also be terminated forcibly by the INITn bit of the DCHCn register. Examples of the forcible termination operation are shown below (n = 0 to 3). Figure 6-11.
Page 194: Boundary Of Memory Area
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.13 Boundary of Memory Area The transfer operation is not guaranteed if the source or the destination address is over the area of DMA objects (external memory, internal RAM, external I/O, or internal peripheral I/O) during DMA transfer. 6.14 Transfer of Misalign Data 16-bit DMA transfer of misalign data is not supported.
Page 195 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) Condition 2 Condition Word data access with external memory at the 8-bit data bus width Tdata × 4 + Tref Response time DMARQn (input) DMAAKn (output) D0 to D15 (input/output) Data (1/4) Data (2/4) Data (3/4) Data (4/4) Refresh DMA cycle (3) Condition 3...
Page 196: One Time Single Transfer With Dmarq0 To Dmarq3
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.17 One Time Single Transfer with DMARQ0 to DMARQ3 To execute one time single transfer to external memory via DMARQn signal input, DMARQn should be inactive within the clock time shown in Table 6-4 from when DMAAKn becomes active (n = 0 to 3). If DMARQn is active for more than the clock time shown in Table 6-4, single transfers are continuously executed.
Page 197: Bus Arbitration For Cpu
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Also, if a single transfer is executed between internal RAM and internal peripheral I/O, it is necessary that the DMARQn signal be inactivated within 8 clock cycles after it is activated. If 8 clock cycles are exceeded, transfer may continue.
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Page 199: Chapter 7 Interrupt/Exception Processing Function
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850E/MS1 is provided with a dedicated interrupt controller (INTC) for interrupt processing and can process a total of 48 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event that is dependent on program execution.
Page 200 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt List (1/3) Type Classification Interrupt/Exception Source Default Exception Handler Restored PC Priority Code Address Name Controlling Source Generating Register Unit Reset Interrupt RESET — RESET input — 0000H 00000000H Undefined Non-maskable Interrupt —...
Page 201 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt List (2/3) Type Classification Interrupt/Exception Source Default Exception Handler Restored Priority Code Address Name Controlling Source Generating Register Unit Maskable Interrupt INTP132/ P13IC2 Match of INTP132 Pin/RPU 01E0H 000001E0H nextPC INTCC132 pin/CC132 Interrupt INTP133/ P13IC3...
Page 202 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt List (3/3) Type Classification Interrupt/Exception Source Default Exception Handler Restored Priority Code Address Name Controlling Source Generating Register Unit Maskable Interrupt INTCSI1 CSIC1 CSI1 transmission/ 0340H 00000340H nextPC reception completion Interrupt INTSER1 SEIC1 UART1 reception 0350H...
Page 203 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-1. Block Diagram of Interrupt Control Function Internal bus ISPR register xxlCn register xxMKn (interrupt mask flag) Handler INTOV10 OVIF10 address INTOV11 OVIF11 INTOV12 generator OVIF12 INTOV13 OVIF13 INTOV14 OVIF14 INTOV15 OVIF15 INTP100/INTCC100 P10IF0 INTP101/INTCC101 P10IF1 INTP102/INTCC102...
Page 204: Non-Maskable Interrupt
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupt A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all other interrupts. A non-maskable interrupt request is input from the NMI pin.
Page 205: Operation
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes the exception code (0010H) to the higher halfword (FECC) of ECR.
Page 206 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-3. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service program is being executed: Main routine (PSW. NP=1) NMI request NMI request NMI request held pending because PSW. NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service program is being executed: Main routine...
Page 207: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.2 Restore Execution is restored from the non-maskable interrupt processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and PSW from FEPC and FEPSW, respectively, because the EP bit of PSW is 0 and the NP bit of PSW is 1.
Page 208: Non-Maskable Interrupt Status Flag (Np)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is bit 7 of the PSW. The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when the NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 209: Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850E/MS1 has 47 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 210 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-5. Maskable Interrupt Processing INT input INTC acknowledgement xxIF=1 Interrupt request? xxMK=0 Is the interrupt mask released? Priority higher than that of interrupt currently being processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority?
Page 211: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.2 Restore To restore from the maskable interrupt processing, the RETI instruction is used. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the values of the PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 212: Priorities Of Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850E/MS1 provides multiple interrupt servicing whereby an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels which are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 213 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Processing in Which Another Interrupt Request Is Issued While Interrupt Is Being Processed (1/2) Main routine Processing of a Processing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority ofb is higher than that of a and interrupts are enabled.
Page 214 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Processing in Which Another Interrupt Request Is Issued While Interrupt Is Being Processed (2/2) Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i.
Page 215 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-8. Example of Processing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Processing of interrupt request b • Interrupt requests b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 216: Interrupt Control Register (Xxicn)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8- or 1-bit units. Address After reset xxICn...
Page 217 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Interrupt Control Register Addresses and Bits (2/2) Address Register FFFFF106H OVIC13 OVIF13 OVMK13 OVPR132 OVPR131 OVPR130 FFFFF108H OVIC14 OVIF14 OVMK14 OVPR142 OVPR141 OVPR140 FFFFF10AH OVIC15 OVIF15 OVMK15 OVPR152 OVPR151 OVPR150 FFFFF10CH CMIC40 CMIF40 CMMK40 CMPR402 CMPR401...
Page 218: In-Service Priority Register (Ispr)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set (1) and remains set while the interrupt is serviced.
Page 219: Noise Elimination
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.7 Noise elimination Digital noise elimination circuits are added to each of the INTPn0 to INTPn3, TIn, TCLRn and ADTRG pins (n = 10 to 15). Using these circuits, these pins’ input level is sampled each sampling clock cycle (f ).
Page 220: Edge Detection Function
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.8 Edge detection function The valid edge of pins INTPn0 to INTPn3 and ADTRG can be selected by program. The valid edge that can be selected is one of the following (n = 10 to 15). •...
Page 221 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The valid edge can be specified independently for each pin, as the rising edge, the falling edge or both the rising and falling edges. These registers can be read/written in 8- or 1-bit units. Address After reset INTM1 ES031...
Page 222: Software Exception
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to EIPC.
Page 223: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.2 Restore To restore from the software exception processing, the RETI instruction is used. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. (1) Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of PSW is 1. (2) Transfers control to the address of the restored PC and PSW.
Page 224: Exception Status Flag (Ep)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.3 Exception status flag (EP) The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset 00000020H Bit Position Bit Name Function Exception Pending Shows that exception processing is in progress.
Page 225: Exception Trap
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5 Exception Trap The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V850E/MS1, an illegal op code exception (ILGOP: ILleGal Opcode trap) is considered an exception trap. An illegal op code exception is generated in the case where the sub op code of the following instruction is an illegal op code when execution of that instruction is attempted.
Page 226: Operation
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.2 Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to DBPC. (2) Saves the current PSW to DBPC. (3) Sets the NP, EP and ID bits of PSW. (4) Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control.
Page 227: Multiple Interrupt Processing Control
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.6 Multiple Interrupt Processing Control Multiple interrupt processing control is a process by which the interrupt request currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is acknowledged and processed first.
Page 228 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) To generate an exception in a service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • TRAP instruction ← Exception such as TRAP instruction acknowledged. •...
Page 229: Interrupt Latency Time
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.7 Interrupt Latency Time The following table describes the V850E/MS1 interrupt latency time (from interrupt generation to start of interrupt processing). Figure 7-13. Pipeline Operation at Interrupt Request Acknowledgement (Outline) 2 system 4 system clocks clocks CLKOUT Interrupt request...
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Page 231: Chapter 8 Clock Generator Functions
CHAPTER 8 CLOCK GENERATOR FUNCTIONS The clock generator (CG) generates and controls the internal system clock ( φ ) which is supplied to each internal unit, of which the CPU is the primary unit. 8.1 Features { Multiplier function using a PLL (phase locked loop) synthesizer { Clock Source = φ...
Page 232: Input Clock Selection
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.3 Input Clock Selection The clock generator is configured from an oscillator and a PLL synthesizer. If, for example an 8 MHz crystal resonator or ceramic resonator is connected to pins X1 and X2, an internal system clock ( φ ) of 40 MHz can be generated.
Page 233: Clock Control Register (Ckc)
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.3.3 Clock control register (CKC) When in the PLL mode, this is an 8-bit register which controls the internal system clock frequency ( φ ), and it can be written to only by a specific combination of instruction sequences so that it cannot be rewritten easily by mistake due to program runaway.
Page 234: Pll Lockup
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.4 PLL Lockup Lockup time (frequency stabilization time) is the amount of time from immediately after the software STOP mode is released after the power is turned on, until the phase locks at the proper frequency and becomes stable. The state until this stabilization occurs is called the unlocked state and the stabilized state is called the locked state.
Page 235: Power Saving Control
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.5 Power Saving Control 8.5.1 Outline The V850E/MS1 standby function comprises the following three modes: (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU’s operation clock stops. Supply of the clock to the other internal peripheral functions is continued. Through intermittent operation by combining with the normal operating mode, the system’s total power consumption can be reduced.
Page 236 CHAPTER 8 CLOCK GENERATOR FUNCTIONS Table 8-1. Clock Generator Operation by Power Save Control Clock Source Power Save Mode Oscillator Supply of Supply of (OSC) Synthesizer Clock to Clock to the Internal Peripheral I/O PLL mode Oscillation by (During normal operation) resonator ×...
Page 237: Control Registers
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.5.2 Control registers (1) Power save control register (PSC) This is an 8-bit register that controls the power save mode. This is one of the specific registers and is active only when accessed by a specific sequence during a write operation.
Page 238: Halt Mode
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.5.3 HALT mode (1) Setting and operating state In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU’s operation clock stops. Supply of the clock to other internal peripheral I/O functions is continued and their operation continues.
Page 239 CHAPTER 8 CLOCK GENERATOR FUNCTIONS (2) Releasing HALT mode The HALT mode can be released by NMI pin input, an unmasked maskable interrupt request, or a RESET signal input. (a) Release by NMI pin input, maskable interrupt request The HALT mode is unconditionally released by NMI pin input or an unmasked maskable interrupt request regardless of the priority.
Page 240: Idle Mode
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.5.4 IDLE mode (1) Settings and operating state In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but supply of the internal system clock is stopped, which causes the system overall to stop. When releasing the system from the IDLE mode, it is not necessary to secure the oscillation stabilization time of the oscillator, so it is possible to switch to normal operation at high speed.
Page 241 CHAPTER 8 CLOCK GENERATOR FUNCTIONS (2) Releasing IDLE mode The IDLE Mode is released by NMI pin input or RESET pin input. (a) Release by NMI pin input This is acknowledged as a NMI request together with a release of the IDLE mode. However, in cases where setting the system in the IDLE mode is included in the NMI processing routine, the IDLE mode is released only, and this interrupt is not acknowledged.
Page 242: Software Stop Mode
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.5.5 Software STOP mode (1) Settings and operating state In this mode, the clock generator (oscillator and PLL synthesizer) is stopped. The system overall is stopped, and it enters an ultra-low power consumption state where only device leakage current is lost. It is possible to enter the software STOP mode by setting the PSC register (specific register) using a store instruction (ST/SST instruction) or a bit manipulation instruction (SET1/CLR1/NOT1 instruction) in software (refer to 3.4.9 Specific registers).
Page 243: Clock Output Inhibit Mode
CHAPTER 8 CLOCK GENERATOR FUNCTIONS (2) Releasing software STOP mode The software STOP mode is released by NMI pin input or RESET pin input. Also, when releasing the software STOP mode in the PLL mode and the oscillator connection mode (CESEL bit of the PSC register = 0), it is necessary to secure oscillation stabilization time for the oscillator.
Page 244: Securing Oscillation Stabilization Time
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.6 Securing Oscillation Stabilization Time 8.6.1 Specifying securing of oscillation stabilization time There are 2 methods for specifying securing of time for stabilizing the oscillator in the stop mode after releasing the software STOP mode. (1) If securing time by the internal time base counter (NMI pin input) If the active edge of the NMI pin is input, the software STOP mode is released.
Page 245 CHAPTER 8 CLOCK GENERATOR FUNCTIONS (2) If securing time by the signal level width (RESET pin input) By inputting the falling edge to the RESET pin, the software STOP mode is released. At the signal low level width input to the pin, enough time is secured until the clock output from the oscillator stabilizes.
Page 246: Time Base Counter (Tbc)
CHAPTER 8 CLOCK GENERATOR FUNCTIONS 8.6.2 Time base counter (TBC) The time base counter (TBC) is used to secure the oscillation stabilization time of the oscillator when the software STOP mode is released. • • • • Resonator connection time (PLL Mode, and CESEL bit of the PSC Register = 0) After releasing the software STOP mode, the oscillation stabilization time is counted by the TBC and after counting is ended, program execution begins.
Page 247: Chapter 9 Timer/Counter Function (Real-Time Pulse Unit)
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.1 Features { Measures the pulse interval and frequency and outputs a programmable pulse. • 16-bit measurements are possible. • Pulse multiple states can be generated (interval pulse, one shot pulse) { Timer 1 •...
Page 248: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.2 Basic Configuration The basic configuration is shown below. Table 9-1. RPU Configuration List Timer Count Clock Register Read/Write Interrupt Signals Capture Timer Other Functions Generated Trigger Output S/R φ /2   Timer 1 TM10 Read...
Page 249: Timer 1
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1) Timer 1 (16-bit timer/event counter) Internal system clock φ TM10 TCLR10 Edge detection ETI10 Clear & count PRS100, control PRS101 Clear & Note 2 TI10 Edge detection start φ OVF10 INTOV10 TM10 (16-bit) Note ALV101 ALV100...
Page 250: Timer 4
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Timer 4 (16-bit interval timer) Internal system clock φ TM40 PRM400, PRM401 PRS400 1/16 Internal count φ clock TM40 (16-bit) Clear & 1/32 start INTCM40 CM40 TM41 INTCM41 User’s Manual U12688EJ4V0UM00...
Page 251 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.2.1 Timer 1 (1) Timers 10 to 15 (TM10 to TM15) TM1n functions as a 16-bit free running timer or as an event counter for an external signal. Mainly, besides period measurement and frequency measurement, it can be used as a pulse output (n = 0 to 5). TM1n is read-only, in 16-bit units.
Page 252 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Capture/compare registers 1n0 to 1n3 (CC1n0 to CC1n3) (n = 0 to 5) The capture/compare registers are 16-bit registers to which TM1n is connected. They can be used as either a capture register or a compare register in accordance with the specification in timer unit mode register 1n (TUM1n).
Page 253 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.2.2 Timer 4 (1) Timers 40, 41 (TM40, TM41) TM4n is a 16-bit timer. It can mainly be used as an interval timer for software (n = 0, 1). TM4n is read-only in 16-bit units. Address After reset TM40...
Page 254: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.3 Control Registers (1) Timer unit mode registers 10 to 15 (TUM10 to TUM15) The TUM1n register is a register which controls the operation of timer 1 and specifies the capture/compare register operation mode (n = 0 to 5). These registers can be read/written in 16-bit units.
Page 255 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Bit Position Bit Name Function 11, 10 TES1n1, TI1n Edge Select TES1n0 Specifies the active edge of the external clock input (TI1n). TES1n1 TES1n0 Active Edge Falling edge Rising edge RFU (reserved) Both the rising and falling edges 9, 8 CES1n1, TCLR1n Edge Select...
Page 256 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Remarks 1. If the A/D converter is set in the timer trigger mode, the compare register’s match interrupt becomes the A/D conversion start trigger, starting the conversion operation. When this happens, the compare register’s match interrupt functions as a compare register match interrupt to the CPU. In order for a compare register match interrupt not to be issued to the CPU, disable interrupts with the interrupt mask bits (P11MK0 to P11MK3) of the interrupt control register (P11IC0 to P11IC3).
Page 257 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Timer control registers 10 to 15 (TMC10 to TMC15) TMC10 to 15 control the respective operations of TM10 to TM15. These registers can be read/written in 8- or 1-bit units. Address After reset TMC10 CE10 ETI10...
Page 258 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Bit Position Bit Name Function 3, 2 PRS1n1, Prescaler Clock Select Selects the internal count clock ( φ m is the intermediate clock). PRS1n0 PRS1n1 PRS1n0 Internal Count Clock φ m φ m/4 φ...
Page 259 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Timer control registers 40, 41 (TMC40, TMC41) TMC40 and TMC41 control the operation of TM40 and TM41, respectively. These registers can be read/written in 8- or 1-bit units. Address After reset TMC40 CE40 PRS400 PRM401...
Page 260 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Timer output control registers 10 to 15 (TOC10 to TOC15) The TOC1n register controls the timer output from the TO1n0 and TO1n1 pins (n = 0 to 5). These registers can be read/written in 8- or 1-bit units. Address After reset TOC10...
Page 261 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) External interrupt mode registers 1 to 6 (INTM1 to INTM6) If CC1n0 to CC1n3 of TM1n are used as a capture register, the active edge of the external interrupt INTP1n0 INTP1n3 signals detected capture trigger...
Page 262: Timer 1 Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4 Timer 1 Operation 9.4.1 Count operation Timer 1 functions as a 16-bit free-running timer or an event counter for an external signal. Whether the timer operates as a free-running timer or event counter is specified by timer control register 1n (TMC1n) (n = 0 to 5).
Page 263: Count Clock Selection
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4.2 Count clock selection The count clock input to Timer 1 is either internal or external, and can be selected by the ETI1n bit in the TMC1n register (n = 0 to 5). Caution Do not change the count clock during timer operation.
Page 264: Overflow
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4.3 Overflow When the TM1n register counts the count clock to FFFFH and overflow occurs as a result, a flag is set in the OVF1n bit of the TOVS register and an overflow interrupt (INTOV1n) is generated (n = 0 to 5). Also, by setting the OSTn bit (1) in the TUM1n register, the timer can be stopped after overflow.
Page 265: Clearing/Starting Timer By Tclr1N Signal Input
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4.4 Clearing/starting timer by TCLR1n signal input Timer 1 ordinarily starts a counting operation when the CE1n bit in the TMC1n register is set (1), but TM1n can be cleared and a count operation started by input of the TCLR1n signal (n = 0 to 5). If the ECLR1n bit of the TUM1n register is set to 1, and the OSTn bit is set to 0, if the active edge is input to the TCLR1n signal after the CE1n bit is set (1), the counting operation starts.
Page 266: Capture Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-4. Relationship Between Clear/Start by TCLR1n Signal Input and Overflow Operation (If ECLR1n = 1 and OSTn = 1) Overflow FFFFH Count start TM1n CE1n TCLR1n TCLR1n TCLR1n INTOV1n Remark n = 0 to 5 9.4.5 Capture operation In synch with an external trigger, a capture operation is performed in which the TM1n count value is captured and held in the capture register asynchronous to the count clock (n = 0 to 5).
Page 267 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) The capture trigger’s active edge is set by the external interrupt mode register (INTM1 to INTM6). If both the rising and falling edges are made capture triggers, the input pulse width from an external source can be measured. Also, if the edge from one side is used as the capture trigger, the input pulse’s period can be measured.
Page 268 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-6. Example of TM11 Capture Operation (When Both Edges Are Specified) FFFFH TM11 count value ∆ ∆ CE11←1 OVF11←1 (count start) (overflow) Interrupt request (INTP110) Capture register (CC110) Remark D0 to D2: TM11 count value User’s Manual U12688EJ4V0UM00...
Page 269: Compare Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.4.6 Compare operation Compare operations in which the value set in the compare register is compared with the TM1n count value are performed (n = 0 to 5). If the TM1n count value matches the value that has been previously set in the compare register, a match signal is sent to the output control circuit (refer to Figure 9-7).
Page 270 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Timer 1 has 12 timer output pins (TO1n0, TO1n1). The TM1n count value and the CC1n0 value are compared and if they match, the output level of the TO1n0 pin is set. Also, the TM1n count value and the CC1n1 value are compared, and if they match, the TO1n0 pin’s output level is reset.
Page 271: Timer 4 Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.5 Timer 4 Operation 9.5.1 Count operation Timer 4 functions as a 16-bit interval timer. Setting of its operation is specified in timer control register 4n (TMC4n) (n = 0, 1). In a timer 4 count operation, the internal count clock ( φ /32 to φ /256) specified by the PRS4n0, PRM4n1, and PRM4n0 bits of the TMC4n register is counted up.
Page 272: Compare Operation
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.5.4 Compare operation In Timer 4, a compare operation which compares the value set in the compare register (CM4n) with the TM4n count value is performed (n = 0, 1). If values are found to match in the compare operation, an interrupt (INTCM4n) is issued. By issuing an interrupt, TM4n is cleared (0) with the following timing (refer to Figure 9-10 (a)).
Page 273 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-10. Example of TM40 Compare Operation (2/2) (b) If 0 is set in CM40 Count clock Count up TM40 clear Clear TM40 FFFFH CM40 Match detected (INTCM40) Overflow Remark Interval time = (FFFFH + 1) × count clock cycle User’s Manual U12688EJ4V0UM00...
Page 274: Application Example
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.6 Application Example (1) Operation as an interval timer (Timer 4) In this example, timer 4 is used as an interval timer that repeatedly issues an interrupt at intervals specified by the count time preset in the compare register (CM4n) (n = 0, 1). Figure 9-11.
Page 275 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Operation for pulse width measurement (Timer 1) In measuring the pulse width, timer 1 is used. Here, an example is given of measurement of high level or low level width of an external pulse input to the INTP112 pin.
Page 276 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-14. Example of Pulse Width Measurement Setting Procedure Initial pulse width measurement setting Setting the TMC11 register Specifies the count clock Setting the INTM2 register Specifies both edges of the INTP112 INTM2.ES121 ← 1 input signal as active edges INTM2.ES120 ←...
Page 277 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Operation as a PWM output (Timer 1) Through a combination of timer 1 and the timer output function, the desired rectangular wave can be output to the timer output pins (TO1n0, TO1n1) and used as a PWM output (n = 0 to 5). Here an example is shown using the capture/compare registers CC100 and CC101.
Page 278 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-17. Example of PWM Output Setting Procedure PWM output initial setting Setting the TOC10 register Specifies the active level (high level) TOC10.ENTO100 ← 1 and enables timer output TOC10.ALV100 ← 1 Setting the TUM10 register TUM10.CMS100 ←...
Page 279 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Operation for frequency measurement (Timer 1) Timer 1 can measure the frequency of an external pulse’s input to pins INTP1n0 to INTP1n3 (n = 0 to 5). Here, an example is shown where timer 1 and the capture/compare register CC110 are combined to measure the frequency of an external pulse input to the INTP110 pin with 16-bit precision.
Page 280 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 9-20. Example of Frequency Measurement Setting Procedure Cycle measurement initial setting Setting the TMC11 register Specifies the count clock. Setting the TUM11 register Specifies operation of the CC110 register as the capture register. TUM11.CMS110 ←...
Page 281: Precaution
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 9.7 Precaution Match detection by the compare register is always performed immediately after timer count up. In the following cases, a match does not occur. (1) When rewriting the compare register (TM10 to TM15, TM40, TM41) Count clock Timer value n Ð...
Page 282 CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) When the timer is cleared (TM40, TM41) Count clock Timer value FFFEH FFFFH Internal matching clear Compare register value 0000H Match detection Match does not occur Remark When operating timer 1 as the free-running timer, the timer’s value becomes 0 when timer overflow occurs.
Page 283: Chapter 10 Serial Interface Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Features Two types of serial interfaces with 6 transmit/receive channels are provided as the serial interface function, and up to 4 channels can be used simultaneously. The following two types of interface configuration are provided. (1) Asynchronous serial interface (UART0, UART1): 2 channels (2) Clocked serial interface (CSI0 to CSI3):...
Page 284: Asynchronous Serial Interfaces 0, 1 (Uart0, Uart1)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2 Asynchronous Serial Interfaces 0, 1 (UART0, UART1) 10.2.1 Features { Transfer rate 150 bps to 76,800 bps (using the exclusive baud rate generator when the internal system clock is 33 MHz) Maximum 4.125 Mbps (using the φ /2 clock when the internal system clock is 33 MHz) { Full duplex communication On-chip receive buffer (RXBn) { 2-pin configuration TXDn: Transmit data output pin RXDn: Receive data input pin...
Page 285: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 Configuration UARTn is controlled by the asynchronous serial interface mode registers (ASIMn0, ASIMn1) and the asynchronous serial interface status registers (ASISn) (n = 0, 1). Receive data is held in the receive buffer (RXBn) and transmit data is written in the transmit shift registers (TXSn).
Page 286 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Transmit shift register (TXS0, TXS0L, TXS1, TXS1L) TXSn are 9-bit shift registers for transmit processing. Writing of data to these registers starts a transmit operation. A transmission complete interrupt request (INTSTn) is generated in synchronization with termination of transmission of 1 frame, which includes TXSn data.
Page 287: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Control registers (1) Asynchronous serial interface mode registers 00, 01, 10, 11 (ASIM00, ASIM01, ASIM10, ASIM11) These registers specify the UART0 and UART1 transfer mode. These registers can be read/written in 8- or 1-bit units. Address After reset ASIM00...
Page 288 CHAPTER 10 SERIAL INTERFACE FUNCTION Bit Position Bit Name Function 5, 4 PSn1, PSn0 Parity Select Specifies the parity bit length. PSn1 PSn0 Operation No parity, expansion bit operation Specifies 0 parity Transmission side → Transmits with parity bit at 0. Reception side →...
Page 289 CHAPTER 10 SERIAL INTERFACE FUNCTION Bit Position Bit Name Function Stop Bit Length Specifies the stop bit length. 0: 1 bit 1: 2 bits 1, 0 SCLSn1, Serial Clock Source SCLSn0 Specifies the serial clock. SCLSn1 SCLSn0 Serial Clock Baud rate generator output φ...
Page 290 CHAPTER 10 SERIAL INTERFACE FUNCTION Address After reset ASIM01 EBS0 FFFFF0C2H ASIM11 EBS1 FFFFF0D2H Bit Position Bit Name Function EBSn Extended Bit Select Specifies transmit/receive data expansion bit operation when no parity operation is specified (PSn1, PSn0 = 00). 0: Expansion bit operation disabled. 1: Expansion bit operation enabled.
Page 291 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1) These registers are configured with 3-bit error flags (PEn, FEn, OVEn), which show the error status when UARTn reception is terminated, and a transmit status flag (SOTn) (n = 0,1). The status flag that shows a receive error always shows the state of the error that occurred most recently.
Page 292 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Receive buffers 0, 0L, 1, 1L (RXB0, RXB0L, RXB1, RXB1L) RXBn are 9-bit buffer registers that hold receive data, with a 0 stored in the higher bits when 7 or 8-bit character data is received (n = 0, 1). During 16-bit access of these registers, specify RXB0 and RXB1, and during lower 8-bit access, specify RXB0L and RXB1L.
Page 293 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Transmit shift registers 0, 0L, 1, 1L (TXS0, TXS0L, TXS1, TXS1L) TXSn are 9-bit shift registers for transmission processing and when transmission is enabled, transmission operations are started (n = 0, 1) by writing of data to these registers. When transmission is disabled, the values are disregarded even if writing is performed.
Page 294: Interrupt Request
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.4 Interrupt request UARTn generates the following three types of interrupt requests (n = 0, 1). • Receive error interrupt (INTSERn) • Reception complete interrupt (INTSRn) • Transmission complete interrupt (INTSTn) The priority order of these three interrupts is, from high to low: receive error interrupt, reception complete interrupt, transmission complete interrupt.
Page 295: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.5 Operation (1) Data format Transmission and reception of full duplex serial data are performed. As shown in Figure 10-2, 1 data frame consists of a start bit, character bits, a parity bit, and a stop bit as the format of transmit/receive data.
Page 296 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Starting a transmit operation In the transmit enabled state, if data is written to the transmit shift register (TXSn or TXSnL), the transmit operation starts. Transmit data is transmitted from the start bit to the LSB header. A start bit, parity/expansion bit and stop bit are added automatically.
Page 297 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Reception If reception is enabled, sampling of the RXDn pin is started and if a start bit is detected, data reception begins. When 1 frame of data reception is completed, the reception complete interrupt (INTSRn) is generated. Normally, with this interrupt processing, receive data is transmitted from the receive buffer (RXBn or RXBnL) to memory (n = 0, 1).
Page 298 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-4. Asynchronous Serial Interface Reception Complete Interrupt Timing Stop Parity/ RXDn (input) expansion Start INTSRn interrupt Remark n = 0, 1 (d) Receive error flag In synchronization with the receive operation, three types of error flags, the parity error flag, framing error flag, and overrun error flag, are affected.
Page 299: Clocked Serial Interfaces 0 To 3 (Csi0 To Csi3)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3) 10.3.1 Features { High transfer rate Max. 10 Mbps (when the internal system clock is operating at 40 MHz) … µ PD703100-40, 703100A-40 Max. 8.25 Mbps (when the internal system clock is operating at 33 MHz) …...
Page 300 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Serial clock counter Counts the serial clock that outputs, or is input during transmit/receive operations, and determines if 8-bit data were transmitted or received. (6) Interrupt control circuit This circuit controls whether or not an interrupt request is generated when the serial clock counter counts 8 clocks.
Page 301: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.3 Control registers (1) Clocked serial interface mode registers 0 to 3 (CSIM0 to CSIM3) These registers specify the basic operation mode of CSI0 to CSI3. These registers can be read/written in 8- or 1-bit units (however, for bit 5, only reading is possible). Address After reset CSIM0...
Page 302 CHAPTER 10 SERIAL INTERFACE FUNCTION Bit Position Bit Name Function 1, 0 CLSn1, Clock Source CLSn0 Specifies the serial clock. CLSn1 CLSn0 Serial Clock Specification SCK Pin External clock Input Internal Specified by the BPRMm Output Note 1 clock register φ...
Page 303 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Serial I/O shift registers 0 to 3 (SIO0 to SIO3) These registers convert 8-bit serial data to 8-bit parallel data and convert 8-bit parallel data to 8-bit serial data. The actual transmit/receive operation is controlled by reading from or writing to the SIOn registers. Shift operation is performed when CTXEn = 1 or CRXEn = 1.
Page 304: Basic Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.4 Basic operation (1) Transfer format CSIn transmits/receives data with three lines: one clock line and two data lines (n = 0 to 3). A serial transfer starts when an instruction that writes transfer data to the SIOn register is executed. In the case of transmission, data is output from the SOn pin at each falling edge of SCKn.
Page 305 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmission/reception enabled CSIn each have only one 8-bit shift register and do not have any buffers, so basically, they conduct transmission and reception simultaneously (n = 0 to 3). (a) Transmission/reception enable conditions Setting of the CSIn transmission and reception enable conditions is accomplished by the CTXEn and CRXEn bits of the CSIMn registers.
Page 306: Transmission By Csi0 To Csi3
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 Transmission by CSI0 to CSI3 After changing the settings to enable transmission by clocked serial interface mode register n (CSIMn), writing to the SIOn registers starts the transmit operation (n = 0 to 3). (1) Starting the transmit operation Starting the transmit operation is accomplished by setting the CTXEn bit of clocked serial interface mode register n (CSIMn) (setting the CRXEn bit to 0), and writing transmit data to shift register n (SIOn).
Page 307: Reception By Csi0 To Csi3
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Reception by CSI0 to CSI3 When the reception disabled setting is changed to reception enabled for clocked serial interface mode register n (CSIMn), and data is read from the SIOn register in the reception enabled state, a receive operation is started (n = 0 to 3).
Page 308: Transmission And Reception By Csi0 To Csi3
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.7 Transmission and reception by CSI0 to CSI3 If both transmission and reception by clocked serial interface mode register n (CSIMn) are enabled, transmit and receive operations can be carried out simultaneously (n = 0 to 3). (1) Starting transmit and receive operations When both the CTXEn bit and CRXEn bit of clocked serial interface mode register n (CSIMn) are set (1), both transmit operations and receive operations can be performed simultaneously (transmit/receive operations).
Page 309: Example Of System Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-9. Timing of 3-Wire Serial I/O Mode (Transmission/Reception) SCKn DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSIn interrupt Serial transmission/reception complete interrupt generation Transfer start in synchronization with falling of SCKn Execution of write instruction to SIOn register Remark n = 0 to 3 10.3.8 Example of system configuration...
Page 310: Dedicated Baud Rate Generators 0 To 2 (Brg0 To Brg2)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2) 10.4.1 Configuration and function A dedicated baud rate generator output or the internal system clock ( φ ) can be selected for the serial interface serial clock for each channel.
Page 311 CHAPTER 10 SERIAL INTERFACE FUNCTION (1) Dedicated baud rate generators 0 to 2 (BRG0 to BRG2) Dedicated baud rate generator BRGn (n = 0 to 2) consists of a dedicated 8-bit timer (TMBRGn) which generates the transmission/reception shift clock plus a compare register (BRGCn) and prescaler. (a) Input clock Internal system clock ( φ...
Page 312 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-2. Baud Rate Generator Setup Values φ = 33 MHz φ = 25 MHz φ = 16 MHz φ = 12.5 MHz Baud Rate [bps] UART0, CSI0 to Error Error Error Error UART1 CSI3 1,760 —...
Page 313: Baud Rate Generator Compare Registers 0 To 2 (Brgc0 To Brgc2)
CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Baud rate error The baud rate generator error is calculated as follows:   Actual baud rate (baud rate with error)     × 100 − 1 Error [%] =   Desired baud rate...
Page 314: Baud Rate Generator Prescaler Mode Registers 0 To 2 (Bprm0 To Bprm2)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.3 Baud rate generator prescaler mode registers 0 to 2 (BPRM0 to BPRM2) These registers control BRG0 to BRG2 timer count operations and select the count clock. These registers can be read/written in 8- or 1-bit units. Address After reset BPRM0...
Page 315: Chapter 11 A/D Converter
CHAPTER 11 A/D CONVERTER 11.1 Features { Analog input: 8 channels { 10-bit A/D converter { On-chip A/D conversion result register (ADCR0 to ADCR7) 10 bits × 8 { A/D conversion trigger mode A/D trigger mode Timer trigger mode External trigger mode { Successive approximation method 11.2 Configuration The A/D converter of the V850E/MS1 adopts the successive approximation method, and uses the A/D converter...
Page 316 CHAPTER 11 A/D CONVERTER (5) Successive approximation register (SAR) The SAR is a 10-bit register in which is set series resistor string voltage tap data, which have values that match analog input voltage values, 1 bit at a time beginning with the most significant bit (MSB). If the data is set in the SAR all the way to the least significant bit (LSB) (A/D conversion completed), the contents of that SAR (conversion results) are held in the A/D conversion results register (ADCRn).
Page 317 CHAPTER 11 A/D CONVERTER Figure 11-1. A/D Converter Block Diagram Series resistor string ANI0 Sample & hold circuit ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 Voltage comparator ANI7 SAR (10) INTAD ADCR0 INTCC110 INTCC111 ADCR1 Controller INTCC112 ADCR2 INTCC113 ADCR3 Noise Edge ADTRG ADCR4...
Page 318: Control Registers
CHAPTER 11 A/D CONVERTER 11.3 Control Registers (1) A/D converter mode register 0 (ADM0) The ADM0 register is an 8-bit register that executes the selection of the analog input pin, specification of operation mode, and conversion operations. This register can be read/written in 8- or 1-bit units, However, when the data is written to the ADM0 register during A/D conversion operations, the conversion operation is initialized and conversion is executed from the beginning.
Page 319 CHAPTER 11 A/D CONVERTER Note In the timer trigger mode (4-trigger mode) during the scan mode, because the scanning sequence of the ANI0 to ANI3 pins is specified by the sequence in which the match signals are generated from the compare register, the number of trigger inputs should be specified instead of a certain analog input pin.
Page 320 CHAPTER 11 A/D CONVERTER (2) A/D converter mode register 1 (ADM1) The ADM1 register is an 8-bit register that specifies the conversion operation time and trigger mode. This register can be read/written in 8- or 1-bit units. However, when the data is written to the ADM1 register during an A/D conversion operation, the conversion operation is initialized and conversion is executed from the beginning again.
Page 321 CHAPTER 11 A/D CONVERTER (3) A/D conversion result registers (ADCR0 to ADCR7, ADCR0H to ADCR7H) The ADCRn register is a 10-bit register holding the A/D conversion results. It is provided with eight 10-bit registers (n = 0 to 7). This register is read-only, in 16- or 8-bit units. During 16-bit access to this register, the ADCRn register is specified, and during higher 8-bit access, the ADCRnH register is specified.
Page 322 CHAPTER 11 A/D CONVERTER Figure 11-2 shows the relationship between the analog input voltage and the A/D conversion results. Figure 11-2. Relationship Between Analog Input Voltage and A/D Conversion Results 1,023 1,022 A/D conversion 1,021 results (ADCRn) 2,043 1,022 2,045 1,023 2,047 2,048...
Page 323: A/D Converter Operation
CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Operation 11.4.1 Basic operation of A/D converter A/D conversion is executed in the following order. (1) The selection of the analog input and specification of the operation mode, trigger mode, etc. should be set in Note 1 the ADM0 and ADM1 registers When the CE bit of the ADM0 register is set (1), A/D conversion starts in the A/D trigger mode.
Page 324: Operation Mode And Trigger Mode
CHAPTER 11 A/D CONVERTER 11.4.2 Operation mode and trigger mode The A/D converter can specify various conversion operations by specifying the operation mode and trigger mode. The operation mode and trigger mode are set by the ADM0 and ADM1 registers. The following shows the relationship between the operation mode and trigger mode.
Page 325 CHAPTER 11 A/D CONVERTER • • • • 1-trigger mode Mode that uses one match interrupt from timer 11 as the A/D conversion start timing. • • • • 4-trigger mode Mode that uses four match interrupts from timer 11 as the A/D conversion start timing. (c) External trigger mode Mode that specifies the conversion timing of the analog input to the ANI0 to ANI3 pins using the ADTRG pin.
Page 326 CHAPTER 11 A/D CONVERTER Figure 11-3. Select Mode Operation Timing: 1-Buffer Mode (ANI1) ANI1 Data 4 Data 5 (input) Data 1 Data 2 Data 3 Data 6 Data 7 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 conversion (ANI1)
Page 327 CHAPTER 11 A/D CONVERTER • 4-buffer mode One analog input is A/D converted four times and the results are stored in the ADCR0 to ADCR3 registers. The A/D conversion end interrupt (INTAD) is generated when the four A/D conversions end. Figure 11-4.
Page 328 CHAPTER 11 A/D CONVERTER (b) Scan mode Selects the analog inputs specified by the ADM0 register sequentially from the ANI0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the analog input. When the conversion of the specified analog input ends, the INTAD interrupt is generated.
Page 329: Operation In A/D Trigger Mode
CHAPTER 11 A/D CONVERTER 11.5 Operation in A/D Trigger Mode When the CE bit of the ADM0 register is set to 1, A/D conversion starts. 11.5.1 Select mode operations The analog input specified by the ADM0 register is A/D converted. The conversion results are stored in the ADCRn register corresponding to the analog input.
Page 330 CHAPTER 11 A/D CONVERTER (2) 4-buffer mode (A/D trigger select: 4-buffer) One analog input is A/D converted four times and the results are stored in the four ADCR0 to ADCR3 registers. When four A/D conversions end, an INTAD interrupt is generated and A/D conversion terminates. Analog Input A/D Conversion Result Register ANIn...
Page 331: Scan Mode Operations
CHAPTER 11 A/D CONVERTER 11.5.2 Scan mode operations The analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to When the conversion of all the specified analog input ends, the INTAD interrupt is generated, and A/D conversion terminates.
Page 332: Operation In Timer Trigger Mode
CHAPTER 11 A/D CONVERTER 11.6 Operation in Timer Trigger Mode The A/D converter is the match interrupt signal of the TM11 compare register, and can set conversion timings to a maximum of four channel analog inputs (ANI0 to ANI3). TM11 and four capture/compare registers (CC110 to CC113) are used for the timer for specifying the analog conversion trigger.
Page 333: Select Mode Operations
CHAPTER 11 A/D CONVERTER 11.6.1 Select mode operations One analog input (ANI0 to ANI3) specified by the ADM0 register is A/D converted. The conversion results are stored in the ADCRn register corresponding to the analog input. For the select mode, the 1-buffer mode and 4-buffer mode are provided according to the storing method of the A/D conversion results (n = 0 to 3).
Page 334 CHAPTER 11 A/D CONVERTER (b) 4-trigger mode (Timer trigger select: 1-buffer, 4-trigger) One analog input is A/D converted four times using four match interrupt signals (INTCC110 to INTCC113) as triggers and the results are stored in one ADCRn register. The INTAD interrupt is generated with each A/D conversion, and the CS bit of the ADM0 register is reset (0).
Page 335 CHAPTER 11 A/D CONVERTER (2) 4-buffer mode operations (Timer trigger select: 4-buffer) One analog input is A/D converted four times, and the results are stored in the ADCR0 to ADCR3 registers. There are two 4-buffer modes, 1-trigger mode and 4-trigger mode, according to the number of triggers. This mode is suitable for applications that calculate the average of the A/D conversion result.
Page 336 CHAPTER 11 A/D CONVERTER (b) 4-trigger mode One analog input is A/D converted four times using four match interrupt signals (INTCC110 to INTCC113) as triggers and the results are stored in four ADCRn registers. The INTAD interrupt is generated when the four A/D conversions end, the CS bit is reset (0), and A/D conversion terminates.
Page 337: Scan Mode Operations
CHAPTER 11 A/D CONVERTER 11.6.2 Scan mode operations The analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin and A/D converted for the specified number of times using the match interrupt signal as a trigger. In the conversion operation, first the analog input lower channels (ANI0 to ANI3) are A/D converted for the specified number of times.
Page 338 CHAPTER 11 A/D CONVERTER Figure 11-13. Example of 1-Trigger Mode (Timer Trigger Scan 1-Trigger) Operation (a) Setting when scanning ANI0 to ANI3 ANI0 ADCR0 ANI1 ADCR1 INTCC110 ANI2 ADCR2 ANI3 ADCR3 A/D converter ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ANI7 ADCR7 CE bit of ADM0 is set to 1 (enable) CC110 compare generation...
Page 339 CHAPTER 11 A/D CONVERTER (2) 4-trigger mode The analog inputs are A/D converted for the number of times specified using the match interrupt signal (INTCC110 to INTCC113) as a trigger. The analog input and ADCRn register correspond one to one. When all the A/D conversions specified have ended, the INTAD interrupt is generated and A/D conversion ends.
Page 340 CHAPTER 11 A/D CONVERTER Figure 11-14. Example of 4-Trigger Mode (Timer Trigger Scan 4-Trigger) Operation (a) Setting when scanning ANI0 to ANI3 No particular order ANI0 ADCR0 ANI1 ADCR1 INTCC110 ANI2 ADCR2 INTCC111 ANI3 ADCR3 A/D converter INTCC112 ANI4 ADCR4 INTCC113 ANI5 ADCR5...
Page 341: Operation In External Trigger Mode
CHAPTER 11 A/D CONVERTER 11.7 Operation in External Trigger Mode In the external trigger mode, the analog inputs (ANI0 to ANI3) are A/D converted by the ADTRG pin input timing. The ADTRG pin is also used as the P127 and INTP153 pins. To set the external trigger mode, set the PMC127 bit of the PMC12 register to 1 and bits TRG2 to TRG0 of the ADM1 register to 110.
Page 342 CHAPTER 11 A/D CONVERTER (2) 4-buffer mode (External trigger select: 4-buffer) One analog input is A/D converted four times using the ADTRG signal as a trigger and the results are stored in the ADCR0 to ADCR3 registers. The INTAD interrupt is generated and conversion ends when the four A/D conversions end.
Page 343: Scan Mode Operations (External Trigger Scan)
CHAPTER 11 A/D CONVERTER 11.7.2 Scan mode operations (external trigger scan) The analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin using the ADTRG signal as a trigger, and A/D converted. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to 7).
Page 344 CHAPTER 11 A/D CONVERTER Figure 11-17. Example of Scan Mode (External Trigger Scan) Operation (a) Setting when scanning ANI0 to ANI3 ANI0 ADCR0 ANI1 ADCR1 ANI2 ADCR2 ANI3 ADCR3 A/D converter ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ADTRG ANI7 ADCR7 CE bit of ADM0 is set to 1 (enable) External trigger generation External trigger generation...
Page 345: Operating Precautions
CHAPTER 11 A/D CONVERTER 11.8 Operating Precautions 11.8.1 Stopping conversion operation When 0 is written to the CE bit of the ADM0 register during a conversion operation, the conversion operation stops and the conversion results are not stored in the ADCRn register (n = 0 to 7). 11.8.2 External/timer trigger interval Set the interval (input time interval) of the trigger in the external or timer trigger mode longer than the conversion time specified by the FR2 to FR0 bits of the ADM1 register.
Page 346: Timer 1 Functions When In External Trigger Mode
CHAPTER 11 A/D CONVERTER 11.8.5 Timer 1 functions when in external trigger mode The external trigger input becomes an A/D conversion start trigger. At this time, the external trigger input also functions as a timer 15 (TM15) capture trigger external interrupt. In order to prevent it from generating capture trigger external interrupts, set TM15 as a compare register and disable interrupts by the interrupt mask bit of the interrupt control register.
Page 347: Chapter 12 Port Functions
CHAPTER 12 PORT FUNCTIONS 12.1 Features • Number of ports Input-only ports I/O ports • Function alternately as the input/output pins of other peripheral functions. • It is possible to specify input and output in bit units. User’s Manual U12688EJ4V0UM00...
Page 348: Port Configuration
CHAPTER 12 PORT FUNCTIONS 12.2 Port Configuration This product incorporates a total of 123 input/output ports (including 9 input-only ports) named ports 0 through 12, and A, B and X. The port configuration is shown below. Port 0 Port 8 Port 1 Port 9 P100...
Page 349 CHAPTER 12 PORT FUNCTIONS (1) Function of each port The port functions of this product are shown below. 8/1-bit operations are possible on all ports, allowing various kinds of control to be performed. In addition to their port functions, these pins also function as internal peripheral I/O input/output pins in the control mode. Note Port Name Pin Name...
Page 350 CHAPTER 12 PORT FUNCTIONS (2) Function when each port’s pins are reset and register which sets the port/control mode (1/3) Port Pin Name Pin Function After Reset Register Which Name Sets the Mode Single-chip Single-chip ROM-less ROM-less Mode 0 Mode 1 Mode 0 Mode 1 Port 0...
Page 351 CHAPTER 12 PORT FUNCTIONS (2/3) Port Pin Name Pin Function After Reset Register Which Name Sets the Mode Single-chip Single-chip ROM-less ROM-less Mode 0 Mode 1 Mode 0 Mode 1 Port 4 P40/D0 to P47/D7 P40 to P47 D0 to D7 (input mode) Port 5 P50/D8 to P57/D15...
Page 352 CHAPTER 12 PORT FUNCTIONS (3/3) Port Pin Name Pin Function After Reset Register Which Name Sets the Mode Single-chip Single-chip ROM-less ROM-less Mode 0 Mode 1 Mode 0 Mode 1 Port 11 P110/TO140 P110 (input mode) PMC11 P111/TO141 P111 (input mode) P112/TCLR14 P112 (input mode) P113/TI14...
Page 353 CHAPTER 12 PORT FUNCTIONS (3) Block diagram of port Figure 12-1. Type A Block Diagram PMCmn PMmn Output signal in control PORT mode Address Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 354 CHAPTER 12 PORT FUNCTIONS Figure 12-2. Type B Block Diagram PMCmn PMmn PORT Address Input signal in Noise elimination control mode edge detection Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 355 CHAPTER 12 PORT FUNCTIONS Figure 12-3. Type C Block Diagram SCKx output PMCmn enable signal PMmn Output signal in control mode PORT Address Input signal in control mode Remark mn: 24, 27 0 (when mn = 24), 1 (when mn = 27) User’s Manual U12688EJ4V0UM00...
Page 356 CHAPTER 12 PORT FUNCTIONS Figure 12-4. Type D Block Diagram PMCmn PMmn PORT Address Input signal in control mode Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 357 CHAPTER 12 PORT FUNCTIONS Figure 12-5. Type E Block Diagram MODE0 to MODE3 MM0 to MM3 I/O controller PMmn Output signal in PORT control mode Address Input signal in control mode Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 358 CHAPTER 12 PORT FUNCTIONS Figure 12-6. Type F Block Diagram MODE0 to MODE3 MM0 to MM3 I/O controller PMmn Output signal in PORT control mode Address Remark m: Port number Bit number Figure 12-7. Type G Block Diagram ANIn Input signal in Sample &...
Page 359 CHAPTER 12 PORT FUNCTIONS Figure 12-8. Type H Block Diagram MODE0 to MODE3 MM0 to MM3 I/O controller PMmn PORT Address Input signal in control mode Figure 12-9. Type I Block Diagram Noise elimination Address Edge detection User’s Manual U12688EJ4V0UM00...
Page 360 CHAPTER 12 PORT FUNCTIONS Figure 12-10. Type J Block Diagram PMmn PORT Address Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 361 CHAPTER 12 PORT FUNCTIONS Figure 12-11. Type K Block Diagram PCSmn PMCmn PMmn Output signal in PORT control mode Address Input signal in Noise elimination control mode edge detection Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 362 CHAPTER 12 PORT FUNCTIONS Figure 12-12. Type L Block Diagram PMCmn PMmn PORT Address Input signal in control mode Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 363 CHAPTER 12 PORT FUNCTIONS Figure 12-13. Type M Block Diagram Note PCSmn PMCmn PMmn PORT Address INTP100 to INTP103, Noise elimination INTP132, INTP142 edge detection DMARQ0 to DMARQ3, SI2, SI3 Note When mn = 36: PCS35 When mn = 116: PCS115 Remark mn: 04 to 07, 36, 116 User’s Manual U12688EJ4V0UM00...
Page 364 CHAPTER 12 PORT FUNCTIONS Figure 12-14. Type N Block Diagram PCSm5 SCKx output enable signal PMCmn PMmn Output signal in PORT control mode Address Noise elimination INTP133, INTP143 edge detection SCK2, SCK3 Remark mn: 37, 117 2 (when mn = 37), 3 (when mn = 117) User’s Manual U12688EJ4V0UM00...
Page 365 CHAPTER 12 PORT FUNCTIONS Figure 12-15. Type O Block Diagram MODE0 to MODE3 MM0 to MM3 PMCmn I/O controller PMmn Output signal in PORT control mode Address Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 366 CHAPTER 12 PORT FUNCTIONS Figure 12-16. Type P Block Diagram PCSmn MODE0 to MODE3 MM0 to MM3 I/O controller PMCmn PMmn Output signal in control mode PORT Address Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 367 CHAPTER 12 PORT FUNCTIONS Figure 12-17. Type Q Block Diagram Serial output PMCmn enable signal PMmn Output signal in control mode PORT Address Remark m: Port number Bit number User’s Manual U12688EJ4V0UM00...
Page 368: Port Pin Functions
CHAPTER 12 PORT FUNCTIONS 12.3 Port Pin Functions 12.3.1 Port 0 Port 0 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset FFFFF000H Undefined Bit Position Bit Name Function 7 to 0 P0n (n = 7 to 0) Port 0 Input/output port...
Page 369 CHAPTER 12 PORT FUNCTIONS (b) Port 0 mode control register (PMC0) This register can be read/written in 8- or 1-bit units. Address After reset PMC0 PMC07 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 FFFFF040H Bit Position Bit Name Function 7 to 4 PMC0n Port Mode Control (n = 7 to 4)
Page 370 CHAPTER 12 PORT FUNCTIONS (c) Port/control select register 0 (PCS0) This register can be read/written in 8- or 1-bit units. However, bits 3 to 0 are fixed at 0, so even if 1 is written, it is disregarded. Address After reset PCS0 PCS07 PCS06...
Page 371: Port 1
CHAPTER 12 PORT FUNCTIONS 12.3.2 Port 1 Port 1 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset FFFFF002H Undefined Bit Position Bit Name Function 7 to 0 P1n (n = 7 to 0) Port 1 Input/output port In addition to their function as port pins, the port 1 pins can also operate as real-time pulse unit (RPU)
Page 372 CHAPTER 12 PORT FUNCTIONS (b) Port 1 mode control register (PMC1) This register can be read/written in 8- or 1-bit units. Address After reset PMC1 PMC17 PMC16 PMC15 PMC14 PMC13 PMC12 PMC11 PMC10 FFFFF042H Bit Position Bit Name Function 7 to 4 PMC1n Port Mode Control (n = 7 to 4)
Page 373 CHAPTER 12 PORT FUNCTIONS (c) Port/control select register 1 (PCS1) This register can be read/written in 8- or 1-bit units. However, bits 3 to 0 are fixed at 0, so even if 1 is written, it is disregarded. Address After reset PCS1 PCS17 PCS16...
Page 374: Port 2
CHAPTER 12 PORT FUNCTIONS 12.3.3 Port 2 Port 2 is an 8-bit input/output port that can be set to input or output in 1-bit units. However, P20 always operates as an NMI input if the edge is input. Address After reset FFFFF004H Undefined Bit Position...
Page 375 CHAPTER 12 PORT FUNCTIONS (2) Input/output mode/control mode setting Port 2 input/output mode setting is performed by means of the port 2 mode register (PM2), and control mode setting is performed by means of the port 2 mode control register (PMC2). Pin P20 is fixed to NMI input mode. (a) Port 2 mode register (PM2) This register can be read/written in 8- or 1-bit units.
Page 376 CHAPTER 12 PORT FUNCTIONS (b) Port 2 mode control register (PMC2) This register can be read/written in 8- or 1-bit units. However, bit 0 is fixed to 1 by hardware, so writing 0 to this bit is ignored. Bit 1 is fixed to 0, so writing 1 to this bit is ignored. Address After reset PMC2...
Page 377: Port 3
CHAPTER 12 PORT FUNCTIONS 12.3.4 Port 3 Port 3 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset FFFFF006H Undefined Bit Position Bit Name Function 7 to 0 P3n (n = 7 to 0) Port 3 Input/output port In addition to their function as port pins, the port 3 pins can also operate as the input/output signals of the real-time...
Page 378 CHAPTER 12 PORT FUNCTIONS (2) Input/output mode/control mode setting Port 3 input/output mode setting is performed by means of the port 3 mode register (PM3), and control mode setting is performed by means of the port 3 mode control register (PMC3) and port/control select register 3 (PCS3).
Page 379 CHAPTER 12 PORT FUNCTIONS (b) Port 3 mode control register (PMC3) This register can be read/written in 8- or 1-bit units. Address After reset PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF046H Bit Position Bit Name Function 7 to 5 PMC3n Port Mode Control (n = 7 to 5)
Page 380: Port 4
CHAPTER 12 PORT FUNCTIONS (c) Port/control select register 3 (PCS3) This register can be read/written in 8- or 1-bit units. However, except for bit 5, all the bits are fixed at 0, so even if 1 is written, it is disregarded. Address After reset PCS3...
Page 381 CHAPTER 12 PORT FUNCTIONS (2) Input/output mode/control mode setting Port 4 input/output mode setting is performed by means of the port 4 mode register (PM4), and control mode (external expansion mode) setting is performed by means of the mode specification pins (MODE0 to MODE3) and the memory expansion mode register (MM: refer to 3.4.6 (1)).
Page 382: Port 5
CHAPTER 12 PORT FUNCTIONS 12.3.6 Port 5 Port 5 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset FFFFF00AH Undefined Bit Position Bit Name Function 7 to 0 P5n (n = 7 to 0) Port 5 Input/output port In addition to their function as port pins, the port 5 pins can also operate in the control mode (external expansion...
Page 383 CHAPTER 12 PORT FUNCTIONS (2) Input/output mode/control mode setting Port 5 input/output mode setting is performed by means of the port 5 mode register (PM5), and control mode (external expansion mode) setting is performed by means of the mode specification pins (MODE0 to MODE3) and the memory expansion mode register (MM: refer to 3.4.6 (1)).
Page 384: Port 6
CHAPTER 12 PORT FUNCTIONS 12.3.7 Port 6 Port 6 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset FFFFF00CH Undefined Bit Position Bit Name Function 7 to 0 P6n (n = 7 to 0) Port 6 Input/output port In addition to their function as port pins, the port 6 pins can also operate in the control mode (external expansion...
Page 385 CHAPTER 12 PORT FUNCTIONS (2) Input/output mode/control mode setting Port 6 input/output mode setting is performed by means of the port 6 mode register (PM6), and control mode (external expansion mode) setting is performed by means of the mode specification pins (MODE0 to MODE3) and the memory expansion mode register (MM: refer to 3.4.6 (1)).
Page 386: Port 7
CHAPTER 12 PORT FUNCTIONS 12.3.8 Port 7 Port 7 is an 8-bit input only port and all pins of port 7 are fixed in the input mode. Address After reset FFFFF00EH Undefined In addition to their function as port pins, the port 7 pins can also operate as analog inputs for A/D converter. This port is used also as the analog input pins (ANI0 to ANI7), but the port and analog input pins cannot be switched.
Page 387: Port 8
CHAPTER 12 PORT FUNCTIONS 12.3.9 Port 8 Port 8 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset FFFFF010H Undefined Bit Position Bit Name Function 7 to 0 P8n (n = 7 to 0) Port 8 Input/output port In addition to their function as port pins, in the control mode, the port 8 pins operate as chip select signal outputs,...
Page 388 CHAPTER 12 PORT FUNCTIONS (2) Input/output mode/control mode setting Port 8 input/output mode setting is performed by means of the port 8 mode register (PM8), and control mode (external expansion mode) setting is performed by means of the mode specification pins (MODE0 to MODE3) and the port 8 mode control register (PMC8).
Page 389 CHAPTER 12 PORT FUNCTIONS (b) Port 8 mode control register (PMC8) This register can be read/written in 8- or 1-bit units. Address After reset PMC8 PMC87 PMC86 PMC85 PMC84 PMC83 PCM82 PMC81 PMC80 FFFFF050H Note Note Single-chip mode 0: 00H Single-chip mode 1: FFH ROM-less mode 0, 1: FFH Bit Position...
Page 390 CHAPTER 12 PORT FUNCTIONS (c) Port/control select register 8 (PCS8) This register can be read/written in 8- or 1-bit units. However, all the bits except for bits 5 and 4 are fixed at 0, so even if 1 is written, it is disregarded. Address After reset PCS8...
Page 391: Port 9
CHAPTER 12 PORT FUNCTIONS 12.3.10 Port 9 Port 9 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset FFFFF012H Undefined Bit Position Bit Name Function 7 to 0 P9n (n = 7 to 0) Port 9 Input/output port In addition to their function as port pins, the port 9 pins can also operate in the control mode (external expansion...
Page 392 CHAPTER 12 PORT FUNCTIONS (2) Input/output mode/control mode setting Port 9 input/output mode setting is performed by means of the port 9 mode register (PM9), and control mode (external expansion mode) setting is performed by means of the mode specification pins (MODE0 to MODE3) and the port 9 mode control register (PMC9).
Page 393 CHAPTER 12 PORT FUNCTIONS (b) Port 9 mode control register (PMC9) This register can be read/written in 8- or 1-bit units. Address After reset PMC9 PMC97 PMC96 PMC95 PMC94 PMC93 PCM92 PMC91 PMC90 FFFFF052H Note Note Single-chip mode 0: 00H Single-chip mode 1: FFH ROM-less mode 0, 1: FFH Bit Position...
Page 394: Port 10
CHAPTER 12 PORT FUNCTIONS 12.3.11 Port 10 Port 10 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset P107 P106 P105 P104 P103 P102 P101 P100 FFFFF014H Undefined Bit Position Bit Name Function 7 to 0...
Page 395 CHAPTER 12 PORT FUNCTIONS (b) Port 10 mode control register (PMC10) This register can be read/written in 8- or 1-bit units. Address After reset PMC10 PMC107 PMC106 PMC105 PMC104 PMC103 PMC102 PMC101 PMC100 FFFFF054H Bit Position Bit Name Function 7 to 4 PMC10n Port Mode Control (n = 7 to 4)
Page 396 CHAPTER 12 PORT FUNCTIONS (c) Port/control select register 10 (PCS10) This register can be read/written in 8- or 1-bit units. However, bits 3 to 0 are fixed at 0, so even if 1 is written, it is disregarded. Address After reset PCS10 PCS107 PCS106...
Page 397: Port 11
CHAPTER 12 PORT FUNCTIONS 12.3.12 Port 11 Port 11 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset P117 P116 P115 P114 P113 P112 P111 P110 FFFFF016H Undefined Bit Position Bit Name Function 7 to 0...
Page 398 CHAPTER 12 PORT FUNCTIONS (2) Input/output mode/control mode setting Port 11 input/output mode setting is performed by means of the port 11 mode register (PM11), and control mode setting is performed by means of the port 11 mode control register (PMC11) and port/control select register 11 (PCS11).
Page 399 CHAPTER 12 PORT FUNCTIONS (b) Port 11 mode control register (PMC11) This register can be read/written in 8- or 1-bit units. Address After reset PMC11 PMC117 PMC116 PMC115 PMC114 PMC113 PMC112 PMC111 PMC110 FFFFF056H Bit Position Bit Name Function 7 to 5 PMC11n Port Mode Control (n = 7 to 5)
Page 400 CHAPTER 12 PORT FUNCTIONS (c) Port/control select register 11 (PCS11) This register can be read/written in 8- or 1-bit units. However, except for bit 5, all bits are fixed at 0, so even if 1 is written, it is disregarded. Address After reset PCS11...
Page 401: Port 12
CHAPTER 12 PORT FUNCTIONS 12.3.13 Port 12 Port 12 is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset P127 P126 P125 P124 P123 P122 P121 P120 FFFFF018H Undefined Bit Position Bit Name Function 7 to 0...
Page 402 CHAPTER 12 PORT FUNCTIONS (b) Port 12 mode control register (PMC12) This register can be read/written in 8- or 1-bit units. Address After reset PMC12 PMC127 PMC126 PMC125 PMC124 PMC123 PMC122 PMC121 PMC120 FFFFF058H Bit Position Bit Name Function PMC127 Port Mode Control Sets operation mode of P127 pin.
Page 403: Port A
CHAPTER 12 PORT FUNCTIONS 12.3.14 Port A Port A is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset FFFFF01CH Undefined Bit Position Bit Name Function 7 to 0 PAn (n = 7 to 0) Port A Input/output port In addition to their function as port pins, the port A pins can also operate in the control mode (external expansion...
Page 404 CHAPTER 12 PORT FUNCTIONS (b) Operation mode of port A Bit of MM Register Operation Mode don’t Port (PA0 to PA7) care Address bus (A0 to A7) For the details of mode selection by the MODE0 to MODE3 pins, refer to 3.3.2 Operating mode specification.
Page 405: Port B
CHAPTER 12 PORT FUNCTIONS 12.3.15 Port B Port B is an 8-bit input/output port that can be set to input or output in 1-bit units. Address After reset Undefined FFFFF01EH Bit Position Bit Name Function 7 to 0 PBn (n = 7 to 0) Port B Input/output port In addition to their function as port pins, the port B pins can also operate in the control mode (external expansion...
Page 406 CHAPTER 12 PORT FUNCTIONS (b) Operation mode of port B Bit of MM Register Operation Mode don’t Port (PB0 to PB7) care For the details of mode selection by the MODE0 to MODE3 pins, refer to 3.3.2 Operating mode specification. In ROM-less modes 0 or 1, or single-chip mode 1, the MM0 to MM3 bits are initialized to 111×...
Page 407: Port X
CHAPTER 12 PORT FUNCTIONS 12.3.16 Port X Port X is a 3-bit input/output port that can be set to input or output in 1-bit units. Address After reset — — — — — Undefined FFFFF41AH Bit Position Bit Name Function 7 to 5 PXn (n = 7 to 5) Port X...
Page 408 CHAPTER 12 PORT FUNCTIONS (b) Port X mode control register (PMCX) This register is write-only, in 8-bit units. However, the lower 5 bits are fixed at 0 by hardware, so even if 1 is written, it is disregarded. Address After reset PMCX PMCX7 PMCX6...
Page 409: Chapter 13 Reset Functions
CHAPTER 13 RESET FUNCTIONS When a low-level signal is input to the RESET pin, a system reset is effected and the hardware is initialized. When the RESET signal level changes from low to high, the reset state is released and program execution is started.
Page 410: Initialization
CHAPTER 13 RESET FUNCTIONS (1) Receiving the reset signal RESET (input) Analog Analog Analog delay delay delay Eliminate as a noise Internal system Note reset signal ∆ ∆ Reset Reset acceptance release Note The internal system reset signal continues in the active state for at least 4 system clock cycles after reset clear timing by the RESET signal.
Page 411 CHAPTER 13 RESET FUNCTIONS Table 13-2. Initial Values of CPU, Internal RAM, and Internal Peripheral I/O after Reset (1/2) Internal Hardware Register Name Initial Value After Reset Program registers General-purpose register (r0) 00000000H General-purpose registers (r1 to r31) Undefined Program counter (PC) 00000000H System registers Status saving register during interrupt (EIPC, EIPSW)
Page 412 CHAPTER 13 RESET FUNCTIONS Table 13-2. Initial Values of CPU, Internal RAM, and Internal Peripheral I/O after Reset (2/2) Internal Hardware Register Name Initial Value After Reset Internal Clock generator System status register (SYS) 0000000×B peri- functions Clock control register (CKC) pheral Power save control register (PSC) Timer/counter...
Page 413: Chapter 14 Flash Memory ( Μ Μ Μ Μ Pd70F3102, 70F3102A)
CHAPTER 14 FLASH MEMORY ( µ µ µ µ PD70F3102, 70F3102A) The µ PD70F3102 and 70F3102A are V850E/MS1 on-chip flash memory products with a 128KB flash memory. In the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock, just as in the mask ROM version.
Page 414: Programming Environment
CHAPTER 14 FLASH MEMORY ( µ µ µ µ PD70F3102, 70F3102A) 14.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V850E/MS1. RS-232-C RESET UART0/CSI0 V850E/MS1 Dedicated flash Host machine programmer A host machine is required for controlling the dedicated flash programmer. UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850E/MS1 to perform writing, erasing, etc.
Page 415: Pin Handling
CHAPTER 14 FLASH MEMORY ( µ µ µ µ PD70F3102, 70F3102A) 14.5 Pin Handling When performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. Also, install a function on-board to switch from the normal operation mode (single-chip modes 0 and 1 or ROM-less modes 0 and 1) to the flash memory programming mode.
Page 416 CHAPTER 14 FLASH MEMORY ( µ µ µ µ PD70F3102, 70F3102A) V850E/MS1 Conflict of signals Dedicated flash programmer connection pin Input pin Other device Output pin In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs.
Page 417: Reset Pin
CHAPTER 14 FLASH MEMORY ( µ µ µ µ PD70F3102, 70F3102A) 14.5.3 RESET pin When connecting the reset signals of the dedicated flash programmer to the RESET pin that is connected to the reset signal generation circuit on-board, conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 418: Power Supply
CHAPTER 14 FLASH MEMORY ( µ µ µ µ PD70F3102, 70F3102A) 14.5.9 Power supply Supply the power supply (V , HV , AV , AV , CV , and CV ) the same as that in normal operation mode. Connect V and GND of the dedicated flash programmer to V and V .
Page 419: Flash Memory Programming Mode
CHAPTER 14 FLASH MEMORY ( µ µ µ µ PD70F3102, 70F3102A) 14.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850E/MS1 in the flash memory programming mode. When switching modes, set the MODE0 to MODE2 and MODE3/V pins before releasing reset.
Page 420: Communication Command
CHAPTER 14 FLASH MEMORY ( µ µ µ µ PD70F3102, 70F3102A) 14.6.4 Communication command The V850E/MS1 communicates with the dedicated flash programmer by means of commands. A command sent from the dedicated flash programmer to the V850E/MS1 is called a “command”. The response signal sent from the V850E/MS1 to the dedicated flash programmer is called a “response command”.
Page 421 CHAPTER 14 FLASH MEMORY ( µ µ µ µ PD70F3102, 70F3102A) The V850E/MS1 sends back response commands to the commands issued from the dedicated flash programmer. The following shows the response commands the V850E/MS1 sends out. Response Command Name Function ACK (acknowledge) Acknowledges command/data, etc.
Page 422 [MEMO] User’s Manual U12688EJ4V0UM00...
Page 423: Appendix A Register Index
APPENDIX A REGISTER INDEX (1/8) Register Symbol Register Name Unit Page ADCR0 A/D conversion result register 0 ADCR0H A/D conversion result register 0H ADCR1 A/D conversion result register 1 ADCR1H A/D conversion result register 1H ADCR2 A/D conversion result register 2 ADCR2H A/D conversion result register 2H ADCR3...
Page 424 APPENDIX A REGISTER INDEX (2/8) Register Symbol Register Name Unit Page CC100 Capture/compare register 100 CC101 Capture/compare register 101 CC102 Capture/compare register 102 CC103 Capture/compare register 103 CC110 Capture/compare register 110 CC111 Capture/compare register 111 CC112 Capture/compare register 112 CC113 Capture/compare register 113 CC120 Capture/compare register 120...
Page 425 APPENDIX A REGISTER INDEX (3/8) Register Symbol Register Name Unit Page CTBP CALLT base pointer CTPC Status saving register during CALLT execution CTPSW Status saving register during CALLT execution DADC0 DMA addressing control register 0 DMAC DADC1 DMA addressing control register 1 DMAC DADC2 DMA addressing control register 2...
Page 426 APPENDIX A REGISTER INDEX (4/8) Register Symbol Register Name Unit Page DSA1H DMA source address register 1H DMAC DSA1L DMA source address register 1L DMAC DSA2H DMA source address register 2H DMAC DSA2L DMA source address register 2L DMAC DSA3H DMA source address register 3H DMAC DSA3L...
Page 427 APPENDIX A REGISTER INDEX (5/8) Register Symbol Register Name Unit Page Port 3 Port Port 4 Port Port 5 Port Port 6 Port Port 7 Port Port 8 Port Port 9 Port Port 10 Port P10IC0 Interrupt control register INTC P10IC1 Interrupt control register INTC...
Page 428 APPENDIX A REGISTER INDEX (6/8) Register Symbol Register Name Unit Page PCS0 Port/control select register 0 Port PCS1 Port/control select register 1 Port PCS3 Port/control select register 3 Port PCS8 Port/control select register 8 Port PCS10 Port/control select register 10 Port PCS11 Port/control select register 11...
Page 429 APPENDIX A REGISTER INDEX (7/8) Register Symbol Register Name Unit Page RFC0 Refresh control register 0 RFC1 Refresh control register 1 RFC2 Refresh control register 2 RFC3 Refresh control register 3 Refresh wait control register RXB0 Receive buffer 0 (9 bits) UART0 RXB0L Receive buffer 0L (Lower order 8 bits)
Page 430 APPENDIX A REGISTER INDEX (8/8) Register Symbol Register Name Unit Page TOC11 Timer output control register 11 TOC12 Timer output control register 12 TOC13 Timer output control register 13 TOC14 Timer output control register 14 TOC15 Timer output control register 15 TOVS Timer overflow status register TUM10...
Page 431: Appendix B Instruction Set List
APPENDIX B INSTRUCTION SET LIST B.1 General Examples (1) Register symbols used to describe operands Register Symbol Explanation reg1 General registers (r0 to r31): Used as source registers. reg2 General registers (r0 to r31): Used mainly as destination registers. reg3 General registers (r0 to r31): Used mainly to store the remainders of division results and the higher order 3 bits of multiplication results.
Page 432 APPENDIX B INSTRUCTION SET LIST (3) Register symbols used in operation (2/2) Register Symbol Explanation store-memory-bit (a, b, c) Write bit b of address a to c. saturated (n) Execute saturated processing of n (n is a 2’s complement). If, as a result of calculations, n ≥...
Page 433 APPENDIX B INSTRUCTION SET LIST (6) Condition codes Condition Name Condition Code Condition Formula Explanation (cond) (cccc) 0 0 0 0 OV = 1 Overflow 1 0 0 0 OV = 0 No overflow 0 0 0 1 CY = 1 Carry Lower (Less than) NC/NL...
Page 434: Instruction Set (In Alphabetical Order)
APPENDIX B INSTRUCTION SET LIST B.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Op Code Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r r r r 0 0 1 1 1 0 R R R R R GR[reg2]←GR[reg2]+GR[reg1] ×...
Page 435 APPENDIX B INSTRUCTION SET LIST (2/6) Mnemonic Operand Op Code Operation Execution Flags Clock CY OV S Z SAT DISPOSE imm5,list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2) Note 4 Note 4 Note 4...
Page 436 APPENDIX B INSTRUCTION SET LIST (3/6) Mnemonic Operand Op Code Operation Execution Flags Clock CY OV S Z SAT LD.HU disp16[reg1],reg2 r r r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]+sign-extend(disp16) ddddddddddddddd1 GR[reg2]←zero-extend(Load-memory(adr,Half- word)) Note 8 Note 11...
Page 437 APPENDIX B INSTRUCTION SET LIST (4/6) Mnemonic Operand Op Code Operation Execution Flags Clock CY OV S Z SAT × × imm16,reg1,reg2 r r r r r 1 1 0 1 0 0 R R R R R GR[reg2]←GR[reg1]OR zero-extend(imm16) i i i i i i i i i i i i i i i i PREPARE list12,imm5...
Page 438 APPENDIX B INSTRUCTION SET LIST (5/6) Mnemonic Operand Op Code Operation Execution Flags Clock CY OV S Z SAT × SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) × reg2,[reg1] r r r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1] 0000000011100000 Z flag←Not(Load-memory-bit(adr,reg2))
Page 439 APPENDIX B INSTRUCTION SET LIST (6/6) Mnemonic Operand Op Code Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r r r r 0 0 1 1 0 1 R R R R R GR[reg2]←GR[reg2]–GR[reg1] ×...
Page 440 APPENDIX B INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the op code. Therefore, the meaning of register specification in the mnemonic description and in the op code differs from other instructions.
Page 441: Appendix C Index
APPENDIX C INDEX BCT................ 105 A/D conversion result registers ......321 BCYST ..............57 A/D converter ............315 Block diagram of port ..........353 A/D converter mode register 0 ....... 318 Block transfer mode ..........180 A/D converter mode register 1 ....... 320 Boundary of memory area........
Page 442 APPENDIX C INDEX CG ................231 CTBP................72 CH0 to CH3 ............173 CTPC ...............72 CKC................233 CTPSW ..............72 CKDIV0, CKDIV1 ...........233 CTXE0 to CTXE3 ...........301 CKSEL ..............62 .................64 CL0, CL1 ..............288 .................64 Clearing/starting timer (timer1) .......265 CY ................73 CLKOUT..............62 Clock control register..........233 Clock generator ............231 D0 to D7 ..............53 Clock generator functions........231 D8 to D15 ..............53...
Page 443 APPENDIX C INDEX DMARQ0 to DMARQ3..........49 FECC ............... 72 DRAM access ............143 FEPC ............... 72 DRAM access during DMA flyby transfer ....151 FEPSW ..............72 DRAM connections ..........137 Flash memory ............413 DRAM controller............. 136 Flash memory programming mode ....74, 419 DRAM configuration registers 0 to 3 ......
Page 444 APPENDIX C INDEX Interrupt/exception table ...........83 Interval timer............274 OE ................57 INTM0..............208 One time single transfer with DMARQ0 to INTM1 to INTM6..........220, 261 DMARQ3 ..............196 INTP100 to INTP103 ..........49 On-page/off-page judgment ........132 INTP110 to INTP113 ..........50 Operation in A/D trigger mode........329 INTP120 to INTP123 ..........58 Operation in external trigger mode ......341 INTP130 to INTP133 ..........52...
Page 445 APPENDIX C INDEX P90 to P97 ............56, 391 PCS104 to PCS107 ..........396 P100 to P107 ........... 58, 394 PCS115..............400 P110 to P117 ........... 59, 397 PE0, PE1 ............... 291 P120 to P127 ........... 60, 401 Periods where interrupt is not acknowledged..227 P10IC0 to P10IC3 ..........
Page 446 APPENDIX C INDEX PMC11 ..............399 Port 0 mode register ..........368 PMC12 ..............402 Port 1 mode register..........371 PMC00 to PMC07 ..........369 Port 2 mode register..........375 PMC10 to PMC17 (bit) ...........372 Port 3 mode register..........378 PMC22 to PMC27 ..........376 Port 4 mode register..........381 PMC30 to PMC37 ..........379 Port 5 mode register..........383 PMC80 to PMC87 ..........389...
Page 447 APPENDIX C INDEX RD................57 SEIF0, SEIF1 ............217 Real-time pulse unit ..........247 Select mode ............325 Receive buffers 0, 0L, 1, 1L ........292 Self-refresh functions ..........158 Receive error interrupt ........... 294 SEMK0, SEMK1............. 217 Reception completion interrupt....... 294 SEPR0n, SEPR1n (n = 0 to 2) .......
Page 448 APPENDIX C INDEX TC0 to TC3...............58 Transfer types ............181 TC0 to TC3.............170 Transmission completion interrupt......294 TCLR10 ..............49 Transmit shift registers 0, 0L, 1, 1L ......293 TCLR11 ..............50 TRG2 to TRG0 ............320 TCLR12 ..............58 Trigger mode............324 TCLR13 ..............52 TTYP ..............169 TCLR14 ..............59 TUM10 to TUM15...........254 TCLR15 ..............60 Two-cycle transfer ..........181...
Page 449 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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NEC V850E/MS1 UPD703100 User Manual

Chapter 1 Introduction

Outline

Features

Applications

Ordering Information

Pin Configuration (Top View)

Function Block

Chapter 2 Pin Functions

List of Pin Functions

Pin Status

Description of Pin Functions

Pin Input/Output Circuits and Recommended Connection of Unused Pins

Pin Input/Output Circuits

Chapter 3 Cpu Function

Features

CPU Register Set

Operation Modes

Address Space

Chapter 4 Bus Control Function

Features

Bus Control Pins

Memory Block Function

Bus Cycle Type Control Function

Bus Access

Wait Function

Idle State Insertion Function

Bus Hold Function

Bus Priority Order

Boundary Operation Conditions

Chapter 5 Memory Access Control Function

SRAM, External ROM, External I/O Interface

Page ROM Controller (ROMC)

DRAM Controller

Chapter 6 Dma Functions (Dma Controller)

Features

Configuration

Control Registers

DMA Bus States

Transfer Mode

Transfer Types

Transfer Objects

DMA Channel Priorities

Next Address Setting Function

DMA Transfer Start Factors

Interrupting DMA Transfer

Terminating DMA Transfer

Boundary of Memory Area

Transfer of Misalign Data

Clocks of DMA Transfer

Maximum Response Time to DMA Request

One Time Single Transfer with DMARQ0 to DMARQ3

Bus Arbitration for CPU

Precaution

Chapter 7 Interrupt/Exception Processing Function

Features

Non-Maskable Interrupt

Maskable Interrupts

Software Exception

Exception Trap

Multiple Interrupt Processing Control

Interrupt Latency Time

Periods in Which Interrupt Is Not Acknowledged

Chapter 8 Clock Generator Functions

Features

Configuration

Input Clock Selection

PLL Lockup

Power Saving Control

Securing Oscillation Stabilization Time

Chapter 9 Timer/Counter Function (Real-Time Pulse Unit)

Features

Basic Configuration

Control Registers

Timer 1 Operation

Timer 4 Operation

Application Example

Precaution

Chapter 10 Serial Interface Function

Features