Page 1 Preliminary User's Manual µ PD780024AS, 780034AS Subseries 8-Bit Single-Chip Microcontrollers µ PD780021AS µ PD780022AS µ PD780023AS µ PD780024AS µ PD780031AS µ PD780032AS µ PD780033AS µ PD780034AS µ PD78F0034BS Document No. U16035EJ1V0UM00 (1st edition) Date Published June 2002 N CP(K) © 2002 Printed in Japan...
Page 2 [MEMO] Preliminary User’s Manual U16035EJ1V0UM...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. FIP, EEPROM, and IEBus are trademarks of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 INTRODUCTION Readers This manual has been prepared for user engineers who understand the functions of the µ PD780024AS, 780034AS Subseries and wish to design and develop application systems and programs for these devices. µ PD780024AS Subseries: µ PD780021AS, 780022AS, 780023AS, 780024AS µ...
Page 7 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: ××× (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ···...
Page 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µ PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY Data Sheet U14042E µ...
Page 9 SEMICONDUCTOR SELECTION GUIDE - Products & Packages - X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Page 10: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ........................1.1 Features ............................ 1.2 Applications ..........................1.3 Ordering Information ....................... 1.4 Pin Configuration (Top View) ....................1.5 78K/0 Series Lineup ......................... 1.6 Block Diagram .......................... 1.7 Outline of Function ........................CHAPTER 2 PIN FUNCTION ......................2.1 Pin Function List ........................
Page 11 3.3 Instruction Address Addressing .................... 3.3.1 Relative addressing ........................3.3.2 Immediate addressing ........................3.3.3 Table indirect addressing ....................... 3.3.4 Register addressing ........................3.4 Operand Address Addressing ....................3.4.1 Implied addressing ........................3.4.2 Register addressing ........................3.4.3 Direct addressing .......................... 3.4.4 Short direct addressing ......................... 3.4.5 Special function register (SFR) addressing ...................
Page 12 5.6.2 System clock and CPU clock switching procedure ................ 103 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 ................104 6.1 Functions of 16-Bit Timer/Event Counter 0 ................104 6.2 Configuration of 16-Bit Timer/Event Counter 0 ..............105 6.3 Registers to Control 16-Bit Timer/Event Counter 0 .............. 108 6.4 Operations of 16-Bit Timer/Event Counter 0 .................
Page 13 10.2 Configuration of Clock Output/Buzzer Output Controller ..........166 10.3 Registers to Control Clock Output/Buzzer Output Controller ........... 166 10.4 Operations of Clock Output/Buzzer Output Controller ............169 10.4.1 Operation as clock output ......................169 10.4.2 Operation as buzzer output ......................169 CHAPTER 11 8-BIT A/D CONVERTER ( µ...
Page 14 CHAPTER 15 INTERRUPT FUNCTIONS ..................246 15.1 Interrupt Function Types ...................... 246 15.2 Interrupt Sources and Configuration ................... 246 15.3 Registers to Control Interrupt Function ................250 15.4 Interrupt Servicing Operations ..................... 256 15.4.1 Non-maskable interrupt request acknowledge operation ............256 15.4.2 Maskable interrupt request acknowledge operation ..............
Page 15 B.2 Flash Memory Writing Tools ....................303 B.3 Debugging Tools ........................304 B.3.1 Hardware ............................304 B.3.2 Software ............................305 APPENDIX C EMBEDDED SOFTWARE ..................306 APPENDIX D REGISTER INDEX ...................... 307 D.1 Register Name Index ....................... 307 D.2 Register Symbol Index ......................309 Preliminary User’s Manual U16035EJ1V0UM...
Page 16 LIST OF FIGURES (1/6) Figure No. Title Page Pin I/O Circuit List ..........................Memory Map ( µ PD780021AS, 780031AS) ..................Memory Map ( µ PD780022AS, 780032AS) ..................Memory Map ( µ PD780023AS, 780033AS) ..................Memory Map ( µ PD780024AS, 780034AS) ..................Memory Map ( µ...
Page 17 LIST OF FIGURES (2/6) Figure No. Title Page System Clock and CPU Clock Switching ..................... 103 Block Diagram of 16-Bit Timer/Event Counter 0 .................. 105 Format of 16-Bit Timer Mode Control Register 0 (TMC0) ..............109 Format of Capture/Compare Control Register 0 (CRC0) ..............110 Format of 16-Bit Timer Output Control Register 0 (TOC0) ..............
Page 18 LIST OF FIGURES (3/6) Figure No. Title Page Format of 8-Bit Timer Mode Control Register 5n (TMC5n) ..............137 Format of Port Mode Register 7 (PM7) ....................139 Interval Timer Operation Timings ......................141 External Event Counter Operation Timing (with Rising Edge Specified) ..........Square-Wave Output Operation Timing ....................
Page 19 LIST OF FIGURES (4/6) Figure No. Title Page 11-16 Analog Input Pin Connection ....................... 187 11-17 A/D Conversion End Interrupt Request Generation Timing ..............188 11-18 Timing of Reading Conversion Result (When Conversion Result Is Undefined) ......... 11-19 Timing of Reading Conversion Result (When Conversion Result Is Normal) ........189 11-20 Pin Connection ...........................
Page 20 LIST OF FIGURES (5/6) Figure No. Title Page 13-8 Timing of Asynchronous Serial Interface Transmit Completion Interrupt Request ....... 230 13-9 Timing of Asynchronous Serial Interface Receive Completion Interrupt Request ....... 231 13-10 Receive Error Timing ........................... 232 13-11 Data Format Comparison Between Infrared Data Transfer Mode and UART Mode ......233 14-1 Block Diagram of Serial Interface (SIO3n) ...................
Page 21 LIST OF FIGURES (6/6) Figure No. Title Page 18-4 Connection of Flashpro III in 3-Wire Serial I/O Mode (Using Handshake) .......... 282 18-5 Connection of Flashpro III in UART Mode ................... 282 18-6 Connection of Flashpro III in Pseudo 3-Wire Serial I/O Mode ............. 283 Development Tool Configuration ......................
Page 22 LIST OF TABLES (1/2) Table No. Title Page Pin I/O Circuit Types ..........................Internal ROM Capacity ........................Vector Table ............................Internal High-Speed RAM Capacity ..................... Internal High-Speed RAM Area ......................Special Function Register List ......................Port Functions ............................Configuration of Ports .......................... Configuration of Clock Generator ......................
Page 23 LIST OF TABLES (2/2) Table No. Title Page 14-1 Configuration of Serial Interface (SIO3n) ..................... 237 15-1 Interrupt Source List ..........................247 15-2 Flags Corresponding to Interrupt Request Sources ................250 15-3 Times from Generation of Maskable Interrupt Until Servicing ............. 259 15-4 Interrupt Request Enabled for Nesting During Interrupt Servicing ............
Page 24: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features • Internal memory Type Program Memory Data Memory Part Number (ROM/Flash Memory) (High-Speed RAM) µ PD780021AS, 780031AS 8 KB 512 bytes µ PD780022AS, 780032AS 16 KB µ PD780023AS, 780033AS 24 KB 1024 bytes µ PD780024AS, 780034AS 32 KB µ...
Page 25: Applications
CHAPTER 1 OUTLINE 1.2 Applications Home electric appliances, pagers, AV equipment, car audios, car electric equipment, office automation equipment, etc. 1.3 Ordering Information Part Number Package Internal ROM µ PD780021ASGB-×××-8ET 52-pin plastic LQFP (10 × 10) Mask ROM µ PD780022ASGB-×××-8ET 52-pin plastic LQFP (10 ×...
Page 26: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 52-pin plastic LQFP (10 × 10) µ PD780021ASGB-×××-8ET, 780022ASGB-×××-8ET, µ PD780023ASGB-×××-8ET, 780024ASGB-×××-8ET, µ PD780031ASGB-×××-8ET, 780032ASGB-×××-8ET, µ PD780033ASGB-×××-8ET, 780034ASGB-×××-8ET, µ PD780034BSGB-8ET 52 51 50 49 48 47 46 45 44 43 42 41 40 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2...
Page 27 CHAPTER 1 OUTLINE ADTRG: AD trigger input P70 to P75: Port 7 ANI0 to ANI3: Analog input PCL: Programmable clock ASCK0: Asynchronous serial clock RESET: Reset Analog power supply RxD0: Receive data Analog reference voltage SCK30, SCK31: Serial clock Analog ground SI30, SI31: Serial input BUZ:...
Page 28: Series Lineup
CHAPTER 1 OUTLINE 1.5 78K/0 Series Lineup The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name. Products in mass production Products under development Y subseries products are compatible with I C bus. Control µ...
Page 29 CHAPTER 1 OUTLINE The major functional differences among the subseries are listed below. Function Timer 8-Bit 10-Bit 8-Bit Serial Interface External Capacity MIN. Subseries Name (Bytes) 8-Bit 16-Bit Watch WDT A/D Expansion Value µ PD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch √...
Page 30: Block Diagram
CHAPTER 1 OUTLINE 1.6 Block Diagram TI00/TO0/P70 16-bit timer/ Port 0 P00 to P03 event counter TI01/P71 8-bit timer/ Port 1 P10 to P13 TI50/TO50/P72 event counter 50 8-bit timer/ TI51/TO51/P73 Port 2 P20 to P25 event counter 51 Watchdog timer Port 3 P34 to P36 Watch timer...
Page 31: Outline Of Function
CHAPTER 1 OUTLINE 1.7 Outline of Function µ PD780021AS µ PD780022AS µ PD780023AS µ PD780024AS µ PD78F0034BS Part Number µ PD780031AS µ PD780032AS µ PD780033AS µ PD780034AS Item Note Internal memory 8 KB 16 KB 24 KB 32 KB 32 KB (Mask ROM) (Mask ROM) (Mask ROM)
Page 32 CHAPTER 1 OUTLINE The outline of the timer/event counter is as follows (for details, refer to CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0, CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51, CHAPTER 8 WATCH TIMER, and CHAPTER 9 WATCHDOG TIMER). 16-Bit Timer/ 8-Bit Timer/ Watch Timer Watchdog Timer...
Page 33: Chapter 2 Pin Function
CHAPTER 2 PIN FUNCTION 2.1 Pin Function List (1) Port pins Alternate Pin Name Function After Reset Function Port 0 Input INTP0 4-bit I/O port INTP1 Input/output mode can be specified in 1-bit units. INTP2 An on-chip pull-up resistor can be used by software settings.
Page 34 CHAPTER 2 PIN FUNCTION (2) Non-port pins (1/2) Alternate Pin Name Function After Reset Function INTP0 Input External interrupt request input with specifiable valid edges Input (rising edge, falling edge, both rising and falling edges) INTP1 INTP2 INTP3 P03/ADTRG SI30 Input Serial interface serial data input Input...
Page 35 CHAPTER 2 PIN FUNCTION (2) Non-port pins (2/2) Alternate Pin Name Function After Reset Function — Ground potential for ports — — — Ground potential other than ports — — — Internally connected. Connect directly to V or V — —...
Page 36: Description Of Pin Functions
CHAPTER 2 PIN FUNCTION 2.2 Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These are 4-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt input, and A/D converter external trigger input. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 4-bit I/O ports.
Page 37: P20 To P25 (Port 2)
CHAPTER 2 PIN FUNCTION 2.2.3 P20 to P25 (Port 2) These are 6-bit I/O ports. Besides serving as I/O ports, they function as serial interface data I/O and clock I/O. The following operating modes can be specified in 1-bit units. (1) Port mode These ports function as 6-bit I/O ports.
Page 38: P40 To P47 (Port 4)
CHAPTER 2 PIN FUNCTION 2.2.5 P40 to P47 (Port 4) These are 8-bit I/O ports. The interrupt request flag (KRIF) can be set to 1 by detecting a falling edge. The following operating mode can be specified in 1-bit units. Caution When using the falling edge detection interrupt (INTKR), be sure to set the memory expansion mode register (MEM) to 01H.
Page 39: P70 To P75 (Port 7)
CHAPTER 2 PIN FUNCTION 2.2.7 P70 to P75 (Port 7) These are 6-bit I/O ports. Besides serving as I/O ports, they function as a timer I/O, clock output, and buzzer output. The following operating modes can be specified in 1-bit units. (1) Port mode Port 7 functions as a 6-bit I/O port.
Page 40: X1 And X2
CHAPTER 2 PIN FUNCTION 2.2.12 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input clock signal to X1 and its inverted signal to X2. 2.2.13 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation. For external clock supply, input the clock signal to XT1 and its inverted signal to XT2.
Page 41: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTION 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the types of pin I/O circuit and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-1.
Page 42 CHAPTER 2 PIN FUNCTION Figure 2-1. Pin I/O Circuit List TYPE 2 TYPE 16 Feedback cut-off P-ch Schmitt-triggered input with hysteresis characteristics TYPE 5-H TYPE 25 Pullup P-ch P-ch enable Comparator – Data N-ch P-ch (threshold voltage) IN/OUT Output N-ch disable Input enable...
Page 43: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Spaces µ PD780024AS, 780034AS Subseries can access 64 KB memory space respectively. Figures 3-1 to 3-5 show memory maps. Caution In case of the internal memory capacity, the initial value of memory size switching register (IMS) of all products ( µ...
Page 44 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ PD780022AS, 780032AS) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH 3FFFH Program area Data memory...
Page 45 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( µ PD780023AS, 780033AS) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH 5FFFH Program area Data memory...
Page 46 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map ( µ PD780024AS, 780034AS) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH 7FFFH Program area Data memory...
Page 47 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( µ PD78F0034BS) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H General-purpose FEFFH registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits FB00H FAFFH 7FFFH Program area Data memory 1000H...
Page 48: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space contains the program and table data. Normally, it is addressed with the program counter (PC). The µ PD780024AS, 780034AS Subseries products incorporate an on-chip ROM (or flash memory), as listed below. Table 3-1.
Page 49: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space The µ PD780024AS, 780034AS Subseries products incorporate an internal high-speed RAM, as listed below. Table 3-3. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM µ PD780021AS, 780031AS 512 × 8 bits (FD00H to FEFFH) µ...
Page 50: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.5 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. The address of an instruction to be executed next is addressed by the program counter (PC) (for details, see 3.3 Instruction Address Addressing).
Page 51 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data Memory Addressing ( µ PD780022AS, 780032AS) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH Internal high-speed RAM 512 ×...
Page 52 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing ( µ PD780023AS, 780033AS) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH Internal high-speed RAM 1024 ×...
Page 53 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing ( µ PD780024AS, 780034AS) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH Internal high-speed RAM 1024 ×...
Page 54 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing ( µ PD78F0034BS) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH Internal high-speed RAM 1024 ×...
Page 55: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD780024AS, 780034AS Subseries products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 56 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to the disable interrupt (DI) state, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all disabled. When 1, the IE is set to the enable interrupt (EI) state and interrupt request acknowledge enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag.
Page 57 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Format of Stack Pointer SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.
Page 58: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers A general-purpose register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register.
Page 59: Special Function Register (Sfr)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function register (SFR) Unlike a general-purpose register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function register can be manipulated like the general-purpose register, with the operation, transfer and bit manipulation instructions.
Page 60 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/2) Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits √ √ FF00H Port 0 — √ √ FF01H Port 1 —...
Page 61 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/2) Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits √ √ FF47H Memory expansion mode register — √ √ FF48H External interrupt rising edge enable register —...
Page 62: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 63: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 64: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 65: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general-purpose register is automatically (implicitly) addressed.
Page 66: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register specify code (Rn and RPn) of an instruction word in the registered bank specified with the register bank select flag (RBS0 and RBS1). Register addressing is carried out when an instruction with the following operand format is executed.
Page 67: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code...
Page 68: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 69: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 70: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory to be manipulated.
Page 71: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory.
Page 72: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory.
Page 73: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD780024AS, 780034AS Subseries products incorporate four input ports and 35 I/O ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations.
Page 74 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Alternate Pin Name Function Function Port 0 INTP0 4-bit I/O port. INTP1 Input/output mode can be specified in 1-bit units. INTP2 An on-chip pull-up resistor can be used by software settings. INTP3/ADTRG P10 to P13 Port 1 ANI0 to ANI3...
Page 75: Configuration Of Ports
CHAPTER 4 PORT FUNCTIONS 4.2 Configuration of Ports A port consists of the following hardware. Table 4-2. Configuration of Ports Item Configuration Control register Port mode register (PMm: m = 0, 2 to 5, 7) Pull-up resistor option register (PUm,: m = 0, 2 to 5, 7) Port Total: 39 ports (4 inputs, 35 inputs/outputs) Pull-up resistor...
Page 76: Port 1
CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P00 to P03 PU00 to PU03 P-ch Alternate function PORT P00/INTP0 to Output latch P02/INTP2, (P00 to P03) P03/INTP3/ADTRG PM00 to PM03 PU: Pull-up resistor option register PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal 4.2.2 Port 1...
Page 77: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is a 6-bit I/O port with output latch. P20 to P25 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). An on-chip pull-up resistor of P20 to P25 pins can be used for them in 1-bit units with a pull-up resistor option register 2 (PU2).
Page 78 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 and P24 PU21, PU24 P-ch Selector PORT Output latch P21/SO30, (P21, P24) P24/TxD0 PM21, PM24 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal Preliminary User’s Manual U16035EJ1V0UM...
Page 79: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 3-bit I/O port with output latch. P34 to P36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified for the P34 to P36 pins in 1- bit units by pull-up resistor option register 3 (PU3).
Page 80 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P35 PU35 P-ch Selector PORT Output latch (P35) P35/SO31 PM35 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal Preliminary User’s Manual U16035EJ1V0UM...
Page 81: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an 8-bit I/O port with output latch. The P40 to P47 pins can specify the input mode/output mode in 1- bit units with port mode register 4 (PM4). An on-chip pull-up resistor of P40 to P47 pins can be used for them in 1- bit units with pull-up resistor option register 4 (PU4).
Page 82: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is an 8-bit I/O port with output latch. The P50 to P57 pins can specify the input mode/output mode in 1- bit units with port mode register 5 (PM5). An on-chip pull-up resistor of P50 to P57 pins can be used for them in 1- bit units with pull-up resistor option register 5 (PU5).
Page 83: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 Port 7 is a 6-bit I/O port with output latch. The P70 to P75 pins can specify the input mode/output mode in 1-bit units with port mode register 7 (PM7). An on-chip pull-up resistor of P70 to P75 pins can be used for them in 1-bit units with pull-up resistor option register 7 (PU7).
Page 84 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P74 and P75 PU74, PU75 P-ch Selector PORT Output latch P74/PCL, (P74, P75) P75/BUZ PM74, PM75 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal Preliminary User’s Manual U16035EJ1V0UM...
Page 85: Registers To Control Port Function
CHAPTER 4 PORT FUNCTIONS 4.3 Registers to Control Port Function The following two types of registers control the ports. • Port mode registers (PM0, PM2 to PM5, PM7) • Pull-up resistor option registers (PU0, PU2 to PU5, PU7) (1) Port mode registers (PM0, PM2 to PM5, PM7) These registers are used to set port input/output in 1-bit units.
Page 86 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Format of Port Mode Register (PM0, PM2 to PM5, PM7) Address: FF20H After reset: FFH Symbol PM03 PM02 PM01 PM00 Address: FF22H After reset: FFH Symbol PM25 PM24 PM23 PM22 PM21 PM20 Address: FF23H After reset: FFH Symbol Note Note...
Page 87 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option registers (PU0, PU2 to PU5, PU7) These registers are used to set whether to use an on-chip pull-up resistor at each port or not. By setting PU0, PU2 to PU5, and PU7, the on-chip pull-up resistors of the port pins corresponding to the bits in PU0, PU2 to PU5, and PU7 can be used.
Page 88 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Pull-Up Resistor Option Register (PU0, PU2 to PU5, PU7) Address: FF30H After reset: 00H Symbol PU03 PU02 PU01 PU00 Address: FF32H After reset: 00H Symbol PU25 PU24 PU23 PU22 PU21 PU20 Address: FF33H After reset: 00H Symbol PU36 PU35...
Page 89: Operations Of Port Function
CHAPTER 4 PORT FUNCTIONS 4.4 Operations of Port Function Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 90: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 8.38 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
Page 91 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Subsystem Watch timer, clock clock output oscillator function Prescaler Clock to Main system peripheral clock hardware Prescaler oscillator Standby CPU clock Wait controller controller STOP MCC FRC CSS PCC2 PCC1 PCC0 Processor clock control register (PCC) Internal bus...
Page 92: Registers To Control Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.3 Registers to Control Clock Generator The clock generator is controlled by the processor clock control register (PCC). The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor.
Page 93 CHAPTER 5 CLOCK GENERATOR Figure 5-3. Format of Processor Clock Control Register (PCC) Note 1 Address: FFFBH After reset: 04H Symbol PCC2 PCC1 PCC0 Note 2 Main system clock oscillation control Oscillation possible Oscillation stopped Note 3 Subsystem clock feedback resistor selection Internal feedback resistor used Internal feedback resistor not used CPU clock status...
Page 94: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR The fastest instructions of µ PD780024AS, 780034AS Subseries are carried out in two CPU clocks. The relationship of CPU clock (f ) and minimum instruction execution time is shown in Table 5-2. Table 5-2. Relationship of CPU Clock and Minimum Instruction Execution Time CPU Clock (f Minimum Instruction Execution Time: 2/f 0.24 µ...
Page 95: Subsystem Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (32.768 kHz TYP.) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and an inverted-phase clock signal to the XT2 pin.
Page 96 CHAPTER 5 CLOCK GENERATOR Cautions 1. When using the main system clock oscillator and a subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-4 and 5-5 to avoid an adverse effect from wiring capacitance. •...
Page 97 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
Page 98: Divider
CHAPTER 5 CLOCK GENERATOR 5.4.3 Divider The divider divides the main system clock oscillator output (f ) and generates various clocks. 5.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows.
Page 99: Clock Generator Operations
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC).
Page 100: Main System Clock Operations
CHAPTER 5 CLOCK GENERATOR 5.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
Page 101: Subsystem Clock Operations
CHAPTER 5 CLOCK GENERATOR Figure 5-7. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation Main system clock oscillation Subsystem clock oscillation CPU clock 5.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
Page 102 CHAPTER 5 CLOCK GENERATOR Table 5-3. Maximum Time Required for CPU Clock Switchover Set Value Before Set Value After Switchover Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 ×...
Page 103: System Clock And Cpu Clock Switching Procedure
CHAPTER 5 CLOCK GENERATOR 5.6.2 System clock and CPU clock switching procedure This section describes switching procedure between the system clock and CPU clock. Figure 5-8. System Clock and CPU Clock Switching RESET Interrupt request signal System clock CPU clock Lowest- Highest- Subsystem...
Page 104: Chapter 6 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.1 Functions of 16-Bit Timer/Event Counter 0 The 16-bit timer/event counter 0 has the following functions. • Interval timer • PPG output • Pulse width measurement • External event counter • Square-wave output (1) Interval timer TM0 generates interrupt request at the preset time interval.
Page 105: Configuration Of 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.2 Configuration of 16-Bit Timer/Event Counter 0 16-bit timer/event counter 0 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 0 Item Configuration 16 bits × 1 (TM0) Timer/counter 16-bit timer capture/compare register: 16 bits × 2 (CR00, CR01) Register Timer output 1 (TO0)
Page 106 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (1) 16-bit timer counter 0 (TM0) TM0 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of an input clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Page 107 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 CR00 is set by a 16-bit memory manipulation instruction. After RESET input, the value of CR00 is undefined. Cautions 1. Set a value other than 0000H in CR00 in the clear & start mode on match between TM0 and CR00.
Page 108: Registers To Control 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.3 Registers to Control 16-Bit Timer/Event Counter 0 The following five types of registers are used to control the 16-bit timer/event counter 0. • 16-bit timer mode control register 0 (TMC0) • Capture/compare control register 0 (CRC0) •...
Page 109 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-2. Format of 16-Bit Timer Mode Control Register 0 (TMC0) Address FF60H After reset: 00H Symbol TMC0 TMC03 TMC02 TMC01 OVF0 Operating mode TMC03 TMC02 TMC01 TO0 output timing selection Interrupt request generation and clear mode selection Operation stop No change...
Page 110 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (2) Capture/compare control register 0 (CRC0) This register controls the operation of the 16-bit timer capture/compare registers (CR00, CR01). CRC0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 00H. Figure 6-3.
Page 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (3) 16-bit timer output control register 0 (TOC0) This register controls the operation of the 16-bit timer/event counter 0 output controller. It sets R-S type flip-flop (LV0) setting/resetting, output inversion enabling/disabling, and 16-bit timer/event counter 0 timer output enabling/disabling.
Page 112 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (4) Prescaler mode register 0 (PRM0) This register is used to set 16-bit timer counter 0 (TM0) count clock and TI00, TI01 input valid edges. PRM0 is set by an 8-bit memory manipulation instruction. RESET input sets PRM0 value to 00H.
Page 113 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (5) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P70/TO0/TI00 pin for timer output, set PM70 and the output latch of P70 to 0. PM7 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM7 value to FFH.
Page 114: Operations Of 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4 Operations of 16-Bit Timer/Event Counter 0 6.4.1 Interval timer operations Setting the 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-7 allows operation as an interval timer. Interrupt request is generated repeatedly using the count value set in 16-bit timer capture/compare register 00 (CR00) beforehand as the interval.
Page 115 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-8. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00 (CR00) INTTM00 16-bit timer counter 0 OVF0 (TM0) Noise TI00/TO0/P70 eliminator Clear circuit Figure 6-9. Timing of Interval Timer Operation Count clock TM0 count value 0000H 0001H 0000H 0001H...
Page 116: Ppg Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.2 PPG output operations Setting the 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-10 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/TI00/P70 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit timer capture/compare register 01 (CR01) and in 16-bit timer capture/compare register 00 (CR00), respectively.
Page 117: Pulse Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/TO0/P70 pin and TI01/P71 pin using the 16-bit timer counter 0 (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/TO0/P70 pin.
Page 118 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-12. Configuration Diagram for Pulse Width Measurement by Free-Running Counter 16-bit timer counter 0 OVF0 (TM0) 16-bit timer capture/compare TI00/TO0/P70 register 01 (CR01) INTTM01 Internal bus Figure 6-13. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock 0000H...
Page 119 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (2) Measurement of two pulse widths with free-running counter When the 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-14), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/TO0/P70 pin and the TI01/P71 pin.
Page 120 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 • Capture operation (free-running mode) Capture register operation in capture trigger input is shown. Figure 6-15. CR01 Capture Operation with Rising Edge Specified Count clock n–3 n–2 n–1 TI00 Rising edge detection CR01 INTTM01 Figure 6-16.
Page 121 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-17), it is possible to measure the pulse width of the signal input to the TI00//TO0/P70 pin. When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the TI00/TO0/P70 pin, the value of TM0 is taken into 16-bit timer capture/compare register 01 (CR01) and an interrupt request signal (INTTM01) is set.
Page 122 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-18. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM0 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI00 pin input CR01 capture value...
Page 123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-19. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts at valid edge of TI00/TO0/P70 pin. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01...
Page 124: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/TO0/P70 pin with the 16-bit timer counter 0 (TM0). TM0 is incremented each time the valid edge specified with the prescaler mode register 0 (PRM0) is input. When the TM0 counted value matches the 16-bit timer capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.
Page 125: Square-Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-22. External Event Counter Configuration Diagram 16-bit timer capture/compare register 00 (CR00) Match INTTM00 Clear 16-bit timer counter 0 (TM0) OVF0 Noise eliminator 16-bit timer capture/compare Valid edge of TI00 Noise eliminator register 01 (CR01) Internal bus Figure 6-23.
Page 126 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-24. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on match between TM0 and CR00 (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 127 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-25. Square-Wave Output Operation Timing Count clock TM0 count value 0000H 0001H 0002H N–1 0000H 0001H 0002H N–1 0000H CR00 INTTM00 TO0 pin output Preliminary User’s Manual U16035EJ1V0UM...
Page 128: Cautions For 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5 Cautions for 16-Bit Timer/Event Counter 0 (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer counter 0 (TM0) is started asynchronously with the count clock. Figure 6-26.
Page 129 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (4) Capture register data retention timings If the valid edge of the TI00/TO0/P70 pin is input during 16-bit timer capture/compare register 01 (CR01) read, CR01 carries out capture operation but the capture value at this time is not guaranteed. However, the interrupt request flag (TMIF01) is set upon detection of the valid edge.
Page 130 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (6) Operation of OVF0 flag <1> OFV0 flag is set to 1 in the following case. Either the clear & start mode on match between TM0 and CR00 or the free-running mode that clears and starts at the valid edge of TIn is selected.
Page 131 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (9) Capture operation <1> If TI00 is specified as the valid edge of the count clock, capture operation by the capture register specified as the trigger for TI00 is not possible. <2> If both the rising and falling edges are selected as the valid edges of TI00, capture is not performed. <3>...
Page 132: Chapter 7 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 (TM50, TM51) have the following two modes. • Mode using 8-bit timer/event counters alone (single mode) • Mode using the cascade connection (16-bit resolution: cascade connection mode) These two modes are described next.
Page 133 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus 8-bit timer compare Selector INTTM50 register 50 (CR50) TI50/TO50/P72 Match 8-bit timer TO50/TI50/P72 counter 50 (TM50) Clear Invert level Selector TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 TCL502 TCL501 TCL500 8-bit timer mode control Timer clock select...
Page 134: Configurations Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.2 Configurations of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 consist of the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration Timer register 8-bit timer counter 5n (TM5n) Register...
Page 135: Registers To Control 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers to Control 8-Bit Timer/Event Counters 50 and 51 The following three types of registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock select register 5n (TCL5n) •...
Page 136 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-4. Format of Timer Clock Select Register 51 (TCL51) Address: FF79H After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection TI51 falling edge TI51 rising edge /2 (4.19 MHz) (1.04 MHz) (261 kHz)
Page 137 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-5. Format of 8-Bit Timer Mode Control Register 5n (TMC5n) Address: FF70H (TMC50) FF78H (TMC51) After reset: 00H Symbol TMC5n TCE5n TMC5n6 TMC5n4 LVS5n LVR5n TMC5n1 TOE5n TCE5n TM5n count operation control After clearing to 0, count operation disabled (prescaler disabled) Count operation start TMC5n6...
Page 138 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Caution Before clearing TCE5n to 0, set the interrupt mask flag (TMMK5n) to 1. This is because an interrupt may occur after TCE5n has been cleared. Clear TCE5n to 0 using the following procedure. TMMK5n = 1 ;...
Page 139 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P72/TO50/TI50 and P73/TI51/TO51 pins for timer output, set PM72, PM73, and output latches of P72 and P73 to 0. PM7 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 140: Operations Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 7.4.1 Interval timer (8-bit) operation The 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count values of the 8-bit timer counter 5n (TM5n) match the values set to CR5n, counting continues with the TM5n values cleared to 0 and the interrupt request signals (INTTM5n) are generated.
Page 141 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-7. Interval Timer Operation Timings (1/3) (a) Basic operation Count clock TM5n count value Start count Clear Clear CR5n TCE5n INTTM5n Interrupt request Interrupt request acknowledged acknowledged TO5n Interval time Interval time Interval time Remarks 1.
Page 142 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-7. Interval Timer Operation Timings (2/3) (b) When CR5n = 00H Count clock CR5n TCE5n INTTM5n TO5n Interval time (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt request acknowledged Interrupt request acknowledged TO5n...
Page 143 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-7. Interval Timer Operation Timings (3/3) (d) Operated by CR5n transition (M < N) Count clock CR5n TCE5n INTTM5n TO5n CR5n transition TM5n overflows since M < N (e) Operated by CR5n transition (M > N) Count clock N–1 M–1...
Page 144: External Event Counter Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI5n by the 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified with the timer clock select register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 145: Square-Wave Output (8-Bit Resolution) Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output (8-bit resolution) operation A square wave with any selected frequency is output at intervals of the value preset to the 8-bit timer compare register 5n (CR5n). TO5n pin output status is reversed at intervals of the count value preset to CR5n by setting bit 0 (TOE5n) of 8- bit timer mode control register 5n (TMC5n) to 1.
Page 146: 8-Bit Pwm Output Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.4 8-bit PWM output operation 8-bit timer/event counter operates as PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty rate pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of PWM pulse to CR5n, and the active level can be selected with bit 1 of TMC5n (TMC5n1).
Page 147 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-10. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N+1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level...
Page 148 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operated by CR5n transition Figure 7-11. Timing of Operation by CR5n Transition (a) CR5n value transits from N to M before overflow of TM5n Count clock TM5n N N+1 N+2 FFH 00H 01H M M+1 M+2 FFH 00H 01H 02H M M+1 M+2...
Page 149: Interval Timer (16-Bit) Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.5 Interval timer (16-bit) operation When “1” is set in bit 4 (TMC514) of 8-bit timer mode control register 51 (TMC51), the 16-bit resolution timer/counter mode is entered. The 8-bit timer/event counter operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit timer compare registers (CR50, CR51).
Page 150: Cautions For 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-12. 16-Bit Resolution Cascade Connection Mode Count clock TM50 N N+1 FFH 00H FFH 00H FFH 00H 01H N 00H 01H A 00H TM51 M–1 M B 00H CR50 CR51 TCE50 TCE51 INTTM50 Interval time...
Page 151 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation after compare register change during timer count operation If the value after the 8-bit timer compare register 5n (CR5n) is changed is smaller than the value of 8-bit timer counter 5n (TM5n), TM5n continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after CR5n is changed is smaller than the value (N) before it was changed, it is necessary to restart the timer after changing CR5n.
Page 152: Chapter 8 Watch Timer
CHAPTER 8 WATCH TIMER 8.1 Functions of Watch Timer The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 8-1 shows the watch timer block diagram. Figure 8-1.
Page 153: Configuration Of Watch Timer
CHAPTER 8 WATCH TIMER (1) Watch timer When the main system clock or subsystem clock is used, interrupt requests (INTWT) are generated at 2 second intervals. Remark f : Watch timer clock frequency (f or f : Main system clock oscillation frequency : Subsystem clock oscillation frequency (2) Interval timer Interrupt requests (INTWTI) are generated at the preset time interval.
Page 154: Register To Control Watch Timer
CHAPTER 8 WATCH TIMER 8.3 Register to Control Watch Timer Watch timer operation mode register (WTM) is a register to control watch timer. • Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control.
Page 155: Operations Of Watch Timer
CHAPTER 8 WATCH TIMER 8.4 Operations of Watch Timer 8.4.1 Watch timer operation The watch timer generates an interrupt request (INTWT) at a specific time interval (2 seconds) by using the main system clock or subsystem clock. The interrupt request is generated at the following time interval. •...
Page 156 CHAPTER 8 WATCH TIMER Figure 8-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time n x T n x T...
Page 157: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer has the following functions. • Watchdog timer • Interval timer • Oscillation stabilization time selection Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and the interval timer cannot be used simultaneously).
Page 158 CHAPTER 9 WATCHDOG TIMER (1) Watchdog timer mode A program loop is detected. Upon detection of the program loop, a non-maskable interrupt request or RESET can be generated. Table 9-1. Watchdog Timer Program Loop Detection Time Program Loop Detection Time ×...
Page 159: Configuration Of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Oscillation stabilization time select register (OSTS) 9.3 Registers to Control Watchdog Timer The following three types of registers are used to control the watchdog timer.
Page 160 CHAPTER 9 WATCHDOG TIMER (1) Watchdog timer clock select register (WDCS) This register sets overflow time of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input sets WDCS to 00H. Figure 9-2. Format of Watchdog Timer Clock Select Register (WDCS) Address: FF42H After reset: 00H Symbol...
Page 161 CHAPTER 9 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3. Format of Watchdog Timer Mode Register (WDTM) Address: FFF9H After reset: 00H Symbol...
Page 162 CHAPTER 9 WATCHDOG TIMER (3) Oscillation stabilization time select register (OSTS) A register to select oscillation stabilization time from reset time or STOP mode released time to the time when oscillation is stabilized. OSTS is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 163: Watchdog Timer Operations
CHAPTER 9 WATCHDOG TIMER 9.4 Watchdog Timer Operations 9.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any program loops. The program loop detection time interval is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS).
Page 164: Interval Timer Operation
CHAPTER 9 WATCHDOG TIMER 9.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. The interval time of interval timer is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS).
Page 165: Chapter 10 Clock Output/Buzzer Output Controller
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output select register (CKS) is output. In addition, the buzzer output is intended for square wave output of buzzer frequency selected with CKS.
Page 166: Configuration Of Clock Output/Buzzer Output Controller
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller consists of the following hardware. Table 10-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select register (CKS) Note Port mode register (PM7) Note See Figure 4-12 Block Diagram of P74 and P75.
Page 167 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 10-2. Format of Clock Output Select Register (CKS) Address: FF40H After reset: 00H R/W Symbol BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ output enable/disable specification Stop clock division circuit operation. BUZ fixed to low level. Enable clock division circuit operation.
Page 168 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register (PM7) This register sets port 7 input/output in 1-bit units. When using the P74/PCL pin for clock output and the P75/BUZ pin for buzzer output, set PM74, PM75 and the output latch of P74, P75 to 0.
Page 169: Operations Of Clock Output/Buzzer Output Controller
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.4 Operations of Clock Output/Buzzer Output Controller 10.4.1 Operation as clock output The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output select register (CKS) (clock pulse output in disabled status).
Page 170: Chapter 11 8-Bit A/D Converter ( Μ Pd780024As Subseries)
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.1 Functions of A/D Converter A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to 4 analog input channels (ANI0 to ANI3). (1) Hardware start Conversion is started by trigger input (ADTRG: rising edge, falling edge, or both rising and falling edges can be specified).
Page 171 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Figure 11-1. Block Diagram of 8-Bit A/D Converter Series resistor string ANI0/P10 Sample & hold circuit ANI1/P11 Voltage comparator ANI2/P12 ANI3/P13 Successive approximation register (SAR) Edge ADTRG/INTP3/P03 detector Controller INTAD0 INTP3 Edge A/D conversion result detector...
Page 172: Configuration Of A/D Converter
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.2 Configuration of A/D Converter The A/D converter consists of the following hardware. Table 11-1. Configuration of A/D Converter Item Configuration Analog input 4 channels (ANI0 to ANI3) Registers Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) Control registers A/D converter mode register 0 (ADM0)
Page 173 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (6) ANI0 to ANI3 pins These are four analog input pins to input analog signals to undergo A/D conversion to the A/D converter. ANI0 to ANI3 are alternate-function pins that can also be used for digital input. Cautions 1.
Page 174: Registers To Control A/D Converter
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.3 Registers to Control A/D Converter The following 4 types of registers are used to control the A/D converter. • A/D converter mode register 0 (ADM0) • Analog input channel specification register 0 (ADS0) •...
Page 175 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Figure 11-2. Format of A/D Converter Mode Register 0 (ADM0) Address: FF80H After reset: 00H R/W Symbol ADM0 ADCS0 TRG0 FR02 FR01 FR00 EGA01 EGA00 ADCS0 A/D conversion operation control Stop conversion operation. Enable conversion operation.
Page 176 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (2) Analog input channel specification register 0 (ADS0) This register specifies the analog voltage input port for A/D conversion. ADS0 is set by an 8-bit memory manipulation instruction. RESET input sets ADS0 to 00H. Figure 11-3.
Page 177: Operations Of A/D Converter
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.4 Operations of A/D Converter 11.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register 0 (ADS0). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 178 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Figure 11-5. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion operations are performed continuously until bit 7 (ADCS0) of the A/D converter mode register 0 (ADM0) is reset (0) by software.
Page 179: Input Voltage And Conversion Results
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the A/D conversion result (stored in the A/D conversion result register 0 (ADCR0)) is shown by the following expression. ×...
Page 180: A/D Converter Operation Mode
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.4.3 A/D converter operation mode Select one analog input channel from among ANI0 to ANI3 by the analog input channel specification register 0 (ADS0) to start A/D conversion. A/D conversion can be started in either of the following two ways. •...
Page 181 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Figure 11-7. A/D Conversion by Hardware Start (When Falling Edge Is Specified) ADTRG ADM0 set ADS0 rewrite ADCS0 = 1, TRG0 = 1 Standby Standby Standby A/D conversion ANIn ANIn ANIn ANIm ANIm ANIm...
Page 182 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (2) A/D conversion by software start When bit 6 (TRG0) and bit 7 (ADCS0) of the A/D converter mode register 0 (ADM0) are set to 0 and 1, respectively, A/D conversion of the voltage applied to the analog input pin specified by the analog input channel specification register 0 (ADS0) starts.
Page 183: How To Read A/D Converter Characteristics Table
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.5 How to Read A/D Converter Characteristics Table Here we will explain the special terms unique to A/D converters. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per 1 bit of digital output is called 1LSB (Least Significant Bit).
Page 184 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (4) Zero scale offset This shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0……000 to 0……001. If the actual measured value is greater than the theoretical value, it shows the difference between the actual measured value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
Page 185 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (8) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. Sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample &...
Page 186: Cautions For A/D Converter
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.6 Cautions for A/D Converter (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (ADCS0) of the A/D converter mode register 0 (ADM0) to 0). Figure 11-15 shows how to reduce the current consumption in the standby mode.
Page 187 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (4) Noise countermeasures To maintain the 8-bit resolution, attention must be paid to noise input to pin AV and pins ANI0 to ANI3. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 11-16 to reduce noise.
Page 188 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (7) Interrupt request flag (ADIF0) The interrupt request flag (ADIF0) is not cleared even if the analog input channel specification register 0 (ADS0) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS0 rewrite.
Page 189 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (10) Timing at which A/D conversion result is undefined The A/D conversion value may be undefined if the timing of completion of A/D conversion and the timing of stopping the A/D conversion conflict with each other. Therefore, read the A/D conversion result during the A/ D conversion operation.
Page 190 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (12) AV The AV pin is the analog circuit power supply pin. It supplies power to the input circuits of the ANI0 to ANI3 pins. Therefore, be sure to apply the same potential as V to this pin even for applications designed to switch to a backup battery for power supply.
Page 191 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (14) Internal equivalent circuit of ANI0 to ANI3 pins and permissible signal source impedance To complete sampling within the sampling time with sufficient A/D conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. Figure 11-22 shows the internal equivalent circuit of the ANI0 to ANI3 pins.
Page 192 CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Figure 11-23. Example of Connection If Signal Source Impedance Is High <Sensor internal circuit> <Microcontroller internal circuit> Output impedance ANIn of sensor µ C0 ≤ 0.1 F Lowpass filter is created. Remark n = 0 to 3 Preliminary User’s Manual U16035EJ1V0UM...
Page 193: Chapter 12 10-Bit A/D Converter ( Μ Pd780034As Subseries)
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) 12.1 Functions of A/D Converter A/D converter is a 10-bit resolution converter that converts analog inputs into digital signals. It can control up to 4 analog input channels (ANI0 to ANI3). (1) Hardware start Conversion is started by trigger input (ADTRG: rising edge, falling edge, or both rising and falling edges can be specified).
Page 194: Configuration Of A/D Converter
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) 12.2 Configuration of A/D Converter A/D converter consists of the following hardware. Table 12-1. Configuration of A/D Converter Item Configuration Analog input 4 channels (ANI0 to ANI3) Registers Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) Control registers A/D converter mode register 0 (ADM0)
Page 195: Registers To Control A/D Converter
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) (6) ANI0 to ANI3 pins These are four analog input pins to input analog signals to undergo A/D conversion to the A/D converter. ANI0 to ANI3 are alternate-function pins that can also be used for digital input. Cautions 1.
Page 196 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) Figure 12-2. Format of A/D Converter Mode Register 0 (ADM0) Address: FF80H After reset: 00H R/W Symbol ADM0 ADCS0 TRG0 FR02 FR01 FR00 EGA01 EGA00 ADCS0 A/D conversion operation control Stop conversion operation. Enable conversion operation.
Page 197 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) (2) Analog input channel specification register 0 (ADS0) This register specifies the analog voltage input port for A/D conversion. ADS0 is set by an 8-bit memory manipulation instruction. RESET input sets ADS0 to 00H. Figure 12-3.
Page 198: Operations Of A/D Converter
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) 12.4 Operations of A/D Converter 12.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register 0 (ADS0). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 199 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) Figure 12-5. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion operations are performed continuously until bit 7 (ADCS0) of the A/D converter mode register 0 (ADM0) is reset (0) by software.
Page 200: Input Voltage And Conversion Results
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) 12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (stored in the A/D conversion result register 0 (ADCR0)) is shown by the following expression. ×...
Page 201: A/D Converter Operation Mode
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) 12.4.3 A/D converter operation mode Select one analog input channel from among ANI0 to ANI3 by the analog input channel specification register 0 (ADS0) to start A/D conversion. A/D conversion can be started in either of the following two ways. •...
Page 202 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) (2) A/D conversion by software start When bit 6 (TRG0) and bit 7 (ADCS0) of the A/D converter mode register 0 (ADM0) are set to 0 and 1, respectively, A/D conversion of the voltage applied to the analog input pin specified by the analog input channel specification register 0 (ADS0) starts.
Page 203: How To Read A/D Converter Characteristics Table
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) 12.5 How to Read A/D Converter Characteristics Table Here we will explain the special terms unique to A/D converters. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per 1 bit of digital output is called 1LSB (Least Significant Bit).
Page 204 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) (4) Zero scale offset This shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0……000 to 0……001. If the actual measured value is greater than the theoretical value, it shows the difference between the actual measured value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
Page 205 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) (8) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. Sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample &...
Page 206: Cautions For A/D Converter
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) 12.6 Cautions for A/D Converter Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (ADCS0) of the A/D converter mode register 0 (ADM0) to 0). Figure 12-15 shows how to reduce the current consumption in the standby mode.
Page 207 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to pin AV and pins ANI0 to ANI3. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 12-16 to reduce noise.
Page 208 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) Figure 12-17. A/D Conversion End Interrupt Request Generation Timing ADM0 rewrite ADS0 rewrite ADIF is set but ANIm (start of ANIn conversion) (start of ANIm conversion) conversion has not ended. A/D conversion ANIn ANIn ANIm...
Page 209 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) (10) Timing at which A/D conversion result is undefined The A/D conversion value may be undefined if the timing of completion of A/D conversion and the timing of stopping the A/D conversion conflict with each other. Therefore, read the A/D conversion result during the A/ D conversion operation.
Page 210 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) (12) AV The AV pin is the analog circuit power supply pin. It supplies power to the input circuits of the ANI0 to ANI3 pins. Therefore, be sure to apply the same potential as V to this pin even for applications designed to switch to a backup battery for power supply.
Page 211 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) (14) Internal equivalent circuit of ANI0 to ANI3 pins and permissible signal source impedance To complete sampling within the sampling time with sufficient A/D conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. Figure 12-22 shows the internal equivalent circuit of the ANI0 to ANI3 pins.
Page 212 CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) Figure 12-23. Example of Connection If Signal Source Impedance Is High <Sensor internal circuit> <Microcontroller internal circuit> Output impedance ANIn of sensor µ C0 ≤ 0.1 F Lowpass filter is created. Remark n = 0 to 3 Preliminary User’s Manual U16035EJ1V0UM...
Page 213: Chapter 13 Serial Interface (Uart0)
CHAPTER 13 SERIAL INTERFACE (UART0) 13.1 Functions of Serial Interface The serial interface (UART0) has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. For details, see 13.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received.
Page 214 CHAPTER 13 SERIAL INTERFACE (UART0) Figure 13-1. Block Diagram of Serial Interface (UART0) Internal bus Asynchronous serial interface mode register 0 (ASIM0) Receive TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 IRDAM0 buffer register 0 (RXB0) Asynchronous serial interface status register 0 (ASIS0) Transmit Receive shift...
Page 215: Configuration Of Serial Interface
CHAPTER 13 SERIAL INTERFACE (UART0) 13.2 Configuration of Serial Interface The serial interface (UART0) consists of the following hardware. Table 13-1. Configuration of Serial Interface (UART0) Item Configuration Registers Transmit shift register 0 (TXS0) Receive shift register 0 (RX0) Receive buffer register 0 (RXB0) Control registers Asynchronous serial interface mode register 0 (ASIM0) Asynchronous serial interface status register 0 (ASIS0)
Page 216: Registers To Control Serial Interface
CHAPTER 13 SERIAL INTERFACE (UART0) (5) Receive controller The receive controller controls receive operations based on the values set to the asynchronous serial interface mode register 0 (ASIM0). During a receive operation, it performs error checking, such as for parity errors, and sets various values to the asynchronous serial interface status register 0 (ASIS0) according to the type of error that is detected.
Page 217 CHAPTER 13 SERIAL INTERFACE (UART0) Figure 13-3. Format of Asynchronous Serial Interface Mode Register 0 (ASIM0) Address: FFA0H After reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 IRDAM0 TXE0 RXE0 Operation mode RxD0/P23 pin function TxD0/P24 pin function Operation stop Port function (P23) Port function (P24) UART mode...
Page 218 CHAPTER 13 SERIAL INTERFACE (UART0) (2) Asynchronous serial interface status register 0 (ASIS0) When a receive error occurs during UART mode, this register indicates the type of error. ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets ASIS0 to 00H. Figure 13-4.
Page 219 CHAPTER 13 SERIAL INTERFACE (UART0) Figure 13-5. Format of Baud Rate Generator Control Register 0 (BRGC0) Address: FFA2H After reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 = 8.38 MHz) TPS02 TPS01 TPS00 Source clock selection for 5-bit counter P25/ASCK0 MDL03 MDL02...
Page 220: Operations Of Serial Interface
CHAPTER 13 SERIAL INTERFACE (UART0) 13.4 Operations of Serial Interface This section explains the three modes of the serial interface (UART0). 13.4.1 Operation stop mode Because serial transfer is not performed during this mode, the power consumption can be reduced. In addition, pins can be used as normal ports.
Page 221: Asynchronous Serial Interface (Uart) Mode
CHAPTER 13 SERIAL INTERFACE (UART0) 13.4.2 Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted or received. The on-chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates.
Page 222 CHAPTER 13 SERIAL INTERFACE (UART0) Address: FFA0H After reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 IRDAM0 TXE0 RXE0 Operation mode RxD0/P23 pin function TxD0/P24 pin function Operation stop Port function (P23) Port function (P24) UART mode Serial function (RxD0) (receive only) UART mode Port function (P23)
Page 223 CHAPTER 13 SERIAL INTERFACE (UART0) (b) Asynchronous serial interface status register 0 (ASIS0) ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets ASIS0 to 00H. Address: FFA1H After reset: 00H Symbol ASIS0 OVE0 Parity error flag No parity error Parity error (Transmit data parity not matched)
Page 224 CHAPTER 13 SERIAL INTERFACE (UART0) (c) Baud rate generator control register 0 (BRGC0) BRGC0 is set by an 8-bit memory manipulation instruction. RESET input sets BRGC0 to 00H. Address: FFA2H After reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 = 8.38 MHz)
Page 225 CHAPTER 13 SERIAL INTERFACE (UART0) The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. • Transmit/receive clock generation for baud rate by using main system clock The main system clock is divided to generate the transmit/receive clock. The baud rate generated from the main system clock is determined according to the following formula.
Page 226 CHAPTER 13 SERIAL INTERFACE (UART0) Table 13-3. Relationship Between Main System Clock and Baud Rate = 8.386 MHz = 8.000 MHz = 7.3728 MHz = 5.000 MHz = 4.1943 MHz Baud Rate (bps) BRGC0 ERR (%) BRGC0 ERR (%) BRGC0 ERR (%) BRGC0 ERR (%)
Page 227 CHAPTER 13 SERIAL INTERFACE (UART0) • Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter’s division rate [1/(16 + k)]. Figure 13-6 shows an example of a baud rate error tolerance range. Figure 13-6.
Page 228 CHAPTER 13 SERIAL INTERFACE (UART0) (2) Communication operations (a) Data format Figure 13-7 shows the format of the transmit/receive data. Figure 13-7. Format of Transmit/Receive Data in Asynchronous Serial Interface 1 data frame Start Parity Stop bit Character bits 1 data frame consists of the following bits. •...
Page 229 CHAPTER 13 SERIAL INTERFACE (UART0) (b) Parity types and operations The parity bit is used to detect bit errors in communication data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected.
Page 230 CHAPTER 13 SERIAL INTERFACE (UART0) (c) Transmission The transmit operation is enabled when bit 7 (TXE0) of the asynchronous serial interface mode register 0 (ASIM0) is set (1). The transmit operation is started when transmit data is written to the transmit shift register 0 (TXS0).
Page 231 CHAPTER 13 SERIAL INTERFACE (UART0) (d) Reception The receive operation is enabled when bit 6 (RXE0) of the asynchronous serial interface mode register 0 (ASIM0) is set (1), and input via the RxD0 pin is sampled. The serial clock specified by ASIM0 is used to sample the RxD0 pin. When the RxD0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed.
Page 232 CHAPTER 13 SERIAL INTERFACE (UART0) (e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of data reception, an error flag is set to the asynchronous serial interface status register 0 (ASIS0), a receive error interrupt request (INTSER0) will occur.
Page 233: Infrared Data Transfer Mode
CHAPTER 13 SERIAL INTERFACE (UART0) 13.4.3 Infrared data transfer mode In infrared data transfer mode, the following data format pulse output and pulse receiving are enabled. The relationship between the main system clock and baud rate is shown in Table 13-3. (1) Data format Figure 16-11 compares the data format used in UART mode with that used in infrared data transfer mode.
Page 234 CHAPTER 13 SERIAL INTERFACE (UART0) (2) Bit rate and pulse width Table 13-5 lists bit rates, bit rate error tolerances, and pulse width values. Table 13-5. Bit Rate and Pulse Width Values 3/16 Pulse Width Bit Rate Bit Rate Error Tolerance Pulse Width Minimum Value Maximum Pulse Width <Nominal Value>...
Page 235 CHAPTER 13 SERIAL INTERFACE (UART0) (3) Input data and internal signals • Transmit operation timing UART Start bit Stop bit output data UART (Inverted data) Infrared data transfer enable signal TxD0 pin output signal • Receive operation timing Data reception is delayed for one-half of the specified baud rate. UART Start bit Stop bit...
Page 236: Chapter 14 Serial Interface (Sio3)
CHAPTER 14 SERIAL INTERFACE (SIO3) The serial interface (SIO3) incorporates two 3-wire serial I/O mode channels (SIO30, SIO31). These two channels have exactly the same functions. 14.1 Functions of Serial Interface The serial interface (SIO3n) has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed.
Page 237: Configuration Of Serial Interface
CHAPTER 14 SERIAL INTERFACE (SIO3) 14.2 Configuration of Serial Interface The serial interface (SIO3n) consists of the following hardware. Table 14-1. Configuration of Serial Interface (SIO3n) Item Configuration Register Serial I/O shift register 3n (SIO3n) Control register Serial operation mode register 3n (CSIM3n) Remark n = 0, 1 (1) Serial I/O shift register 3n (SIO3n) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations)
Page 238: Registers To Control Serial Interface
CHAPTER 14 SERIAL INTERFACE (SIO3) 14.3 Registers to Control Serial Interface The serial interface (SIO3n) is controlled by serial operation mode register 3n (CSIM3n). (1) Serial operation mode register 30 (CSIM30) This register is used to enable or disable SIO30’s serial clock, operation modes, and specific operations. CSIM30 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 239 CHAPTER 14 SERIAL INTERFACE (SIO3) Figure 14-2. Format of Serial Operation Mode Register 30 (CSIM30) Address: FFB0H After reset: 00H Symbol CSIM30 CSIE30 MODE0 SCL301 SCL300 Enable/disable specification for SIO30 CSIE30 Shift register operation Serial counter Port Note 1 Operation disabled Clear Port function Note 2...
Page 240 CHAPTER 14 SERIAL INTERFACE (SIO3) (2) Serial operation mode register 31 (CSIM31) This register is used to enable or disable SIO31’s serial clock, operation modes, and specific operations. CSIM31 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM31 to 00H. Caution In 3-wire serial I/O mode, set the port mode register (PMXX) as follows.
Page 241 CHAPTER 14 SERIAL INTERFACE (SIO3) Figure 14-3. Format Serial Operation Mode Register 31 (CSIM31) Address: FFB8H After reset: 00H Symbol CSIM31 CSIE31 MODE1 SCL311 SCL310 Enable/disable specification for SIO31 CSIE31 Shift register operation Serial counter Port Note 1 Operation disabled Clear Port function Note 2...
Page 242: Operations Of Serial Interface
CHAPTER 14 SERIAL INTERFACE (SIO3) 14.4 Operations of Serial Interface This section explains the two modes of the serial interface (SIO3n). 14.4.1 Operation stop mode Because the serial transfer is not performed during this mode, the power consumption can be reduced. In addition, pins can be used as normal I/O ports.
Page 243: 3-Wire Serial I/O Mode
CHAPTER 14 SERIAL INTERFACE (SIO3) 14.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection to a peripheral I/O incorporating a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK3n), serial output line (SO3n), and serial input line (SI3n).
Page 244 CHAPTER 14 SERIAL INTERFACE (SIO3) Address: FFB0H (SIO30), FFB8H (SIO31) After reset: 00H Symbol CSIM3n CSIE3n MODEn SCL3n1 SCL3n0 Enable/disable specification for SIO3n CSIE3n Shift register operation Serial counter Port Note 1 Operation disabled Clear Port function Note 2 Operation enabled Count operation enabled Serial function + port function Transfer operation modes and flags...
Page 245 CHAPTER 14 SERIAL INTERFACE (SIO3) (2) Communication operations In the 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is transmitted or received in synchronization with the serial clock. The serial I/O shift register 3n (SIO3n) is shifted in synchronization with the falling edge of the serial clock. Transmission data is held in the SO3n latch and is output from the SO3n pin.
Page 246: Chapter 15 Interrupt Functions
CHAPTER 15 INTERRUPT FUNCTIONS 15.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in an interrupt disabled state. It does not undergo priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 247 CHAPTER 15 INTERRUPT FUNCTIONS Table 15-1. Interrupt Source List Vector Basic Interrupt Source Interrupt Default Internal/ Table Configuration Note 1 Type Priority External Name Trigger Note 2 Address Type Non- — INTWDT Watchdog timer overflow Internal 0004H maskable (with watchdog timer mode 1 selected) Maskable INTWDT Watchdog timer overflow...
Page 248 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt Vector table Priority controller request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table Interrupt Priority controller address generator request Standby release signal...
Page 249 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (INTKR) Internal bus Interrupt Vector table Falling Priority controller request address generator edge detector 1 when MEM = 01H Standby release signal (E) Software interrupt Internal bus Interrupt Vector table...
Page 250: Registers To Control Interrupt Function
CHAPTER 15 INTERRUPT FUNCTIONS 15.3 Registers to Control Interrupt Function The following 7 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specification flag register (PR0L, PR0H, PR1L) •...
Page 251 CHAPTER 15 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 252 CHAPTER 15 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt service. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register MK0, they are set by a 16-bit memory manipulation instruction.
Page 253 CHAPTER 15 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flags are used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set by a 16-bit memory manipulation instruction.
Page 254 CHAPTER 15 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP3. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H.
Page 255 CHAPTER 15 INTERRUPT FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for an interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control nesting processing are mapped.
Page 256: Interrupt Servicing Operations
CHAPTER 15 INTERRUPT FUNCTIONS 15.4 Interrupt Servicing Operations 15.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag and ISP flag are reset (0), and the contents of the vector table are loaded into PC and branched.
Page 257 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-8. Non-Maskable Interrupt Request Generation to Acknowledge Flowchart Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending Interrupt...
Page 258 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-10. Non-Maskable Interrupt Request Acknowledge Operation (a) If a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main routine Execution of NMI request <1> NMI request <1> NMI request <2> held pending NMI request <2>...
Page 259: Maskable Interrupt Request Acknowledge Operation
CHAPTER 15 INTERRUPT FUNCTIONS 15.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if in the interrupt enable state (when IE flag is set to 1).
Page 260 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-11. Interrupt Request Acknowledge Processing Algorithm Start ××IF = 1? Yes (Interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 261: Software Interrupt Request Acknowledge Operation
CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-12. Interrupt Request Acknowledge Timing (Minimum Time) 6 clocks PSW and PC save, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 15-13.
Page 262: Nesting Interrupt Servicing
CHAPTER 15 INTERRUPT FUNCTIONS 15.4.4 Nesting interrupt servicing Nesting occurs when another interrupt request is acknowledged during execution of an interrupt. Nesting does not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except non- maskable interrupts). Also, when an interrupt request is acknowledged, interrupt request acknowledge becomes disabled (IE = 0).
Page 263 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-14. Nesting Examples (1/2) Example 1. Nesting occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI RETI...
Page 264 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-14. Nesting Examples (2/2) Example 3. Nesting does not occur because interrupt is not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 0 1 instruction execution RETI Interrupt is not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request...
Page 265: Interrupt Request Hold
CHAPTER 15 INTERRUPT FUNCTIONS 15.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 266: Chapter 16 Standby Function
CHAPTER 16 STANDBY FUNCTION 16.1 Standby Function and Configuration 16.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. The system clock oscillator continues oscillating.
Page 267: Standby Function Control Register
CHAPTER 16 STANDBY FUNCTION 16.1.2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 268: Operations Of Standby Function
CHAPTER 16 STANDBY FUNCTION 16.2 Operations of Standby Function 16.2.1 HALT mode (1) HALT mode setting and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock.
Page 269 CHAPTER 16 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released with the following three types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledge is enabled, vectored interrupt service is carried out.
Page 270 CHAPTER 16 STANDBY FUNCTION (c) Release by RESET input When RESET signal is input, HALT mode is released. And, as in the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 16-3. HALT Mode Release by RESET Input Wait HALT instruction : 15.6 ms)
Page 271: Stop Mode
CHAPTER 16 STANDBY FUNCTION 16.2.2 STOP mode (1) STOP mode setting and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull-up resistor to minimize the leakage current at the crystal oscillator.
Page 272 CHAPTER 16 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
Page 273 CHAPTER 16 STANDBY FUNCTION (b) Release by RESET input The STOP mode is released when RESET signal is input, and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 16-5. STOP Mode Release by RESET Input Wait STOP instruction : 15.6 ms)
Page 274: Chapter 17 Reset Function
CHAPTER 17 RESET FUNCTION 17.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 275 CHAPTER 17 RESET FUNCTION Figure 17-2. Timing of Reset by RESET Input Oscillation Normal operation Reset period stabilization Normal operation (Reset processing) (Oscillation stop) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 17-3. Timing of Reset Due to Watchdog Timer Overflow Oscillation Normal operation Reset period...
Page 276 CHAPTER 17 RESET FUNCTION Table 17-1. Hardware Statuses After Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General-purpose register...
Page 277 CHAPTER 17 RESET FUNCTION Table 17-1. Hardware Statuses After Reset (2/2) Hardware Status After Reset Clock output/buzzer output controller Clock output select register (CKS) A/D converter Conversion result register (ADCR0) Mode register (ADM0) Analog input channel specification register (ADS0) Serial interface (UART0) Asynchronous serial interface mode register (ASIM0) Asynchronous serial interface status register (ASIS0) Baud rate generator control register (BRGC0)
Page 278: Chapter 18 Μ Pd78F0034Bs
CHAPTER 18 µ PD78F0034BS The µ PD78F0034BS is provided as the flash memory version of the µ PD780024AS, 780034AS Subseries. The µ PD78F0034BS replaces the internal mask ROM of the µ PD780034BS with flash memory to which a program can be written, erased and overwritten while mounted on the board. Table 18-1 lists the differences among the µ...
Page 279: Memory Size Switching Register
CHAPTER 18 µ PD78F0034BS 18.1 Memory Size Switching Register The µ PD78F0034BS allows users to select the internal memory capacity using the memory size switching register (IMS) so that the same memory map as that of the µ PD780021AS, 780022AS, 780023AS, 780024AS and µ...
Page 280: Flash Memory Programming
CHAPTER 18 µ PD78F0034BS 18.2 Flash Memory Programming On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done after connecting a dedicated flash programmer (Flashpro III (FL-PR3, PG-FP3)) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro III.
Page 281: Flash Memory Programming Function
CHAPTER 18 µ PD78F0034BS Figure 18-2. Format of Communication Mode Selection pulses 10 V RESET Flash memory write mode 18.2.2 Flash memory programming function Flash memory writing is performed through command and data transmit/receive operations using the selected communication mode. The main functions are listed in Table 18-4. Table 18-4.
Page 282: Connection Of Flashpro Iii
CHAPTER 18 µ PD78F0034BS 18.2.3 Connection of Flashpro III Connection of the Flashpro III and the µ PD78F0034BS differs depending on communication mode (3-wire serial I/O and UART). Each type of connection is shown in Figures 18-3 to 18-6. Figure 18-3. Connection of Flashpro III in 3-Wire Serial I/O Mode µ...
Page 283 CHAPTER 18 µ PD78F0034BS Figure 18-6. Connection of Flashpro III in Pseudo 3-Wire Serial I/O Mode µ Flashpro III PD78F0034BS RESET RESET P72 (Serial clock input) P70 (Serial data input) P71 (Serial data output) Preliminary User’s Manual U16035EJ1V0UM...
Page 284: Chapter 19 Instruction Set
CHAPTER 19 INSTRUCTION SET This chapter lists each instruction set of the µ PD780024AS, 780034AS Subseries in table form. For details of its operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). Preliminary User’s Manual U16035EJ1V0UM...
Page 285: Conventions
CHAPTER 19 INSTRUCTION SET 19.1 Conventions 19.1.1 Operand identifiers and specification methods Operands are written in “Operand” column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more methods, select one of them.
Page 286: Description Of "Operation" Column
CHAPTER 19 INSTRUCTION SET 19.1.2 Description of “operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 287: Operation List
CHAPTER 19 INSTRUCTION SET 19.2 Operation List Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 r ← byte 8-bit data r, #byte – transfer (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte –...
Page 288 CHAPTER 19 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 rp ← word 16-bit MOVW rp, #word – data (saddrp) ← word saddrp, #word transfer sfrp ← word sfrp, #word – AX ←...
Page 289 CHAPTER 19 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A, CY ← A – byte × × × 8-bit A, #byte – operation (saddr), CY ← (saddr) – byte × ×...
Page 290 CHAPTER 19 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A ← A byte × 8-bit A, #byte – operation (saddr) ← (saddr) byte × saddr, #byte Note 3 A ← A r ×...
Page 291 CHAPTER 19 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 AX, CY ← AX + word × × × 16-bit ADDW AX, #word – operation AX, CY ← AX – word ×...
Page 292 CHAPTER 19 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 CY ← CY (saddr.bit) × AND1 CY, saddr.bit manipu- CY ← CY sfr.bit × CY, sfr.bit – late CY ← CY A.bit ×...
Page 293 CHAPTER 19 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) Call/return CALL !addr16 – PC ← addr16, SP ← SP – 2 (SP –...
Page 294 CHAPTER 19 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Condi- saddr.bit, $addr16 tional PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...
Page 295: Instructions Listed By Addressing Type
CHAPTER 19 INSTRUCTION SET 19.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Preliminary User’s Manual U16035EJ1V0UM...
Page 296 CHAPTER 19 INSTRUCTION SET Second Operand [HL + byte] Note #byte saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 None First Operand [HL + C] ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC SUBC SUBC ADDC SUBC B, C...
Page 297 CHAPTER 19 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand Note #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 298 CHAPTER 19 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U16035EJ1V0UM...
Page 299: Appendix A Differences Between Μ Pd780024A, 780024As, 780034A
APPENDIX A DIFFERENCES BETWEEN µ PD780024A, 780024AS, 780034A, AND 780034AS SUBSERIES Table A-1 shows the major differences between µ PD780024A, 780024AS, 780034A, and 780034AS Subseries. Table A-1. Major Differences Between µ PD780024A, 780024AS, 780034A, and 780034AS Subseries µ PD780024A µ PD780034A µ...
Page 300: Appendix B Development Tools
APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µ PD780024AS, 780034AS Subseries. Figure B-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products compatible with IBM PC/AT computers are compatible with PC98-NX series computers.
Page 301 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tool • System simulator • Integrated debugger • Device file Embedded Software •...
Page 302: Language Processing Software
APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software This is a software package that includes the development tools common to the SP78K0 78K/0 Series. 78K/0 Series Software Package Part number: µ S××××SP78K0 This assembler converts programs written in mnemonics into object codes RA78K0 executable with a microcontroller.
Page 303: Flash Memory Writing Tools
APPENDIX B DEVELOPMENT TOOLS µ S××××SP78K0 ×××× Host machine Supply medium AB17 PC-9800 Series, Windows (Japanese version) CD-ROM IBM PC/AT or compatibles BB17 Windows (English version) µ S××××RA78K0 µ S××××CC78K0 ×××× Host machine Supply medium AB13 PC-9800 Series, Windows (Japanese version) 3.5-inch 2HD FD IBM PC/AT or compatibles BB13...
Page 304: Debugging Tools
APPENDIX B DEVELOPMENT TOOLS B.3 Debugging Tools B.3.1 Hardware IE-78K0-NS The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to integrated In-Circuit Emulator debugger (ID78K0-NS). This emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine.
Page 305: Software
APPENDIX B DEVELOPMENT TOOLS B.3.2 Software SM78K0 This system simulator is used to perform debugging at C source level or assembler System Simulator level while simulating the operation of the target system on a host machine. This simulator runs on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency...
Page 306: Appendix C Embedded Software
APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of the µ PD780024AS, 780034AS Subseries, the following embedded software products are available. Real-Time OS RX78K/0 is a real-time OS conforming to the µ ITRON specifications. RX78K0 Real-time OS Tool (configurator) for generating nucleus of RX78K0 and plural information tables is supplied.
Page 307: Appendix D Register Index
APPENDIX D REGISTER INDEX D.1 Register Name Index A/D conversion result register 0 (ADCR0) … 172, 194 A/D converter mode register 0 (ADM0) … 174, 195 Analog input channel specification register 0 (ADS0) … 176, 195 Asynchronous serial interface mode register 0 (ASIM0) … 216 Asynchronous serial interface status register 0 (ASIS0) …...
Page 308 APPENDIX D REGISTER INDEX Port 3 (P3) … 79 Port 4 (P4) … 81 Port 5 (P5) … 82 Port 7 (P7) … 83 Port mode register 0 (PM0) … 85 Port mode register 2 (PM2) … 85 Port mode register 3 (PM3) … 85 Port mode register 4 (PM4) …...
Page 309: Register Symbol Index
APPENDIX D REGISTER INDEX D.2 Register Symbol Index ADCR0: A/D conversion result register 0 … 172, 194 ADM0: A/D converter mode register 0 … 174, 195 ADS0: Analog input channel specification register 0 … 176, 197 ASIM0: Asynchronous serial interface mode register 0 … 216 ASIS0: Asynchronous serial interface status register 0 …...
Page 310 APPENDIX D REGISTER INDEX Port 7 … 83 PCC: Processor clock control register … 93 PM0: Port mode register 0 … 85 PM2: Port mode register 2 … 85 PM3: Port mode register 3 … 85 PM4: Port mode register 4 … 85 PM5: Port mode register 5 …...
Page 311 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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NEC mPD780024AS Series Preliminary User's Manual

Chapter 1 Outline

Chapter 2 Pin Function

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer/Event Counter 0

Chapter 7 8-Bit Timer/Event Counters 50 and 51

Chapter 8 Watch Timer

Chapter 9 Watchdog Timer

Chapter 10 Clock Output/Buzzer Output Controller

CHAPTER 11 8-BIT A/D CONVERTER ( Μ PD780024AS SUBSERIES)

CHAPTER 12 10-BIT A/D CONVERTER ( Μ PD780034AS SUBSERIES)

Chapter 13 Serial Interface (Uart0)

Chapter 14 Serial Interface (Sio3)

Chapter 15 Interrupt Functions

Chapter 16 Standby Function

Chapter 17 Reset Function

CHAPTER 18 Μ PD78F0034BS

Chapter 19 Instruction Set

APPENDIX A DIFFERENCES between Μ PD780024A, 780024AS, 780034A

Appendix B Development Tools

Appendix C Embedded Software

Appendix D Register Index

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Summary of Contents for NEC mPD780024AS Series