NEC mPD780208 Subseries User Manual

8-bit single-chip microcontrollers

page of 418

/ 418
Contents
Table of Contents
Bookmarks

Table of Contents

Quick Links

Download this manual

User's Manual

µ PD780208 Subseries

8-Bit Single-Chip Microcontrollers

µ PD780204

µ PD780204A

µ PD780205

µ PD780205A

µ PD780206

µ PD780208

µ PD78P0208

Document No.

U11302EJ4V0UM00 (4th edition)

Date Published July 2003 N CP(K)

Printed in Japan

Table of Contents

Summary of Contents for NEC mPD780208 Subseries

Page 1 User’s Manual µ PD780208 Subseries 8-Bit Single-Chip Microcontrollers µ PD780204 µ PD780204A µ PD780205 µ PD780205A µ PD780206 µ PD780208 µ PD78P0208 Document No. U11302EJ4V0UM00 (4th edition) Date Published July 2003 N CP(K) Printed in Japan...
Page 2 [MEMO] User’s Manual U11302EJ4V0UM...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. FIP and IEBus are trademarks of NEC Electronics Corporation. MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition Page Description Throughout Addition of the following products to target products • µ PD780204A • µ PD780205A Deletion of the following package from target products • µ PD78P0208KL-T (100-pin ceramic WQFN) CHAPTER 1 OUTLINE p.29 •...
Page 7: User's Manual U11302Ej4V0Um
INTRODUCTION Readers This manual has been prepared for user engineers who wish to understand the functions of the µ PD780208 Subseries and design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
Page 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µ PD780204, 780205, 780206, 780208 Data Sheet U10436E µ PD78P0208 Data Sheet U11295E µ...
Page 9 Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 10: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ......................... 24 Features ..........................24 Applications ......................... 25 Ordering Information ......................25 Quality Grade ........................25 Pin Configuration (Top View) .................... 26 78K/0 Series Lineup ......................29 Block Diagram ........................31 Overview of Functions ....................... 32 Mask Options ........................
Page 11 3.1.4 Data memory addressing ......................Processor Registers ......................60 3.2.1 Control registers ........................3.2.2 General-purpose registers ...................... 3.2.3 Special-function registers (SFRs) ................... Instruction Address Addressing ..................68 3.3.1 Relative addressing ......................... 3.3.2 Immediate addressing ......................3.3.3 Table indirect addressing ......................3.3.4 Register addressing ........................
Page 12 5.4.3 Divider ............................113 5.4.4 When subsystem clock is not used ..................113 Clock Generator Operations ..................... 114 5.5.1 Main system clock operations ....................115 5.5.2 Subsystem clock operations ....................116 Changing System Clock and CPU Clock Settings ............117 5.6.1 Time required for switchover between system clock and CPU clock ........
Page 13 CHAPTER 10 CLOCK OUTPUT CONTROLLER ................. 182 10.1 Clock Output Controller Functions .................. 182 10.2 Clock Output Controller Configuration ................183 10.3 Clock Output Function Control Registers ..............183 CHAPTER 11 BUZZER OUTPUT CONTROLLER ................186 11.1 Buzzer Output Controller Functions ................186 11.2 Buzzer Output Controller Configuration .................
Page 14 15.7 Key Scan Flag and Key Scan Data .................. 314 15.7.1 Key scan flag ........................... 314 15.7.2 Key scan data .......................... 314 15.8 Light Leakage of VFD ......................315 15.9 Display Examples ....................... 317 15.9.1 Segment type (display mode 1: DSPM05 = 0) ..............318 15.9.2 Dot type (display mode 1: DSPM05 = 0) ................
Page 15 CHAPTER 20 INSTRUCTION SET ....................... 383 20.1 Conventions ........................384 20.1.1 Operand identifiers and description methods ................ 384 20.1.2 Description of “operation” column ..................385 20.1.3 Description of “flag operation” column ................... 385 20.2 Operation List ........................386 20.3 Instructions Listed by Addressing Type ................. 394 APPENDIX A DIFFERENCES BETWEEN µ...
Page 16 LIST OF FIGURES (1/6) Figure No. Title Page Pin I/O Circuits ..........................Memory Map ( µ PD780204 and µ PD780204A) ................Memory Map ( µ PD780205 and µ PD780205A) ................Memory Map ( µ PD780206) ......................Memory Map ( µ PD780208) ......................Memory Map ( µ...
Page 17 LIST OF FIGURES (2/6) Figure No. Title Page Block Diagram of 16-Bit Timer/Event Counter (Timer Mode) ............123 Block Diagram of 16-Bit Timer/Event Counter (PWM Mode) ............124 Block Diagram of 16-Bit Timer/Event Counter Output Controller ..........125 Format of Timer Clock Select Register 0 ..................128 Format of 16-Bit Timer Mode Control Register ................
Page 18 LIST OF FIGURES (3/6) Figure No. Title Page Watch Timer Block Diagram ......................170 Format of Timer Clock Select Register 2 ..................171 Format of Watch Timer Mode Control Register ................172 Watchdog Timer Block Diagram ..................... 176 Format of Timer Clock Select Register 2 ..................178 Format of Watchdog Timer Mode Register ..................
Page 19 LIST OF FIGURES (4/6) Figure No. Title Page 13-16 Data ..............................229 13-17 Acknowledge Signal ........................230 13-18 BUSY and READY Signals ......................231 13-19 RELT, CMDT, RELD, and CMDD Operations (Master) ..............236 13-20 RELD and CMDD Operations (Slave) .................... 236 13-21 ACKT Operation ..........................
Page 20 LIST OF FIGURES (5/6) Figure No. Title Page 15-1 VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0) ........... 300 15-2 VFD Controller/Driver Block Diagram .................... 302 15-3 Format of Display Mode Register 0 ....................305 15-4 Format of Display Mode Register 1 ....................307 15-5 Format of Display Mode Register 2 ....................
Page 21 LIST OF FIGURES (6/6) Figure No. Title Page 16-12 Interrupt Request Acknowledge Processing Algorithm ..............351 16-13 Interrupt Request Acknowledgment Timing (Minimum Time) ............352 16-14 Interrupt Request Acknowledgment Timing (Maximum Time) ............352 16-15 Multiple Interrupt Servicing Example ....................354 16-16 Interrupt Request Hold ........................
Page 22 LIST OF TABLES (1/2) Table No. Title Page Mask Options in Mask ROM Versions ................... Types of Pin I/O Circuits ......................... Internal ROM Capacity ........................Vector Table ............................ Special-Function Register List ......................Port Functions ..........................Port Configuration ........................... Port Mode Register and Output Latch Setting When Alternate Function Is Used ...... Comparison Between Mask Option of Mask ROM Version and µ...
Page 23 LIST OF TABLES (2/2) Table No. Title Page Interval Timer Interval Time ......................181 10-1 Clock Output Controller Configuration ................... 183 11-1 Buzzer Output Controller Configuration ..................186 12-1 A/D Converter Configuration ......................190 13-1 Differences Between Channels 0 and 1 ..................205 13-2 Modes of Serial Interface Channel 0 ....................
Page 24: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features Internal high-capacity ROM and RAM Item Program Memory Data Memory PROM Internal High- Buffer RAM VFD Display Internal Part Number Speed RAM Expansion RAM µ PD780204 32 KB — 1024 bytes 64 bytes 80 bytes None µ...
Page 25: Applications
CHAPTER 1 OUTLINE 1.2 Applications Compact home stereo sets, cassette decks, tuners, CD players, VCRs, etc. 1.3 Ordering Information Part Number Package Internal ROM µ PD780204GF-xxx-3BA 100-pin plastic QFP (14 x 20) Mask ROM µ PD780204AGF-xxx-3BA 100-pin plastic QFP (14 x 20) Mask ROM µ...
Page 26: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) (1) Normal operating mode • 100-pin plastic QFP (14 x 20) µ PD780204GF-xxx-3BA, 780204AGF-xxx-3BA, 780205GF-xxx-3BA, 780205AGF-xxx-3BA, µ PD780206GF-xxx-3BA, 780208GF-xxx-3BA, 78P0208GF-3BA P87/FIP20 LOAD P36/BUZ P90/FIP21 P35/PCL P91/FIP22 P34/TI2 P92/FIP23 P33/TI1 P93/FIP24 P32/TO2 P94/FIP25 P31/TO1 P95/FIP26 P30/TO0...
Page 27 CHAPTER 1 OUTLINE ANI0 to ANI7: Analog input P110 to P117: Port 11 Analog power supply P120 to P127: Port 12 Analog reference voltage PCL: Programmable clock Analog ground RESET: Reset BUSY: Busy SB0, SB1: Serial bus BUZ: Buzzer clock SCK0, SCK1: Serial clock FIP0 to FIP52:...
Page 28 CHAPTER 1 OUTLINE (2) PROM programming mode • 100-pin plastic QFP (14 x 20) µ PD78P0208GF-3BA RESET Open Open Cautions 1. (L): Connect independently to V via a pull-down resistor. 2. (D): Connect via a driver. 3. V Connect to ground. 4.
Page 29: Series Lineup
CHAPTER 1 OUTLINE 1.6 78K/0 Series Lineup The 78K/0 Series product lineup is illustrated below. The part numbers in boxes indicate subseries names. Products in mass production Products under development Y subseries products are compatible with I C bus. Control µ...
Page 30 CHAPTER 1 OUTLINE The following lists the main functional differences between subseries products. • Non-Y subseries Function Timer 8-Bit 10-Bit 8-Bit Serial Interface External Capacity MIN. (Bytes) 8-Bit 16-Bit Watch WDT A/D Expansion Subseries Name Value µ √ Control PD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch –...
Page 31: Block Diagram
CHAPTER 1 OUTLINE 1.7 Block Diagram TO0/P30 16-bit timer/ Port 0 P01 to P03 TI0/P00 event counter TO1/P31 8-bit timer/ Port 1 P10 to P17 event counter 1 TI1/P33 TO2/P32 Port 2 8-bit timer/ P20 to P27 TI2/P34 event counter 2 Port 3 P30 to P37 Watchdog timer...
Page 32: Overview Of Functions
CHAPTER 1 OUTLINE 1.8 Overview of Functions µ PD780206 µ PD780208 µ PD78P0208 µ PD780204 µ PD780205 Part Number µ PD780204A µ PD780205A Item Mask ROM One-time Internal memory PROM 32 KB Note 1 40 KB Note 1 48 KB 60 KB 60 KB Note 2...
Page 33: Mask Options
CHAPTER 1 OUTLINE µ PD780205 µ PD780204 µ PD780206 µ PD780208 µ PD78P0208 Part Number Item µ PD780204A µ PD780205A Timer • 16-bit timer/event counter: 1 channel • 8-bit timer/event counter: 2 channels • Watch timer: 1 channel • Watchdog timer: 1 channel Timer output 3 outputs (14-bit PWM generation possible from one output)
Page 34: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List 2.1.1 Normal operating mode pins (1) Port pins (1/2) After Alternate Pin Name Function Reset Function Port 0. Input Input only Input INTP0/TI0 5-bit I/O port. Input/output can be specified in 1-bit units. Input INTP1 If used as an input port, use of an on-chip...
Page 35 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) After Alternate Pin Name Function Reset Function P70 to P74 Port 7. Input — N-ch open-drain 5-bit I/O port. LEDs can be driven directly. Input/output can be specified in 1-bit units. In mask ROM versions, use of an on-chip pull-up resistor can be specified in 1-bit units with the mask option.
Page 36 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) After Alternate Pin Name Function Reset Function External interrupt request inputs for which the valid edges (rising INTP0 Input Input P00/TI0 edge, falling edge, or both rising and falling edges) can be INTP1 specified.
Page 37: Prom Programming Mode Pins ( Μ Pd78P0208 Only)
CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) After Alternate Pin Name Function Reset Function Input Crystal resonator connection for main system clock oscillation — — — — — Input Crystal resonator connection for subsystem clock oscillation Input — — —...
Page 38: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P04 (Port 0) These pins constitute a 5-bit I/O port. Besides serving as I/O port pins, they function as external interrupt request inputs, an external count clock input to the timer, a capture trigger signal input, and crystal resonator connection for subsystem clock oscillation.
Page 39: P20 To P27 (Port 2)
Serial interface serial data I/O pins (b) SCK0 and SCK1 Serial interface serial clock I/O pins (c) SB0 and SB1 NEC Electronics standard serial bus interface I/O pins (d) BUSY Serial interface automatic transmit/receive busy input pin (e) STB Serial interface automatic transmit/receive strobe output pin Caution If port 2 is used as serial interface pins, the I/O and output latches must be set according to the function.
Page 40: P70 To P74 (Port 7)
CHAPTER 2 PIN FUNCTIONS (2) Control mode P30 to P37 function as timer I/O, clock output, and buzzer output pins. (a) TI1 and TI2 Pins for external count clock input to the 8-bit timer/event counter. (b) TO0 to TO2 Timer output pins (c) PCL Clock output pin (d) BUZ...
Page 41: P100 To P107 (Port 10)
CHAPTER 2 PIN FUNCTIONS 2.2.8 P100 to P107 (Port 10) These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as display outputs for the VFD controller/driver. Port 10 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P100 to P107 function as an 8-bit I/O port.
Page 42: Vload
CHAPTER 2 PIN FUNCTIONS 2.2.12 V LOAD This is the pull-down resistor connection pin of the VFD controller/driver. 2.2.13 AV The A/D converter’s reference voltage should be input from this pin. 2.2.14 AV This pin supplies power for A/D converter operations. Always make this pin the same potential as the V pin even if the A/D converter is not used.
Page 43: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the I/O circuit types of pins and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-1.
Page 44 CHAPTER 2 PIN FUNCTIONS Table 2-1. Types of Pin I/O Circuits (2/2) Pin Name Recommended Connection of Unused Pins Circuit Type µ PD78P0208 P30/TO0 Input: Independently connect to V or V via a resistor. Output: Leave open. P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ...
Page 45: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (1/3) Type 2 Type 8-A Pull-up P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Type 5-A Type 8-B Pull-up P-ch Pull-up enable P-ch enable Data P-ch Data P-ch IN/OUT...
Page 46 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (2/3) Type 11 Type 14 Pull-up P-ch enable Data P-ch P-ch P-ch IN/OUT Output N-ch Data disable P-ch Comparator N-ch – N-ch LOAD (Threshold voltage) Input enable Type 13-B Type 14-A Mask option IN/OUT...
Page 47 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (3/3) Type 15-B Type 16 P-ch P-ch Feedback cut-off Data IN/OUT P-ch N-ch N-ch Type 15-C P-ch P-ch Data IN/OUT N-ch Mask option N-ch LOAD Mask option User’s Manual U11302EJ4V0UM...
Page 48: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Each product of the µ PD780208 Subseries accesses a memory space of 64 KB. Figures 3-1 to 3-5 show memory maps. Caution The initial values of the internal memory size switching register (IMS) in the µ PD780204A, 780205A, and 78P0208 are fixed to CFH, regardless of the internal memory capacity.
Page 49: Memory Map ( Μ Pd780205 And Μ Pd780205A)
CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ PD780205 and µ PD780205A) FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits 9FFFH FB00H FAFFH Program area...
Page 50: Memory Map ( Μ Pd780206)
CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( µ PD780206) FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FB00H BFFFH FAFFH Buffer RAM 64 x 8 bits Program area FAC0H...
Page 51: Memory Map ( Μ Pd780208)
CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map ( µ PD780208) FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FB00H EFFFH FAFFH Buffer RAM 64 x 8 bits Program area FAC0H...
Page 52: Memory Map ( Μ Pd78P0208)
CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( µ PD78P0208) FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FB00H EFFFH FAFFH Buffer RAM 64 x 8 bits Program area FAC0H...
Page 53: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. Normally, this space is addressed using the program counter (PC). Each product in the µ PD780208 Subseries contains internal ROM (or PROM) with the capacity shown below. Table 3-1.
Page 54: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space The µ PD780208 Subseries units incorporate the following RAMs. (1) Internal high-speed RAM Internal high-speed RAM is allocated to the 1024-byte area from FB00H to FEFFH of the µ PD780208 Subseries. Four banks of general-purpose registers, each bank consisting of eight 8-bit registers are allocated in the 32- byte area FEE0H to FEFFH.
Page 55: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing The method to specify the address of the instruction to be executed next or the address of a register or memory area to be manipulated when an instruction is executed is called addressing. The address of the instruction to be executed next is specified by the program counter (PC) (for details, refer to 3.3 Instruction Address Addressing).
Page 56: Data Memory Addressing ( Μ Pd780205 And Μ Pd780205A)
CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data Memory Addressing ( µ PD780205 and µ PD780205A) FFFFH Special-function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing Short direct 32 x 8 bits addressing FEE0H FEDFH Internal high-speed RAM...
Page 57: Data Memory Addressing ( Μ Pd780206)
CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing ( µ PD780206) FFFFH Special-function registers (SFRs) SFR addressing 256 x 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 x 8 bits Short direct FEE0H addressing FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH...
Page 58: Data Memory Addressing ( Μ Pd780208)
CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing ( µ PD780208) FFFFH Special-function registers (SFRs) SFR addressing 256 x 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing 32 x 8 bits Short direct FEE0H addressing FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH...
Page 59: Data Memory Addressing ( Μ Pd78P0208)
CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing ( µ PD78P0208) FFFFH Special-function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH General-purpose registers Register addressing Short direct 32 x 8 bits addressing FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH...
Page 60: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD780208 Subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses, and stack memory. The program counter (PC), program status word (PSW), and stack pointer (SP) are control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 61: Stack Pointer Format
CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts.
Page 62: Data To Be Saved To Stack Memory
CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Data to Be Saved to Stack Memory Interrupt and BRK instruction CALL, CALLF, and PUSH rp instruction CALLT instructions SP – 3 SP – 2 SP – 2 SP – 3 PC7 to PC0 Lower SP –...
Page 63: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. They consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL).
Page 64: Special-Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special-function registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. The special-function registers are allocated in the FF00H to FFFFH area. Special-function registers can be manipulated, like general-purpose registers, with operation, transfer, and bit manipulation instructions.
Page 65: Special-Function Register List
CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special-Function Register List (1/3) After Address Special-Function Register (SFR) Name Symbol Manipulatable Bit Unit Reset 1 Bit 8 Bits 16 Bits √ √ FF00H Port 0 – √ √ FF01H Port 1 – √ √...
Page 66 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special-Function Register List (2/3) After Address Special-Function Register (SFR) Name Symbol Manipulatable Reset Bit Unit 1 Bit 8 Bits 16 Bits √ √ FF60H Serial operating mode register 0 CSIM0 – √ √ FF61H Serial bus interface control register SBIC –...
Page 67 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special-Function Register List (3/3) After Address Special-Function Register (SFR) Name Symbol Manipulatable Reset Bit Unit 1 Bit 8 Bits 16 Bits √ Note FFF0H Internal memory size switching register – – √ Note FFF4H Internal expansion RAM size switching register –...
Page 68: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of the instruction to be fetched each time another instruction is executed.
Page 69: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces.
Page 70: Table Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed.
Page 71: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] User’s Manual U11302EJ4V0UM...
Page 72: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general-purpose register area is automatically (implicitly) addressed.
Page 73: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified by register bank select flags (RBS0 and RBS1) and the register specification code (Rn, RPn) in the operation code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 74: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code Opcode [Illustration]...
Page 75: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied to is the 256-byte space from FE20H to FF1FH. An internal high-speed RAM and special-function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 76: Special-Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special-function register (SFR) addressing [Function] A memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 77: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specification code in the instruction code.
Page 78: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1).
Page 79: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1).
Page 80: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD780208 Subseries units incorporate two input ports, 16 output ports, and 56 I/O ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out various control operations.
Page 81: Port Functions
CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (1/2) Pin Name Function Alternate Function Input only. INTP0/TI0 Port 0. 5-bit I/O port. Input/output can be specified in 1-bit units. INTP1 If used as an input port, on-chip pull-up resistors INTP2 can be used by software settings.
Page 82 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (2/2) Alternate Pin Name Function Function P100 to P107 Port 10. FIP29 to FIP36 P-ch open-drain 8-bit high withstanding voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected to V or V...
Page 83: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration A port consists of the following hardware. Table 4-2. Port Configuration Item Configuration Control registers Port mode register (PMm: m = 0, 1, 2, 3, 7, 10, 11, 12) Pull-up resistor option register (PUO) Ports Total: 74 (2 input, 16 output, 56 I/O) Pull-up resistors...
Page 84: Block Diagram Of P00 And P04
CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P00 and P04 P00/INTP0/TI0, P04/XT1 Figure 4-3. Block Diagram of P01 to P03 PUO0 P-ch Selector PORT Output latch P01/INTP1, (P01 to P03) P02/INTP2, P03/INTP3 PM01 to PM03 PUO: Pull-up resistor option register Port mode register Port 0 read signal Port 0 write signal...
Page 85: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. The P10 to P17 pins can be set to input mode/output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pull- up resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO).
Page 86: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit I/O port with an output latch. The P20 to P27 pins can be set to input mode/output mode in 1-bit units using port mode register 2 (PM2). When the P20 to P27 pins are used as input port pins, on-chip pull- up resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO).
Page 87: Block Diagram Of P22 And P27
CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 and P27 PUO2 P-ch Selector PORT Output latch P22/SCK1, (P22, P27) P27/SCK0 PM22, PM27 Alternate function PUO: Pull-up resistor option register Port mode register Port 2 read signal Port 2 write signal User’s Manual U11302EJ4V0UM...
Page 88: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is an 8-bit I/O port with an output latch. The P30 to P37 pins can be set to input mode/output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P37 pins are used as input port pins, on-chip pull- up resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO).
Page 89: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 7 Port 7 is a 5-bit I/O port with an output latch. The P70 to P74 pins can be set to input mode/output mode in 1- bit units using port mode register 7 (PM7). In mask ROM versions, use of pull-up resistors can be specified in 1- bit units with the mask option.
Page 90: Port 8
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 8 Port 8 is an 8-bit output-only port. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to V or V can be specified in 4-bit units. The LOAD µ...
Page 91: Port 9
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 9 Port 9 is an 8-bit output-only port. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to V or V can be specified in 4-bit units. The LOAD µ...
Page 92: Port 10
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 10 Port 10 is an 8-bit I/O port with an output latch. The P100 to P107 pins can be set to input mode/output mode in 1-bit units using port mode register 10 (PM10). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option.
Page 93: Port 11
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 11 Port 11 is an 8-bit I/O port with an output latch. The P110 to P117 pins can be set to input mode/output mode in 1-bit units using port mode register 11 (PM11). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option.
Page 94: Port 12
CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 12 Port 12 is an 8-bit I/O port with an output latch. The P120 to P127 pins can be set to input mode/output mode in 1-bit units using port mode register 12 (PM12). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option.
Page 95: Port Function Control Registers
CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM1, PM2, PM3, PM7, PM10, PM11, PM12) • Pull-up resistor option register (PUO) (1) Port mode registers (PM0, PM1, PM2, PM3, PM7, PM10, PM11, PM12) These registers are used to set port input/output in 1-bit units.
Page 96: Format Of Port Mode Register
CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Port Mode Register Symbol Address After reset PM03 PM02 PM01 FF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM36 PM35 PM34 PM33 PM32 PM31 PM37 PM30 FF23H...
Page 97: Format Of Pull-Up Resistor Option Register
CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option register (PUO) The PUO register enables or disables the on-chip pull-up resistor for each port pin. To enable the on-chip pull- up resistor of a port pin, the pin must be in the input mode and the corresponding bit in the PUO register must be set to 1.
Page 98: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 99: Selection Of Mask Option
CHAPTER 4 PORT FUNCTIONS 4.5 Selection of Mask Option The following mask option is provided in mask ROM versions. The µ PD78P0208 has no mask option. Table 4-4. Comparison Between Mask Option of Mask ROM Version and µ PD78P0208 µ PD78P0208 Pin Name Mask Option of Mask ROM Version Can incorporate pull-down resistors in...
Page 100: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
Page 101: Clock Generater Block Diagram
CHAPTER 5 CLOCK GENERATOR Figure 5-1. Clock Generator Block Diagram XT1/P04 Subsystem Clock output function clock oscillator Watch timer Noise eliminator DIGS0 to Note 2 DIGS3 Note 1 DSPM06 Prescaler Watchdog timer Clock to peripheral Main system Prescaler hardware clock oscillator Standby CPU clock controller...
Page 102: Clock Generator Control Registers
CHAPTER 5 CLOCK GENERATOR 5.3 Clock Generator Control Registers The clock generator is controlled by the following three registers. • Processor clock control register (PCC) • Display mode register 0 (DSPM0) • Display mode register 1 (DSPM1) (1) Processor clock control register (PCC) PCC sets CPU clock selection, the ratio of division, main system clock oscillator operation/stop, and subsystem clock oscillator internal feedback resistor enable/disable.
Page 103: Format Of Processor Clock Control Register
CHAPTER 5 CLOCK GENERATOR Figure 5-3. Format of Processor Clock Control Register Symbol <7> <6> <5> <4> Address After reset Note 1 PCC2 PCC1 PCC0 FFFBH CPU clock (f ) selection PCC2 PCC1 PCC0 Setting prohibited Other than above CPU clock status Main system clock Subsystem clock Subsystem clock feedback resistor selection...
Page 104: Relationship Between Cpu Clock And Minimum Instruction Execution Time
CHAPTER 5 CLOCK GENERATOR The fastest instruction of the µ PD780208 Subseries is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f ) and minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (f Minimum Instruction Execution Time: 2/f 0.4 µ...
Page 105: Format Of Display Mode Register 0
CHAPTER 5 CLOCK GENERATOR Figure 5-4. Format of Display Mode Register 0 (1/2) Symbol Address After reset DSPM0 DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 F F A 0 H 0 0 H R/W SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 Display segment (display mode 1) Display output total (display mode 2) Note Note...
Page 106 CHAPTER 5 CLOCK GENERATOR Figure 5-4. Format of Display Mode Register 0 (2/2) Symbol Address After reset Note 1 DSPM0 DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 F F A 0 H 0 0 H R/W DSPM05 Display mode setting Display mode 1 (segment/character type) Display mode 2 (type in which a segment spans two or more grids) Note 2...
Page 107 CHAPTER 5 CLOCK GENERATOR (3) Display mode register 1 (DSPM1) Register to set display operation/stop. DSPM1 is set with an 8-bit memory manipulation instruction. RESET input sets DSPM1 to 00H. Remark In addition to setting display operation/stop, DSPM1 can also set the display digits/number of display patterns, cut width of the VFD output, and display cycle.
Page 108: Format Of Display Mode Register 1
CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Display Mode Register 1 Symbol Address After reset DSPM1 DIGS3 DIGS2 DIGS1 DIGS0 DIMS3 DIMS2 DIMS1 DIMS0 F F A 1 H 0 0 H DIMS0 Display mode cycle setting is 1 display cycle (1 display cycle = 204.8 µ s: @ 5.0 MHz operation) 1024/f is 1 display cycle (1 display cycle = 409.6 µ...
Page 109: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and its inverted signal to the X2 pin.
Page 110: Subsystem Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and its inverted signal to the XT2 pin.
Page 111: Examples Of Incorrect Resonator Connection
CHAPTER 5 CLOCK GENERATOR Figure 5-8. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines PORTn (n = 0 to 3, 7 to 12) (c) High alternating current close to (d) Current flowing through ground line signal lines of oscillator (potentials at points A, B, and C change)
Page 112 CHAPTER 5 CLOCK GENERATOR Figure 5-8. Examples of Incorrect Resonator Connection (2/2) (e) Signal fetched Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2. Cautions 2.
Page 113: Divider
CHAPTER 5 CLOCK GENERATOR 5.4.3 Divider The divider divides the main system clock oscillator output (f ) and generates various clocks. 5.4.4 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows.
Page 114: Clock Generator Operations
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f • Subsystem clock f • CPU clock f •...
Page 115: Main System Clock Operations
CHAPTER 5 CLOCK GENERATOR 5.5.1 Main system clock operations During operation with the main system clock (when bit 5 (CLS) of the processor clock control register (PCC) is set to 0), the following operations are carried out via PCC settings. (a) Because the operation guaranteed instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by setting bits 0 to 2 (PCC0 to PCC2) of PCC.
Page 116: Subsystem Clock Operations
CHAPTER 5 CLOCK GENERATOR Figure 5-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC during main system clock operation Main system clock oscillation Subsystem clock oscillation CPU clock 5.5.2 Subsystem clock operations During operation with the subsystem clock (when bit 5 (CLS) of the processor clock control register (PCC) is set to 1), the following operations are carried out.
Page 117: Changing System Clock And Cpu Clock Settings
CHAPTER 5 CLOCK GENERATOR 5.6 Changing System Clock and CPU Clock Settings 5.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC).
Page 118: System Clock And Cpu Clock Switching Procedure
CHAPTER 5 CLOCK GENERATOR 5.6.2 System clock and CPU clock switching procedure This section describes the procedure for switching between the system clock and CPU clock. Figure 5-10. System Clock and CPU Clock Switching RESET Interrupt request signal System clock CPU clock Minimum Maximum speed...
Page 119: Chapter 6 16-Bit Timer/Event Counter
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.1 Outline of Timers Incorporated in µ PD780208 Subseries This chapter explains the 16-bit timer/event counter. First of all, the timers incorporated in the µ PD780208 Subseries and other related parts are outlined below. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an interval timer, PWM output, pulse width measurement (infrared remote control receive function), external event counter or square-wave output of any frequency.
Page 120: 16-Bit Timer/Event Counter Functions
CHAPTER 6 16-BIT TIMER/EVENT COUNTER Table 6-1. Timer/Event Counter Operations 16-Bit Timer/ 8-Bit Timer/ Watch Watchdog Event Counter Event Counter Timer Timer Note 1 Note 2 Operation Interval timer 1 channel 2 channels 1 channel 1 channel √ √ mode External event counter –...
Page 121: 16-Bit Timer/Event Counter Interval Time
CHAPTER 6 16-BIT TIMER/EVENT COUNTER (1) Interval timer TM0 generates interrupt requests at the preset time interval. Table 6-2. 16-Bit Timer/Event Counter Interval Time Minimum Interval Time Maximum Interval Time Resolution 2 x TI0 input cycle x TI0 input cycle TI0 input edge cycle 2 x 1/f (400 ns)
Page 122: 16-Bit Timer/Event Counter Configuration
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 6-4. 16-Bit Timer/Event Counter Configuration Item Configuration Timer register 16 bits x 1 (TM0) Registers 16-bit compare register: 1 (CR00) 16-bit capture register: 1 (CR01) Timer outputs...
Page 123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER User’s Manual U11302EJ4V0UM...
Page 124 CHAPTER 6 16-BIT TIMER/EVENT COUNTER User’s Manual U11302EJ4V0UM...
Page 125 CHAPTER 6 16-BIT TIMER/EVENT COUNTER User’s Manual U11302EJ4V0UM...
Page 126 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (1) 16-bit compare register (CR00) CR00 is a 16-bit register whose value is constantly compared with the 16-bit timer register (TM0) count value, and an interrupt request (INTTM0) is generated if they match. It can also be used as the register that holds the interval time when TM0 is set to interval timer operation, and as the register that sets the pulse width when TM0 is set to PWM output operation.
Page 127: 16-Bit Timer/Event Counter Control Registers
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.4 16-Bit Timer/Event Counter Control Registers The following six registers are used to control the 16-bit timer/event counter. • Timer clock select register 0 (TCL0) • 16-bit timer mode control register (TMC0) • 16-bit timer output control register (TOC0) •...
Page 128: Format Of Timer Clock Select Register 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-4. Format of Timer Clock Select Register 0 Symbol <7> Address After reset TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H PCL output clock selection TCL03 TCL02 TCL01 TCL00 (32.768 kHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz)
Page 129 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (2) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. TMC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC0 to 00H.
Page 130: Format Of 16-Bit Timer Mode Control Register
CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-5. Format of 16-Bit Timer Mode Control Register Symbol <0> Address After reset TMC0 TMC03 TMC02 TMC01 OVF0 FF48H OVF0 16-bit timer register overflow detection Overflow not detected Overflow detected Operating mode & clear TO0 output timing Interrupt request TMC03 TMC02 TMC01...
Page 131: Format Of 16-Bit Timer Output Control Register
CHAPTER 6 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output controller. It sets/resets the R-S type flip-flop (LV0), sets the active level in PWM mode, and enables/disables inversion in modes other than PWM mode and data output mode.
Page 132: Format Of Port Mode Register 3
CHAPTER 6 16-BIT TIMER/EVENT COUNTER (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and the output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Page 133: Format Of External Interrupt Mode Register
CHAPTER 6 16-BIT TIMER/EVENT COUNTER (5) External interrupt mode register (INTM0) This register is used to set the INTP0 to INTP2 and TI0 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 to 00H. Remarks 1.
Page 134: Format Of Sampling Clock Select Register
CHAPTER 6 16-BIT TIMER/EVENT COUNTER (6) Sampling clock select register (SCS) This register sets the clock to be used for sampling the valid edge input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is eliminated using the sampling clock. SCS is set with an 8-bit memory manipulation instruction.
Page 135: 16-Bit Timer/Event Counter Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5 16-Bit Timer/Event Counter Operations 6.5.1 Interval timer operations By setting bits 2 and 3 (TMC02 and TMC03) of the 16-bit timer mode control register (TMC0) to 1, 1, the 16-bit timer/event counter operates as an interval timer. Interrupt requests are generated repeatedly using the count value set in the 16-bit compare register (CR00) beforehand as the interval.
Page 136: 16-Bit Timer/Event Counter Interval Time
CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-11. Interval Timer Operation Timing Count clock TM0 count value 0000 0001 0000 0001 0000 0001 Count start Clear Clear CR00 INTTM0 Interrupt request acknowledgment Interrupt request acknowledgment Interval time Interval time Interval time Remark Interval time = (N + 1) x t: N = 0001H to FFFFH Table 6-5.
Page 137: Pwm Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.2 PWM output operations By setting bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) to 1, 0, 0, the 16-bit timer/ event counter operates as PWM output. Pulses with a duty determined by the value set in the 16-bit compare register (CR00) beforehand are output from the TO0/P30 pin.
Page 138: Pulse Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-13 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner. Figure 6-13. TV Tuner Application Circuit Example +110 V µ PD780205 22 kΩ...
Page 139: Configuration Diagram For Pulse Width Measurement In Free-Running Mode
CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-14. Configuration Diagram for Pulse Width Measurement in Free-Running Mode 16-bit timer register (TM0) OVF0 16-bit capture TI0/P00/INTP0 register (CR01) INTP0 Internal bus Figure 6-15. Timing of Pulse Width Measurement Operation in Free-Running Mode (with Both Edges Specified) Count clock TM0 count value...
Page 140: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER (2) Pulse width measurement by means of restart When input of a valid edge to the TI0/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into the 16-bit capture register (CR01), and then the pulse width of the signal input to the TI0/P00 pin is measured by clearing TM0 and restarting the count.
Page 141: External Event Counter Configuration Diagram
CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-17. External Event Counter Configuration Diagram 16-bit compare register (CR00) INTTM0 Clear TI0 valid edge 16-bit timer register (TM0) OVF0 INTP0 16-bit capture register (CR01) Internal bus Figure 6-18. External Event Counter Operation Timing (with Rising Edge Specified) TI0 pin input N _ 1 TM0 count value...
Page 142: Square-Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.5 Square-wave output operation The 16-bit timer/event counter outputs a square-wave of any frequency with the value preset to the 16-bit compare register (CR00) as the interval. The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1.
Page 143: 16-Bit Timer/Event Counter Operating Precautions
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously to the count pulse. Figure 6-20.
Page 144: Capture Register Data Retention Timing
CHAPTER 6 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timing If the valid edge of the TI0/P00 pin is input during 16-bit capture register (CR01) read, CR01 holds the data without carrying out the capture operation. However, the interrupt request signal (INTTM0) is generated upon detection of the valid edge.
Page 145: Chapter 7 8-Bit Timer/Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.1 8-Bit Timer/Event Counter Functions The following two modes are available for the 8-bit timer/event counter incorporated in the µ PD780208 Subseries. • 8-bit timer/event counter mode: Two-channel 8-bit timer/event counter with each channel used separately •...
Page 146: 8-Bit Timer/Event Counter Interval Time
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 7-1. 8-Bit Timer/Event Counter Interval Time Minimum Interval Time Maximum Interval Time Resolution (102.4 µ s) 2 x 1/f (400 ns) x 1/f 2 x 1/f (400 ns)
Page 147: 8-Bit Timer/Event Counter Square-Wave Output Ranges
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 7-2. 8-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution...
Page 148: 16-Bit Timer/Event Counter Mode
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 7-3. Interval Time When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter Minimum Interval Time Maximum Interval Time Resolution 2 x 1/f...
Page 149: Is Used As 16-Bit Timer/Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 7-4. Square-Wave Output Ranges When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter Minimum Pulse Width Maximum Pulse Width...
Page 150: 8-Bit Timer/Event Counter Configuration
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counter consists of the following hardware. Table 7-5. 8-Bit Timer/Event Counter Configuration Item Configuration Timer register 8 bits x 2 (TM1, TM2) Registers 8-bit compare register: 2 (CR10, CR20) Timer outputs 2 (TO1, TO2) Control registers...
Page 151 CHAPTER 7 8-BIT TIMER/EVENT COUNTER User’s Manual U11302EJ4V0UM...
Page 152: Block Diagram Of 8-Bit Timer/Event Counter Output Controller 1
CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter Output Controller 1 Level F/F (LV1) LVR1 TO1/P31 LVS1 TOC11 Note PM31 output latch INTTM1 TOE1 Note Bit 1 of port mode register 3 (PM3) Remark The circuitry enclosed by the dotted line is the output controller. Figure 7-3.
Page 153: 8-Bit Timer/Event Counter Control Registers
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (1) 8-bit compare registers (CR10, CR20) These are 8-bit registers used to compare the value set to CR10 with the 8-bit timer register 1 (TM1) count value, and the value set to CR20 with the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively).
Page 154: Format Of Timer Clock Select Register 1
CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-4. Format of Timer Clock Select Register 1 Symbol Address After reset TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 FF41H 8-bit timer register 1 count TCL13 TCL12 TCL11 TCL10 clock selection TI1 falling edge TI1 rising edge /2 (2.5 MHz) (1.25 MHz)
Page 155: Format Of 8-Bit Timer Mode Control Register
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8- bit timer registers 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H.
Page 156: Format Of 8-Bit Timer Output Control Register
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output controllers 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8- bit timer registers 1 and 2.
Page 157: Format Of Port Mode Register 3
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and the output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 158: 8-Bit Timer/Event Counter Operations
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4 8-Bit Timer/Event Counter Operations 7.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counter operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit compare registers (CR10 and CR20). When the count values of 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20, counting continues with the TM1 and TM2 values cleared to 0 and interrupt request signals (INTTM1 and INTTM2) are generated.
Page 159: 8-Bit Timer/Event Counter 1 Interval Time
CHAPTER 7 8-BIT TIMER/EVENT COUNTER Table 7-6. 8-Bit Timer/Event Counter 1 Interval Time TCL13 TCL12 TCL11 TCL10 Minimum Interval Time Maximum Interval Time Resolution TI1 input cycle x TI1 input cycle TI1 input edge cycle TI1 input cycle x TI1 input cycle TI1 input edge cycle (102.4 µ...
Page 160: External Event Counter Operation Timing (With Rising Edge Specified)
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) External event counter operation The external event counter counts the number of external clock pulses input to the TI1/P33 and TI2/P34 pins using 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified by timer clock select register 1 (TCL1) is input.
Page 161: 8-Bit Timer/Event Counter Square-Wave Output Ranges
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (3) Square-wave output operation The 8-bit timer/event counter outputs a square wave of any frequency with the value preset to the 8-bit compare register (CR10, CR20) as the interval. The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1.
Page 162: 16-Bit Timer/Event Counter Mode
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set. In this mode, the count clock is selected using bits 0 to 3 (TCL10 to TCL13) of the timer clock select register (TCL1). The overflow signal of 8-bit timer/event counter 1 (TM1) is used as the count clock of 8-bit timer/event counter 2 (TM2).
Page 163: (Tm1 And Tm2) Is Used As 16-Bit Timer/Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, an interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output controller 1 is inverted. Thus, when using the 8-bit timer/event counter as a 16-bit interval timer, set the mask flag TMMK1 to 1 to disable INTTM1 acknowledgment.
Page 164: External Event Counter Operation Timing (With Rising Edge Specified)
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) External event counter operations The external event counter counts the number of external clock pulses input to the TI1/P33 pin by using the two channels of 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 is incremented each time the valid edge specified by timer clock select register 1 (TCL1) is input.
Page 165: (Tm1 And Tm2) Are Used As 16-Bit Timer/Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (3) Square-wave output operation Square-wave signals can be generated at the user-specified frequency. The frequency or pulse interval is determined by the value preset in the 8-bit compare registers (CR10 and CR20). To set a count value, set the value of the higher 8 bits to CR20, and the value of the lower 8 bits to CR10.
Page 166: 8-Bit Timer/Event Counter Operating Precautions
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5 8-Bit Timer/Event Counter Operating Precautions (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously to the count pulse.
Page 167: Timing After Compare Register Change During Timer Count Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTER (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR10 and CR20) are changed are smaller than those of the 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0.
Page 168: Chapter 8 Watch Timer
CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5-second or 0.25-second intervals. In addition, when the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5-second or 1-second intervals.
Page 169: Watch Timer Configuration
CHAPTER 8 WATCH TIMER 8.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 8-2. Watch Timer Configuration Item Configuration Counter 5 bits x 1 Control registers Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) 8.3 Watch Timer Control Registers The following two registers are used to control the watch timer.
Page 170 CHAPTER 8 WATCH TIMER User’s Manual U11302EJ4V0UM...
Page 171: Format Of Timer Clock Select Register 2
CHAPTER 8 WATCH TIMER Figure 8-2. Format of Timer Clock Select Register 2 Symbol Address After reset TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H Count clock selection TCL22 TCL21 TCL20 Watchdog timer mode Interval timer mode (625 kHz) (313 kHz) (313 kHz) (156 kHz)
Page 172: Format Of Watch Timer Mode Control Register
CHAPTER 8 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC2 to 00H.
Page 173: Watch Timer Operations
CHAPTER 8 WATCH TIMER 8.4 Watch Timer Operations 8.4.1 Watch timer operation When the 32.768 kHz subsystem clock is used, the timer operates as a watch timer with a 0.5-second or 0.25- second interval. In addition, when the 4.19 MHz main system clock is used, the timer can operate as a watch timer with a 0.5-second or 1-second interval.
Page 174: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (WDTM) (the watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer mode This mode detects an inadvertent program loop.
Page 175: Watchdog Timer Configuration
CHAPTER 9 WATCHDOG TIMER 9.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 9-3. Watchdog Timer Configuration Item Configuration Control registers Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) User’s Manual U11302EJ4V0UM...
Page 176 CHAPTER 9 WATCHDOG TIMER User’s Manual U11302EJ4V0UM...
Page 177: Watchdog Timer Control Registers
CHAPTER 9 WATCHDOG TIMER 9.3 Watchdog Timer Control Registers The following two registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock.
Page 178: Format Of Timer Clock Select Register 2
CHAPTER 9 WATCHDOG TIMER Figure 9-2. Format of Timer Clock Select Register 2 Symbol Address After reset TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H Count clock selection TCL22 TCL21 TCL20 Watchdog timer mode Interval timer mode (625 kHz) (313 kHz) (313 kHz) (156 kHz)
Page 179: Format Of Watchdog Timer Mode Register
CHAPTER 9 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3. Format of Watchdog Timer Mode Register Symbol <7>...
Page 180: Watchdog Timer Operations
CHAPTER 9 WATCHDOG TIMER 9.4 Watchdog Timer Operations 9.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer operates to detect an inadvertent program loop. The watchdog timer count clock (program loop detection time interval) can be selected using bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2).
Page 181: Interval Timer Operation
CHAPTER 9 WATCHDOG TIMER 9.4.2 Interval timer operation The watchdog timer operates as an interval timer that generates interrupt requests repeatedly at intervals of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is cleared to 0. The count clock (interval time) can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2).
Page 182: Chapter 10 Clock Output Controller
CHAPTER 10 CLOCK OUTPUT CONTROLLER 10.1 Clock Output Controller Functions The clock output controller is used for carrier output during remote controlled transmission and clock output for supply to a peripheral LSI. The clock selected by timer clock select register 0 (TCL0) is output from the PCL/ P35 pin.
Page 183: Clock Output Controller Configuration
CHAPTER 10 CLOCK OUTPUT CONTROLLER 10.2 Clock Output Controller Configuration The clock output controller consists of the following hardware. Table 10-1. Clock Output Controller Configuration Item Configuration Control registers Timer clock select register 0 (TCL0) Port mode register 3 (PM3) Figure 10-2.
Page 184: Format Of Timer Clock Select Register 0
CHAPTER 10 CLOCK OUTPUT CONTROLLER Figure 10-3. Format of Timer Clock Select Register 0 Symbol <7> Address After reset TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H TCL03 TCL02 TCL01 TCL00 PCL output clock selection (32.768 kHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz)
Page 185: Format Of Port Mode Register 3
CHAPTER 10 CLOCK OUTPUT CONTROLLER (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P35/PCL pin for clock output, set PM35 and the output latch of P35 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Page 186: Chapter 11 Buzzer Output Controller
CHAPTER 11 BUZZER OUTPUT CONTROLLER 11.1 Buzzer Output Controller Functions The buzzer output controller outputs a 1.2 kHz, 2.4 kHz, or 4.9 kHz frequency square-wave. The buzzer frequency selected by timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency.
Page 187: Buzzer Output Function Control Registers
CHAPTER 11 BUZZER OUTPUT CONTROLLER 11.3 Buzzer Output Function Control Registers The following two registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency.
Page 188: Format Of Timer Clock Select Register 2
CHAPTER 11 BUZZER OUTPUT CONTROLLER Figure 11-2. Format of Timer Clock Select Register 2 Symbol Address After reset TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H Count clock selection TCL22 TCL21 TCL20 Watchdog timer mode Interval timer mode (625 kHz) (313 kHz) (313 kHz) (156 kHz)
Page 189: Format Of Port Mode Register 3
CHAPTER 11 BUZZER OUTPUT CONTROLLER (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output, set PM36 and the output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Page 190: Chapter 12 A/D Converter
CHAPTER 12 A/D CONVERTER 12.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR).
Page 191: A/D Converter Block Diagram
CHAPTER 12 A/D CONVERTER Figure 12-1. A/D Converter Block Diagram Internal bus A/D converter input select register ADIS3 ADIS2 ADIS1 ADIS0 Series resistor string ANI0/P10 ANI1/P11 Sample & hold circuit Voltage ANI2/P12 comparator ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 Successive approximation ANI7/P17 register (SAR) ADM1 to ADM3 Falling edge...
Page 192 CHAPTER 12 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to the A/D conversion result register (ADCR).
Page 193 CHAPTER 12 A/D CONVERTER (7) AV This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between and AV Caution A series resistor string of approximately 10 kΩ is connected between the AV pin and the AV pin.
Page 194: A/D Converter Control Registers
CHAPTER 12 A/D CONVERTER 12.3 A/D Converter Control Registers The following two registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop, and external trigger.
Page 195: Format Of A/D Converter Mode Register
CHAPTER 12 A/D CONVERTER Figure 12-2. Format of A/D Converter Mode Register Symbol <7> <6> Address After reset FR0 ADM3 ADM2 ADM1 FF80H ADM3 ADM2 ADM1 Analog input channel selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 A/D conversion time selection Note 1 When operated at f = 5.0 MHz...
Page 196: Format Of A/D Converter Input Select Register
CHAPTER 12 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. The pins that are not selected for analog input pins can be used as I/O port pins. ADIS is set with an 8-bit memory manipulation instruction.
Page 197: A/D Converter Operations
CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Operations 12.4.1 Basic operations of A/D converter [1] Set the number of analog input channels using the A/D converter input select register (ADIS). [2] From among the analog input channels set by ADIS, select the channel for A/D conversion using the A/ D converter mode register (ADM).
Page 198: Basic Operation Of A/D Converter
CHAPTER 12 A/D CONVERTER Figure 12-4. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion defined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software. If a write to ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if CS is set (1), conversion starts again from the beginning.
Page 199: Input Voltage And Conversion Results
CHAPTER 12 A/D CONVERTER 12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/ D conversion result (the value stored in the A/D conversion result register (ADCR)) is shown by the following expression.
Page 200: A/D Converter Operating Mode
CHAPTER 12 A/D CONVERTER 12.4.3 A/D converter operating mode Select one analog input channel from among ANI0 to ANI7 using the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and start A/D conversion. A/D conversion can be started in the following two ways. •...
Page 201: A/D Conversion By Software Start
CHAPTER 12 A/D CONVERTER (2) A/D conversion by software start When bit 6 (TRG) and bit 7 (CS) of the A/D converter mode register (ADM) are set to 0 and 1, respectively, A/D conversion starts on the voltage applied to the analog input pins specified by bits 1 to 3 (ADM1 to ADM3) of ADM.
Page 202: A/D Converter Precautions
CHAPTER 12 A/D CONVERTER 12.5 A/D Converter Precautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV pin at this time, this current must be cut in order to minimize the overall system power consumption.
Page 203: Analog Input Pin Processing
CHAPTER 12 A/D CONVERTER (2) Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage greater than or equal to AV or less than or equal to AV is input (even if within the absolute maximum rating range), the conversion value for that channel will be undefined, and the conversion values of the other channels may also be affected.
Page 204: A/D Conversion End Interrupt Request Generation Timing
CHAPTER 12 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result for the analog input before changing and ADIF may be set immediately before rewriting ADM.
Page 205: Chapter 13 Serial Interface Channel 0
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 The µ PD780208 Subseries incorporates two clocked serial interface channels. The differences between channels 0 and 1 are as follows (refer to CHAPTER 14 SERIAL INTERFACE CHANNEL 1 for details of serial interface channel 1). Table 13-1.
Page 206: Functions Of Serial Interface Channel 0
• High-speed serial interface complying with the NEC Electronics standard bus format. • Address, command, and data information sent on the serial bus • The wakeup function for handshake and acknowledge and busy signal output function can also be used.
Page 207: Configuration Of Serial Interface Channel 0
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 13.2 Configuration of Serial Interface Channel 0 Serial interface channel 0 consists of the following hardware. Table 13-3. Configuration of Serial Interface Channel 0 Item Configuration Registers Serial I/O shift register 0 (SIO0) Slave address register (SVA) Control registers Timer clock select register 3 (TCL3) Serial operating mode register 0 (CSIM0) Serial bus interface control register (SBIC)
Page 208 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 User’s Manual U11302EJ4V0UM...
Page 209 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register used to carry out parallel/serial conversion and serial transmission/reception (shift operations) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation.
Page 210 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates an interrupt request signal in the following cases. • In the 3-wire serial I/O mode and 2-wire serial I/O mode This circuit generates an interrupt request signal every eight serial clocks.
Page 211: Control Registers Of Serial Interface Channel 0
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 13.3 Control Registers of Serial Interface Channel 0 The following four registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...
Page 212: Format Of Timer Clock Select Register 3
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 Figure 13-2. Format of Timer Clock Select Register 3 Symbol Address After reset TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H Serial interface channel 0 TCL33 TCL32 TCL31 TCL30 serial clock selection (1.25 MHz) (625 kHz) (313 kHz)
Page 213: Format Of Serial Operating Mode Register 0
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 Figure 13-3. Format of Serial Operating Mode Register 0 Symbol <7> <6> <5> 4 Address After reset CSIM CSIM CSIM CSIM CSIM CSIM0 CSIE0 COI WUP Note 1 FF60H R/W CSIM CSIM Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Page 214: Format Of Serial Bus Interface Control Register
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (3) Serial bus interface control register (SBIC) This register sets the serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 13-4.
Page 215 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 Figure 13-4. Format of Serial Bus Interface Control Register (2/2) R/W ACKE Acknowledge signal output control Acknowledge signal automatic output disabled (output with ACKT enabled) Before completion The acknowledge signal is output in synchronization with the 9th clock of transfer falling edge of SCK0 (automatically output when ACKE = 1).
Page 216: Format Of Interrupt Timing Specification Register
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (4) Interrupt timing specification register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Page 217: Operations Of Serial Interface Channel 0
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 13.4 Operations of Serial Interface Channel 0 The following four operating modes are available for serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode • 2-wire serial I/O mode 13.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode.
Page 218: 3-Wire Serial I/O Mode Operation
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 13.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is used for connection of peripheral ICs and display controllers that incorporate a clocked serial interface. Communication is carried out using three lines: a serial clock (SCK0), serial output (SO0), and serial input (SI0).
Page 219 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 Symbol <7> <6> <5> 4 Address After reset CSIM CSIM CSIM CSIM CSIM CSIM0 COI WUP Note 1 CSIE0 FF60H CSIM CSIM Serial interface channel 0 clock selection × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM CSIM CSIM...
Page 220 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H...
Page 221: Wire Serial I/O Mode Timing
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/ reception is carried out bit by bit in synchronization with the serial clock. Shift operations of serial I/O shift register 0 (SIO0) are carried out at the falling edge of the serial clock (SCK0).
Page 222: Relt And Cmdt Operations
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (3) Signals Figure 13-7 shows the RELT and CMDT operations. Figure 13-7. RELT and CMDT Operations SO0 latch RELT CMDT (4) MSB/LSB switching as the start bit In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB. Figure 13-8 shows the configuration of serial I/O shift register 0 (SIO0) and the internal bus.
Page 223: Sbi Mode Operation
(CSIIF0) is set. 13.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface that complies with the NEC Electronics serial bus format. SBI is a single-master high-speed serial bus with a format in which a bus configuration function has been added to the clocked serial I/O method so that it can carry out communication with two or more devices using two signal lines.
Page 224: Example Of Serial Bus Configuration With Sbi
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 Figure 13-9. Example of Serial Bus Configuration with SBI Serial clock SCK0 SCK0 Slave CPU Master CPU Serial data bus SB0 (SB1) SB0 (SB1) Address 1 SCK0 Slave CPU SB0 (SB1) Address 2 SCK0 Slave IC SB0 (SB1) Address N...
Page 225 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (1) SBI functions With the conventional serial I/O method, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary to distinguish chip select signals and command/data and to judge the busy state because only a data transfer function is available.
Page 226: Sbi Transfer Timing
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (2) SBI definition The SBI serial data format is defined as follows. Serial data to be transferred with SBI is distinguished into three types, “address”, “command”, and “data”. Figure 13-10 shows the address, command, and data transfer timing. Figure 13-10.
Page 227: Bus Release Signal
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (a) Bus release signal (REL) The bus release signal is identified when the SB0 (SB1) line has changed from low level to high level while the SCK0 line is high level (without serial clock output). This signal is output by the master device.
Page 228: Address
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 13-13. Address SCK0 SB0 (SB1) Address Bus release signal...
Page 229: Commands
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 13-15. Commands SCK0 SB0 (SB1) Command Command signal Figure 13-16. Data SCK0 SB0 (SB1) Data 8-bit data following a command signal is defined as “command”...
Page 230: Acknowledge Signal
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between the transmitter and receiver. Figure 13-17. Acknowledge Signal [When output in synchronization with 11th clock of SCK0] SCK0 SB0 (SB1) [When output in synchronization with 9th clock of SCK0] SCK0 SB0 (SB1)
Page 231: Busy And Ready Signals
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is used to report to the master device that the slave device is not ready for data transmission/reception. The READY signal is used to report to the master device that the slave device is ready for data transmission/reception.
Page 232 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Symbol <7> <6> <5> 4 Address After reset CSIM CSIM CSIM CSIM CSIM...
Page 233 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset Note SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT...
Page 234 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (continued) ACKE Acknowledge signal output control Acknowledge signal automatic output disabled (output with ACKT enabled) Before completion The acknowledge signal is output in synchronization with the 9th clock of transfer falling edge of SCK0 (automatically output when ACKE = 1). After completion The acknowledge signal is output in synchronization with the falling edge of SCK0 of transfer...
Page 235 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> Address After reset Note 1 SINT SIC SVAM FF63H SVAM SVA bit to be used as slave address...
Page 236: Relt, Cmdt, Reld, And Cmdd Operations (Master)
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (4) Signals Figures 13-19 to 13-24 show the signals and operations of the flags of the serial bus interface control register (SBIC) in SBI. Table 13-4 lists the signals in SBI. Figure 13-19. RELT, CMDT, RELD, and CMDD Operations (Master) Slave address write to SIO0 (transfer start instruction) SIO0...
Page 237: Ackt Operation
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 Figure 13-21. ACKT Operation SCK0 ACK signal is output for SB0/SB1 a period of one clock just after setting ACKT When set during this period Caution Do not set ACKT before termination of transfer. User’s Manual U11302EJ4V0UM...
Page 238: Acke Operations
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 Figure 13-22. ACKE Operations (a) When ACKE = 1 upon completion of transfer SCK0 ACK signal is output SB0/SB1 at 9th clock ACKE When ACKE = 1 at this point (b) When set after completion of transfer SCK0 SB0/SB1 ACK signal is output for...
Page 239: Ackd Operations
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 Figure 13-23. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0 Transfer start instruction SIO0 Transfer start SCK0 SB0/SB1 ACKD (b) When ACK signal is output after 9th clock of SCK0 Transfer start instruction SIO0...
Page 240 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 User’s Manual U11302EJ4V0UM...
Page 241 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 User’s Manual U11302EJ4V0UM...
Page 242: Pin Configuration
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0: Serial clock I/O pin [1] Master: CMOS and push-pull output [2] Slave: Schmitt input (b) SB0 (SB1): Serial data I/O alternate-function pin Both master and slave devices have an N-ch open-drain output and a Schmitt input.
Page 243 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. A match of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave address transmitted by the master matches the address set to SVA when the wakeup function specification bit (WUP) = 1.
Page 244 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 User’s Manual U11302EJ4V0UM...
Page 245 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 User’s Manual U11302EJ4V0UM...
Page 246 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 User’s Manual U11302EJ4V0UM...
Page 247 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 User’s Manual U11302EJ4V0UM...
Page 248 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (9) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 •...
Page 249: 2-Wire Serial I/O Mode Operation
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (d) For the pin that is to be used for data I/O, be sure to set as follows before serial transfer of the 1st byte after RESET input. [1] Set the P25 and P26 output latches to 1. [2] Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
Page 250 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Symbol <7> <6> <5> 4 Address After reset CSIM CSIM CSIM CSIM CSIM...
Page 251 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H...
Page 252 CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Symbol <6> <5> <4> Address After reset Note 1 SINT SIC SVAM FF63H SVAM SVA bit to be used as slave address...
Page 253: Wire Serial I/O Mode Timing
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/ reception is carried out bit by bit in synchronization with the serial clock. Shift operations of serial I/O shift register 0 (SIO0) are carried out in synchronization with the falling edge of the serial clock (SCK0).
Page 254: Relt And Cmdt Operations
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 (3) Signals Figure 13-32 shows the RELT and CMDT operations. Figure 13-32. RELT and CMDT Operations SO0 latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
Page 255: Sck0/P27 Pin Output Manipulation
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 13.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software (SI0/SB0 and SO0/SB1 pins to be controlled with bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC)).
Page 256: Chapter 14 Serial Interface Channel 1
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 14.1 Functions of Serial Interface Channel 1 Serial interface channel 1 has the following three modes. Table 14-1. Modes of Serial Interface Channel 1 Operation Mode Pins Used Features Usage Operation stop – • Used when serial transfer is not carried out. –...
Page 257: Configuration Of Serial Interface Channel 1
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 14.2 Configuration of Serial Interface Channel 1 Serial interface channel 1 consists of the following hardware. Table 14-2. Configuration of Serial Interface Channel 1 Item Configuration Registers Serial I/O shift register 1 (SIO1) Automatic data transmit/receive address pointer (ADTP) Control registers Timer clock select register 3 (TCL3) Serial operating mode register 1 (CSIM1)
Page 258 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 User’s Manual U11302EJ4V0UM...
Page 259 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register used to carry out parallel/serial conversion and serial transmission/reception (shift operations) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation.
Page 260: Control Registers Of Serial Interface Channel 1
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 14.3 Control Registers of Serial Interface Channel 1 The following four registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) •...
Page 261: Format Of Timer Clock Select Register 3
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 1. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Remark Besides setting the serial clock of serial interface channel 1, TCL3 sets the serial clock of serial interface channel 0.
Page 262: Format Of Serial Operating Mode Register 1
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets the serial interface channel 1 serial clock, operating mode, operation enable/stop, and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
Page 263 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable, and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
Page 264: Format Of Automatic Data Transmit/Receive Control Register
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Figure 14-4. Format of Automatic Data Transmit/Receive Control Register Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset Note 1 ADTC ARLD ERCE ERR TRF STRB FF69H BUSY1 BUSY0 BUSY1 BUSY0 Busy input control ×...
Page 265: Format Of Automatic Data Transmit/Receive Interval Specification Register
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specification register (ADTI) This register sets the automatic transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure 14-5.
Page 266 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Notes 1. The interval is dependent only on CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if the minimum calculated by the following expression is smaller than 2/f , the minimum interval time is 2/f...
Page 267 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Figure 14-5. Format of Automatic Data Transmit/Receive Interval Specification Register (2/2) Symbol Address After reset ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH Data transfer interval specification (f = 5.0 MHz operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Minimum Note Maximum...
Page 268: Operations Of Serial Interface Channel 1
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 14.4 Operations of Serial Interface Channel 1 The following three operating modes are available for serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 14.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode.
Page 269: 3-Wire Serial I/O Mode Operation
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 14.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is used for connection of peripheral ICs and display controllers that incorporate a clocked serial interface. Communication is carried out using three lines: a serial clock (SCK1), serial output (SO1), and serial input (SI1).
Page 270: Wire Serial I/O Mode Timing
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/ reception is carried out bit by bit in synchronization with the serial clock. Shift operations of serial I/O shift register 1 (SIO1) are carried out at the falling edge of the serial clock (SCK1).
Page 271: Circuit For Switching Transfer Bit Order
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (3) MSB/LSB switching as the start bit In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB. Figure 14-7 shows the configuration of serial I/O shift register 1 (SIO1) and the internal bus. As shown in the figure, the MSB/LSB can be read/written in reverse form.
Page 272: 3-Wire Serial I/O Mode Operation With Automatic Transmit/Receive Function
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 14.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of up to 64-byte data without using software. Once transfer is started, the set number of bytes of the data prestored in the RAM can be transmitted, and the set number of bytes of data can be received and stored in the RAM.
Page 273 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (a) Serial operating mode register 1 (CSIM1) CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H. Symbol <7> 6 <5> 4 Address After reset CSIM CSIM CSIM1 DIR ATE CSIE1...
Page 274 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H. Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset Note 1 ADTC...
Page 275 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specification register (ADTI) This register sets the data transfer interval of the automatic transmit/receive function. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Symbol Address After reset...
Page 276 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Notes 1. The interval is dependent only on CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if the minimum calculated by the following expression is smaller than 2/f , the minimum interval time is 2/f...
Page 277 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Symbol Address After reset ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH Data transfer interval specification (f = 5.0 MHz operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Minimum Note Maximum Note 446.4 µ s + 0.5/f 449.6 µ...
Page 278 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting [1] Write transmit data from the least significant address of buffer RAM, FAC0H (up to FAFFH). The transmit data should be in the order from higher address to lower address. [2] Set the automatic data transmit/receive address pointer (ADTP) to the value obtained by subtracting 1 from the number of transmit data bytes.
Page 279: Basic Transmission/Reception Mode Operation Timing
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which the specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is set to 1.
Page 280: Basic Transmission/Reception Mode Flowchart
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Figure 14-9. Basic Transmission/Reception Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
Page 281 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmission/reception mode, buffer RAM operates as follows. (i) Before transmission/reception (refer to Figure 14-10 (a)) After arbitrary data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
Page 282 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Figure 14-10. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmission/Reception Mode) (2/2) (b) 4th byte transmission/reception point FAFFH FAC5H Receive data 1 (R1) Receive data 4 (R4) SIO1 Receive data 2 (R2) Receive data 3 (R3) ADTP Transmit data 4 (T4) —1...
Page 283: Basic Transmission Mode Operation Timing
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is set to 1.
Page 284: Basic Transmission Mode Flowchart
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Figure 14-12. Basic Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
Page 285: Buffer Ram Operation In 6-Byte Transmission (In Basic Transmission Mode)
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 0, RE = 0) in basic transmission mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 14-13 (a)) After arbitrary data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
Page 286 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Figure 14-13. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode) (2/2) (b) 4th byte transmission point FAFFH FAC5H Transmit data 1 (T1) SIO1 Transmit data 2 (T2) Transmit data 3 (T3) ADTP Transmit data 4 (T4) —1 Transmit data 5 (T5)
Page 287: Repeat Transmission Mode Operation Timing
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is set to 1.
Page 288: Repeat Transmission Mode Flowchart
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Figure 14-15. Repeat Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmission/reception operation interval time in ADTI Write any data to SIO1 (Start trigger)
Page 289: Buffer Ram Operation In 6-Byte Transmission (In Repeat Transmission Mode)
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 When data of 6 bytes are transmitted in repeat transmission mode (ARLD = 1, RE = 0), the buffer RAM operates as follows. (i) Before transmission (refer to Figure 14-16 (a)) After arbitrary data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
Page 290 CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Figure 14-16. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (2/2) (b) Upon completion of transmission of 6 bytes FAFFH FAC5H Transmit data 1 (T1) SIO1 Transmit data 2 (T2) Transmit data 3 (T3) ADTP Transmit data 4 (T4) Transmit data 5 (T5)
Page 291: Automatic Transmission/Reception Suspension And Restart
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by resetting bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) to 0. If 8-bit data transfer is in progress, the transmission/reception is not suspended if bit 7 (CSIE1) is reset to 0.
Page 292: System Configuration With Busy Control Option
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are used to synchronize transmission/reception data between the master device and slave device. By using these functions, a bit slippage in data being transmitted/received can be detected. (a) Busy control option Busy control is used to allow a slave device to output a busy signal to the master device, so that the master device puts serial transmission/reception into a wait state while the busy signal is active.
Page 293: Operation Timing When Using Busy Control Option (Busy0 = 0)
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Figure 14-19. Operation Timing When Using Busy Control Option (BUSY0 = 0) SCK1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY Wait...
Page 294: Operation Timing When Using Busy & Strobe Control Option (Busy0 = 0)
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (b) Busy & strobe control option Strobe control is used to synchronize data transmission/reception between the master device and a slave device. The master device outputs a strobe signal from the STB/P23 pin on completion of transmission/reception of 8-bit data.
Page 295: Operation Timing Of Bit Slippage Detection Function Using Busy Signal (Busy0 = 1)
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (c) Bit slippage detection function with busy signal During automatic transmission/reception, bit slippage may take place in the serial clock of the slave device due to the noise carried on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit slippage affects transmission of the next byte.
Page 296: Automatic Transmit/Receive Interval
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval When the automatic transmit/receive function is used, one byte is transmitted/received and then the buffer RAM is read/written; therefore an interval is inserted before the next transmission/reception. When the automatic transmit/receive function is performed using an internal clock, since the read/write operations from/to the buffer RAM are done in parallel with CPU processing, the interval depends on the CPU processing at the timing of the serial clock’s eighth rising-edge and the value set in the automatic data transmit/receive interval specification register (ADTI).
Page 297: Interval Determined By Cpu Processing (With Internal Clock Operation)
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (a) When automatic transmit/receive function is performed using an internal clock The internal clock operation is selected when bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) is set to 1. In this case, the interval is determined as follows by CPU processing. When bit 7 (ADTI7) of the automatic data transmit/receive interval specification register (ADTI) is set to 0, the interval is determined by CPU processing.
Page 298: Interval Determined By Cpu Processing (With External Clock Operation)
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 (b) When automatic transmit/receive function is performed using an external clock The external clock operation is selected when bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) is cleared to 0. When the automatic transmit/receive function is performed using an external clock, the clock must be selected so that the interval is longer than the values shown below.
Page 299: Chapter 15 Vfd Controller/Driver
CHAPTER 15 VFD CONTROLLER/DRIVER 15.1 VFD Controller/Driver Functions The functions of the VFD controller/driver incorporated in the µ PD780208 Subseries are as follows. (1) Automatically outputs the segment signals (DMA operation) and digit signals by automatically reading data displayed. (2) Controls 9- to 40-segment and 2- to 16-digit VFDs (vacuum fluorescent display) using display mode registers 0, 1, and 2 (DSPM0 to DSPM2).
Page 300: Vfd Controller Operation Timing In Display Mode 1 (Dspm05 = 0)
CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-1. VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0) Digit signal FIP0 FIP1 FIP2 FIPn Key scan flag (KSF) Can be changed whenever necessary Segment Note signal 1 display cycle Key scan timing DSPM05: Bit 5 of display mode register 0 (DSPM0) Displayed digits –...
Page 301: Vfd Controller/Driver Configuration
CHAPTER 15 VFD CONTROLLER/DRIVER There are 53 display output pins. Of these, 40 pins, FIP13 to FIP52, have alternate port functions. These pins are used as port pins when display stop is set using bits 4 to 7 (DIGS0 to DIGS3) of display mode register 1 (DSPM1). Even when display is enabled, display output pins not used for outputting digit signals and segment signals can be used as port pins.
Page 302 CHAPTER 15 VFD CONTROLLER/DRIVER User’s Manual U11302EJ4V0UM...
Page 303: Vfd Controller/Driver Control Registers
CHAPTER 15 VFD CONTROLLER/DRIVER 15.3 VFD Controller/Driver Control Registers 15.3.1 Control registers There are three registers for controlling the VFD controller/driver. • Display mode register 0 (DSPM0) • Display mode register 1 (DSPM1) • Display mode register 2 (DSPM2) (1) Display mode register 0 (DSPM0) (see Figure 15-3) This register sets the following and displays the display timing/key scan state.
Page 304 CHAPTER 15 VFD CONTROLLER/DRIVER (3) Display mode register 2 (DSPM2) (see Figure 15-5) DSPM2 is the register that holds the number of mask bits in the display data storage area when display mode 2 (DSPM05 = 1) is selected by display mode register 0 (DSPM0). By using this register to mask the part of the display data that does not need to be rewritten, the software workload is reduced.
Page 305: Format Of Display Mode Register 0
CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-3. Format of Display Mode Register 0 (1/2) Symbol Address After reset DSPM0 DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 F F A 0 H 0 0 H R/W SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 Display segment (display mode 1) Display output total (display mode 2) Note Note...
Page 306 CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-3. Format of Display Mode Register 0 (2/2) Symbol Address After reset Note 1 DSPM0 DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 F F A 0 H 0 0 H R/W DSPM05 Display mode setting Display mode 1 (Segment/character type) Display mode 2 (Type in which a segment spans over two or more grids.) Note 2...
Page 307: Format Of Display Mode Register 1
CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-4. Format of Display Mode Register 1 Symbol Address After reset DSPM1 DIGS3 DIGS2 DIGS1 DIGS0 DIMS3 DIMS2 DIMS1 DIMS0 F F A 1 H 0 0 H DIMS0 Display mode cycle setting is 1 display cycle. (1 display cycle = 204.8 µ s: when operated at 5.0 MHz) 1024/f is 1 display cycle.
Page 308: Format Of Display Mode Register 2
CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-5. Format of Display Mode Register 2 (1/2) Symbol Address After reset DSPM2 USEG5 USEG4 USEG3 USEG2 USEG1 USEG0 F F A 2 H 0 0 H USEG5 USEG4 USEG3 USEG2 USEG1 USEG0 Number of mask bits to be written None User’s Manual U11302EJ4V0UM...
Page 309 CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-5. Format of Display Mode Register 2 (2/2) Symbol Address After reset DSPM2 USEG5 USEG4 USEG3 USEG2 USEG1 USEG0 F F A 2 H 0 0 H USEG5 USEG4 USEG3 USEG2 USEG1 USEG0 Number of mask bits to be written Other than the above Setting prohibited User’s Manual U11302EJ4V0UM...
Page 310: One-Display Period And Cut Width
CHAPTER 15 VFD CONTROLLER/DRIVER 15.3.2 One-display period and cut width The digit signal is equally cut at the beginning and end of the display period by the cut width set by bits 1 to 3 (DIMS1 to DIMS3) of display mode register 1 (DSPM1). Figure 15-6.
Page 311: Selecting Display Mode
CHAPTER 15 VFD CONTROLLER/DRIVER 15.4 Selecting Display Mode The number of segments and digits displayed by the VFD controller/driver depends on the display mode set. Figure 15-8. Selection of Display Mode Number of digits selected Caution When the total number of digits and segments together exceeds 53, the digits have priority. User’s Manual U11302EJ4V0UM...
Page 312: Display Mode And Display Output
CHAPTER 15 VFD CONTROLLER/DRIVER 15.5 Display Mode and Display Output The on-chip VFD controller/driver assigns pins FIP0 to FIP52/P127 to digit signals and segment signals (in this order). The number assigned is specified by display mode registers 0 and 1 (DSPM0 and DSPM1). The remaining pins are assigned as general-purpose ports.
Page 313: Display Data Memory
CHAPTER 15 VFD CONTROLLER/DRIVER 15.6 Display Data Memory The display data memory is the area for storing the segment data to be displayed. This memory is mapped at addresses FA30H to FA7FH. To display data on the VFD, the VFD controller reads the data stored in this memory regardless of the type of operations performed by the CPU (DMA operations).
Page 314: Key Scan Flag And Key Scan Data
CHAPTER 15 VFD CONTROLLER/DRIVER 15.7 Key Scan Flag and Key Scan Data 15.7.1 Key scan flag The key scan flag (KSF) is set to 1 during the key scan timing and reset automatically to 0 during the display timing. KSF is mapped at bit 7 of display mode register 0 (DSPM0) and can be tested one bit at a time. It cannot be written.
Page 315: Light Leakage Of Vfd
CHAPTER 15 VFD CONTROLLER/DRIVER 15.8 Light Leakage of VFD Light may leak when a VFD is driven using the µ PD780208 Subseries. Two possible causes are as follows. (1) Light leakage due to a short blanking time Figure 15-11 shows the signal waveforms when only the first digit of two digits to be displayed is lit. As shown in this figure, when the blanking time is short, the T1 signal rises before the segment signal disappears, resulting in light leakage.
Page 316 CHAPTER 15 VFD CONTROLLER/DRIVER Depending on the duty cycle of the spike noise voltage for the whole display period, the ease with which light leaks due to C varies. The fewer the number of digits displayed, the easier it is for light to leak. Lowering the luminance of the display is also effective.
Page 317: Display Examples
CHAPTER 15 VFD CONTROLLER/DRIVER 15.9 Display Examples The µ PD780208 Subseries has a VFD controller/driver that enables the following three types of VFD display. Display types can be switched by setting bit 5 (DSPM05) of display mode register 0 (DSPM0). •...
Page 318: Segment Type (Display Mode 1: Dspm05 = 0)
CHAPTER 15 VFD CONTROLLER/DRIVER 15.9.1 Segment type (display mode 1: DSPM05 = 0) Figure 15-14 shows the display data memory configuration and data reading order when the device controls a 10-segment x 11-digit VFD display. As “segment type” (display mode 1) is selected, the display data memory stores segment data. Figure 15-14.
Page 319 CHAPTER 15 VFD CONTROLLER/DRIVER User’s Manual U11302EJ4V0UM...
Page 320: Dot Type (Display Mode 1: Dspm05 = 0)
CHAPTER 15 VFD CONTROLLER/DRIVER 15.9.2 Dot type (display mode 1: DSPM05 = 0) Figure 15-16 shows the display data memory configuration and data reading order when the device controls a 35-segment (5 x 7 dots) x 16-digit VFD display. As “dot type” (display mode 1) is selected, the display data memory stores segment data. Figure 15-16.
Page 321: Relationship Between Display Data Memory Contents And Segment Outputs In 35-Segment X 16-Digit Display Mode
CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-17. Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode Display data memory FA7FH FA7EH FA7DH FA7CH FA7BH FA7AH FA79H FA78H FA77H FA76H FA75H FA74H FA73H FA72H FA71H FA70H FA6FH FA6EH FA6DH...
Page 322: Display Type In Which A Segment Spans Two Or More Grids (Display Mode 2: Dspm05 = 1)
CHAPTER 15 VFD CONTROLLER/DRIVER 15.9.3 Display type in which a segment spans two or more grids (display mode 2: DSPM05 = 1) In display mode 2, all of the display output data are stored in the display data memory. Figure 15-18 shows the display data RAM configuration and data reading order in a 23-segment x 5-grid display. Figure 15-18.
Page 323 CHAPTER 15 VFD CONTROLLER/DRIVER User’s Manual U11302EJ4V0UM...
Page 324: Grid Driving Timing
CHAPTER 15 VFD CONTROLLER/DRIVER The light timing of each segment is discussed next. In display example (3) in 15.9, a segment spans two grids (that is, 2G and 3G, 4G and 5G). Therefore, these segments will be lit at the timing from T0 to T6 as shown in Figure 15-20.
Page 325 CHAPTER 15 VFD CONTROLLER/DRIVER User’s Manual U11302EJ4V0UM...
Page 326: Calculating Total Power Dissipation
CHAPTER 15 VFD CONTROLLER/DRIVER 15.10 Calculating Total Power Dissipation The total power dissipation of the µ PD780208 Subseries is the sum of the values of the following three parts. Design your application set so that the sum is lower than the total power dissipation P stipulated in Figure 15-22.
Page 327 CHAPTER 15 VFD CONTROLLER/DRIVER By placing the above conditions in calculations <1> to <3>, the total dissipation can be worked out. <1> CPU power dissipation: 5.5 V × 21.6 mA = 118.8 mW <2> Output pin power dissipation: Total current value of each grid ) ×...
Page 328: Relationship Between Display Data Memory Contents And Segment Outputs In 10-Segment X 11-Digit Display Mode
CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-23 shows a display example and display data for “segment type”. Figure 15-23. Relationship Between Display Data Memory Contents and Segment Outputs in 10-Segment x 11-Digit Display Mode Display data memory FA7AH FA79H FA78H FA77H FA76H FA75H FA74H...
Page 329: Dot Type (Display Mode 1: Dspm05 = 0)
CHAPTER 15 VFD CONTROLLER/DRIVER 15.10.2 Dot type (display mode 1: DSPM05 = 0) The calculation method for the total power dissipation in the case of the display example in Figure 15-24 is described below. Example Assume the following conditions: = 5 V ±10%, 5.0 MHz oscillation Supply current (I ) = 21.6 mA Display output: 16 grids ×...
Page 330 CHAPTER 15 VFD CONTROLLER/DRIVER <3> Pull-down resistor power dissipation: – V No. of grids LOAD × × Digit width (1 – Cut width) = Grid Pull-down resistor value No. of grids + 1 (5.5 V – 2 V – (–35 V)) 16 grids ×...
Page 331: Relationship Between Display Data Memory Contents And Segment Outputs In 35-Segment X 16-Digit Display Mode
CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-24. Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode Display data memory FA7FH FA7EH FA7DH FA7CH FA7BH FA7AH FA79H FA78H FA77H FA76H FA75H FA74H FA73H FA72H FA71H FA70H FA6FH FA6EH FA6DH...
Page 332: Display Type In Which A Segment Spans Two Or More Grids (Display Mode 2: Dspm05 = 1)
CHAPTER 15 VFD CONTROLLER/DRIVER 15.10.3 Display type in which a segment spans two or more grids (display mode 2: DSPM05 = 1) The calculation method for the total power dissipation in the case of the display example in Figure 15-26 is described below.
Page 333: Grid Driving Timing
CHAPTER 15 VFD CONTROLLER/DRIVER Figure 15-25. Grid Driving Timing 1 display cycle Key scan timing User’s Manual U11302EJ4V0UM...
Page 334 CHAPTER 15 VFD CONTROLLER/DRIVER User’s Manual U11302EJ4V0UM...
Page 335: Chapter 16 Interrupt And Test Functions
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS 16.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally (that is, even in the interrupt disabled state). It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 336: Interrupt Sources And Configuration
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS 16.2 Interrupt Sources and Configuration A total of 15 interrupt sources are provided including non-maskable, maskable, and software interrupts (see Table 16-1). Table 16-1. Interrupt Source List Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority...
Page 337: Basic Configuration Of Interrupt Function
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Vector table Interrupt Priority controller address request generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table address Priority controller Interrupt generator...
Page 338 CHAPTER 16 INTERRUPT AND TEST FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) Internal bus External interrupt mode register (INTM0) Vector table address Priority controller Interrupt Edge generator request detector Standby release signal (E) Software interrupt Internal bus Vector table...
Page 339: Interrupt Function Control Registers
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS 16.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H) • Interrupt mask flag register (MK0L, MK0H) • Priority specification flag register (PR0L, PR0H) •...
Page 340: Format Of Interrupt Request Flag Register
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET.
Page 341: Format Of Interrupt Mask Flag Register
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing and to set standby clear enable/disable. MK0L and MK0H are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for setting.
Page 342: Format Of Priority Specification Flag Register
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H) The priority specification flag is used to set the corresponding maskable interrupt priority order. PR0L and PR0H are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for setting.
Page 343: Format Of External Interrupt Mode Register
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS (4) External interrupt mode register (INTM0) This register sets the valid edge for INTP0 to INTP2 and TI0. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Remarks 1. INTP0 is also used for TI0/P00. 2.
Page 344: Format Of Sampling Clock Select Register
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS (5) Sampling clock select register (SCS) This register is used to set the clock used to sample the valid edge input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is eliminated using the sampling clock. SCS is set with an 8-bit memory manipulation instruction.
Page 345: Noise Eliminator I/O Timing (When Rising Edge Is Detected)
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS The noise eliminator sets the interrupt request flag (PIF0) to 1 if the input level of the sampled INTP0 is active twice in succession. Figure 16-7 shows the noise eliminator I/O timing. Figure 16-7. Noise Eliminator I/O Timing (When Rising Edge Is Detected) (a) When input is less than the sampling cycle (t Sampling clock INTP0...
Page 346: Format Of Program Status Word
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag used to set maskable interrupt enable/disable and the ISP flag used to control multiple interrupt servicing are mapped to the PSW.
Page 347: Interrupt Servicing Operations
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS 16.4 Interrupt Servicing Operations 16.4.1 Non-maskable interrupt request acknowledgment operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledgment disabled state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents of program status word (PSW) and program counter (PC) are saved in the stacks in that order.
Page 348: Non-Maskable Interrupt Request Acknowledgment Flowchart
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS Figure 16-9. Non-Maskable Interrupt Request Acknowledgment Flowchart Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt request selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending...
Page 349: Non-Maskable Interrupt Request Acknowledgment Operation
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS Figure 16-11. Non-Maskable Interrupt Request Acknowledgment Operation If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main routine Execution of NMI request <1> NMI request <1> NMI request <2> held pending NMI request <2>...
Page 350: Maskable Interrupt Request Acknowledgment Operation
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS 16.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (MK) flag of the interrupt request is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled state (with IE flag set to 1).
Page 351: Interrupt Request Acknowledge Processing Algorithm
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS Figure 16-12. Interrupt Request Acknowledge Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (high priority) ××PR = 0? No (low priority) Any high- priority interrupt request among simultaneously generated simultaneously ××...
Page 352: Software Interrupt Request Acknowledgment Operation
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS Figure 16-13. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC save, Interrupt CPU processing Instruction Instruction jump to interrupt servicing servicing program ××IF (××PR = 1) 8 clocks ××IF (×× PR = 0) 7 clocks Remark 1 clock cycle = 1/f : CPU clock)
Page 353: Multiple Interrupt Servicing
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS 16.4.4 Multiple interrupt servicing Multiple interrupt servicing occurs when an interrupt request is acknowledged during execution of another interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1) (except non-maskable interrupts).
Page 354: Multiple Interrupt Servicing Example
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS Figure 16-15. Multiple Interrupt Servicing Example (1/2) Example 1. Two interrupts are generated Main processing INTxx INTyy INTzz servicing servicing servicing IE = 0 IE = 0 IE = 0 INTyy INTzz INTxx (PR = 0) (PR = 0) (PR = 1) RETI...
Page 355 CHAPTER 16 INTERRUPT AND TEST FUNCTIONS Figure 16-15. Multiple Interrupt Servicing Example (2/2) Example 3. Multiple interrupt servicing is not generated because interrupts are not enabled Main processing INTxx INTyy servicing servicing IE = 0 INTyy INTxx (PR = 0) (PR = 0) RETI IE = 0...
Page 356: Interrupt Request Hold
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS 16.4.5 Interrupt request hold Some instructions hold an interrupt request, if any, pending until the completion of execution of the next instruction. These instructions (that hold an interrupt request pending) are listed below. • MOV PSW, #byte •...
Page 357: Test Functions
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS 16.5 Test Functions The internal test input flag (WTIF) is set to 1 and a standby release signal is generated when the watch timer overflows. Unlike the interrupt function, this function does not perform vector processing. The basic configuration is shown in Figure 16-17.
Page 358: Test Input Signal Acknowledgment Operation
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register (IF0H) This register indicates whether a watch timer overflow is detected or not. IF0H is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears IF0H to 00H. Figure 16-18.
Page 359: Chapter 17 Standby Function
CHAPTER 17 STANDBY FUNCTION 17.1 Standby Function and Configuration 17.1.1 Standby function The standby function is used to decrease the power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock stops. The system clock oscillator continues oscillation.
Page 360: Standby Function Control Register
CHAPTER 17 STANDBY FUNCTION 17.1.2 Standby function control register The wait time after the STOP mode is released by an interrupt request until the oscillation stabilizes is controlled by the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 361: Standby Function Operations
CHAPTER 17 STANDBY FUNCTION 17.2 Standby Function Operations 17.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set during main system clock or the subsystem clock operation. The operating status in the HALT mode is described below.
Page 362: Halt Mode Release By Interrupt Request Generation
CHAPTER 17 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following four sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt request acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 363: Halt Mode Release By Reset Input
CHAPTER 17 STANDBY FUNCTION (d) Release by RESET input When a RESET signal is input, the HALT mode is released. As is the case with a normal reset operation, the program is executed after branch to the reset vector address. Figure 17-3.
Page 364: Stop Mode
CHAPTER 17 STANDBY FUNCTION 17.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only during main system clock operation. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull-up resistor to suppress the leakage at the crystal oscillator.
Page 365: Stop Mode Release By Interrupt Request Generation
CHAPTER 17 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following three sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. If interrupt request acknowledgment is enabled after the lapse of oscillation stabilization time, vectored interrupt servicing is carried out.
Page 366: Stop Mode Release By Reset Input
CHAPTER 17 STANDBY FUNCTION (c) Release by RESET input When a RESET signal is input, the STOP mode is released. After the lapse of oscillation stabilization time, a reset operation is carried out. Figure 17-5. STOP Mode Release by RESET Input Wait STOP : 26.2 ms)
Page 367: Chapter 18 Reset Function
CHAPTER 18 RESET FUNCTION 18.1 Reset Function The following two operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop time detection External reset and internal reset have no functional differences. In both cases, program execution starts at addresses 0000H and 0001H by RESET input.
Page 368: Timing Of Reset By Reset Input
CHAPTER 18 RESET FUNCTION Figure 18-2. Timing of Reset by RESET Input Oscillation Reset period Normal operation stabilization Normal operation (oscillation stop) (reset processing) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 18-3. Timing of Reset due to Watchdog Timer Overflow Oscillation Reset period Normal operation...
Page 369: Hardware Status After Reset
CHAPTER 18 RESET FUNCTION Table 18-1. Hardware Status After Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2...
Page 370 CHAPTER 18 RESET FUNCTION Table 18-1. Hardware Status After Reset (2/2) Hardware Status After Reset Watch timer Clock select register (TCL2) Watchdog timer Mode register (WDTM) Serial interface Clock select register (TCL3) Shift registers (SIO0, SIO1) Undefined Mode registers (CSIM0, CSIM1) Serial bus interface control register (SBIC) Slave address register (SVA) Undefined...
Page 371: Chapter 19 Μ Pd78P0208
CHAPTER 19 µ PD78P0208 The µ PD78P0208 is a product integrating a one-time programmable ROM (one-time PROM). Table 19- 1 shows the differences between the µ PD78P0208 and the mask ROM versions ( µ PD780204, 780204A, 780205, 780205A, 780206, and 780208). Table 19-1.
Page 372: Internal Memory Size Switching Register
CHAPTER 19 µ PD78P0208 19.1 Internal Memory Size Switching Register The internal memory capacity of the µ PD78P0208 can be selected by using the internal memory size switching register (IMS). The same memory map as that of the mask ROM version with a different internal memory capacity is possible by setting IMS.
Page 373: Format Of Internal Memory Size Switching Register (Ims)
CHAPTER 19 µ PD78P0208 Figure 19-1. Format of Internal Memory Size Switching Register (IMS) Symbol Address After reset Note IMS RAM2 RAM1 RAM0 ROM3 ROM2 ROM1 ROM0 FFF0H Internal ROM capacity ROM3 ROM2 ROM1 ROM0 selection 32 KB 40 KB 48 KB 60 KB Other than above...
Page 374: Internal Expansion Ram Size Switching Register
CHAPTER 19 µ PD78P0208 19.2 Internal Expansion RAM Size Switching Register By setting the internal expansion RAM size swtiching register (IXS), the µ PD78P0208 can have the same memory map as used in mask ROM versions that have a different internal expansion RAM capacity. For the mask ROM versions, IXS does not need to be set.
Page 375: Prom Programming
CHAPTER 19 µ PD78P0208 19.3 PROM Programming The µ PD78P0208 incorporates a 60 KB PROM as program memory. When programming, the PROM programming mode is set by means of the V pin and the RESET pin. For the connection of unused pins, refer to 1.5 Pin Configuration (Top View) (2) PROM programming mode.
Page 376 CHAPTER 19 µ PD78P0208 (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit. (5) Page write mode After a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed by applying a 0.1 ms program pulse (active-low) to the PGM pin while CE = H and OE = H.
Page 377: Prom Write Procedure
CHAPTER 19 µ PD78P0208 19.3.2 PROM write procedure Figure 19-3. Page Program Mode Flowchart Start Address = G = 6.5 V, V = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1...
Page 378: Page Program Mode Timing
CHAPTER 19 µ PD78P0208 Figure 19-4. Page Program Mode Timing Page data latch Page program Program verify A2 to A16 A0, A1 D0 to D7 Data input Data output + 1.5 User’s Manual U11302EJ4V0UM...
Page 379: Byte Program Mode Flowchart
CHAPTER 19 µ PD78P0208 Figure 19-5. Byte Program Mode Flowchart Start Address = G = 6.5 V, V = 12.5 V X = 0 X = X + 1 X = 10? 0.1 ms program pulse Address = Address + 1 Fail Verify Pass...
Page 380: Byte Program Mode Timing
CHAPTER 19 µ PD78P0208 Figure 19-6. Byte Program Mode Timing Program Program verify A0 to A16 D0 to D7 Data input Data output + 1.5 Cautions 1. Ensure that V is applied before V and removed after V 2. Ensure that V does not exceed +13.5 V including overshoot.
Page 381: Prom Read Procedure
CHAPTER 19 µ PD78P0208 19.3.3 PROM read procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V pin. Unused pins are handled as shown in 1.5 Pin Configuration (Top View) (2) PROM programming mode.
Page 382: Screening Of One-Time Prom Version
19.4 Screening of One-Time PROM Version A one-time PROM device ( µ PD78P0208GF-3BA) cannot be fully tested by NEC Electronics before shipment due to the nature of PROM. After the necessary data has been written, it is recommended to implement a screening process, that is, the written contents should be verified after the device has been stored under the following high-temperature conditions.
Page 383: Chapter 20 Instruction Set
CHAPTER 20 INSTRUCTION SET This chapter describes the instruction set for the µ PD780208 Subseries. For details of the operations and mnemonics (instruction codes) of each instruction, refer to the 78K/0 Series Instructions User’s Manual (U12326E). User’s Manual U11302EJ4V0UM...
Page 384: Conventions
CHAPTER 20 INSTRUCTION SET 20.1 Conventions 20.1.1 Operand identifiers and description methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them.
Page 385: Description Of "Operation" Column
CHAPTER 20 INSTRUCTION SET 20.1.2 Description of “operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 386: Operation List
CHAPTER 20 INSTRUCTION SET 20.2 Operation List Clocks Flag Instruc- Mnemonic Operands Bytes Operation tion Z AC CY Note 1 Note 2 Group r ← byte r, #byte – 8-bit data (saddr) ← byte saddr, #byte transfer sfr ← byte sfr, #byte –...
Page 387 CHAPTER 20 INSTRUCTION SET Instruc- Mnemonic Operands Bytes Operation Clocks Flag tion Z AC CY Note 1 Note 2 Group rp ← word MOVW rp, #word – 16-bit (saddrp) ← word data saddrp, #word transfer sfrp ← word sfrp, #word –...
Page 388 CHAPTER 20 INSTRUCTION SET Instruc- Mnemonic Operands Bytes Operation Clocks Flag tion Z AC CY Note 1 Note 2 Group A, CY ← A–byte × × × 8-bit A, #byte – operation (saddr), CY ← (saddr)–byte × × × saddr, #byte Note 3 A, CY ←...
Page 389 CHAPTER 20 INSTRUCTION SET Instruc- Mnemonic Operands Bytes Operation Clocks Flag tion Z AC CY Note 1 Note 2 Group A ← A × 8-bit A, #byte – byte operation (saddr) ← (saddr) × saddr, #byte byte Note 3 A ← A ×...
Page 390 CHAPTER 20 INSTRUCTION SET Instruc- Mnemonic Operands Bytes Operation Clocks Flag tion Z AC CY Note 1 Note 2 Group AX, CY ← AX+word × × × 16-bit ADDW AX, #word – operation AX, CY ← AX–word × × × SUBW AX, #word –...
Page 391 CHAPTER 20 INSTRUCTION SET Instruc- Mnemonic Operands Bytes Operation Clocks Flag tion Z AC CY Note 1 Note 2 Group CY ← CY × AND1 CY, saddr.bit (saddr.bit) CY ← CY × manipu- CY, sfr.bit – sfr.bit lation CY ← CY ×...
Page 392 CHAPTER 20 INSTRUCTION SET Instruc- Mnemonic Operands Bytes Operation Clocks Flag tion Z AC CY Note 1 Note 2 Group (SP–1) ← (PC+3) , (SP–2) ← (PC+3) Call CALL !addr16 – return PC ← addr16, SP ← SP–2 (SP–1) ← (PC+2) , (SP–2) ←...
Page 393 CHAPTER 20 INSTRUCTION SET Instruc- Mnemonic Operands Bytes Operation Clocks Flag tion Z AC CY Note 1 Note 2 Group PC ← PC+3+jdisp8 if (saddr.bit) = 1 saddr.bit, $addr16 Condi- PC ← PC+4+jdisp8 if sfr.bit = 1 tional sfr.bit, $addr16 –...
Page 394: Instructions Listed By Addressing Type
CHAPTER 20 INSTRUCTION SET 20.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ User’s Manual U11302EJ4V0UM...
Page 395 CHAPTER 20 INSTRUCTION SET Second Note #byte saddr !addr16 [DE] [HL] None [HL+byte] $addr16 Operand [HL+B] First Operand [HL+C] ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC SUBC SUBC ADDC SUBC B, C DBNZ saddr DBNZ ADDC SUBC !addr16...
Page 396 CHAPTER 20 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 397 CHAPTER 20 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User’s Manual U11302EJ4V0UM...
Page 398: Appendix A Differences Between Μ Pd78044H, 780228, And 780208 Subseries
APPENDIX A DIFFERENCES BETWEEN µ PD78044H, 780228, AND 780208 SUBSERIES Table A-1 shows the major differences between the µ PD78044H, 780228, and 780208 Subseries. Table A-1. Major Differences Between µ PD78044H, 780228, and 780208 Subseries µ PD78044H Subseries µ PD780228 Subseries µ...
Page 399: Appendix Bdevelopment Tools
APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD780208 Subseries. Figure B-1 shows the configuration of the development tools. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatible machines can be used for PC98- NX series computers.
Page 400: B-1 Configuration Of Development Tools
APPENDIX B DEVELOPMENT TOOLS Figure B-1. Configuration of Development Tools Software package • Software package Debugging software Language processing software • Assembler package • Integrated debugger • C compiler package • System simulator • Device file Note 1 • C library source file Control software •...
Page 401: Software Package
APPENDIX B DEVELOPMENT TOOLS B.1 Software Package SP78K0 This package contains various software tools for 78K/0 Series development. Software package The following tools are included. RA78K0, CC78K0, ID78K0-NS, SM78K0, and various device files Part Number: µ S××××SP78K0 Remark ×××× in the part number differs depending on the OS used. µ...
Page 402: Control Software
APPENDIX B DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 ×××× Host Machine Supply Medium AB13 PC-9800 series, Windows (Japanese version) 3.5-inch 2HD FD BB13 IBM PC/AT and compatibles Windows (English version) AB17 Windows (Japanese version)
Page 403: Prom Programming Tools
APPENDIX B DEVELOPMENT TOOLS B.4 PROM Programming Tools B.4.1 Hardware PG-1500 This PROM programmer allows users to encode the PROM in single-chip microcontrollers PROM programmer stand-alone or using a host machine. This requires connection of the accompanying board and separately-sold PROM programmer adapter to the PROM programmer. Besides internal PROMs, general discrete PROM devices whose capacities range from 256 Kb to 4 Mb can be programmed.
Page 404: Debugging Tools (Hardware)
APPENDIX B DEVELOPMENT TOOLS B.5 Debugging Tools (Hardware) B.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A The in-circuit emulator serves to debug hardware and software when developing IE-78K0-NS application systems using a 78K/0 Series product. It can be used with an integrated In-circuit emulator debugger (ID78K0-NS).
Page 405: When Using In-Circuit Emulator Ie-78001-R-A
APPENDIX B DEVELOPMENT TOOLS B.5.2 When using in-circuit emulator IE-78001-R-A This is an in-circuit emulator for debugging the hardware and software when an IE-78001-R-A application system using the 78K/0 Series is developed. It can be used with an In-circuit emulator integrated debugger (ID78K0).
Page 406: Debugging Tools (Software)
APPENDIX B DEVELOPMENT TOOLS B.6 Debugging Tools (Software) SM78K0 This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based System simulator software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine.
Page 407: Embedded Software
APPENDIX B DEVELOPMENT TOOLS B.7 Embedded Software The RX78K0 is a real-time OS conforming to the µ ITRON specifications. RX78K0 Real-time OS A tool (configurator) for generating the nucleus of the RX78K0 and multiple information tables is supplied. Used in combination with an assembler package (RA78K0) and device file (DF780208) (both sold separately).
Page 408: Method For Upgrading From Former In-Circuit Emulator For 78K/0 Series To Ie-78001-R-A
Table B-1. Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A Note In-Circuit Emulator Owned In-Circuit Emulator Cabinet System-Up Board to Be Purchased IE-78000-R Required IE-78001-R-BK IE-78000-R-A Not required Note For upgrading a cabinet, send your in-circuit emulator to NEC Electronics. User’s Manual U11302EJ4V0UM...
Page 409: Conversion Socket (Ev-9200Gf-100) Package Drawing And Recommended Footprint
APPENDIX B DEVELOPMENT TOOLS B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended Footprint Figure B-2. EV-9200GF-100 Package Drawing (for Reference Purposes only) EV-9200GF-100 No.1 pin index EV-9200GF-100-G0 ITEM MILLIMETERS INCHES 24.6 0.969 0.827 0.591 18.6 0.732 4-C 2 4-C 0.079 0.031 12.0 0.472...
Page 410: B-3 Recommended Footprint For Ev-9200Gf-100 (For Reference Purposes Only)
APPENDIX B DEVELOPMENT TOOLS Figure B-3. Recommended Footprint for EV-9200GF-100 (for Reference Purposes only) EV-9200GF-100-P1 ITEM MILLIMETERS INCHES 26.3 1.035 21.6 0.85 0.65 ± 0.02 × 29=18.85 ± 0.05 +0.001 +0.002 × 1.142=0.742 0.026 _ 0.002 —0.002 0.65 ± 0.02 × 19=12.35 ± 0.05 +0.001 +0.003 ×...
Page 411: Notes On Target System Design
APPENDIX B DEVELOPMENT TOOLS B.10 Notes on Target System Design The following shows the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Among the products described in this appendix, the NP-100GF-TQ and NP-H100GF-TQ are products of Naito Densei Machida Mfg.
Page 412: B-5 Connection Conditions Of Target System (When Np-100Gf-Tq Is Used)
APPENDIX B DEVELOPMENT TOOLS Figure B-5. Connection Conditions of Target System (When NP-100GF-TQ Is Used) Emulation board IE-780208-NS-EM1 Emulation probe NP-100GF-TQ Conversion adapter 11 mm TGF-100RBP 27.5 mm Pin 1 21 mm 40 mm 34 mm Target system Figure B-6. Connection Conditions of Target System (When NP-H100GF-TQ Is Used) Emulation board IE-780208-NS-EM1 Emulation probe...
Page 413: Appendix Cregister Index
APPENDIX C REGISTER INDEX C.1 Register Index (by Register Name) A/D conversion result register (ADCR) ... 192 A/D converter input select register (ADIS) ... 196 A/D converter mode register (ADM) ... 194 Automatic data transmit/receive address pointer (ADTP) ... 259 Automatic data transmit/receive control register (ADTC) ...
Page 414 APPENDIX C REGISTER INDEX Port 11 (P11) ... 93 Port 12 (P12) ... 94 Port mode register 0 (PM0) ... 95 Port mode register 1 (PM1) ... 95 Port mode register 2 (PM2) ... 95 Port mode register 3 (PM3) ... 95, 132, 157, 185, 189 Port mode register 7 (PM7) ...
Page 415: Register Index (By Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (by Register Symbol) ADCR: A/D conversion result register ... 192 ADIS: A/D converter input select register ... 196 ADM: A/D converter mode register ... 194 ADTC: Automatic data transmit/receive control register ... 263, 274 ADTI: Automatic data transmit/receive interval specification register ...
Page 416 APPENDIX C REGISTER INDEX PCC: Processor clock control register ... 102 PM0: Port mode register 0 ... 95 PM1: Port mode register 1 ... 95 PM2: Port mode register 2 ... 95 PM3: Port mode register 3 ... 95, 132, 157, 185, 189 PM7: Port mode register 7 ...
Page 417: Appendix D Revision History
APPENDIX D REVISION HISTORY Here is the revision history of this manual. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/2) Edition Revisions from Previous Edition Applied to: • The following products are already developed: µ PD780204GF-×××-3BA, Second Throughout µ...
Page 418 APPENDIX D REVISION HISTORY (2/2) Edition Revisions from Previous Edition Applied to: Third Correction of Cautions when the STOP mode is set CHAPTER 17 STANDBY FUNCTION µ Addition of APPENDIX A DIFFERENCES AMONG PD78044H, 780228, AND APPENDIX A 780208 SUBSERIES DIFFERENCES AMONG µ...

This manual is also suitable for:

Mpd780204 Mpd780206Mpd780208Mpd78p0208 Mpd780204a Mpd780205a ... Show all

NEC mPD780208 Subseries User Manual

Chapter 1 Outline

Features

Applications

Ordering Information

Quality Grade

Pin Configuration (Top View)

Series Lineup

Block Diagram

Overview of Functions

Mask Options

Chapter 2 Pin Functions

Pin Function List

Description of Pin Functions

Pin I/O Circuits and Recommended Connection of Unused Pins

Chapter 3 Cpu Architecture

Memory Space

Processor Registers

Instruction Address Addressing

Operand Address Addressing

Chapter 4 Port Functions

Port Configuration

Port Function Control Registers

Port Function Operations

Selection of Mask Option

Chapter 5 Clock Generator

Clock Generator Functions

Clock Generator Configuration

Clock Generator Control Registers

System Clock Oscillator

Clock Generator Operations

Changing System Clock and CPU Clock Settings

Chapter 6 16-Bit Timer/Event Counter

Outline of Timers Incorporated in Μ PD780208 Subseries

16-Bit Timer/Event Counter Functions

16-Bit Timer/Event Counter Configuration

16-Bit Timer/Event Counter Control Registers

16-Bit Timer/Event Counter Operations

16-Bit Timer/Event Counter Operating Precautions

Chapter 7 8-Bit Timer/Event Counter

8-Bit Timer/Event Counter Functions

8-Bit Timer/Event Counter Configuration

8-Bit Timer/Event Counter Control Registers

8-Bit Timer/Event Counter Operations

8-Bit Timer/Event Counter Operating Precautions

Chapter 8 Watch Timer

Watch Timer Functions

Watch Timer Configuration

Watch Timer Control Registers

Watch Timer Operations

Chapter 9 Watchdog Timer

Watchdog Timer Functions

Watchdog Timer Configuration

Watchdog Timer Control Registers

Watchdog Timer Operations

Chapter 10 Clock Output Controller

Clock Output Controller Functions

Clock Output Controller Configuration

Clock Output Function Control Registers

Chapter 11 Buzzer Output Controller

Buzzer Output Controller Functions

Buzzer Output Controller Configuration

Buzzer Output Function Control Registers

Chapter 12 A/D Converter

A/D Converter Functions

A/D Converter Configuration

A/D Converter Control Registers

A/D Converter Operations

A/D Converter Precautions

Chapter 13 Serial Interface Channel 0

Functions of Serial Interface Channel 0

Configuration of Serial Interface Channel 0

Control Registers of Serial Interface Channel 0

Operations of Serial Interface Channel 0

Chapter 14 Serial Interface Channel 1

Functions of Serial Interface Channel 1

Configuration of Serial Interface Channel 1

Control Registers of Serial Interface Channel 1

Operations of Serial Interface Channel 1

Quick Links