Page 1 Preliminary User’s Manual µPD780852 Subseries 8-Bit Single-Chip Microcontrollers µPD780851(A) µPD780852(A) µPD78F0852 Document No. U14581EJ3V0UM00 (3rd edition) Date Published October 2000 J CP(K) © 2000 Printed in Japan...
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Page 3 SUMMARY OF CONTENTS CHAPTER 1 OUTLINE ........................CHAPTER 2 PIN FUNCTION ......................CHAPTER 3 CPU ARCHITECTURE ....................CHAPTER 4 PORT FUNCTIONS ..................... CHAPTER 5 CLOCK GENERATOR ....................CHAPTER 6 16-BIT TIMER 0 TM0 ....................101 CHAPTER 7 8-BIT TIMER 1 TM1 ....................113 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 ..........
Page 4 Major Revisions in This Edition Page Description p.29 Changing 1.5 Pin Configuration (Top View) p.34 Changing description of supply voltage in 1.8 Outline of Function p.107 Changing 6.4 (4) Port mode register 4 (PM4) p.111 Changing Figure 6-11 Capture Register Data Retention Timing p.211 Adding Caution 3 to Figure 16-4 LCD Display Control Register (LCDC) Format p.278...
Page 5 Reset operation must be executed immediately after power-on for devices having reset function. IEBus is a trademark of NEC Corporation. Windows and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 6 NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
Page 7 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
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Page 9 INTRODUCTION Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD780852 Subseries and design and develop its application systems and programs. µ PD780852 Subseries: µ PD780851(A), 780852(A), 78F0852 Purpose This manual is designed to help users understand the following functions using the organization below.
Page 10 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Related documents for µ PD780852 Subseries Document No. Document Name Japanese English µ PD780851(A), 780852(A) Preliminary Product Information U14577J U14577E µ...
Page 11 English SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
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Page 13: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ........................1.1 Features ..........................1.2 Applications ......................... 1.3 Ordering Information ......................1.4 Quality Grade ........................1.5 Pin Configuration (Top View) ..................... 1.6 78K/0 Series Product Development ................... 1.7 Block Diagram ........................1.8 Outline of Function ......................CHAPTER 2 PIN FUNCTION ......................
Page 14 3.2.2 General registers ........................3.2.3 Special-function registers (SFRs) ....................3.3 Instruction Address Addressing ..................3.3.1 Relative addressing ........................3.3.2 Immediate addressing ........................ 3.3.3 Table indirect addressing ......................3.3.4 Register addressing ........................3.4 Operand Address Addressing .................... 3.4.1 Implied addressing ........................3.4.2 Register addressing ........................
Page 15 CHAPTER 6 16-BIT TIMER 0 TM0 ....................101 6.1 Outline of Internal Timer of µ PD780852 Subseries ............101 6.2 16-Bit Timer 0 TM0 Functions ..................... 103 6.3 16-Bit Timer 0 TM0 Configuration ..................104 6.4 16-Bit Timer 0 TM0 Control Registers ................105 6.5 16-Bit Timer 0 TM0 Operations ...................
Page 16 11.4 Clock Output Controller Operation ..................152 CHAPTER 12 A/D CONVERTER ...................... 153 12.1 A/D Converter Functions ....................153 12.2 A/D Converter Configuration ....................155 12.3 A/D Converter Control Registers ..................157 12.4 A/D Converter Operations ....................160 12.4.1 Basic operations of A/D converter ....................12.4.2 Input voltage and conversion results ..................
Page 17 CHAPTER 17 SOUND GENERATOR ....................223 17.1 Sound Generator Function ....................223 17.2 Sound Generator Configuration ..................224 17.3 Sound Generator Control Registers .................. 225 17.4 Sound Generator Operations ..................... 229 17.4.1 To output basic cycle signal SGO ....................CHAPTER 18 METER CONTROLLER/DRIVER ................231 18.1 Meter Controller/Driver Functions ..................
Page 18 23.1 Legend for Operation List ....................282 23.1.1 Operand identifiers and description formats ................23.1.2 Description of “Operation” column ....................23.1.3 Description of “flag operation” column ..................23.2 Operation List ........................284 23.3 Instructions Listed by Addressing Type ................292 APPENDIX A DEVELOPMENT TOOLS ...................
Page 19 LIST OF FIGURES (1/5) Figure No. Title Page I/O Circuits of Pins ..........................Memory Map ( µ PD780851(A)) ......................Memory Map ( µ PD780852(A)) ......................Memory Map ( µ PD78F0852) ......................Data Memory Addressing ( µ PD780851(A)) ..................Data Memory Addressing ( µ PD780852(A)) ..................Data Memory Addressing ( µ...
Page 20 LIST OF FIGURES (2/5) Figure No. Title Page CR0m Capture Operation with Rising Edge Specified ..............Pulse Width Measurement Operation Timing by Free-Running Counter (with Both Edges Specified) ......................6-10 16-Bit Timer Register Start Timing ....................6-11 Capture Register Data Retention Timing ..................8-Bit Timer 1 TM1 Block Diagram .....................
Page 21 LIST OF FIGURES (3/5) Figure No. Title Page 12-6 Power-Fail Compare Threshold Value Register (PFT) Format ............12-7 Basic Operation of 8-Bit A/D Converter .................... 12-8 Relation between Analog Input Voltage and A/D Conversion Result ..........12-9 A/D Conversion ..........................12-10 Example of Method of Reducing Current Consumption in Standby Mode ........
Page 22 LIST OF FIGURES (4/5) Figure No. Title Page 17-1 Sound Generator Block Diagram ...................... 17-2 Concept of Basic Cycle Output Signal SGO ..................17-3 Sound Generator Control Register (SGCR) Format ................. 17-4 Sound Generator Buzzer Control Register (SGBR) Format ............. 17-5 Sound Generator Amplitude Register (SGAM) Format ..............
Page 23 LIST OF FIGURES (5/5) Figure No. Title Page 22-1 Memory Size Switching Register (IMS) Format ................22-2 Internal Expansion RAM Size Switching Register (IXS) Format ............22-3 Transmission Method Selection Format ................... 22-4 Flashpro III Connection Using 3-Wire Serial I/O Method (SIO3) ............22-5 Flashpro III Connection Using 3-Wire Serial I/O Method (SIO2) ............
Page 24 LIST OF TABLES (1/2) Table No. Title Page Pin Input/Output Circuit Types ......................Internal Memory Capacity ......................... Vector Table ............................Special-Function Register List ......................Port Functions ........................... Port Configuration ..........................Clock Generator Configuration ......................Relation between CPU Clock and Minimum Instruction Execution Time .......... Maximum Time Required for Switching CPU Clock ................
Page 25 LIST OF TABLES (2/2) Table No. Title Page 16-1 Maximum Number of Display Pixels ....................16-2 LCD Controller/Driver Configuration ....................16-3 COM Signals ............................. 16-4 LCD Drive Voltage ..........................16-5 LCD Drive Voltage ..........................16-6 Selection and Non-Selection Voltages (COM0 to COM3) ..............17-1 Sound Generator Configuration ......................
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Page 27: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features • Internal memory Item Program Memory Data Memory Part Number (ROM/Flash Memory) Internal High-Speed RAM Internal Expansion RAM LCD Display RAM µ PD780851(A) 20 × 4 bits 32 Kbytes 1,024 bytes 512 bytes µ PD780852(A) 40 Kbytes µ...
Page 28: Ordering Information
Remark ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Device" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Preliminary User’s Manual U14581EJ3V0UM00...
Page 29: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) • 80-pin plastic QFP (14 × 14 mm) µ PD780851GC(A)-×××-8BT, 780852GC(A)-×××-8BT, 78F0852GC-8BT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P85/S15 P84/S16 P83/S17...
Page 30 CHAPTER 1 OUTLINE ANI0 to ANI4: Analog Input SCK2, SCK3: Serial Clock Analog Reference Voltage SGO: Sound Generator Output Analog Ground SI2, SI3: Serial Input COM0 to COM3: Common Output SM11 to SM14, SM21 to SM24, SM31 to SM34, SM41 to SM44: Internally Connected Meter Output INTP0 to INTP2: External Interrupt Input...
Page 31: Series Product Development
CHAPTER 1 OUTLINE 1.6 78K/0 Series Product Development These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I C bus.
Page 32 CHAPTER 1 OUTLINE The major functional differences among the subseries are shown below. Function Timer 8-Bit 10-Bit 8-Bit External Serial Interface MIN. Capacity A/D D/A Expansion 8-Bit 16-Bit Watch WDT Subseries Name Value µ PD78075B 32 K to 40 K Control 4 ch 1 ch...
Page 33: Block Diagram
CHAPTER 1 OUTLINE 1.7 Block Diagram TI00/P40 to TI02/P42 P00 to P07 16-bit TIMER0 PORT0 TPO/PCL/P60 P10 to P14 8-bit TIMER1 PORT1 8-bit TIMER/ TIO2/P43 EVENT PORT2 P20 to P27 COUNTER2 8-bit TIMER/ TIO3/P44 EVENT PORT3 P30 to P37 COUNTER3 WATCHDOG PORT4 P40 to P44...
Page 34: Outline Of Function
CHAPTER 1 OUTLINE 1.8 Outline of Function Part Number µ PD780851(A) µ PD780852(A) µ PD78F0852 Item Internal memory 32 Kbytes 40 Kbytes 40 Kbytes (Mask ROM) (Mask ROM) (Flash memory) High-speed RAM 1,024 bytes Expanded RAM 512 bytes 20 × 4 bits LCD display RAM 8 bits ×...
Page 35: Pin Function
CHAPTER 2 PIN FUNCTION 2.1 Pin Function List (1) Port Pins Alternate Pin Name Input/Output Function After Reset Function Port 0 P00 to P02 Input/Output Input INTP0 to INTP2 8-bit input/output port. SCK2 Input/output mode can be specified in 1-bit units. On-chip pull-up resistor can be used by software.
Page 36 CHAPTER 2 PIN FUNCTION (2) Non-port pins Alternate Pin Name Input/Output Function After Reset Function INTP0 to INTP2 Input External interrupt request input with specifiable valid edges Input P00 to P02 (rising edge, falling edge, and both rising and falling edges). Input Serial interface SIO2 serial data input.
Page 37 CHAPTER 2 PIN FUNCTION Alternate Pin Name Input/Output Function After Reset Function — Regulator output pin for power supply of pins other than — — ROUT via a 0.1- µ F port pins. Connect this pin to V or V capacitor.
Page 38: Description Of Pin Functions
CHAPTER 2 PIN FUNCTION 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit input/output port. In addition, they also function as external interrupt request input, serial interface data input/output, and clock input/output pins. The following operation modes can be specified in 1-bit units.
Page 39: P20 To P27 (Port 2)
CHAPTER 2 PIN FUNCTION 2.2.3 P20 to P27 (Port 2) These pins constitute an 8-bit output only port. In addition, they also function as PWM output pins for meter control. The following operation modes can be specified in 1-bit units. (1) Port mode In this mode, P20 to P27 function as an 8-bit output only port.
Page 40: P50 To P54 (Port 5)
CHAPTER 2 PIN FUNCTION 2.2.6 P50 to P54 (Port 5) These pins constitute a 5-bit input/output port. In addition, they also function as serial interface data input/output and clock input/output pins. The following operation modes can be specified in 1-bit units. (1) Port mode In this mode, P50 to P54 function as a 5-bit input/output port.
Page 41: P81 To P87 (Port 8)
CHAPTER 2 PIN FUNCTION 2.2.8 P81 to P87 (Port 8) These pins constitute a 7-bit input/output port. In addition, they also function as segment signal output pins of the LCD controller/driver. The following operation modes can be specified in 1-bit units. (1) Port mode In this mode, P81 to P87 function as a 7-bit input/output port.
Page 42: Smv Dd
CHAPTER 2 PIN FUNCTION 2.2.16 SMV This pin supplies a positive power to the meter controller/driver. 2.2.17 SMV This is the ground pin of the meter controller/driver. 2.2.18 V Positive power supply port pin. 2.2.19 V ROUT This is a regulator output pin for the power supply to pins other than port pins. Connect this pin to V or V via a 0.1- µ...
Page 43: Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTION 2.3 Input/Output Circuits and Recommended Connection of Unused Pins Table 2-1 shows the input/output circuit types of pins and the recommended connection for unused pins. See Figure 2-1 for the configuration of the input/output circuit of each type. Table 2-1.
Page 44 CHAPTER 2 PIN FUNCTION Figure 2-1. I/O Circuits of Pins (1/2) Type 2 Type 8 data P-ch IN/OUT output N-ch disable Schmitt-triggered input with hysteresis characteristics Type 4 Type 8-A pullup P-ch enable data P-ch data P-ch IN/OUT output N-ch output disable N-ch...
Page 45 CHAPTER 2 PIN FUNCTION Figure 2-1. I/O Circuits of Pins (2/2) Type 17 Type 17-G P-ch N-ch data P-ch P-ch IN/OUT data output N-ch N-ch P-ch disable N-ch input enable Type 18 P-ch N-ch P-ch P-ch N-ch N-ch data P-ch N-ch P-ch N-ch...
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Page 47: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Spaces The µ PD780852 Subseries can access a 64-Kbyte memory space. Figures 3-1 to 3-3 show memory maps of the respective devices. Figure 3-1. Memory Map ( µ PD780851(A)) FFFFH Special function registers (SFRs) 256 ×...
Page 48 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ PD780852(A)) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H FEFFH General registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1,024 × 8 bits FB00H FAFFH Reserved FA6DH FA6CH 9FFFH...
Page 49 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( µ PD78F0852) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H FEFFH General registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1,024 × 8 bits FB00H FAFFH Reserved FA6DH FA6CH 9FFFH...
Page 50: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space contains the program and table data. Normally, it is addressed with the program counter (PC). The µ PD780852 Subseries incorporate internal ROM (or flash memory), as listed below. Table 3-1.
Page 51: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space The µ...
Page 52: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. The address of an instruction to be executed next is addressed by the program counter (PC) (for details, see 3.3 Instruction Address Addressing).
Page 53 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Data Memory Addressing ( µ PD780852(A)) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH Internal high-speed RAM 1,024 ×...
Page 54 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Data Memory Addressing ( µ PD78F0852) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH Internal high-speed RAM 1,024 ×...
Page 55: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD780852 Subseries incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, status, and stack memory. The control registers consist of a program counter (PC), a program status word (PSW), and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 56 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to DI, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all disabled. When 1, the IE is set to EI and interrupt request acknowledge enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specify flag.
Page 57 CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-9. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented prior to write (save) to the stack memory and is incremented after read (restore) from the stack memory.
Page 58: General Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General registers General registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. Four banks of general registers, each consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H) are available. Each register can also be used as an 8-bit register.
Page 59: Special-Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special-function registers (SFRs) Unlike the general registers, these registers have special functions. They are allocated in the FF00H to FFFFH area. The special-function registers can be manipulated like the general registers, with the operation, transfer and bit manipulation instructions.
Page 60 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special-Function Register List (1/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits FF00H Port 0 — FF01H Port 1 — — Note FF02H Port 2 —...
Page 61 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special-Function Register List (2/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits FF20H Port mode register 0 — FF22H Port mode register 2 — FF23H Port mode register 3 —...
Page 62 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special-Function Register List (3/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits FF80H A/D converter mode register ADM1 — FF81H Analog input channel specification register ADS1 —...
Page 63: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 64: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16, BR !addr16, or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 65: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 66: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed.
Page 67: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general register to be specified is accessed as an operand with the register specify code (Rn and RPn) in an operation code and with the register bank select flags (RBS0 and RBS1). Register addressing is carried out when an instruction with the following operand format is executed.
Page 68: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code...
Page 69: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal high-speed RAM and a special- function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 70: Special-Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special-function register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 71: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] This addressing is to address a memory area to be manipulated by using as an operand address the contents of a register pair specified by the register bank select flags (RBS0 and RBS1) and the register pair specification code in the operation code.
Page 72: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flags (RBS0 and RBS1) and the sum is used to address the memory.
Page 73: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only.
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Page 75: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD780852 Subseries are provided with five input port pins, sixteen output port pins, and thirty-five input/output port pins. Figure 4-1 shows the port configuration. Every port can be manipulated in 1-bit or 8-bit units controlled in various ways.
Page 76 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Alternate Pin Name Input/Output Function Function P00 to P02 Input/Output Port 0 INTP0 to INTP2 8-bit input/output port. SCK2 Input/output mode can be specified in 1-bit units. On-chip pull-up resistor can be used by software. P06, P07 —...
Page 77: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration A port consists of the following hardware. Table 4-2. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 2 to 6, 8, 9) Pull-up resistor option register (PU0) Port Total: 56 (5 inputs, 16 outputs, 35 inputs/outputs) Pull-up resistor Total: 8 (software specifiable: 8)
Page 78: Port 1
CHAPTER 4 PORT FUNCTIONS Figure 4-2. P00 to P07 Block Diagram PU00 to PU07 P-ch Selector PORT P00/INTP0 to P02/INTP2 P03/SCK2 Output latch P04/SO2 (P00 to P07) P05/SI2 PM00 to PM07 Alternate functions PU: Pull-up resistor option register PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal 4.2.2 Port 1...
Page 79: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an 8-bit output only port with output latch. P20 to P27 pins go into a high-impedance state when the ENn of port mode control register (PMC) is set to 0 and the port mode register 2 (PM2) is set to 1. Alternate functions include meter control PWM output.
Page 80: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is an 8-bit output only port with output latch. P30 to P37 pins go into a high-impedance state when the ENn of port mode control register (PMC) is set to 0 and the port mode register 3 (PM3) is set to 1. Alternate functions include meter control PWM output.
Page 81: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is a 5-bit input/output port with output latch. P40 to P44 pins can specify the input mode/output mode in 1-bit units with the port mode register 4 (PM4). Alternate functions also include timer input/output. RESET input sets port 4 to input mode.
Page 82: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is a 5-bit input/output port with output latch. P50 to P54 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). Alternate functions include serial interface data input/output and clock input/output. RESET input sets port 5 to input mode.
Page 83: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 6 Port 6 is a 2-bit input/output port with output latch. P60 and P61 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). Alternate functions include clock output and sound generator output. RESET input sets port 6 to input mode.
Page 84: Port 8
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 8 Port 8 is a 7-bit input/output port with output latch. P81 to P87 pins can specify the input mode/output mode in 1-bit units with the port mode register 8 (PM8). Alternate functions also include segment signal output of the LCD controller/driver. Segment output and input/output port can be switched by setting the LCD display control register (LCDC).
Page 85: Port 9
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 9 Port 9 is an 8-bit input/output port with output latch. P90 to P97 pins can specify the input mode/output mode in 1-bit units with the port mode register 9 (PM9). Alternate functions also include segment signal output of the LCD controller/driver. Segment output and input/output port can be switched by setting the LCD display control register (LCDC).
Page 86: Port Function Control Registers
CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM2 to PM6, PM8, PM9) • Pull-up resistor option register (PU0) (1) Port mode registers (PM0, PM2 to PM6, PM8, PM9) These registers are used to set port input/output in 1-bit units.
Page 87 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Port Mode Register (PM0, PM4 to PM6, PM8, PM9) Format Address: FF20H After Reset: FFH Symbol PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 Address: FF24H After Reset: FFH Symbol PM44 PM43 PM42 PM41 PM40 Address: FF25H After Reset: FFH Symbol...
Page 88 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option register (PU0) This register is used to set whether to use an on-chip pull-up resistor at port 0 or not. By setting the PU0, the on-chip pull-up resistor of the corresponding port pin can be used. PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 89: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
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Page 91: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. • Main system clock oscillator This circuit oscillates at frequencies of 4.00 to 8.38 MHz. Oscillation can be stopped by executing the STOP instruction.
Page 92: Clock Generator Control Registers
CHAPTER 5 CLOCK GENERATOR 5.3 Clock Generator Control Registers The following two types of registers are used to control the clock generator. • Processor clock control register (PCC) • Oscillator mode register (OSCM) (1) Processor clock control register (PCC) PCC sets the division ratio of the CPU clock. PCC is set with a 1-bit or 8-bit memory manipulation instruction.
Page 93 CHAPTER 5 CLOCK GENERATOR (2) Oscillator mode register (OSCM) The µ PD780851(A) and µ PD780852(A) can be set to the reduced current consumption mode by setting OSCM (only when operated at f = 4 to 4.19 MHz). OSCM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears OSCM to 00H.
Page 94: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.38 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an inverted clock signal to the X2 pin.
Page 95 CHAPTER 5 CLOCK GENERATOR Figure 5-5. Incorrect Examples of Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 6, 8 and 9) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current...
Page 96: Divider Circuit
CHAPTER 5 CLOCK GENERATOR Figure 5-5. Incorrect Examples of Resonator Connection (2/2) Signals are fetched 5.4.2 Divider circuit The divider circuit divides the output of the main system clock oscillator (f ) to generate various clocks. Preliminary User’s Manual U14581EJ3V0UM00...
Page 97: Clock Generator Operations
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode: • Main system clock • CPU clock • Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) and oscillator mode register (OSCM) as follows: (a) The slowest mode (3.81 µ...
Page 98: Changing Setting Of Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Changing Setting of CPU Clock 5.6.1 Time required for switching CPU clock The CPU clock can be selected by using bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 5-3).
Page 99: Switching Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6.2 Switching CPU clock The following figure illustrates how the CPU clock switches. Figure 5-6. Switching CPU Clock RESET CPU clock Slowest Fastest operation operation Wait (15.6 ms: at 8.38-MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the main system clock starts oscillating.
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Page 101: Chapter 6 16-Bit Timer 0 Tm0
CHAPTER 6 16-BIT TIMER 0 TM0 6.1 Outline of Internal Timer of µ PD780852 Subseries This chapter explains the 16-bit timer 0. Before that, the internal timers of the µ PD780852 Subseries, and the related functions are briefly explained below. (1) 16-bit timer 0 TM0 The TM0 can be used for pulse widths measurement, divided output of input pulse.
Page 102 CHAPTER 6 16-BIT TIMER 0 TM0 Table 6-1. Timer/Event Counter Operations 8-Bit Timer/Event 16-Bit Timer TM0 8-Bit Timer TM1 Watch Timer Watchdog Timer Counter TM2, TM3 Note 1 Note 2 Operating Interval timer 2 channels 1 channel 2 channels 1 channel 1 channel mode External event counter...
Page 103: 16-Bit Timer 0 Tm0 Functions
CHAPTER 6 16-BIT TIMER 0 TM0 6.2 16-Bit Timer 0 TM0 Functions The 16-bit timer 0 TM0 has the following functions. • Pulse width measurement • Divided output of input pulse Figure 6-1 shows 16-bit timer 0 TM0 block diagram. Figure 6-1.
Page 104: 16-Bit Timer 0 Tm0 Configuration
CHAPTER 6 16-BIT TIMER 0 TM0 6.3 16-Bit Timer 0 TM0 Configuration 16-bit timer 0 TM0 consists of the following hardware. Table 6-2. 16-Bit Timer 0 TM0 Configuration Item Configuration 16 bits × 1 (TM0) Timer register Capture register: 16 bits × 3 (CR00 to CR02) Register Control register 16-bit timer mode control register (TMC0)
Page 105: 16-Bit Timer 0 Tm0 Control Registers
CHAPTER 6 16-BIT TIMER 0 TM0 6.4 16-Bit Timer 0 TM0 Control Registers The following four types of registers are used to control 16-bit timer 0 TM0. • 16-bit timer mode control register (TMC0) • Capture pulse control register (CRC0) •...
Page 106 CHAPTER 6 16-BIT TIMER 0 TM0 (2) Capture pulse control register (CRC0) This register specifies the division ratio of the capture pulse input to the 16-bit capture register (CR02) from an external source. CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC0 to 00H.
Page 107 CHAPTER 6 16-BIT TIMER 0 TM0 (3) Prescaler mode register (PRM0) This register is used to set TM0 count clock and valid edge of TI00 to TI02 input. PRM0 is set with an 8-bit memory manipulation instruction. RESET input clears PRM0 to 00H. Figure 6-4.
Page 108: 16-Bit Timer 0 Tm0 Operations
CHAPTER 6 16-BIT TIMER 0 TM0 6.5 16-Bit Timer 0 TM0 Operations 6.5.1 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P40 to TI02/P42 pins using the 16-bit timer register (TM0). TM0 is used in free-running mode. (1) Pulse width measurement with free-running counter and one capture register (TI00) When the edge specified by prescaler mode register (PRM0) is input to the TI00/P40 pin, the value of TM0 is taken into 16-bit capture register 00 (CR00) and an external interrupt request signal (INTTM00) is set.
Page 109 CHAPTER 6 16-BIT TIMER 0 TM0 (2) Measurement of three pulse widths with free-running counter The 16-bit timer register (TM0) allows simultaneous measurement of the pulse widths of the three signals input to the TI00/P40 to TI02/P42 pins. When the edge specified by bits 2 and 3 (ES00 and ES01) of prescaler mode register (PRM0) is input to the TI00/P40 pin, the value of TM0 is taken into 16-bit capture register 00 (CR00) and an external interrupt request signal (INTTM00) is set.
Page 110 CHAPTER 6 16-BIT TIMER 0 TM0 Figure 6-9. Pulse Width Measurement Operation Timing by Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H FFFFH 0000H TM0 count value TI0m pin input Value loaded to CR0m INTTM0m TI0n pin input Value loaded to CR0n INTTM0n INTOVF...
Page 111: 16-Bit Timer 0 Tm0 Cautions
CHAPTER 6 16-BIT TIMER 0 TM0 6.6 16-Bit Timer 0 TM0 Cautions (1) Timer start errors An error with a maximum of one clock may occur until counting is started after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse. Figure 6-10.
Page 112 CHAPTER 6 16-BIT TIMER 0 TM0 (4) Occurrence of INTTM0n INTTM0n occurs even if no capture pulse exists, immediately after the timer operation has been started (TMC02 of TMC0 has been set to 1) with a high level applied to input pins TI00 to TI02 of 16-bit timer 0, and with the rising edge (with ESn1 and ESn0 of PRM0 set to 0, 1), or both the rising and falling edges (with ESn1 and ESn0 of PRM0 set to 1, 1) selected.
Page 113: Chapter 7 8-Bit Timer 1 Tm1
CHAPTER 7 8-BIT TIMER 1 TM1 7.1 8-Bit Timer 1 TM1 Functions The 8-bit timer 1 TM1 operates as an 8-bit interval timer. Figure 7-1 shows timer 1 TM1 block diagram. Figure 7-1. 8-Bit Timer 1 TM1 Block Diagram Internal bus 8-bit compare register 1 (CR1) Coincidence INTTM1...
Page 114: 8-Bit Timer 1 Tm1 Configuration
CHAPTER 7 8-BIT TIMER 1 TM1 7.2 8-Bit Timer 1 TM1 Configuration 8-bit timer 1 TM1 consists of the following hardware. Table 7-1. 8-Bit Timer 1 TM1 Configuration Item Configuration Timer register 8-bit counter 1 (TM1) Register 8-bit compare register 1 (CR1) Control register Timer clock select register 1 (TCL1) 8-bit timer mode control register 1 (TMC1)
Page 115: 8-Bit Timer 1 Tm1 Control Registers
CHAPTER 7 8-BIT TIMER 1 TM1 7.3 8-Bit Timer 1 TM1 Control Registers The following two types of registers are used to control 8-bit timer 1 TM1. • Timer clock select register 1 (TCL1) • 8-bit timer mode control register 1 (TMC1) (1) Timer clock select register 1 (TCL1) This register sets count clocks of 8-bit timer 1.
Page 116 CHAPTER 7 8-BIT TIMER 1 TM1 (2) 8-bit timer mode control register 1 (TMC1) TMC1 is a register that controls the counting operation of the 8-bit counter 1 (TM1). TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC1 to 00H.
Page 117: 8-Bit Timer 1 Tm1 Operations
CHAPTER 7 8-BIT TIMER 1 TM1 7.4 8-Bit Timer 1 TM1 Operations 7.4.1 8-bit interval timer operation The 8-bit timer 1 operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to 8-bit compare register 1 (CR1). When the count values of the 8-bit counter 1 (TM1) match the values set to CR1, counting continues with the TM1 values cleared to 0 and the interrupt request signal (INTTM1) is generated.
Page 118 CHAPTER 7 8-BIT TIMER 1 TM1 Figure 7-4. Interval Timer Operation Timings (2/3) (b) When CR1 = 00H Count clock TCE1 INTTM1 TM1 interval time Interval time (c) When CR1 = FFH Count clock TCE1 INTTM1 Interrupt received Interrupt received TM1 interval time Interval time Preliminary User’s Manual U14581EJ3V0UM00...
Page 119 CHAPTER 7 8-BIT TIMER 1 TM1 Figure 7-4. Interval Timer Operation Timings (3/3) (d) Operated by CR1 transition (M < N) Count clock TCE1 INTTM1 TM1 interval time CR1 transition TM1 overflows since M < N (e) Operated by CR1 transition (M > N) Count clock N –...
Page 120: 8-Bit Timer 1 Tm1 Cautions
CHAPTER 7 8-BIT TIMER 1 TM1 7.5 8-Bit Timer 1 TM1 Cautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because 8-bit counter 1 (TM1) is started asynchronously with the count pulse. Figure 7-5.
Page 121: Chapter 8 8-Bit Timer/Event Counters 2 Tm2 And 3 Tm3
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 8.1 8-Bit Timer/Event Counters 2 TM2 and 3 TM3 Functions The 8-bit timer/event counters 2 TM2 and 3 TM3 can have the following functions. • Interval timer • External event counter •...
Page 122 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 Figure 8-2. 8-Bit Timer/Event Counter 3 TM3 Block Diagram Internal bus 8-bit compare Selector INTTM3 register 3 (CR3) TIO3/P44 Coincidence 8-bit counter 3 TIO3/P44 (TM3) Note Clear P44 output latch PM44 Invert level Selector...
Page 123: 8-Bit Timer/Event Counters 2 Tm2 And 3 Tm3 Configurations
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 8.2 8-Bit Timer/Event Counters 2 TM2 and 3 TM3 Configurations The 8-bit timer/event counters 2 TM2 and 3 TM3 consist of the following hardware. Table 8-1. 8-Bit Timer/Event Counters 2 TM2 and 3 TM3 Configurations Item Configuration 8-bit counter ×...
Page 124: 8-Bit Timer/Event Counters 2 Tm2 And 3 Tm3 Control Registers
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 8.3 8-Bit Timer/Event Counters 2 TM2 and 3 TM3 Control Registers The following three types of registers are used to control 8-bit timer/event counters 2 TM2 and 3 TM3. • Timer clock select registers 2, 3 (TCL2, TCL3) •...
Page 125 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 Figure 8-4. Timer Clock Select Register 3 (TCL3) Format Address: FF75H After Reset: 00H Symbol TCL3 TCL32 TCL31 TCL30 TCL32 TCL31 TCL30 Count Clock Selection TIO3 falling edge TIO3 rising edge (523 kHz) (130 kHz) (65.4 kHz)
Page 126 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 Figure 8-5. 8-Bit Timer Mode Control Registers 2 and 3 (TMC2 and TMC3) Format Address: FF77H (TMC2) FF78H (TMC3) After Reset: 00H Symbol TMCn TCEn TMCn6 LVSn LVRn TMCn1 TOEn TCEn TMn Count Operation Control After clearing counter to 0, count operation disabled (prescaler disabled)
Page 127 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 (3) Port mode register 4 (PM4) This register sets port 4 to the input or output mode in 1-bit units. To use the P43/TIO2 and P44/TIO3 pins as timer output pins, clear the output latches of PM43 and PM44 and P43 and P44 to 0.
Page 128: 8-Bit Timer/Event Counters 2 Tm2 And 3 Tm3 Operations
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 8.4 8-Bit Timer/Event Counters 2 TM2 and 3 TM3 Operations 8.4.1 8-bit interval timer operation The 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare register n (CRn).
Page 129 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 Figure 8-7. Interval Timer Operation Timings (2/3) (b) When CRn = 00H Count clock TCEn INTTMn TIOn Interval time (c) When CRn = FFH Count clock TCEn INTTMn Interrupt received Interrupt received TIOn...
Page 130: External Event Counter Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 Figure 8-7. Interval Timer Operation Timings (3/3) (d) Operated by CRn transition (M < N) Count clock TCEn INTTMn TIOn CRn transition TMn overflows since M < N (e) Operated by CRn transition (M > N) Count clock N –...
Page 131: Square-Wave Output Operation (8-Bit Resolution)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 Figure 8-8. External Event Counter Operation Timings (with Rising Edge Specified) TIOn TMn count value 0000 0001 0002 0003 0004 0005 N – 1 0000 0001 0002 0003 INTTMn Remark n = 2, 3 8.4.3 Square-wave output operation (8-bit resolution) A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare register n (CRn).
Page 132: 8-Bit Pwm Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 8.4.4 8-bit PWM output operation 8-bit timer/event counters operate as PWM output when bit 6 (TMCn6) of 8-bit timer mode control register n (TMCn) is set to 1. The duty rate pulse determined by the value set to 8-bit compare register n (CRn) is output from TIOn. Set the active level width of PWM pulse to CRn, and the active level can be selected with bit 1 (TMCn1) of TMCn.
Page 133 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 (a) PWM output basic operation Figure 8-9. PWM Output Operation Timing (i) Basic operation (active level = H) Count clock 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H TCEn INTTMn...
Page 134 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 (b) Operation by change of CRn Figure 8-10. Operation Timing by Change of CRn (i) Change of CRn value to N to M before overflow of TMn Count clock N N + 1 N + 2 FFH 00H 01H M M + 1 M + 2 FFH 00H 01H 02H...
Page 135: 8-Bit Timer/Event Counters 2 Tm2 And 3 Tm3 Cautions
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TM2 AND 3 TM3 8.5 8-Bit Timer/Event Counters 2 TM2 and 3 TM3 Cautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start.
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Page 137: Chapter 9 Watch Timer
CHAPTER 9 WATCH TIMER 9.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 9-1 shows watch timer block diagram. Figure 9-1. Watch Timer Block Diagram INTWT 5-bit counter Clear...
Page 138: Watch Timer Configuration
CHAPTER 9 WATCH TIMER (1) Watch timer When the main system clock is used, interrupt requests (INTWT) are generated at 0.25 second (at f = 8.38- MHz operation) intervals. (2) Interval timer Interrupt requests (INTWT) are generated at the preset time interval. Table 9-1.
Page 139: Watch Timer Control Register
CHAPTER 9 WATCH TIMER 9.3 Watch Timer Control Register The watch timer mode control register (WTM) is used to control the watch timer. • Watch timer mode control register (WTM) This register sets the watch timer count clock, watch timer operation mode, prescaler interval time, and prescaler and 5-bit counter operation enable/disable.
Page 140: Watch Timer Operations
CHAPTER 9 WATCH TIMER 9.4 Watch Timer Operations 9.4.1 Watch timer operation When the 8.38-MHz main system clock is used, the timer operates as a watch timer with a 0.25-second interval. The watch timer generates interrupt requests at a constant time interval. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer mode control register (WTM) are set to 1, the count operation starts.
Page 141 CHAPTER 9 WATCH TIMER Figure 9-3. Watch Timer/Interval Timer Operation Timing 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.25 s) Interrupt time of watch timer (0.25 s) Interval timer interrupt INTWTI Interval timer Remark f...
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Page 143: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM). Figure 10-1 shows the watchdog timer block diagram. Figure 10-1.
Page 144 CHAPTER 10 WATCHDOG TIMER (1) Watchdog timer mode A runaway is detected. Upon detection of the runaway, a non-maskable interrupt request or RESET can be generated. Table 10-1. Watchdog Timer Runaway Detection Time Runaway Detection Time (489 µ s) × 1/f ×...
Page 145: Watchdog Timer Configuration
CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 10-3. Watchdog Timer Configuration Item Configuration Control register Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) 10.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer.
Page 146 CHAPTER 10 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 10-3. Watchdog Timer Mode Register (WDTM) Format Address: FFF9H After Reset: 00H Symbol...
Page 147: Watchdog Timer Operations
CHAPTER 10 WATCHDOG TIMER 10.4 Watchdog Timer Operations 10.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaways. A watchdog timer count clock (runaway detection time interval) can be selected by using bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS).
Page 148: Interval Timer Operation
CHAPTER 10 WATCHDOG TIMER 10.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt request repeatedly at an interval of the preset count value when bit 3 (WDTM3) and bit 4 (WDTM4) of the watchdog timer mode register (WDTM) are set to 1 and 0, respectively.
Page 149: Chapter 11 Clock Output Controller
CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.1 Clock Output Controller Functions The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output from the PCL/TPO/P60 pin.
Page 150: Clock Output Control Controller Registers
CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.3 Clock Output Control Controller Registers The following two types of registers are used to control the clock output controller. • Clock output selection register (CKS) • Port mode register 6 (PM6) (1) Clock output selection register (CKS) This register sets output clock.
Page 151 CHAPTER 11 CLOCK OUTPUT CONTROLLER (2) Port mode register 6 (PM6) This register sets port 6 input/output in 1-bit units. When using the P60/PCL/TPO pin for clock output, set PM60 and the output latch of P60 to 0. PM6 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM6 to FFH.
Page 152: Clock Output Controller Operation
CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.4 Clock Output Controller Operation To output the clock pulse, follow the procedure described below. <1> Select the clock pulse output frequency with bits 0 to 2 (CCS0 to CCS2) of the clock output selection register (CKS) (clock pulse output in disabled status).
Page 153: Chapter 12 A/D Converter
CHAPTER 12 A/D CONVERTER 12.1 A/D Converter Functions The A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to 5 analog input channels (ANI0 to ANI4). This A/D converter has the following functions: (1) A/D conversion with 8-bit resolution One channel of analog input is selected from ANI0 to ANI4, and A/D conversion is repeatedly executed with a resolution of 8 bits.
Page 154 CHAPTER 12 A/D CONVERTER Figure 12-1. A/D Converter Block Diagram Series resistor string ANI0/P10 Sample & hold circuit ANI1/P11 Voltage comparator ANI2/P12 ANI3/P13 ANI4/P14 Successive approximation register (SAR) Controller INTAD A/D conversion result register (ADCR1) ADS12 ADS11 ADS10 ADCS1 FR12 FR11 FR10 Analog input channel A/D converter mode register (ADM1)
Page 155: A/D Converter Configuration
CHAPTER 12 A/D CONVERTER 12.2 A/D Converter Configuration A/D converter consists of the following hardware. Table 12-1. A/D Converter Configuration Item Configuration Analog input 5 channels (ANI0 to ANI4) Register Successive approximation register (SAR) A/D conversion result register (ADCR1) Control register A/D converter mode register (ADM1) Analog input channel specification register (ADS1) Power-fail compare mode register (PFM)
Page 156 CHAPTER 12 A/D CONVERTER (7) AV pin (Shared with AV pin) This pin inputs the A/D converter reference voltage. This pin also functions as an analog power supply pin. Supply power to this pin when the A/D converter is used. It converts signals input to ANI0 to ANI4 into digital signals according to the voltage applied between AV The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AV pin to AV...
Page 157: A/D Converter Control Registers
CHAPTER 12 A/D CONVERTER 12.3 A/D Converter Control Registers The following four types of registers are used to control A/D converter. • A/D converter mode register (ADM1) • Analog input channel specification register (ADS1) • Power-fail compare mode register (PFM) •...
Page 158 CHAPTER 12 A/D CONVERTER (2) Analog input channel specification register (ADS1) This register specifies the analog voltage input port for A/D conversion. ADS1 is set with an 8-bit memory manipulation instruction. RESET input clears ADS1 to 00H. Figure 12-4. Analog Input Channel Specification Register (ADS1) Format Address: FF81H After Reset: 00H R/W Symbol ADS1...
Page 159 CHAPTER 12 A/D CONVERTER (3) Power-fail compare mode register (PFM) The power-fail compare mode register (PFM) controls a comparison operation. RESET input clears PFM to 00H. Figure 12-5. Power-Fail Compare Mode Register (PFM) Format Address: FF82H After Reset: 00H R/W Symbol PFEN PFCM...
Page 160: A/D Converter Operations
CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Operations 12.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register (ADS1). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 161 CHAPTER 12 A/D CONVERTER Figure 12-7. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR1 result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS1) of the A/D converter mode register (ADM1) is reset (to 0) by software.
Page 162: Input Voltage And Conversion Results
CHAPTER 12 A/D CONVERTER 12.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI4) and the A/D conversion result (stored in the A/D conversion result register (ADCR1)) is shown by the following expression. ×...
Page 163: A/D Converter Operation Mode
CHAPTER 12 A/D CONVERTER 12.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One analog input channel is selected from among ANI0 to ANI4 with the analog input channel specification register (ADS1) and A/D conversion is performed. The following two types of functions can be selected by setting the PFEN flag of the PFM register.
Page 164 CHAPTER 12 A/D CONVERTER Figure 12-9. A/D Conversion ADM1 rewrite ADCS1 = 1 ADS1 rewrite ADCS1 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion suspended; Stop Conversion results are not stored ADCR1 ANIn ANIn ANIm INTAD (PFEN = 0) INTAD (PFEN = 1) First conversion Condition satisfied...
Page 165: A/D Converter Cautions
CHAPTER 12 A/D CONVERTER 12.5 A/D Converter Cautions (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by setting bit 7 (ADCS1) of the A/D converter mode register (ADM1) to 0 to stop conversion. Figure 12-10 shows how to reduce the current consumption in the standby mode.
Page 166 CHAPTER 12 A/D CONVERTER (5) Noise countermeasures To maintain 8-bit resolution, attention must be paid to noise input to pin AV and pins ANI0 to ANI4. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 12-11 to reduce noise.
Page 167 CHAPTER 12 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS1) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS1 rewrite, and when ADIF is read immediately after the ADS1 rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended.
Page 168: Cautions On Emulation
CHAPTER 12 A/D CONVERTER 12.6 Cautions on Emulation (1) D/A converter mode register (DAM1) To perform debugging with an in-circuit emulator (IE-78K0-NS), the D/A converter mode register (DAM1) must be set. DAM1 is a register used to set a probe board (IE-780852-NS-EM4). DAM1 is used when the power-fail detection function is used.
Page 169: Chapter 13 Serial Interface Uart
CHAPTER 13 SERIAL INTERFACE UART 13.1 Serial Interface Functions The serial interface UART has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. For details, see 13.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data is transmitted and received after the start bit.
Page 170: Serial Interface Configuration
CHAPTER 13 SERIAL INTERFACE UART 13.2 Serial Interface Configuration The serial interface UART consists of the following hardware. Table 13-1. Serial Interface UART Configuration Item Configuration Registers Transmit shift register (TXS) Receive shift register (RXS) Receive buffer register (RXB) Control registers Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC)
Page 171: Serial Interface Control Registers
CHAPTER 13 SERIAL INTERFACE UART (5) Receive controller The receive controller controls receive operations based on the values set to the asynchronous serial interface mode register (ASIM). During a receive operation, it performs error checking, such as for parity errors, and sets various values to the asynchronous serial interface status register (ASIS) according to the type of error that is detected.
Page 172 CHAPTER 13 SERIAL INTERFACE UART Figure 13-2. Asynchronous Serial Interface Mode Register (ASIM) Format Address: FF85H After Reset: 00H Symbol ASIM ISRM Operation Mode RxD/P53 Pin Function TxD/P54 Pin Function Operation stop Port function (P53) Port function (P54) UART mode (receive only) Serial function (RxD) Port function (P54) UART mode (transmit only) Port function (P53)
Page 173 CHAPTER 13 SERIAL INTERFACE UART (2) Asynchronous serial interface status register (ASIS) When a receive error occurs during UART mode, this register indicates the type of error. ASIS is read with an 8-bit memory manipulation instruction. RESET input clears ASIS to 00H. Figure 13-3.
Page 174 CHAPTER 13 SERIAL INTERFACE UART Figure 13-4. Baud Rate Generator Control Register (BRGC) Format Address: FF87H After Reset: 00H Symbol BRGC TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 = 8.38 MHz) TPS2 TPS1 TPS0 Source Clock Selection for 5-bit Counter MDL3 MDL2 MDL1...
Page 175: Serial Interface Operations
CHAPTER 13 SERIAL INTERFACE UART 13.4 Serial Interface Operations This section explains the two modes of the serial interface UART. 13.4.1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. In the operation stop mode, P53/RxD and P54/TxD pins can be used as ordinary ports. (1) Register settings Operation stop mode is set with the asynchronous serial interface mode register (ASIM).
Page 176 CHAPTER 13 SERIAL INTERFACE UART (a) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM to 00H. Caution In UART mode, set the port mode register (PM5X) as follows. Besides that, set all output latches to 0.
Page 177 CHAPTER 13 SERIAL INTERFACE UART (b) Asynchronous serial interface status register (ASIS) ASIS is read with an 8-bit memory manipulation instruction. RESET input clears ASIS to 00H. Address: FF86H After Reset: 00H Symbol ASIS Parity Error Flag No parity error Parity error (Transmit data parity does not match) Framing Error Flag...
Page 178 CHAPTER 13 SERIAL INTERFACE UART (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input clears BRGC to 00H. Address: FF87H After Reset: 00H Symbol BRGC TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 = 8.38 MHz) TPS2...
Page 179 CHAPTER 13 SERIAL INTERFACE UART The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. • Use of main system clock to generate a transmit/receive clock for baud rate The main system clock is divided to generate the transmit/receive clock. The baud rate generated by the main system clock is determined according to the following formula.
Page 180 CHAPTER 13 SERIAL INTERFACE UART • Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter’s division rate [1/(16 + k)]. Table 13-3 describes the relation between the main system clock and the baud rate and Figure 13-5 shows an example of a baud rate error tolerance range.
Page 181 CHAPTER 13 SERIAL INTERFACE UART (2) Communication operations (a) Data format Figure 13-6 shows the transmit/receive data format. Figure 13-6. Format of Transmit/Receive Data in Asynchronous Serial Interface 1 data frame Start Parity Stop bit Character bits One data frame consists of the following each bit. •...
Page 182 CHAPTER 13 SERIAL INTERFACE UART (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected.
Page 183 CHAPTER 13 SERIAL INTERFACE UART (c) Transmission The transmit operation is started when transmit data is written to the transmit shift register (TXS). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXS, thereby emptying TXS, after which a transmit completion interrupt (INTST) is issued.
Page 184 CHAPTER 13 SERIAL INTERFACE UART (d) Reception The receive operation is enabled when “1” is set to bit 6 (RXE) of the asynchronous serial interface mode register (ASIM), and input via the RxD pin is sampled. The serial clock specified by ASIM is used when sampling the RxD pin. When the RxD pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed.
Page 185 CHAPTER 13 SERIAL INTERFACE UART (e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of data reception, an error flag is set to the asynchronous serial interface status register (ASIS), a receive error interrupt (INTSER) will occur.
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Page 187: Chapter 14 Serial Interface Sio2
CHAPTER 14 SERIAL INTERFACE SIO2 14.1 Serial Interface Functions The serial interface SIO2 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 14.4.1 Operation stop mode. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK2), a serial output line (SO2), and a serial input line (SI2).
Page 188: Serial Interface Configuration
CHAPTER 14 SERIAL INTERFACE SIO2 14.2 Serial Interface Configuration The serial interface SIO2 consists of the following hardware. Table 14-1. Serial Interface SIO2 Configuration Item Configuration Registers Serial I/O shift register 2 (SIO2) Serial receive data buffer register (SIRB2) Control registers Serial operation mode register 2 (CSIM2) Serial receive data buffer status register (SRBS2) Port mode register 0 (PM0)
Page 189: Serial Interface Control Registers
CHAPTER 14 SERIAL INTERFACE SIO2 14.3 Serial Interface Control Registers The following three types of registers are used to control the serial interface SIO2. • Serial operation mode register 2 (CSIM2) • Serial receive data buffer status register (SRBS2) • Port mode register 0 (PM0) (1) Serial operation mode register 2 (CSIM2) This register is used to set the SIO2 interface’s serial clock, operation mode, and operation enable/disable.
Page 190 CHAPTER 14 SERIAL INTERFACE SIO2 Cautions 1. Bits 5 and 6 must be set to 0. 2. While a serial transfer operation is enabled (CSIE2 = 1), be sure to stop the serial transfer operation once before changing the values of bits other than CSIE2 to different data. 3.
Page 191 CHAPTER 14 SERIAL INTERFACE SIO2 (2) Serial receive data buffer status register (SRBS2) This register is used to indicate the status of serial receive data buffer register (SIRB2). SRBS2 is set with an 8-bit memory manipulation instruction. RESET input clears SRBS2 to 00H. Figure 14-4.
Page 192 CHAPTER 14 SERIAL INTERFACE SIO2 (3) Port mode register 0 (PM0) This register is used to specify the input/output of port 0 in 1-bit units. When using the P03/SCK2, P04/SO2, and P05/SI2 pins in the 3-wire serial I/O mode, set PM03 to PM05 as shown in Table 14-2 below.
Page 193: Serial Interface Operations
CHAPTER 14 SERIAL INTERFACE SIO2 14.4 Serial Interface Operations This section explains the two modes of the serial interface SIO2. 14.4.1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. In addition, in this mode, the P03/SCK2, P04/SO2, and P05/SI2 pins can be used as normal I/O port pins. (1) Register setting The operation stop mode is set with the serial operation mode register 2 (CSIM2).
Page 194: 3-Wire Serial I/O Mode
CHAPTER 14 SERIAL INTERFACE SIO2 14.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful when connecting to devices such as peripheral I/Os and display controllers, which incorporate a clocked serial interface. This mode executes data transfer via three lines: a serial clock line (SCK2), a serial output line (SO2), and a serial input line (SI2).
Page 195 CHAPTER 14 SERIAL INTERFACE SIO2 Cautions 1. Bits 5 and 6 must be set to 0. 2. While a serial transfer operation is enabled (CSIE2 = 1), be sure to stop the serial transfer operation once before changing the values of bits other than CSIE2 to different data. 3.
Page 196 CHAPTER 14 SERIAL INTERFACE SIO2 (4) Operation mode (a) Master mode (with internal clock SCK2) Serial interface SIO2 operates in the master mode (with internal clock SCK2) if bits 1 and 0 (SCL21 and SCL20) of the serial operation mode register 2 (CSIM2) are set to (0, 1), (1, 0), or (1, 1). Transfer is started when data has been read from or written to the serial I/O shift register 2 (SIO2).
Page 197 CHAPTER 14 SERIAL INTERFACE SIO2 (5) Transfer format A simultaneous transmit/receive operation can be performed when the receive data is transferred from the serial I/O shift register 2 (SIO2) to the receive data buffer register (SIRB2). (a) Clock phase and polarity The phase and polarity of the serial clock can be selected from four combinations by setting bits 3 and 4 (CLPO and CLPH) of the serial operation mode register 2 (CSIM2).
Page 198 CHAPTER 14 SERIAL INTERFACE SIO2 (c) Transfer format when CLPH = 1 Figure 14-7 shows the operation timing when CLPH = 1. Two waves of SCK2, when CLPO = 1 and when CLPO = 0, are shown in the figure. Data is transmitted or received in 8-bit units.
Page 199 CHAPTER 14 SERIAL INTERFACE SIO2 Figure 14-8 shows the status of each register (SIO2, SIRB2, SRBS2) during a receive operation. Figure 14-8. Receive Operation (11) DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 Data reception end SIO2 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 SIRB2 DATA1...
Page 200 CHAPTER 14 SERIAL INTERFACE SIO2 (7) Operation in standby mode (a) Operation in HALT mode Even after a HALT instruction has been executed, serial interface SIO2 continues to operate. In the HALT mode, the CPU cannot access the registers of serial interface SIO2. If it is not necessary to use serial interface SIO2 in the HALT mode, the power consumption can be reduced by stopping the operation of the serial interface SIO2 before the HALT instruction is executed.
Page 201: Chapter 15 Serial Interface Sio3
CHAPTER 15 SERIAL INTERFACE SIO3 15.1 Serial Interface Functions The serial interface SIO3 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 15.4.1 Operation stop mode. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK3), serial output line (SO3), and serial input line (SI3).
Page 202: Serial Interface Configuration
CHAPTER 15 SERIAL INTERFACE SIO3 15.2 Serial Interface Configuration The serial interface SIO3 consists of the following hardware. Table 15-1. Serial Interface SIO3 Configuration Item Configuration Register Serial I/O shift register 3 (SIO3) Control register Serial operation mode register 3 (CSIM3) (1) Serial I/O shift register 3 (SIO3) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock.
Page 203: Serial Interface Control Register
CHAPTER 15 SERIAL INTERFACE SIO3 15.3 Serial Interface Control Register The serial operation mode register 3 (CSIM3) is used to control the serial interface SIO3. This register is used to set the SIO3’s serial clock, operation mode, and operation enable/disable. CSIM3 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 204: Serial Interface Operations
CHAPTER 15 SERIAL INTERFACE SIO3 15.4 Serial Interface Operations This section explains the two modes of the serial interface SIO3. 15.4.1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. In the operation stop mode, the P50/SCK3, P51/SO3, and P52/SI3 pins can be used as normal I/O port pins. (1) Register settings Operation stop mode is set with the serial operation mode register 3 (CSIM3).
Page 205: 3-Wire Serial I/O Mode
CHAPTER 15 SERIAL INTERFACE SIO3 15.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful when connecting a peripheral I/O device that includes a clocked serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK3), serial output line (SO3), and serial input line (SI3).
Page 206 CHAPTER 15 SERIAL INTERFACE SIO3 (2) Communication operations In the 3-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is transmitted or received in synchronization with the serial clock. The serial I/O shift register 3 (SIO3) is shifted in synchronization with the falling edge of the serial clock. Transmission data is held in the SO3 latch and is output from the SO3 pin.
Page 207: Chapter 16 Lcd Controller/Driver
CHAPTER 16 LCD CONTROLLER/DRIVER 16.1 LCD Controller/Driver Functions The functions of the LCD controller/driver incorporated in the µ PD780852 Subseries are shown below. (1) Automatic output of segment signals and common signals is possible by automatic reading of the display data memory.
Page 208: Lcd Controller/Driver Configuration
CHAPTER 16 LCD CONTROLLER/DRIVER 16.2 LCD Controller/Driver Configuration The LCD controller/driver consists of the following hardware. Table 16-2. LCD Controller/Driver Configuration Item Configuration Display outputs Segment signals: 20 Dedicated segment signals: 5 Segment signal/input or output port alternate function: 14 Segment signal/input or output port/16-bit timer prescaler output alternate function: 1 Common signals: 4 (COM0 to COM3) Control registers...
Page 209 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-2. LCD Clock Selector Block Diagram Prescaler LCDCL LCDM6 LCDM5 LCDM4 LCD display mode register Internal bus Remarks 1. LCDCL: LCD clock 2. f LCD clock frequency Preliminary User’s Manual U14581EJ3V0UM00...
Page 210: Lcd Controller/Driver Control Registers
CHAPTER 16 LCD CONTROLLER/DRIVER 16.3 LCD Controller/Driver Control Registers The following two types of registers are used to control the LCD controller/driver. • LCD display mode register (LCDM) • LCD display control register (LCDC) (1) LCD display mode register (LCDM) This register sets display operation enabling/disabling, the LCD clock, and frame frequency.
Page 211 CHAPTER 16 LCD CONTROLLER/DRIVER (2) LCD display control register (LCDC) This register sets cutoff of the current flowing to split resistors for LCD drive voltage generation and switchover between segment output and input/output port functions. LCDC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears LCDC to 00H.
Page 212: Lcd Controller/Driver Settings
CHAPTER 16 LCD CONTROLLER/DRIVER 16.4 LCD Controller/Driver Settings LCD controller/driver settings should be performed as shown below. <1> Set the initial value in the display data memory (FA59H to FA6CH). <2> Set the pins to be used as segment outputs in the LCD display control register (LCDC). <3>...
Page 213: Lcd Display Data Memory
CHAPTER 16 LCD CONTROLLER/DRIVER 16.5 LCD Display Data Memory The LCD display data memory is mapped onto addresses FA59H to FA6CH. The data stored in the LCD display data memory can be displayed on an LCD panel by the LCD controller/driver. Figure 16-5 shows the relation between the LCD display data memory contents and the segment outputs/common outputs.
Page 214: Common Signals And Segment Signals
CHAPTER 16 LCD CONTROLLER/DRIVER 16.6 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the LCD drive voltage V ).
Page 215 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-6 shows the common signal waveform, and Figure 16-7 shows the common signal and segment signal voltages and phases. Figure 16-6. Common Signal Waveform COMn (Divided by 4) = 4 × T One LCDCL cycle : Frame frequency Figure 16-7.
Page 216: Supplying Lcd Drive Voltage
CHAPTER 16 LCD CONTROLLER/DRIVER 16.7 Supplying LCD Drive Voltage V , and V The µ PD780852 Subseries have a split resistor to create an LCD drive voltage, and the drive voltage is fixed to 1/3 bias. To supply various LCD drive voltages, internal V or external V supply voltage can be selected.
Page 217 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-8. Example of Connection of LCD Drive Power Supply (a) To supply LCD drive voltage from V LIPS P-ch (= 1) Open V (b) To supply LCD drive voltage from external source LIPS P-ch (= 0) 3R •...
Page 218: Display Mode
CHAPTER 16 LCD CONTROLLER/DRIVER 16.8 Display Mode 16.8.1 4-time-division display example Figure 16-10 shows the connection of a 4-time-division type 10-digit LCD panel with the display pattern shown in Figure 16-9 with the µ PD780852 Subseries segment signals (S0 to S19) and common signals (COM0 to COM3). The display example is “1234567890,”...
Page 219 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-10. 4-Time-Division LCD Panel Connection Example COM3 COM2 COM1 COM0 FA6CH FA5FH FA59H Preliminary User’s Manual U14581EJ3V0UM00...
Page 220 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-11. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) COM0 COM1 COM2 COM3 +1/3V COM0 to S8 –1/3V –V +1/3V COM1 to S8 –1/3V –V Preliminary User’s Manual U14581EJ3V0UM00...
Page 221: Cautions On Emulation
CHAPTER 16 LCD CONTROLLER/DRIVER 16.9 Cautions on Emulation (1) LCD timer control register (LCDTM) To perform debugging with an in-circuit emulator (IE-78K0-NS), the LCD timer control register (LCDTM) must be set. LCDTM is a register used to set a probe board (IE-780852-NS-EM4). LCDTM is a write-only register that controls supply of the LCD clock.
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Page 223: Chapter 17 Sound Generator
CHAPTER 17 SOUND GENERATOR 17.1 Sound Generator Function The sound generator has the function to sound the buzzer from an external speaker, and the following signal are output. • Basic cycle output signal The signal is a buzzer signal with a variable frequency. By setting bits 0 to 2 (SGCL0 to SGCL2) of the sound generator control register (SGCR), the signal in a range of 0.12 to 4.0 kHz can be output (when f = 8.38 MHz).
Page 224: Sound Generator Configuration
CHAPTER 17 SOUND GENERATOR 17.2 Sound Generator Configuration The sound generator consists of the following hardware. Table 17-1. Sound Generator Configuration Item Configuration 8 bits × 1, 5 bits × 1 Counter SG output Control register Sound generator control register (SGCR) Sound generator buzzer control register (SGBR) Sound generator amplitude register (SGAM) Preliminary User’s Manual U14581EJ3V0UM00...
Page 225: Sound Generator Control Registers
CHAPTER 17 SOUND GENERATOR 17.3 Sound Generator Control Registers The following three types of registers are used to control the sound generator. • Sound generator control register (SGCR) • Sound generator buzzer control register (SGBR) • Sound generator amplitude register (SGAM) (1) Sound generator control register (SGCR) SGCR is a register which sets up the following three types.
Page 226 CHAPTER 17 SOUND GENERATOR Figure 17-3. Sound Generator Control Register (SGCR) Format Address: FF94H After Reset: 00H Symbol SGCR SGCL2 SGCL1 SGCL0 Sound Generator Operation Selection Timer operation stopped SGO for low-level output Sound generator operation SGO for output SGCL2 SGCL1 5-Bit Counter Input Frequency f Selection...
Page 227 CHAPTER 17 SOUND GENERATOR (2) Sound generator buzzer control register (SGBR) SGBR is a register that sets the basic frequency of the sound generator output signal. SGBR is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SGBR to 00H. Figure 17-4 shows the SGBR format.
Page 228 CHAPTER 17 SOUND GENERATOR Figure 17-5. Sound Generator Amplitude Register (SGAM) Format Address: FFC1H After Reset: 00H Symbol SGAM SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0 SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0 Amplitude 0/128 2/128 3/128 4/128 5/128 6/128 7/128 8/128 9/128...
Page 229: Sound Generator Operations
CHAPTER 17 SOUND GENERATOR 17.4 Sound Generator Operations 17.4.1 To output basic cycle signal SGO The basic cycle signal is output from the SGO pin if the bit 7 (TCE) of the sound generator control register (SGCR) is set to “1”. The basic cycle signal of the frequency set by SGCL0 to SGCL2 and SGBR0 to SGBR3 is output.
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Page 231: Chapter 18 Meter Controller/Driver
CHAPTER 18 METER CONTROLLER/DRIVER 18.1 Meter Controller/Driver Functions The meter controller/driver is a function to drive a stepping motor for external meter control or cross coil. • Can set pulse width with a precision of 8 bits • Can set pulse width with a precision of 8 + 1 bits with 1-bit addition function •...
Page 232: Meter Controller/Driver Configuration
CHAPTER 18 METER CONTROLLER/DRIVER Figure 18-2. 1-Bit Addition Circuit Block Diagram Compare register (MCMPnm) ADBn1 ADBn0 Compare control register (MCMPCn) Internal bus Remark n = 1 to 4, m = 0, 1 18.2 Meter Controller/Driver Configuration The meter controller/driver consists of the following hardware. Table 18-1.
Page 233 CHAPTER 18 METER CONTROLLER/DRIVER (2) Compare register n0 (MCMPn0) MCMPn0 is an 8-bit register that can rewrite compare values through specification of bit 4 (TENn) of the compare control register n (MCMPCn). RESET input clears this register to 00H and clears hardware to 0. MCMPn0 is a register that supports read/write only for 8-bit access instructions.
Page 234: Meter Controller/Driver Control Registers
CHAPTER 18 METER CONTROLLER/DRIVER 18.3 Meter Controller/Driver Control Registers The following three types of registers are used to control the meter controller/driver. • Timer mode control register (MCNTC) • Compare control register n (MCMPCn) • Port mode control register (PMC) Remark n = 1 to 4 (1) Timer mode control register (MCNTC) MCNTC is an 8-bit register that controls the operation of the free-running up counter (MCNT).
Page 235 CHAPTER 18 METER CONTROLLER/DRIVER (2) Compare control register n (MCMPCn) MCMPCn is an 8-bit register that controls the operation of the compare register and output direction of the PWM pin. MCMPCn is set with an 8-bit memory manipulation instruction. RESET input clears MCMPCn to 00H. Figure 18-4 shows the MCMPCn format.
Page 236 CHAPTER 18 METER CONTROLLER/DRIVER (3) Port mode control register (PMC) PMC is an 8-bit register that specifies PWM/port output. PMC is set with an 8-bit memory manipulation instruction. RESET input clears PMC to 00H. Figure 18-5 shows the PMC format. Figure 18-5.
Page 237: Meter Controller/Driver Operations
CHAPTER 18 METER CONTROLLER/DRIVER 18.4 Meter Controller/Driver Operations 18.4.1 Basic operation of free-running up counter (MCNT) The free-running up counter (MCNT) is counted up by the count clock selected by the PCS bit of the timer mode control register (MCNTC). RESET input clears the value of MCNT.
Page 238: 1-Bit Addition Circuit Operation
CHAPTER 18 METER CONTROLLER/DRIVER 18.4.3 1-bit addition circuit operation Figure 18-7. Timing in 1-Bit Addition Circuit Operation MCNT value OVF (overflow) Match signal of expected value N PWM output of expected value N (1-bit non-addition) PWM output of expected value N (1-bit addition) PWM output of expected value N + 1...
Page 239: Pwm Output Operation (Output With 1 Clock Shifted)
CHAPTER 18 METER CONTROLLER/DRIVER 18.4.4 PWM output operation (output with 1 clock shifted) Figure 18-8. Timing of Output with 1 Clock Shifted Count clock Meter 1 sin (SM11, SM12) Meter 1 cos (SM13, SM14) Meter 2 sin (SM21, SM22) Meter 2 cos (SM23, SM24) Meter 3 sin (SM31, SM32)
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Page 241: Chapter 19 Interrupt Functions
CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled state. It does not undergo priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 242 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List Vector Basic Interrupt Source Note 1 Internal/ Interrupt Type Default Table Configuration External Name Trigger Note 2 Priority Address Type Non-maskable — INTWDT Watchdog timer overflow Internal 0004H (with non-maskable interrupt selected) Maskable INTWDT Watchdog timer overflow...
Page 243 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt Vector table Priority controller request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal...
Page 244 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except 16-bit timer capture input) Internal bus External interrupt edge enable register (EGP, EGN) Vector table Interrupt Edge Priority controller address generator request detector Standby release signal (E) Software interrupt Internal bus...
Page 245: Interrupt Function Control Registers
CHAPTER 19 INTERRUPT FUNCTIONS 19.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) •...
Page 246 CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 247 CHAPTER 19 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt service. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register MK0, they are set with a 16-bit memory manipulation instruction.
Page 248 CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag registers are used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
Page 249 CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP) and external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP2. EGP and EGN are set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 250 CHAPTER 19 INTERRUPT FUNCTIONS (5) Prescaler mode register (PRM0) This register specifies the valid edge for TI00/P40 to TI02/P42 pins input. PRM0 is set with an 8-bit memory manipulation instruction. RESET input clears PRM0 to 00H. Figure 19-6. Prescaler Mode Register (PRM0) Format Address: FF70H After Reset: 00H R/W Symbol PRM0...
Page 251 CHAPTER 19 INTERRUPT FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for an interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped.
Page 252: Interrupt Servicing Operations
CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag and ISP flag are reset (to 0), and the contents of the vector table are loaded into PC and branched.
Page 253 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-8. Non-Maskable Interrupt Request Generation to Acknowledge Flowchart Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending Interrupt...
Page 254 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Non-Maskable Interrupt Request Acknowledge Operation (a) If a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main routine Execution of NMI request <1> NMI request <1> NMI request <2> held pending NMI request <2>...
Page 255: Maskable Interrupt Request Acknowledge Operation
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt is cleared to 0. A vectored interrupt request is acknowledged if in the interrupt enable state (when IE flag is set to 1).
Page 256 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-11. Interrupt Request Acknowledge Processing Algorithm Start ××IF = 1? Yes (Interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority interrupt request among those Any interrupt request among those simultaneously generated...
Page 257: Software Interrupt Request Acknowledge Operation
CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-12. Interrupt Request Acknowledge Timing (Minimum Time) 6 clocks PSW and PC save, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 19-13.
Page 258: Multiple Interrupt Servicing
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Multiple interrupt servicing Multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except non-maskable interrupts).
Page 259 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-14. Multiple Interrupt Examples (1/2) Example 1. Multiple interrupts occur twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI RETI...
Page 260 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-14. Multiple Interrupt Examples (2/2) Example 3. Multiple interrupt servicing does not occur because interrupt is not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx (PR = 0) RETI IE = 0 1 instruction execution...
Page 261: Interrupt Request Hold
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
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Page 263: Chapter 20 Standby Function
CHAPTER 20 STANDBY FUNCTION 20.1 Standby Function and Configuration 20.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. The system clock oscillator continues oscillating.
Page 264: Standby Function Control Register
CHAPTER 20 STANDBY FUNCTION 20.1.2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 265: Standby Function Operations
CHAPTER 20 STANDBY FUNCTION 20.2 Standby Function Operations 20.2.1 HALT mode (1) HALT mode setting and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Table 20-1. HALT Mode Operating Status HALT Mode Setting During HALT Instruction Execution Using Main System Clock Item...
Page 266 CHAPTER 20 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled, vectored interrupt service is carried out.
Page 267 CHAPTER 20 STANDBY FUNCTION (c) Clear upon RESET input As in the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 20-3. HALT Mode Clear upon RESET Input Wait HALT instruction : 15.6 ms) RESET signal Reset...
Page 268: Stop Mode
CHAPTER 20 STANDBY FUNCTION 20.2.2 STOP mode (1) STOP mode setting and operating status The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull-up resistor to minimize the leakage current at the crystal oscillator.
Page 269 CHAPTER 20 STANDBY FUNCTION (2) STOP mode clear The STOP mode can be cleared with the following two types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the STOP mode. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
Page 270 CHAPTER 20 STANDBY FUNCTION (b) Clear upon RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 20-5. STOP Mode Clear upon RESET Input Wait STOP instruction : 15.6 ms) RESET signal Reset...
Page 271: Chapter 21 Reset Function
CHAPTER 21 RESET FUNCTION 21.1 Reset Functions The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 272 CHAPTER 21 RESET FUNCTION Figure 21-2. Timing of Reset by RESET Input Oscillation Normal operation Reset period stabilization Normal operation (Reset processing) (Oscillation stop) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 21-3. Timing of Reset due to Watchdog Timer Overflow Oscillation Normal operation Reset period...
Page 273 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (1/2) Hardware Status after Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General register...
Page 274 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (2/2) Hardware Status after Reset 8-bit timer TM1 to TM3 Timer counters (TM1 to TM3) Compare registers (CR1 to CR3) Clock select registers (TCL1 to TCL3) Mode control registers (TMC1 to TMC3) Watch timer Mode control register (WTM) Watchdog timer...
Page 275: Chapter 22 Μ Pd78F0852
CHAPTER 22 µ PD78F0852 The µ PD78F0852 is a version with a flash memory in µ PD780852 Subseries. The µ PD78F0852 replaces the internal ROM of the µ PD780852(A) with flash memory to which a program can be written, deleted and overwritten while mounted on a board. Table 22-1 lists the differences between the µ PD78F0852 and the mask ROM version.
Page 276: Memory Size Switching Register (Ims)
CHAPTER 22 µ PD78F0852 22.1 Memory Size Switching Register (IMS) The µ PD78F0852 allows users to select the internal memory capacity using the memory size switching register (IMS) so that the same memory map as that of the mask ROM version with a different size of internal memory capacity can be achieved.
Page 277: Internal Expansion Ram Size Switching Register (Ixs)
CHAPTER 22 µ PD78F0852 22.2 Internal Expansion RAM Size Switching Register (IXS) The internal expansion RAM size switching register (IXS) is used to select the capacity of the internal expansion RAM. IXS is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0CH.
Page 278: Flash Memory Programming
CHAPTER 22 µ PD78F0852 22.3 Flash Memory Programming On-board writing of flash memory (with the device mounted on the target system) is supported. On-board writing is done after connecting a dedicated flash writer (Flashpro III (part number: FL-PR3, PG-FP3) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro III.
Page 279: Flash Memory Programming Function
CHAPTER 22 µ PD78F0852 22.3.2 Flash memory programming function Flash memory programming functions such as flash memory writing are performed through command and data transmit/receive operations using the selected transmission method. The main functions are listed in Table 22-4. Table 22-4. Main Functions of Flash Memory Programming Function Description Reset...
Page 280: Flashpro Iii Connection
CHAPTER 22 µ PD78F0852 22.3.3 Flashpro III connection Connection of Flashpro III and the µ PD78F0852 differs depending on the transmission method (3-wire serial I/O and UART). Each case of connection shows in Figures 22-4, 22-5, and 22-6. Figure 22-4. Flashpro III Connection Using 3-Wire Serial I/O Method (SIO3) µ...
Page 281: Chapter 23 Instruction Set
CHAPTER 23 INSTRUCTION SET This chapter lists the instruction set of the µ PD780852 Subseries. For details of the operation and machine language (instruction code), refer to the separate document 78K/0 SERIES USER'S MANUAL Instructions (U12326E). Preliminary User’s Manual U14581EJ3V0UM00...
Page 282: Legend For Operation List
CHAPTER 23 INSTRUCTION SET 23.1 Legend for Operation List 23.1.1 Operand identifiers and description formats Operands are described in “Operand” column of each instruction in accordance with the description format of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description formats, select one of them.
Page 283: Description Of "Operation" Column
CHAPTER 23 INSTRUCTION SET 23.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 284: Operation List
CHAPTER 23 INSTRUCTION SET 23.2 Operation List Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 r ← byte r, #byte – (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte – A ← r Note 3 A, r –...
Page 285 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 rp ← word rp, #word – (saddrp) ← word saddrp, #word sfrp ← word sfrp, #word – AX ← (saddrp) AX, saddrp (saddrp) ←...
Page 286 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A, CY ← A – byte × × × A, #byte – (saddr), CY ← (saddr) – byte × × × saddr, #byte A, CY ←...
Page 287 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A ← A byte × A, #byte – (saddr) ← (saddr) byte × saddr, #byte A ← A r × Note 3 A, r –...
Page 288 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 AX, CY ← AX + word × × × ADDW AX, #word – 16-bit AX, CY ← AX – word × ×...
Page 289 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 CY ← CY (saddr.bit) × CY, saddr.bit CY ← CY sfr.bit × CY, sfr.bit – CY ← CY A.bit × AND1 CY, A.bit –...
Page 290 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) CALL !addr16 – PC ← addr16, SP ← SP – 2 (SP –...
Page 291 CHAPTER 23 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 saddr.bit, $addr16 PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...
Page 292: Instructions Listed By Addressing Type
CHAPTER 23 INSTRUCTION SET 23.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Preliminary User’s Manual U14581EJ3V0UM00...
Page 293 CHAPTER 23 INSTRUCTION SET Second Operand [HL + byte] Note #byte saddr !addr16 PSW [DE] [HL] $addr16 None [HL + B] First Operand [HL + C] MOV MOV MOV MOV MOV MOV MOV MOV ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC...
Page 294 CHAPTER 23 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand Note #word sfrp saddrp !addr16 None 1st Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 295 CHAPTER 23 INSTRUCTION SET (4) Call/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U14581EJ3V0UM00...
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Page 297: Appendix Adevelopment Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µ PD780852 Subseries. Figure A-1 shows the development tool configuration. Preliminary User’s Manual U14581EJ3V0UM00...
Page 298 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tools • System simulator • Integrated debugger • Device file Embedded Software •...
Page 299: Language Processing Software
APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K/0 This assembler converts programs written in mnemonics into an object code Assembler Package executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler is used in combination with an optional device file (DF780852).
Page 300: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS µ S××××RA78K0 µ S××××CC78K0 µ S××××DF780852 µ S××××CC78K0-L ×××× Host Machine Supply Medium AA13 PC-9800 Series Windows 3.5-inch 2HD FD Note Japanese version AB13 IBM PC/AT™ and compatibles Windows 3.5-inch 2HC FD Note Japanese version BB13 Windows Note English version...
Page 301: Debugging Tools
APPENDIX A DEVELOPMENT TOOLS A.3 Debugging Tools A.3.1 Hardware IE-78K0-NS This in-circuit emulator is used to debug hardware and software when developing application In-circuit Emulator systems using the 78K/0 Series. It is compatible with the integrated debugger (ID78K0). This emulator is used in combination with an emulation probe and an interface adapter for connection to a host machine.
Page 302: Software
APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (1/2) SM78K0 This system simulator is used to perform debugging at C source level or assembler System Simulator level while simulating the operation of the target system on a host machine. The SM78K0 operates on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency...
Page 303 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (2/2) ID78K0-NS This is a control program used to debug the 78K/0 Series. The graphical user interfaces employed are Windows for personal computers and OSF/ Integrated Debugger (Supports in-circuit emulator Motif for EWSs, offering the standard appearance and operability typical of these IE-78K0-NS) interfaces.
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Page 305: Appendix Bembedded Software
APPENDIX B EMBEDDED SOFTWARE For efficient development and maintenance of the µ PD780852 Subseries, the following embedded software products are available. Real-Time OS (1/2) RX78K/0 is a real-time OS conforming with the µ ITRON specifications. RX78K/0 Real-time OS Tool (configurator) for generating nucleus of RX78K/0 and plural information tables is supplied.
Page 306 APPENDIX B EMBEDDED SOFTWARE Real-Time OS (2/2) µ lTRON specification subset OS. Nucleus of MX78K0 is supplied. MX78K0 This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next.
Page 307: Appendix Cregister Index
APPENDIX C REGISTER INDEX C.1 Register Index (in Alphabetical Order with Respect to Register Name) A/D conversion result register (ADCR1) … 155 A/D converter mode register (ADM1) … 157 Analog input channel specification register (ADS1) … 158 Asynchronous serial interface mode register (ASIM) … 170 Asynchronous serial interface status register (ASIS) …...
Page 308 APPENDIX C REGISTER INDEX External interrupt rising edge enable register (EGP) … 249 Internal expansion RAM size switching register (IXS) ... 277 Interrupt mask flag register 0H (MK0H) … 247 Interrupt mask flag register 0L (MK0L) … 247 Interrupt mask flag register 1L (MK1L) … 247 Interrupt request flag register 0H (IF0H) …...
Page 309 APPENDIX C REGISTER INDEX Processor clock control register (PCC) … 92 Program status word (PSW) ... 55, 251 Pull-up resistor option register (PU0) … 88 Receive buffer register (RXB) … 170 Serial receive data buffer register (SIRB2) ... 188 Serial receive data buffer status register (SRBS2) ... 191 Serial I/O shift register 2 (SIO2) …...
Page 310: Register Index (In Alphabetical Order With Respect To Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (in Alphabetical Order with Respect to Register Symbol) ADCR1 A/D conversion result register … 155 ADM1 A/D converter mode register … 157 ADS1 Analog input channel specification register … 158 ASIM Asynchronous serial interface mode register … 170 ASIS Asynchronous serial interface status register …...
Page 311 APPENDIX C REGISTER INDEX MCMP30 : Compare register (sin side) … 233 MCMP31 : Compare register (cos side) … 233 MCMP40 : Compare register (sin side) … 233 MCMP41 : Compare register (cos side) … 233 MCMPC1 : Compare control register 1 … 235 MCMPC2 : Compare control register 2 …...
Page 312 APPENDIX C REGISTER INDEX SGAM Sound generator amplitude register … 227 SGBR Sound generator buzzer control register … 227 SGCR Sound generator control register … 225 SIO2 Serial I/O shift register 2 … 188 SIO3 Serial I/O shift register 3 … 202 SIRB2 Serial receive data buffer register …...
Page 313: Appendix Drevision History
APPENDIX D REVISION HISTORY The following table shows the revision history of this manual. "Chapter" indicates the chapter of the newest edition where revision was made. Edition Major Revision from Previous Edition Chapter 2nd edition Changing 1.5 Pin Configuration (Top View) CHAPTER 1 OUTLINE Changing description of supply voltage in 1.8 Outline of Function Changing 6.4 (4) Port mode register 4 (PM4)
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Page 315 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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Mpd780851 Mpd780851a Mpd780852a Mpd78f0852

NEC mPD780852 Series Preliminary User's Manual

Chapter 1 Outline

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer 0 Tm0

Chapter 7 8-Bit Timer 1 Tm1

Chapter 8 8-Bit Timer/Event Counters 2 Tm2 and 3 Tm3

Chapter 9 Watch Timer

Chapter 10 Watchdog Timer

Chapter 11 Clock Output Controller

Chapter 12 A/D Converter

Chapter 13 Serial Interface Uart

Chapter 14 Serial Interface Sio2

Chapter 15 Serial Interface Sio3

Chapter 16 Lcd Controller/Driver

Chapter 17 Sound Generator

Chapter 18 Meter Controller/Driver

Chapter 19 Interrupt Functions

Chapter 20 Standby Function

Chapter 21 Reset Function

CHAPTER 22 Μ PD78F0852

Chapter 23 Instruction Set

Appendix Adevelopment Tools

Appendix Bembedded Software

Appendix Cregister Index

Appendix Drevision History

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Summary of Contents for NEC mPD780852 Series