1. Manuals
  2. Brands
  3. NEC Manuals
  4. Microcontrollers
  5. mPD780065 Series
  6. Preliminary user's manual

NEC mPD780065 Series Preliminary User's Manual

8-bit single-chip microcontrollers
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Preliminary User's Manual
µ PD780065 Subseries
8-Bit Single-Chip Microcontrollers
µ PD780065
µ PD78F0066
Document No.
U13420EJ2V0UM00 (2nd edition)
Date Published May 1999 N CP(K)
©
1998, 1999
Printed in Japan

Advertisement

Table of Contents
loading

Related Manuals for NEC mPD780065 Series

Summary of Contents for NEC mPD780065 Series

  • Page 1 Preliminary User’s Manual µ PD780065 Subseries 8-Bit Single-Chip Microcontrollers µ PD780065 µ PD78F0066 Document No. U13420EJ2V0UM00 (2nd edition) Date Published May 1999 N CP(K) © 1998, 1999 Printed in Japan...
  • Page 2 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...
  • Page 3 Reset operation must be executed immediately after power-on for devices having reset function. FIP, EEPROM, and IEBus are trademarks of NEC Corporation. Windows, and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
  • Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
  • Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 6 Major Revisions in This Edition Page Description p.29 Renewal of 1.5 78K/0 Series Lineup p.33 Modification of description of on-chip pull-up resistor specification and function description of TI00 pin in 2.1 Pin Functions pp.41, 42 Addition of input/output circuit type and Figure 2-1 Pin Input/Output Circuits in 2.3 Pin I/O Circuits and Recommended Connections of Unused Pins p.43 Modification of Caution in 3.1 Memory Space...
  • Page 7 INTRODUCTION Readers This manual has been prepared for user engineers who understand the functions of the µ PD780065 Subseries and wish to design and develop application systems and programs for these devices. µ PD780065 Subseries: µ PD780065 µ PD78F0066 Purpose This manual is intended to provide users an understanding of the functions described in the organization below.
  • Page 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Related documents for the device Document No. Document Name English Japanese µ PD780065 Preliminary Product Information U13732E U13732J µ...
  • Page 9 Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
  • Page 10 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 11: Table Of Contents

    CONTENTS CHAPTER 1 OUTLINE ........................1.1 Features ..........................1.2 Applications ......................... 1.3 Ordering Information ......................1.4 Pin Configuration (Top View) ....................1.5 78K/0 Series Lineup ......................1.6 Block Diagram ........................1.7 Outline of Function ......................CHAPTER 2 PIN FUNCTION ......................2.1 Pin Functions ........................
  • Page 12 3.2 Processor Registers ......................3.2.1 Control registers ......................... 3.2.2 General registers ........................3.2.3 Special Function Register (SFR) ....................3.3 Instruction Address Addressing ..................3.3.1 Relative addressing ........................3.3.2 Immediate addressing ........................ 3.3.3 Table indirect addressing ......................3.3.4 Register addressing ........................3.4 Operand Address Addressing ....................
  • Page 13 5.5 Clock Generator Operations ....................5.5.1 Main system clock operations ....................5.5.2 Subsystem clock operations ...................... 5.6 Changing System Clock and CPU Clock Settings ............100 5.6.1 Time required for switchover between system clock and CPU clock ......... 5.6.2 System clock and CPU clock switching procedure ..............CHAPTER 6 16-BIT TIMER/EVENT COUNTER ................
  • Page 14 9.3 Registers to Control the Watchdog Timer ................. 163 9.4 Watchdog Timer Operations ....................167 9.4.1 Watchdog timer operation ......................9.4.2 Interval timer operation ......................CHAPTER 10 CLOCK OUTPUT CONTROL CIRCUITS ..............169 10.1 Clock Output Control Circuit Functions ................169 10.2 Clock Output Control Circuit Configuration ..............
  • Page 15 CHAPTER 15 SERIAL INTERFACE (SIO30) ................... 251 15.1 Serial Interface (SIO30) Functions ..................251 15.2 Serial Interface (SIO30) Configuration ................252 15.3 Register to Control Serial Interface (SIO30) ..............253 15.4 Serial Interface (SIO30) Operations ..................254 15.4.1 Operation stop mode ........................15.4.2 2-wire serial I/O mode ........................
  • Page 16 CHAPTER 20 RESET FUNCTION ....................301 20.1 Reset Function ........................301 CHAPTER 21 µ PD78F0066 ....................... 305 21.1 Memory Size Switching Register ..................306 21.2 Internal Expansion RAM Size Switching Register ............307 21.3 Flash Memory Programming ....................308 21.3.1 Selection of transmission method ....................21.3.2 Flash memory programming function ..................
  • Page 17 LIST OF FIGURES (1/5) Figure No. Title Page Pin Input/Output Circuits ........................Memory Map ( µ PD780065) ......................Memory Map ( µ PD78F0066) ......................Data Memory Addressing ( µ PD780065) ................... Data Memory Addressing ( µ PD78F0066) ..................Program Counter Format ........................Program Status Word Format ......................
  • Page 18 LIST OF FIGURES (2/5) Figure No. Title Page Timing of Interval Timer Operation ....................6-10 Control Register Settings for PPG Output Operation ............... 6-11 Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register ........................ 6-12 Configuration Diagram for Pulse Width Measurement by Free-Running Counter ......
  • Page 19 LIST OF FIGURES (3/5) Figure No. Title Page Watch Timer Block Diagram ......................Format of Watch Timer Mode Control Register (WTM) ..............Operation Timing of Watch Timer/Interval Timer ................Watchdog Timer Block Diagram ....................... Format of Watchdog Timer Clock Select Register (WDCS) .............. Format of Watchdog Timer Mode Register (WDTM) ................
  • Page 20 LIST OF FIGURES (4/5) Figure No. Title Page 14-10 Basic Transmit Mode Operation Timings ..................14-11 Basic Transmit Mode Flowchart ......................14-12 Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ........14-13 Repeat Transmit Mode Operation Timing ..................14-14 Repeat Transmit Mode Flowchart .....................
  • Page 21 LIST OF FIGURES (5/5) Figure No. Title Page 18-6 External Memory Write Timing ......................18-7 External Memory Read Modify Write Timing ..................Connection Example of µ PD780065 and Memory ................18-8 19-1 Format of Oscillation Stabilization Time Select Register (OSTS) ............. 19-2 HALT Mode Clear Upon Interrupt Request Generation ..............
  • Page 22 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...
  • Page 23 LIST OF TABLES (1/2) Table No. Title Page Connections of Unused Pins ......................Internal ROM Capacity ........................Vector Table ............................Special Function Register List ......................Port Functions ........................... Port Configuration ..........................Clock Generator Configuration ......................Relationship of CPU Clock and Min. Instruction Execution Time ............. Maximum Time Required for CPU Clock Switchover ...............
  • Page 24 LIST OF TABLES (2/2) Table No. Title Page 15-1 Serial Interface (SIO30) Configuration ....................16-1 Serial Interface (SIO31) Configuration ....................17-1 Interrupt Source List ......................... 17-2 Flags Corresponding to Interrupt Request Sources ................. 17-3 Times from Generation of Maskable Interrupt until Servicing ............17-4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ........

  • Page 25: Chapter 1 Outline

    CHAPTER 1 OUTLINE 1.1 Features • Internal Memory Type Program Memory Data Memory Part Number (Mask ROM/Flash memory) High-Speed RAM Expansion RAM Buffer RAM µ PD780065 40 Kbytes 1024 bytes 4096 bytes 32 bytes µ PD78F0066 Note 48 Kbytes Note The capacity of internal flash memory can be changed by means of the memory size switching register (IMS). •...

  • Page 26: Applications

    CHAPTER 1 OUTLINE 1.2 Applications Car audio supporting CD text, etc. 1.3 Ordering Information Part Number Package Internal ROM µ PD780065GC-×××-8BT 80-pin plastic QFP (14 × 14 mm) Mask ROM µ PD78F0066GC-×××-8BT 80-pin plastic QFP (14 × 14 mm) Flash memory Remark ×××...

  • Page 27: Pin Configuration (Top View)

    CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 80-pin plastic QFP (14 × 14 mm) µ PD780065GC-×××-8BT µ PD78F0066GC-8BT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ANI7 P42/AD2 ANI6...
  • Page 28 CHAPTER 1 OUTLINE A8 to A15: Address Bus PCL: Programmable Clock AD0 to AD7: Address/Data Bus Read Strobe ANI0 to ANI7: Analog Input RESET: Reset ASCK0: Asynchronous Serial Clock RxD0: Receive Data ASTB: Address Strobe SCK1, SCK30, SCK31: Serial Clock Analog Reference Voltage SDIO30: Serial Data Input/Output...

  • Page 29: Series Lineup

    CHAPTER 1 OUTLINE 1.5 78K/0 Series Lineup The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I C bus. Control µ...
  • Page 30 CHAPTER 1 OUTLINE Major functional differences among the subseries are listed below. Function Timer 8-bit 10-bit 8-bit External Serial Interface Capacity 8-bit 16-bit Watch WDT A/D MIN. Value Expansion Subseries Name Control µ PD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch √...

  • Page 31: Block Diagram

    CHAPTER 1 OUTLINE 1.6 Block Diagram TI00/TO0/P20 16-bit TIMER/ PORT 0 P00 to P07 EVENT COUNTER TI01/P21 8-bit TIMER/ PORT 2 P20 to P27 TI50/TO50/P22 EVENT COUNTER 50 8-bit TIMER/ TI51/TO51/P23 PORT 3 P30 to P37 EVENT COUNTER 51 WATCHDOG TIMER PORT 4 P40 to P47 WATCH TIMER...

  • Page 32: Outline Of Function

    CHAPTER 1 OUTLINE 1.7 Outline of Function Part Number µ PD780065 µ PD78F0066 Item Note Internal memory 40 Kbytes (Mask ROM) 48 Kbytes (Flash memory) High-speed RAM 1024 bytes Expansion RAM 4096 bytes Buffer RAM 32 bytes Memory space 64 Kbytes 8 bits ×...

  • Page 33: Chapter 2 Pin Function

    CHAPTER 2 PIN FUNCTION 2.1 Pin Functions (1) Port Pins (1/2) Alternate Pin Name Input/Output Function After Reset Function P00 to P03 Input/Output Port 0 Input INTP0 to INTP3 8-bit input/output port Input/output mode can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software.
  • Page 34 CHAPTER 2 PIN FUNCTION (1) Port Pins (2/2) Alternate Pin Name Input/Output Function After Reset Function Input/Output Port 7 Input 8-bit input/output port ASCK0 Input/output mode can be specified in 1-bit units. TxD0 An on-chip pull-up resistor can be specified by means of software.
  • Page 35 CHAPTER 2 PIN FUNCTION (2) Non-port Pins (2/2) Alternate Pin Name Input/Output Function After Reset Function ASCK0 Input Asynchronous serial interface serial clock input Input TI00 Input External count clock input to 16-bit timer (TM0) Input P20/TO0 Capture trigger input to TM0 capture registers (CR00, CR01) TI01 Capture trigger input to TM0 capture register (CR00) TI50...

  • Page 36: Description Of Pin Functions

    CHAPTER 2 PIN FUNCTION 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) This is an 8-bit input/output port. Besides serving as an input/output port, these pins function as external interrupt request inputs. The following operating modes can be specified in 1-bit units. (1) Port mode These pins function as an 8-bit input/output port.

  • Page 37: P30 To P37 (Port 3)

    CHAPTER 2 PIN FUNCTION 2.2.3 P30 to P37 (Port 3) This is an 8-bit input/output port. These pins can be specified in 1-bit units as input or output ports with port mode register 3 (PM3). On-chip pull-up resistors can be specified by defining pull-up resistor option register 3 (PU3). 2.2.4 P40 to P47 (Port 4) This is an 8-bit input/output port.

  • Page 38: P70 To P77 (Port 7)

    CHAPTER 2 PIN FUNCTION 2.2.7 P70 to P77 (Port 7) This is an 8-bit input/output port. Besides serving as input/output ports, these pins function as the serial data input/ output, serial clock input/output, and clock output of the serial interface. The following operating modes can be specified in 1-bit units.

  • Page 39: P80 To P84 (Port 8)

    CHAPTER 2 PIN FUNCTION 2.2.8 P80 to P84 (Port 8) This is a 5-bit input/output port. Besides serving as input/output ports, these pins function as the data input/output, clock input/output, automatic transmission/reception busy input, and strobe output of serial interface. The following operating modes can be specified in 1-bit units.

  • Page 40: Av Ref

    CHAPTER 2 PIN FUNCTION 2.2.11 AV This is an A/D converter reference voltage input pin. This pin is also used for analog power supply. When no A/D converter is used, connect this pin to V 2.2.12 AV This is a ground voltage pin of A/D converter. Always use the same voltage as that of the V pin even when no A/D converter is used.

  • Page 41: Pin I/O Circuits And Recommended Connections Of Unused Pins

    CHAPTER 2 PIN FUNCTION 2.3 Pin I/O Circuits and Recommended Connections of Unused Pins The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, refer to Figure 2-1. Table 2-1.
  • Page 42 CHAPTER 2 PIN FUNCTION Figure 2-1. Pin Input/Output Circuits Type 2 Type 8-C pullup P-ch enable data P-ch IN/OUT output N-ch disable Schmitt-triggered input with hysteresis characteristics Type 5-H Type 16 feedback cut-off pullup P-ch enable P-ch data P-ch IN/OUT output N-ch disable...

  • Page 43: Chapter 3 Cpu Architecture

    CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space µ PD780065 Subseries can access 64-Kbyte memory space respectively. Figures 3-1 and 3-2 show memory maps. Caution As the initial setting of the program, set the memory size switching register (IMS) and internal expansion RAM size switching register (IXS) as follows.
  • Page 44 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ PD78F0066) FFFFH Special function registers (SFRs) 256 × 8 bits FF00H FEFFH General registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 1024 × 8 bits BFFFH FB00H FAFFH Program area Reserved FAE0H...

  • Page 45: Internal Program Memory Space

    CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space contains the program and table data. Normally, it is addressed with the program counter (PC). The µ PD780065 Subseries products incorporate an internal ROM (or flash memory), as listed below. Table 3-1.
  • Page 46 CHAPTER 3 CPU ARCHITECTURE (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16- bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.

  • Page 47: Internal Data Memory Space

    CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space The µ PD780065 Subseries incorporates the following RAM. (1) Internal high-speed RAM The internal high-speed RAM has an 1024 × 8-bit (FB00H to FEFFH) configuration. Four general-purpose register banks composed of eight 8-bit registers are allocated to the 32-byte area of FEE0H to FEFFH. The internal high-speed RAM can also be used as a stack memory.

  • Page 48: Data Memory Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.1.5 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. The address of an instruction to be executed next is addressed by the program counter (PC) (for details, see 3.3 Instruction Address Addressing).
  • Page 49 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Data Memory Addressing ( µ PD78F0066) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General registers Register addressing 32 × 8 bits Short direct FEE0H addressing FEDFH Internal high-speed RAM 1024 ×...

  • Page 50: Processor Registers

    CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD780065 Subseries products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
  • Page 51 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to the disable interrupt (DI) state, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all disabled. When 1, the IE is set to the enable interrupt (EI) state and interrupt request acknowledge enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag.
  • Page 52 CHAPTER 3 CPU ARCHITECTURE Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before instruction execution. Figure 3-8. Data to be Saved to Stack Memory Interrupt and PUSH rp Instruction CALL, CALLF, and BRK Instructions CALLT Instructions SP _ 3 SP _ 2...

  • Page 53: General Registers

    CHAPTER 3 CPU ARCHITECTURE 3.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register.

  • Page 54: Special Function Register (Sfr)

    CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions.
  • Page 55 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Register List (1/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 bit 8 bits 16 bits √ √ FF00H Port0 — √ √ FF02H Port2 — √ √ FF03H Port3 —...
  • Page 56 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special-Function Register List (2/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 8 bits 16 bits 1 bit √ √ FF30H Pull-up resistor option register 0 — √ √ FF32H Pull-up resistor option register 2 —...
  • Page 57 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special-Function Register List (3/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 bit 8 bits 16 bits √ √ FFB0H Serial operation mode register 30 CSIM30 — √ √ FFB1H Serial operation mode register 31 CSIM31 —...

  • Page 58: Instruction Address Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.

  • Page 59: Immediate Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
  • Page 60 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.

  • Page 61: Register Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 62: Operand Address Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed.

  • Page 63: Register Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general register to be specified is accessed as an operand with the register specify code (Rn and RPn) of an instruction word in the registered bank specified with the register bank select flag (RBS0 to RBS1). Register addressing is carried out when an instruction with the following operand format is executed.

  • Page 64: Direct Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code...

  • Page 65: Short Direct Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
  • Page 66 CHAPTER 3 CPU ARCHITECTURE [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration]...

  • Page 67: Special-Function Register (Sfr) Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special-function register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.

  • Page 68: Register Indirect Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory to be manipulated.

  • Page 69: Based Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory.

  • Page 70: Based Indexed Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag (RBS0 and RBS1) and the sum is used to address the memory.

  • Page 71: Chapter 4 Port Functions

    CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD780065 Subseries products incorporate sixty input/output ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins.
  • Page 72 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Alternate Pin Name Function Function Port 0 P00 to P03 INTP0 to INTP3 8-bit input/output port. Input/output mode can be specified in 1-bit units. P04 to P07 — An on-chip pull-up resistor can be specified by means of software. Port 2 TI00/TO0 8-bit input/output port.

  • Page 73: Port Configuration

    CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration A port consists of the following hardware: Table 4-2. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 2 to 9) Pull-up resistor option register (PUm: m = 0, 2 to 9) Port Input/output: 60 Pull-up resistor...
  • Page 74 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P00 to P07 PU00 to PU07 P-ch Selector PORT P00/INTP0 to Output latch P03/INTP3, (P00 to P07) P04 to P07 PM00 to PM07 PU: Pull-up resistor option register PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 75: Port 2

    CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 2 Port 2 is an 8-bit input/output port with output latch. Input mode/output mode can be specified for pins P20 to P27 in 1-bit units with port mode register 2 (PM2). For pins P20 to P27, an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 2 (PU2).

  • Page 76: Port 3

    CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is an 8-bit input/output port with output latch. Input mode/output mode can be specified for pins P30 to P37 in 1-bit units with port mode register 3 (PM3). For pins P30 to P37, an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 3 (PU3).

  • Page 77: Port 4

    CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 Port 4 is an 8-bit input/output port with output latch. Input mode/output mode can be specified for pins P40 to P47 in 1-bit units with port mode register 4 (PM4). For pins P40 to P47, a pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (PU4).

  • Page 78: Port 5

    CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 5 Port 5 is an 8-bit input/output port with output latch. Input mode/output mode can be specified for pins P50 to P57 in 1-bit units with port mode register 5 (PM5). For pins P50 to P57, an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 5 (PU5).

  • Page 79: Port 6

    CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 Port 6 is a 4-bit input/output port with output latch. Input mode/output mode can be specified for pins P64 to P67 in 1-bit units with port mode register 6 (PM6). For pins P64 to P67, an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 6 (PU6).

  • Page 80: Port 7

    CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 This is an 8-bit input/output port with output latch. Input mode/output mode can be specified for pins P70 to P77 in 1-bit units by means of port mode register 7 (PM7). For pins P70 to P77, an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 7 (PU7).
  • Page 81 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P76 and P77 PU76, PU77 P-ch Selector PORT Output latch P76, P77 (P76, P77) PM76, PM77 PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 82: Port 8

    CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 8 This is a 5-bit input/output port with output latch. Input mode/output mode can be specified for pins P80 to P84 in 1-bit units with port mode register 8 (PM8). For pins P80 to P84, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register 8 (PU8).

  • Page 83: Port 9

    CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 9 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified for pins P90 to P92 in 1-bit units with port mode register 9 (PM9). For pins P90 to P92, an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 9 (PU9).

  • Page 84: Port Function Control Registers

    CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM2 to PM9) • Pull-up resistor option register (PU0, PU2 to PU9) (1) Port mode registers (PM0, PM2 to PM9) These registers are used to set port input/output in 1-bit units.
  • Page 85 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Format of Port Mode Registers (PM0, PM2 to PM9) Address: FF20H After Reset: FFH Symbol PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 Address: FF22H After Reset: FFH Symbol PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20...
  • Page 86 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option registers (PU0, PU2 to PU9) This register is used to set whether to use an internal pull-up resistor at each port or not. An on-chip pull-up resistor for each port pin can be specified by setting PU0, and PU2 to PU9. PU0 and PU2 to PU9 are set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 87 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Format of Pull-Up Resistor Option Registers (PU0, PU2 to PU9) Address: FF30H After Reset: 00H Symbol PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00 Address: FF32H After Reset: 00H Symbol PU27 PU26 PU25 PU24 PU23 PU22 PU21...

  • Page 88: Port Function Operations

    CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

  • Page 89: Chapter 5 Clock Generator

    CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 8.38 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
  • Page 90 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Clock Generator Block Diagram Subsystem Watch timer clock clock oscillator output Prescaler function Clock to Main system peripheral clock hardware Prescaler oscillator Standby Wait CPU clock control control circuit circuit To INTP0 sampling clock STOP MCC FRC CSS PCC2 PCC1 PCC0...

  • Page 91: Clock Generator Control Register

    CHAPTER 5 CLOCK GENERATOR 5.3 Clock Generator Control Register The clock generator is controlled by the processor clock control register (PCC). The PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor. The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
  • Page 92 CHAPTER 5 CLOCK GENERATOR Figure 5-3. Format of Processor Clock Control Register (PCC) Note 1 Address: FFFBH After Reset: 04H Symbol PCC2 PCC1 PCC0 Note 2 Main system clock oscillation control Oscillation possible Oscillation stopped Subsystem clock feedback resistor select Internal feedback resistor used Internal feedback resistor not used CPU clock status...

  • Page 93: System Clock Oscillator

    CHAPTER 5 CLOCK GENERATOR The fastest instructions of µ PD780065 Subseries are carried out in 2 CPU clocks. The relationship of CPU clock ) and minimum instruction execution time is shown in Table 5-2. Table 5-2. Relationship of CPU Clock and Min. Instruction Execution Time CPU Clock (f Min.

  • Page 94: Subsystem Clock Oscillator

    CHAPTER 5 CLOCK GENERATOR 5.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin and an inverted-phase clock signal to the XT2 pin.
  • Page 95 CHAPTER 5 CLOCK GENERATOR Cautions 1. When using the main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in Figures 5-4 and 5-5 to prevent any effects from wiring capacitance. • Minimize the wiring length. •...
  • Page 96 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Examples of Incorrect Oscillator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.

  • Page 97: Scaler

    CHAPTER 5 CLOCK GENERATOR 5.4.3 Scaler The scaler divides the main system clock oscillator output (f ) and generates various clocks. 5.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows.

  • Page 98: Clock Generator Operations

    CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC).

  • Page 99: Main System Clock Operations

    CHAPTER 5 CLOCK GENERATOR 5.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.

  • Page 100: Subsystem Clock Operations

    CHAPTER 5 CLOCK GENERATOR Figure 5-7. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation Main system clock oscillation Subsystem clock oscillation CPU clock 5.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
  • Page 101 CHAPTER 5 CLOCK GENERATOR Table 5-3. Maximum Time Required for CPU Clock Switchover Set Value before Set Value after Switchover Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 ×...

  • Page 102: System Clock And Cpu Clock Switching Procedure

    CHAPTER 5 CLOCK GENERATOR 5.6.2 System clock and CPU clock switching procedure This section describes switching procedure between the system clock and CPU clock. Figure 5-8. System Clock and CPU Clock Switching RESET Interrupt request signal System clock CPU clock Lowest- Highest- Subsystem...

  • Page 103: Chapter 6 16-Bit Timer/Event Counter

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.1 Outline of Timer Integrated in µ PD780065 Subseries In this chapter, the 16-bit timer/event counter is described. The timers integrated in the µ PD780065 Subseries are outlined below. (1) 16-bit timer/event counter (TM0) The TM0 can be used as an interval timer, pulse widths measurement (infrared ray remote control receive function), external event counter, PPG output, square wave output of any frequency, or one-shot pulse output.

  • Page 104: 16-Bit Timer/Event Counter Functions

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER Table 6-1. Timer/Event Counter Operations 16-bit Timer/ 8-bit Timer/ Watch Timer Watchdog Timer Event Counter Event Counter Note1 Note2 Operation Interval timer 1 channel 2 channels 1 channel 1 channel Mode √ √ External event counter —...
  • Page 105 CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-1. 16-Bit Timer/Event Counter Block Diagram Internal bus Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 INTTM00 Noise 16-bit timer capture/ elimi- TI01/P21 compare register 00 (CR00) nation circuit Coincidence 16-bit timer/counter 0 Clear Output (TM0) TO0/TI00/...

  • Page 106: 16-Bit Timer/Event Counter Configuration

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.3 16-Bit Timer/Event Counter Configuration 16-bit timer/event counter consists of the following hardware. Table 6-2. 16-Bit Timer/Event Counter Configuration Item Configuration 16 bits × 1 (TM0) Timer register Capture/compare register: 16 bits × 2 (CR00, CR01) Register Timer output 1 (TO0)
  • Page 107 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (2) 16-bit timer capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0 (CRC0).

  • Page 108: Registers To Control 16-Bit Timer/Event Counter

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer capture/compare register 01 (CR01) CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register 0 (CRC0). •...
  • Page 109 CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-2. Format of 16-Bit Timer Mode Control Register 0 (TMC0) Address FF60H After reset: 00H Symbol TMC0 TMC03 TMC02 TMC01 OVF0 Operating mode TMC03 TMC02 TMC01 TO0 output timing selection Interrupt request generation and clear mode selection Operation stop No change Not generated...
  • Page 110 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (2) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 00H. Figure 6-3.
  • Page 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer output control register 0 (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flip- flop (LV0) setting/resetting, output inversion enabling/disabling, 16-bit timer/event counter timer output enabling/ disabling, one-shot pulse output operation enabling/disabling, and output trigger for a one-shot pulse by software.
  • Page 112 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (4) Prescaler mode register 0 (PRM0) This register is used to set 16-bit timer/counter 0 (TM0) count clock and TI00, TI01 input valid edges. PRM0 is set with an 8-bit memory manipulation instruction. RESET input sets PRM0 value to 00H. Figure 6-5.
  • Page 113 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (5) Port mode register 2 (PM2) This register sets port 2 input/output in 1-bit units. When using the P20/TO0/TI00 pin for timer output, set PM20 and the output latch of P20 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM7 value to FFH.

  • Page 114: 16-Bit Timer/Event Counter Operations

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5 16-Bit Timer/Event Counter Operations 6.5.1 Interval timer operations Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-7 allows operation as an interval timer. Interrupt request is generated repeatedly using the count value set in 16-bit timer capture/compare register 00 (CR00) beforehand as the interval.
  • Page 115 CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-8. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00 (CR00) INTTM00 16-bit timer/counter 0 OVF0 (TM0) Noise TI00/TO0/P20 elimination Clear circuit circuit Figure 6-9. Timing of Interval Timer Operation Count clock TM0 count value 0000H 0001H 0000H 0001H...

  • Page 116: Ppg Output Operations

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.2 PPG output operations Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-10 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/TI00/P20 pin with the pulse width and the cycle that corresponds to the count values set beforehand in 16-bit timer capture/compare register 01 (CR01) and in 16-bit timer capture/compare register 00 (CR00), respectively.

  • Page 117: Pulse Width Measurement Operations

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/TO0/P20 pin and TI01/P21 pin using 16-bit timer/counter 0 (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/TO0/P20 pin.
  • Page 118 CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-12. Configuration Diagram for Pulse Width Measurement by Free-Running Counter 16-bit timer/counter 0 OVF0 (TM0) 16-bit timer capture/compare TI00/TO0/P20 register 01 (CR01) INTTM01 Internal bus Figure 6-13. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock TM0 count value...
  • Page 119 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter When 16-bit timer/counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-14), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/TO0/P20 pin and the TI01/P21 pin.
  • Page 120 CHAPTER 6 16-BIT TIMER/EVENT COUNTER • Capture operation (Free-Running mode) Capture register operation in capture trigger input is shown. Figure 6-15. Capture Operation with Rising Edge Specified Count clock n–3 n–2 n–1 TI00 Rising edge detection CR01 INTTM01 Figure 6-16. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H...
  • Page 121 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer/counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-17), it is possible to measure the pulse width of the signal input to the TI00//TO0/P20 pin. When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the TI00/TO0/P20 pin, the value of TM0 is taken into 16-bit timer capture/compare register 01 (CR01) and an external interrupt request signal (INTTM01) is set.
  • Page 122 CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-18. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM0 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI00 pin input CR01 capture value CR00 capture value...
  • Page 123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-19. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts at valid edge of TI00/TO0/P20 pin. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01...

  • Page 124: External Event Counter Operation

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.5.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/TO0/P20 pin with 16-bit timer/counter 0 (TM0). TM0 is incremented each time the valid edge specified with the prescaler mode register 0 (PRM0) is input. When the TM0 counted value matches 16-bit timer capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.

  • Page 125: Square-Wave Output Operation

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-22. External Event Counter Configuration Diagram 16-bit timer capture/compare register (CR00) Coincidence INTTM00 Clear 16-bit timer/counter 0 (TM0) OVF0 Noise elimination circuit 16-bit timer capture/compare Valid edge of TI00 register (CR01) Internal bus Figure 6-23. External Event Counter Operation Timings (with Rising Edge Specified) TI00 pin input TM0 count value 0000H 0001H 0002H 0003H 0004H 0005H...
  • Page 126 CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-24. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on coincidence between TM0 and CR00. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...

  • Page 127: One-Shot Pulse Output Operation

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-25. Square-Wave Output Operation Timing Count clock TM0 count value 0000H 0001H 0002H N–1 0000H 0001H 0002H N–1 0000H CR00 INTTM00 TO0 pin output 6.5.6 One-shot pulse output operation It is possible to output one-shot pulses by software trigger. If 16-bit timer mode control register 0 (TMC0), capture/compare control register 0 (CRC0), and 16-bit timer output control register 0 (TOC0) are set as shown in Figure 6-26, and 1 is set in bit 6 (OSPT) of TOC0 by software, a one- shot pulse is output from the TO0/TI00/P20 pin.
  • Page 128 CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-26. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Free-running mode (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0...
  • Page 129 CHAPTER 6 16-BIT TIMER/EVENT COUNTER Figure 6-27. Timing of One-Shot Pulse Output Operation Using Software Trigger Sets 0CH to TMC0 (TM0 count starts) Count clock TM0 count value 0000H 0001H 0000H N–1 M–1 M+1 M+2 CR01 set value CR00 set value OSPT INTTM01 INTTM00...

  • Page 130: 16-Bit Timer/Event Counter Operating Precautions

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 6.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because 16-bit timer/counter 0 (TM0) is started asynchronously with the count pulse. Figure 6-28.
  • Page 131 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/TO0/P20 pin is input during 16-bit timer capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (TMIF01) is set upon detection of the valid edge.
  • Page 132 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag <1> OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH. ↓...
  • Page 133 CHAPTER 6 16-BIT TIMER/EVENT COUNTER (10) Capture operation If TI00 is specified as the valid edge of the count clock, capture operation by the capture register specified as the trigger for TI00 is not possible. (11) Compare operation <1> When 16-bit timer capture/compare register (CR00/CR01) is overwritten during timer operation, match interrupt may be generated or clear operation may not be performed normally if that value is close to the timer value and larger than the timer value.
  • Page 134 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 135: Chapter 7 8-Bit Timer/Event Counter

    CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.1 8-Bit Timer/Event Counter Functions 8-bit timer/event counter (TM50, TM51) has the following two modes. • Mode using 8-bit timer/event counters alone (individual mode) • Mode using the cascade connection (16-bit resolution: cascade connection mode) These two modes are described next.
  • Page 136 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-1. 8-Bit Timer/Event Counter 50 Block Diagram Internal bus 8-bit compare Selector INTTM50 register 50 (CR50) TI50/TO50/P22 Coincidence 8-bit counter 50 TO50/TI50/P22 (TM50) Clear Invert level Selector TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 TCL502 TCL501 TCL500 Timer mode control Timer clock selection...

  • Page 137: 8-Bit Timer/Event Counter Configurations

    CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.2 8-Bit Timer/Event Counter Configurations 8-bit timer/event counter consists of the following hardware. Table 7-1. 8-Bit Timer/Event Counter Configurations Item Configuration Timer register 8-bit counter 5n (TM5n) Register 8-bit compare register 5n (CR5n) Timer output 2 (TO5n) Control register Timer clock select register 5n (TCL5n)

  • Page 138: Registers To Control 8-Bit Timer/Event Counter

    CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.3 Registers to Control 8-Bit Timer/Event Counter The following three types of registers are used to control 8-bit timer/event counters. • Timer clock select register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
  • Page 139 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-4. Format of Timer Clock Select Register 51 (TCL51) Address: FF75H After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection TI51 Falling edge TI51 Rising edge /2 (4.19 MHz) (1.04 MHz) (261 kHz) (65.4 kHz)
  • Page 140 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-5. Format of 8-Bit Timer Mode Control Register 5n (TMC5n) Address: FF70H (TMC50) FF74H (TMC51) After reset: 04H Symbol TMC5n TCE5n TMC5n6 TMC5n4 LVS5n LVR5n TMC5n1 TOE5n TCE5n TM5n count operation control After cleaning to 0, count operation disabled (prescaler disabled) Count operation start TMC5n6 TM5n operating mode selection...
  • Page 141 CHAPTER 7 8-BIT TIMER/EVENT COUNTER (3) Port mode register 2 (PM2) This register sets port 2 input/output in 1-bit units. When using the P22/TO50/TI50 and P23/TI51/TO51 pins for timer output, set PM22, PM23, and output latches of P22 and P23 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 142: 8-Bit Timer/Event Counter Operations

    CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4 8-Bit Timer/Event Counter Operations 7.4.1 8-bit interval timer operation The 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare register 5n (CR5n). When the count values of 8-bit counter 5n (TM5n) match the values set to CR5n, counting continues with the TM5n values cleared to 0 and the interrupt request signals (INTTM5n) are generated.
  • Page 143 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-7. Interval Timer Operation Timings (1/3) (a) Basic operation Count clock TM5n count value Start count Clear Clear CR5n TCE5n INTTM5n Interrupt request received Interrupt request received TO5n Interval time Interval time Interval time Remarks 1.
  • Page 144 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-7. Interval Timer Operation Timings (2/3) (b) When CR5n = 00H Count clock CR5n TCE5n INTTM5n TO5n Interval time (c) When CR5n = FFH Count clock TM5n FEH FFH 00H CR5n TCE5n INTTM5n Interrupt request received Interrupt request received...
  • Page 145 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-7. Interval Timer Operation Timings (3/3) (d) Operated by CR5n transition (M < N) Count clock CR5n TCE5n INTTM5n TO5n CR5n transition TM5n overflows since M < N (e) Operated by CR5n transition (M > N) Count clock N–1 M–1...

  • Page 146: External Event Counter Operation

    CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit counter 5n (TM5n). TM5n is incremented each time the valid edge specified with timer clock select register 5n (TCL5n) is input. Either the rising or falling edge can be selected.

  • Page 147: Square-Wave Output (8-Bit Resolution) Operation

    CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.3. Square-wave output (8-bit resolution) operation A square wave with any selected frequency is output at intervals of the value preset to the 8-bit compare register 5n (CR5n). TO5n pin output status is reversed at intervals of the count value preset to CR5n by setting bit 0 (TOE5n) of 8- bit timer mode control register 5n (TMC5n) to 1.

  • Page 148: 8-Bit Pwm Output Operation

    CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.4 8-bit PWM output operation The 8-bit timer/event counter operates as PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty rate pulse determined by the value set to 8-bit compare register 5n (CR5n). Set the active level width of PWM pulse to CR5n, and the active level can be selected with bit 1 of TMC5n (TMC5n1).
  • Page 149 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-10. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N+1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level (b) CR5n = 0 Count clock...
  • Page 150 CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) Operated by CR5n transition Figure 7-11. Timing of Operation by Change of CR5n (a) CR5n value transits from N to M before overflow of TM5n Count clock TM5n N N+1 N+2 FFH 00H 01H M M+1 M+2 FFH 00H 01H 02H M M+1 M+2...

  • Page 151: Interval Timer (16-Bit) Operations

    CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.5 Interval timer (16-bit) operations When bit 4 (TMC514) of 8-bit timer mode control register 51 (TM51) is set to 1, the 16-bit resolution timer/counter mode is entered. The 8-bit timer/event counter operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit compare registers (CR50, CR51).

  • Page 152: 8-Bit Timer/Event Counter Cautions

    CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-12. 16-Bit Resolution Cascade Connection Mode Count clock TM50 N N+1 FFH 00H FFH 00H FFH 00H 01H N 00H 01H A 00H TM51 M–1 M B 00H CR50 CR51 TCE50 TCE51 INTTM50 Interval time TO50 Interrupt request Operation...
  • Page 153 CHAPTER 7 8-BIT TIMER/EVENT COUNTER (2) Operation after compare register transition during timer count operation If the value after 8-bit compare register 5n (CR5n) is transmitted is smaller than the value of 8-bit counter 5n (TM5n), TM5n continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after CR5n is smaller than value (N) before transition, it is necessary to restart the timer after transiting CR5n.
  • Page 154 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 155: Chapter 8 Watch Timer

    CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 8-1 shows the watch timer block diagram. Figure 8-1.

  • Page 156: Watch Timer Configuration

    CHAPTER 8 WATCH TIMER (1) Watch timer When the main system clock or subsystem clock is used, interrupt requests (INTWT) are generated at 0.5 second or 0.25 second intervals. (2) Interval timer Interrupt requests (INTWTI) are generated at the preset time interval. Table 8-1.

  • Page 157: Register To Control Watch Timer

    CHAPTER 8 WATCH TIMER 8.3 Register to Control Watch Timer Watch timer mode control register (WTM) is a register to control watch timer. • Watch timer mode control register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control.

  • Page 158: Watch Timer Operations

    CHAPTER 8 WATCH TIMER 8.4 Watch Timer Operations 8.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 8.38-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer generates an interrupt request (INTWT) at the constant time interval. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer mode control register (WTM) is set to 1, the 5-bit counter is cleared and the count operation stops.
  • Page 159 CHAPTER 8 WATCH TIMER Figure 8-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time n ×...
  • Page 160 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 161: Chapter 9 Watchdog Timer

    CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer • Oscillation stabilization time selection Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM).
  • Page 162 CHAPTER 9 WATCHDOG TIMER (1) Watchdog timer mode A runaway is detected. Upon detection of the runaway, a non-maskable interrupt request or RESET can be generated. Table 9-1. Watchdog Timer Runaway Detection Times Runaway Detection Times × 1/f (489 µ s) ×...

  • Page 163: Watchdog Timer Configuration

    CHAPTER 9 WATCHDOG TIMER 9.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 9-3. Watchdog Timer Configuration Item Configuration Control register Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Oscillation stabilization time select register (OSTS) 9.3 Registers to Control the Watchdog Timer The following three types of registers are used to control the watchdog timer.
  • Page 164 CHAPTER 9 WATCHDOG TIMER (1) Watchdog timer clock select register (WDCS) This register sets overflow time of the watchdog timer and the interval timer. WDCS is set by an 8-bit memory manipulation instruction. RESET input sets WDCS to 00H. Figure 9-2. Format of Watchdog Timer Clock Select Register (WDCS) Address: FF42H After reset: 00H Symbol...
  • Page 165 CHAPTER 9 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3. Format of Watchdog Timer Mode Register (WDTM) Address: FFF9H After reset: 00H Symbol...
  • Page 166 CHAPTER 9 WATCHDOG TIMER (3) Oscillation Stabilization Time Select Register (OSTS) A register to select oscillation stabilization time from reset time or STOP mode released time to the time when oscillation is stabilized. OSTS is set by an 8-bit memory operation instruction. By RESET input, it is turned into 04H.

  • Page 167: Watchdog Timer Operations

    CHAPTER 9 WATCHDOG TIMER 9.4 Watchdog Timer Operations 9.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The runaway detection time interval is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS).

  • Page 168: Interval Timer Operation

    CHAPTER 9 WATCHDOG TIMER 9.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 3 (WDTM3) and bit 4 (WDTM4) of the watchdog timer mode register (WDTM) are set to 1 and 0, respectively.

  • Page 169: Chapter 10 Clock Output Control Circuits

    CHAPTER 10 CLOCK OUTPUT CONTROL CIRCUITS 10.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. Figure 10-1 shows the block diagram of clock output control circuits.

  • Page 170: Clock Output Control Circuit Configuration

    CHAPTER 10 CLOCK OUTPUT CONTROL CIRCUITS 10.2 Clock Output Control Circuit Configuration The clock output control circuits consists of the following hardware. Table 10-1. Configuration of Clock Output Control Circuits Item Configuration Control register Clock output select register (CKS) Note Port mode register (PM7) Note See Block Diagram of Figure 4-8.
  • Page 171 CHAPTER 10 CLOCK OUTPUT CONTROL CIRCUITS Figure 10-2. Format of Clock Output Select Register (CKS) Address: FF40H After reset: 00H R/W Symbol CLOE CCS3 CCS2 CCS1 CCS0 CLOE PCL output enable/disable setting Stop clock division circuit operation. PCL fixed to low level Enable clock division circuit operation.

  • Page 172: Clock Output Control Circuit Operations

    CHAPTER 10 CLOCK OUTPUT CONTROL CIRCUITS 10.4 Clock Output Control Circuit Operations The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status).

  • Page 173: Chapter 11 A/D Converter

    CHAPTER 11 A/D CONVERTER 11.1 A/D Converter Functions A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to 8 analog input channels (ANI0 to ANI7). A/D conversion operation is started by setting the A/D converter mode register (ADM0). Select one channel for analog input from ANI0 to ANI7 to perform A/D conversion.

  • Page 174: A/D Converter Configuration

    CHAPTER 11 A/D CONVERTER 11.2 A/D Converter Configuration The A/D converter consists of the following hardware. Table 11-1. A/D Converter Configuration Item Configuration Analog input 8 channels (ANI0 to ANI7) Registers Successive approximation register (SAR) A/D conversion result register (ADCR0) Control register A/D converter mode register (ADM0) Analog input channel specification register (ADS0)
  • Page 175 CHAPTER 11 A/D CONVERTER (6) ANI0 to ANI7 pins These are eight analog input pins to input analog signals to undergo A/D conversion to the A/D converter. ANI0 to ANI7 are alternate-function pins that can also be used for digital input. Cautions 1.

  • Page 176: Registers To Control A/D Converter

    CHAPTER 11 A/D CONVERTER 11.3 Registers to Control A/D Converter The following 2 types of registers are used to control the A/D converter. • A/D converter mode register (ADM0) • Analog input channel specification register (ADS0) (1) A/D converter mode register (ADM0) This register sets the conversion time for analog input to be A/D converted and conversion start/stop.
  • Page 177 CHAPTER 11 A/D CONVERTER (2) Analog input channel specification register (ADS0) This register specifies the analog voltage input port for A/D conversion. ADS0 is set by an 8-bit memory manipulation. RESET input sets ADS0 to 00H. Figure 11-3. Format of Analog Input Channel Specification Register (ADS0) Address: FF81H After reset: 00H R/W Symbol ADS0...

  • Page 178: A/D Converter Operations

    CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Operations 11.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register (ADS0). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
  • Page 179 CHAPTER 11 A/D CONVERTER Figure 11-4. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion operations are performed continuously until bit 7 (ADCS0) of the A/D converter mode register (ADM0) is reset (0) by software.

  • Page 180: Input Voltage And Conversion Results

    CHAPTER 11 A/D CONVERTER 11.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (stored in the A/D conversion result register (ADCR0)) is shown by the following expression. ×...

  • Page 181: A/D Converter Operation Mode

    CHAPTER 11 A/D CONVERTER 11.4.3 A/D converter operation mode One analog input channel is selected from among ANI0 to ANI7 by the analog input channel specification register (ADS0) and start A/D conversion. When bit 7 (ADCS0) of the A/D converter mode register (ADM0) is set to 1, A/D conversion of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS0) starts.

  • Page 182: A/D Converter Cautions

    CHAPTER 11 A/D CONVERTER 11.5 A/D Converter Cautions (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (ADCS0) of the A/D converter mode register (ADM0) to 0). Figure 11-7 shows how to reduce the current consumption in the standby mode.
  • Page 183 CHAPTER 11 A/D CONVERTER (4) Noise countermeasures To maintain the 8-bit resolution, attention must be paid to noise input to pin AV and pins ANI0 to ANI7. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 11-8 to reduce noise.
  • Page 184 CHAPTER 11 A/D CONVERTER (7) Interrupt request flag (ADIF0) The interrupt request flag (ADIF0) is not cleared even if the analog input channel specification register (ADS0) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS0 rewrite.

  • Page 185: Chapter 12 Serial Interface Outline

    CHAPTER 12 SERIAL INTERFACE OUTLINE The µ PD780065 Subseries is equipped with four channels of on-chip serial interfaces. The outline of the serial interfaces are listed in Table 12-1. For details, refer to the respective chapter. Table 12-1. Outline of On-Chip Serial Interface of the µ PD780065 Subseries Channel Serial Transfer Mode UART0...
  • Page 186 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 187: Chapter 13 Serial Interface (Uart0)

    CHAPTER 13 SERIAL INTERFACE (UART0) 13.1 Serial Interface (UART0) Functions The serial interface (UART0) has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. For details, see 13.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received.

  • Page 188: Serial Interface (Uart0) Configuration

    CHAPTER 13 SERIAL INTERFACE (UART0) 13.2 Serial Interface (UART0) Configuration The serial interface (UART0) includes the following hardware. Table 13-1. Serial Interface (UART0) Configuration Item Configuration Registers Transmit shift register (TXS0) Receive shift register (RX0) Receive buffer register (RXB0) Control registers Asynchronous serial interface mode register (ASIM0) Asynchronous serial interface status register (ASIS0) Baud rate generator control register (BRGC0)

  • Page 189: Registers To Control Serial Interface (Uart0)

    CHAPTER 13 SERIAL INTERFACE (UART0) (5) Reception control circuit The reception control circuit controls receive operations based on the values set to the asynchronous serial interface mode register (ASIM0). During a receive operation, it performs error checking, such as for parity errors, and sets various values to the asynchronous serial interface status register (ASIS0) according to the type of error that is detected.
  • Page 190 CHAPTER 13 SERIAL INTERFACE (UART0) Figure 13-2. Format of Asynchronous Serial Interface Mode Register (ASIM0) Address: FFA0H After reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 IRDAM0 TXE0 RXE0 Operation mode RxD0/P73 pin function TxD0/P72 pin function Operation stop Port function (P73) Port function (P72) UART mode...
  • Page 191 CHAPTER 13 SERIAL INTERFACE (UART0) (2) Asynchronous serial interface status register (ASIS0) When a receive error occurs during UART mode, this register indicates the type of error. ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets ASIS0 to 00H. Figure 13-3.
  • Page 192 CHAPTER 13 SERIAL INTERFACE (UART0) Figure 13-4. Format of Baud Rate Generator Control Register (BRGC0) Address: FFA2H After reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 = 8.38 MHz) TPS02 TPS01 TPS00 Source clock selection for 5-bit counter P71/ASCK0 MDL03 MDL02...

  • Page 193: Serial Interface (Uart0) Operations

    CHAPTER 13 SERIAL INTERFACE (UART0) 13.4 Serial Interface (UART0) Operations This section explains the three modes of the serial interface (UART0). 13.4.1 Operation stop mode Because serial transfer is not performed during this mode, the power consumption can be reduced. In addition, pins can be used as ordinary ports.

  • Page 194: Asynchronous Serial Interface (Uart) Mode

    CHAPTER 13 SERIAL INTERFACE (UART0) 13.4.2 Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data after the start bit is transmitted or received. The on-chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates.
  • Page 195 CHAPTER 13 SERIAL INTERFACE (UART0) Address: FFA0H After reset: 00H Symbol ASIM0 TXE0 RXE0 PS01 PS00 ISRM0 IRDAM0 TXE0 RXE0 Operation mode RxD0/P73 pin function TxD0/P72 pin function Operation stop Port function (P73) Port function (P72) UART mode Serial function (RxD0) (receive only) UART mode Port function (P73)
  • Page 196 CHAPTER 13 SERIAL INTERFACE (UART0) (b) Asynchronous serial interface status register (ASIS0) ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input sets ASIS0 to 00H. Address: FFA1H After reset: 00H Symbol ASIS0 OVE0 Parity error flag No parity error Parity error (Incorrect parity bit detected) Framing error flag...
  • Page 197 CHAPTER 13 SERIAL INTERFACE (UART0) (c) Baud rate generator control register (BRGC0) BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets BRGC0 to 00H. Address: FFA2H After reset: 00H Symbol BRGC0 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 = 8.38 MHz)
  • Page 198 CHAPTER 13 SERIAL INTERFACE (UART0) The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. • Transmit/receive clock generation for baud rate by using main system clock The main system clock is divided to generate the transmit/receive clock. The baud rate generated from the main system clock is determined according to the following formula.
  • Page 199 CHAPTER 13 SERIAL INTERFACE (UART0) • Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter’s division rate [1/(16 + k)]. Table 13-3 describes the relationship between the main system clock and the baud rate and Figure 13- 5 shows an example of a baud rate error tolerance range.
  • Page 200 CHAPTER 13 SERIAL INTERFACE (UART0) Table 13-3. Relationship between Main System Clock and Baud Rate (2/2) = 2.000 MHz = 1.000 MHz Baud Rate (bps) BRGC0 ERR (%) BRGC0 ERR (%) 0.16 0.16 1.36 1.36 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16...
  • Page 201 CHAPTER 13 SERIAL INTERFACE (UART0) (2) Communication operations (a) Data format Figure 13-6 shows the format of the transmit/receive data. Figure 13-6. Format of Transmit/Receive Data in Asynchronous Serial Interface 1 data frame Start Parity Stop bit Character bits 1 data frame consists of the following bits. •...
  • Page 202 CHAPTER 13 SERIAL INTERFACE (UART0) (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected.
  • Page 203 CHAPTER 13 SERIAL INTERFACE (UART0) (c) Transmission The transmit operation is started when transmit data is written to the transmit shift register (TXS0). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXS0, thereby emptying TXS0, after which a transmit completion interrupt request (INTST0) is issued.
  • Page 204 CHAPTER 13 SERIAL INTERFACE (UART0) (d) Reception The receive operation is enabled when “1” is set to bit 6 (RXE0) of the asynchronous serial interface mode register (ASIM0), and input via the RxD0 pin is sampled. The serial clock specified by ASIM0 is used to sample the RxD0 pin. When the RxD0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed.
  • Page 205 CHAPTER 13 SERIAL INTERFACE (UART0) (e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of data reception, an error flag is set to the asynchronous serial interface status register (ASIS0), a receive error interrupt request (INTSER0) will occur.

  • Page 206: Infrared Data Transfer Mode

    CHAPTER 13 SERIAL INTERFACE (UART0) 13.4.3 Infrared data transfer mode In infrared data transfer mode, the following data format pulse output and pulse receiving are enabled. The relationship between the main system clock and baud rate is shown in Table 13-3. (1) Data format Figure 13-10 compares the data format used in UART mode with that used in infrared data transfer mode.
  • Page 207 CHAPTER 13 SERIAL INTERFACE (UART0) (2) Bit rate and pulse width Table 13-5 lists bit rates, bit rate error tolerances, and pulse width values. Table 13-5. Bit Rate and Pulse Width Values 3/16 Pulse Width Bit Rate Bit Rate Error Tolerance Pulse Width Minimum Value Maximum Pulse Width <Nominal Value>...
  • Page 208 CHAPTER 13 SERIAL INTERFACE (UART0) (3) Input data and internal signals • Transmit operation timing UART Start bit Stop bit output data UART (Inverted data) Infrared data transfer enable signal TxD0 pin output signal • Receive operation timing Data reception is delayed for one-half of the specified baud rate. UART Start bit Stop bit...

  • Page 209: Chapter 14 Serial Interface (Sio1)

    CHAPTER 14 SERIAL INTERFACE (SIO1) 14.1 Serial Interface (SIO1) Functions The serial interface (SIO1) employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not carried out.

  • Page 210: Serial Interface (Sio1) Configuration

    CHAPTER 14 SERIAL INTERFACE (SIO1) 14.2 Serial Interface (SIO1) Configuration Serial interface (SIO1) consists of the following hardware. Table 14-1. Configuration of Serial Interface (SIO1) Item Configuration Register Serial I/O shift register 1 (SIO1) Automatic data transmit/receive address pointer (ADTP0) Control register Serial operating mode register 1 (CSIM1) Automatic data transmit/receive control register (ADTC0)
  • Page 211 CHAPTER 14 SERIAL INTERFACE (SIO1) Preliminary User’s Manual U13420EJ2V0UM00...
  • Page 212 CHAPTER 14 SERIAL INTERFACE (SIO1) (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When the value in bit 7 (CSIE10) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts the serial operation.

  • Page 213: Serial Interface (Sio1) Control Registers

    CHAPTER 14 SERIAL INTERFACE (SIO1) 14.3 Serial Interface (SIO1) Control Registers The following three types of registers are used to control serial interface (SIO1). • Serial operation mode register 1 (CSIM1) • Automatic data transmit/receive control register (ADTC0) • Automatic data transmit/receive interval specification register (ADTI0) (1) Serial operation mode register 1 (CSIM1) This register sets the serial interface (SIO1) serial clock, operation mode, operation enable/stop and automatic transmit/receive operation enable/stop.
  • Page 214 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-2. Format of Serial Operation Mode Register 1 (CSIM1) Address: FF68H After reset: 00H Symbol CSIM1 CSIE10 DIR10 ATE0 LCSK10 SCL101 SCL100 CSIE10 Enables/disables operation of serial interface (SIO1) Note 1 Shift register operation Serial counter Port Stops operation...
  • Page 215 CHAPTER 14 SERIAL INTERFACE (SIO1) (2) Automatic data transmit/receive control register (ADTC0) This register sets the automatic receive enable/disable, operating mode, strobe output enable/disable, busy input enable/disable and displays the automatic transmit/receive execution. ADTC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
  • Page 216 CHAPTER 14 SERIAL INTERFACE (SIO1) Notes 1. Bits 3 and 4 (TRF0 and ERR0) are read-only bits. 2. When BUSY10 is reset to 0, P81 (CMOS I/O) is used even when bit 7 (CSIE10) of the serial operating mode register 1 (CSIM1) is set to 1. 3.
  • Page 217 CHAPTER 14 SERIAL INTERFACE (SIO1) (3) Automatic data transmit/receive interval specification register (ADTI0) This register sets the automatic data transmit/receive function data transfer interval. ADTI0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure 14-4.
  • Page 218 CHAPTER 14 SERIAL INTERFACE (SIO1) Notes 1. The interval time is 2/ fSCK 2. The data transfer interval time is calculated from the following expressions (n: Value set to ADTI00 to ADTI04). <1> n = 0 Interval time = <2> n = 1 to 31 Interval time = Cautions 1.
  • Page 219 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-4. Format of Automatic Data Transmit/Receive Interval Specification Register (ADTI0) (2/2) Address: FF6BH After reset: 00H Symbol ADTI0 ADTI07 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 ADTI04 ADT0I3 ADTI02 ADTI01 ADTI00 Data transfer interval specification (f = 8.38 MHz, f = 1.05 MHz) Note...

  • Page 220: Serial Interface (Sio1) Operations

    CHAPTER 14 SERIAL INTERFACE (SIO1) 14.4 Serial Interface (SIO1) Operations The following three operating modes are available to the serial interface (SIO1). • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 14.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode.

  • Page 221: 3-Wire Serial I/O Mode

    CHAPTER 14 SERIAL INTERFACE (SIO1) 14.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface. Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1). (1) Register setting The 3-wire serial I/O mode is set with serial operating mode register 1 (CSIM1).
  • Page 222 CHAPTER 14 SERIAL INTERFACE (SIO1) SCL101 SCL100 Selects serial clock of serial interface (SIO1) Note 2 External clock input to SCK1 pin (1.05 MHz) (524 kHz) (262 kHz) Notes 1. When CSIE10 = 0 (SIO1 operation stop status), P84/SI1, P83/SO1, P82/SCK1, P81/BUSY, and P80/STB pins can be used as port pins.
  • Page 223 CHAPTER 14 SERIAL INTERFACE (SIO1) (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode has a function that enables it to select the transfer to start from either MSB or LSB. Figure 14-6 shows the configuration of the serial I/O shift register 1 (SIO1) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.

  • Page 224: 3-Wire Serial I/O Mode With Automatic Transmit/Receive Function

    CHAPTER 14 SERIAL INTERFACE (SIO1) 14.4.3 3-wire serial I/O mode with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and data can be received and stored in the RAM by the set number of bytes.
  • Page 225 CHAPTER 14 SERIAL INTERFACE (SIO1) Address: FF68H After reset: 00H Symbol CSIM1 CSIE10 DIR10 ATE0 LCSK10 SCL101 SCL100 CSIE10 Enables/disables operation of serial interface (SIO1) Note 1 Shift register operation Serial counter Port Stops operation Cleared Port function Enables operation Enables count operation Serial function + port function DIR10...
  • Page 226 CHAPTER 14 SERIAL INTERFACE (SIO1) (b) Automatic data transmit/receive control register (ADTC0) ADTC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC0 to 00H. Note 1 Address: FF69H After reset: 00H Symbol ADTC0 RE0 ARLD0 ERCE0 ERR0 TRF0 STRB0 BUSY10BUSY00 Busy input control BUSY10...
  • Page 227 CHAPTER 14 SERIAL INTERFACE (SIO1) Notes 1. Bits 3 and 4 (TRF0 and ERR0) are read-only bits. 2. When BUSY10 is reset to 0, P81 (CMOS I/O) is used even when bit 7 (CSIE10) of the serial operating mode register 1 (CSIM1) is set to 1. 3.
  • Page 228 CHAPTER 14 SERIAL INTERFACE (SIO1) (c) Automatic data transmit/receive interval specification register (ADTI0) This register sets the automatic data transmit/receive function data transfer interval. ADTI0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Address: FF6BH After reset: 00H Symbol ADTI0...
  • Page 229 CHAPTER 14 SERIAL INTERFACE (SIO1) Address: FF6BH After reset: 00H Symbol ADTI0 ADTI07 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 Data transfer interval specification (f = 8.38 MHz, f = 1.05 MHz) Note µ 16.2 s + 0.5/f µ...
  • Page 230 CHAPTER 14 SERIAL INTERFACE (SIO1) (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address. <2>...
  • Page 231 CHAPTER 14 SERIAL INTERFACE (SIO1) (3) Communication operation (a) Basic transmit/receive mode This transmit/receive mode is the same as the 3-wire serial I/O mode in which a specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE10) of the serial operating mode register 1 (CSIM1) is set to 1.
  • Page 232 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-8. Basic Transmit/Receive Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmit/receive operation interval time in ADTI0 Write any data to SIO1 (Start trigger)
  • Page 233 CHAPTER 14 SERIAL INTERFACE (SIO1) In 6-byte transmission/reception (bit 6 (ARLD0) and bit 7 (RE0) of the automatic data transmit/receive control register (ADTC0) = 0, and 1, respectively) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (refer to Figure 14-9 (a)) After any data has been written to SIO1 (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
  • Page 234 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-9. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception FADFH Receive data 1 (R1) FAC5H Receive data 4 (R4) SIO1 Receive data 2 (R2) Receive data 3 (R3) ADTP0 Transmit data 4 (T4) Transmit data 5 (T5)
  • Page 235 CHAPTER 14 SERIAL INTERFACE (SIO1) (b) Basic transmit mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE10) of the serial operating mode register 1 (CSIM1) is set to 1, and bit 7 (RE0) of the automatic data transmit/ receive control register (ADTC0) is set to 0.
  • Page 236 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-11. Basic Transmit Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmit/receive operation interval time in ADTI0 Write any data to SIO1 (Start trigger)
  • Page 237 CHAPTER 14 SERIAL INTERFACE (SIO1) In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of the automatic data transmit/receive control register (ADTC0) are 0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 14-12 (a)) After any data has been written to SIO1 (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
  • Page 238 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point FADFH FAC5H Transmit data 1 (T1) SIO1 Transmit data 2 (T2) Transmit data 3 (T3) ADTP0 Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6)
  • Page 239 CHAPTER 14 SERIAL INTERFACE (SIO1) (c) Repeat transmit mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE10) of the serial operating mode register 1 (CSIM1) is set to 1, and bit 7 (RE0) of the automatic data transmit/ receive control register (ADTC0) is set to 0.
  • Page 240 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-14. Repeat Transmit Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set the transmit/receive operation interval time in ADTI0 Write any data to SIO1 (Start trigger)
  • Page 241 CHAPTER 14 SERIAL INTERFACE (SIO1) In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of the automatic data transmit/receive control register (ADTC0) are 1 and 0, respectively) in repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 14-15 (a)) After any data has been written to SIO1 (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1.
  • Page 242 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes FADFH FAC5H Transmit data 1 (T1) SIO1 Transmit data 2 (T2) Transmit data 3 (T3) ADTP0 Transmit data 4 (T4) Transmit data 5 (T5)
  • Page 243 CHAPTER 14 SERIAL INTERFACE (SIO1) (d) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE10) of the serial operating mode register 1 (CSIM1) to 0. If, during 8-bit data transfer, the transmission/reception is not suspended, it is suspended upon completion of 8-bit data transfer.
  • Page 244 CHAPTER 14 SERIAL INTERFACE (SIO1) (4) Synchronization control Busy control and strobe control are functions to synchronize transmission/reception between the master device and a slave device. By using these functions, a shift in bits being transmitted or received can be detected. (a) Busy control option Busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active.
  • Page 245 CHAPTER 14 SERIAL INTERFACE (SIO1) When using the busy control option, select the internal clock as the serial clock. Control with the busy signal cannot be implemented with the external clock. Figure 14-18 shows the operation timing when the busy control option is used. Caution The busy control cannot be used simultaneously with the interval time control function of the automatic data transmit/receive interval specification register (ADTI0).
  • Page 246 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-19. Busy Signal and Wait Release (when BUSY00 = 0) SCK1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY 1.5 clock (min.)
  • Page 247 CHAPTER 14 SERIAL INTERFACE (SIO1) (c) Busy & strobe control option Usually, the busy control and strobe control options are simultaneously used as handshake signals. In this case, the strobe signal is output from the STB/P80 pin, and the BUSY/P81 pin is sampled, and transmission/reception can be kept waiting while the busy signal is input.
  • Page 248 CHAPTER 14 SERIAL INTERFACE (SIO1) Figure 14-21. Operation Timing When Busy & Strobe Control Options Are Used (when BUSY00 = 0) SCK1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY CSIIF1...
  • Page 249 CHAPTER 14 SERIAL INTERFACE (SIO1) (d) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte.
  • Page 250 CHAPTER 14 SERIAL INTERFACE (SIO1) (5) Timing of interrupt request signal generation The interrupt request signal is generated in synchronization with the timing shown in Table 14-2. Table 14-2. Timing of Interrupt Request Signal Generation Operating Mode Timing of Interrupt Request Signal Single mode Master mode 10th serial clock at end of transfer...

  • Page 251: Chapter 15 Serial Interface (Sio30)

    CHAPTER 15 SERIAL INTERFACE (SIO30) 15.1 Serial Interface (SIO30) Functions The serial interface (SIO30) has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 15.4.1 Operation stop mode. (2) 2-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using two lines: a serial clock line (SCK30) and serial data input/output line (SDIO30).

  • Page 252: Serial Interface (Sio30) Configuration

    CHAPTER 15 SERIAL INTERFACE (SIO30) 15.2 Serial Interface (SIO30) Configuration The serial interface (SIO30) includes the following hardware. Table 15-1. Serial Interface (SIO30) Configuration Item Configuration Registers Serial I/O shift register 30 (SIO30) Control registers Serial operation mode register 30 (CSIM30) (1) Serial I/O shift register 30 (SIO30) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock.

  • Page 253: Register To Control Serial Interface (Sio30)

    CHAPTER 15 SERIAL INTERFACE (SIO30) 15.3 Register to Control Serial Interface (SIO30) The serial interface (SIO30) uses the following type of register to control functions. • Serial operation mode register 30 (CSIM30) (1) Serial operation mode register 30 (CSIM30) This register is used to enable or disable SIO30’s serial clock, operation modes, and specific operations. CSIM30 can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 254: Serial Interface (Sio30) Operations

    CHAPTER 15 SERIAL INTERFACE (SIO30) Note When CSIE30 = 0 (SIO30 operation stop status), pins SDIO30 and SCK30 can be used as port functions. Remarks 1. f : main system clock oscillation frequency 2. Figures in parentheses are for operation with f = 8.38 MHz.

  • Page 255: 2-Wire Serial I/O Mode

    CHAPTER 15 SERIAL INTERFACE (SIO30) 15.4.2 2-wire serial I/O mode The 2-wire serial I/O mode is useful for connection to a peripheral I/O incorporating a clock-synchronous serial interface, a display controller, etc. This mode executes data transfers via two lines: a serial clock line (SCK30) and serial data input/output line (SDIO30).
  • Page 256 CHAPTER 15 SERIAL INTERFACE (SIO30) (2) Communication operations In 2-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is sent or received in synchronization with the serial clock. Serial I/O shift register 30 (SIO30) is shifted in synchronization with the falling edge of the serial clock. Transmission data is held in the SDIO30 latch and is output from the SDIO30 pin.

  • Page 257: Chapter 16 Serial Interface (Sio31)

    CHAPTER 16 SERIAL INTERFACE (SIO31) 16.1 Serial Interface (SIO31) Functions The serial interface (SIO31) has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 16.4.1 Operation stop mode. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK31), serial output line (SO31), and serial input line (SI31).

  • Page 258: Serial Interface (Sio31) Configuration

    CHAPTER 16 SERIAL INTERFACE (SIO31) 16.2 Serial Interface (SIO31) Configuration The serial interface (SIO31) includes the following hardware. Table 16-1. Serial Interface (SIO31) Configuration Item Configuration Registers Serial I/O shift register 31 (SIO31) Control registers Serial operation mode register 31 (CSIM31) (1) Serial I/O shift register 31 (SIO31) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock.

  • Page 259: Register To Control Serial Interface (Sio31)

    CHAPTER 16 SERIAL INTERFACE (SIO31) 16.3 Register to Control Serial Interface (SIO31) The serial interface (SIO31) uses the following type of register to control functions. • Serial operation mode register 31 (CSIM31) (1) Serial operation mode register 31 (CSIM31) This register is used to enable or disable SIO31’s serial clock, operation modes, and specific operations. CSIM31 can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 260: Serial Interface (Sio31) Operations

    CHAPTER 16 SERIAL INTERFACE (SIO31) Notes 1. When CSIE31 = 0 (SIO31 operation stop status), the pins SI31, SO31, and SCK31 can be used for port functions. 2. When CSIE31 = 1 (SIO31 operation enabled state), the SI31 pin can be used as a port pin if only the send function is used, and the SO31 pin can be used as a port pin if only the receive-only mode is used.

  • Page 261: 3-Wire Serial I/O Mode

    CHAPTER 16 SERIAL INTERFACE (SIO31) 16.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection to a peripheral I/O incorporating a clock-synchronous serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK31), serial output line (SO31), and serial input line (SI31).
  • Page 262 CHAPTER 16 SERIAL INTERFACE (SIO31) Notes 1. When CSIE31 = 0 (SIO31 operation stop status), the pins SI31, SO31, and SCK31 can be used for port functions. 2. When CSIE31 = 1 (SIO31 operation enabled state), the SI31 pin can be used as a port pin if only the send function is used, and the SO31 pin can be used as a port pin if only the receive-only mode is used.

  • Page 263: Chapter 17 Interrupt Functions

    CHAPTER 17 INTERRUPT FUNCTIONS 17.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo priority control and is given top priority over all other interrupt requests. It generates a standby release signal.
  • Page 264 CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List Vector Basic Interrupt Source Interrupt Default Internal/ Table Configuration Note 1 Type Priority External Name Trigger Note 2 Address Type Non- — INTWDT Watchdog timer overflow Internal 0004H maskable (with watchdog timer mode 1 selected) Maskable INTWDT Watchdog timer overflow...
  • Page 265 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal Bus Interrupt Priority Control Vector Table request Circuit Address Generator Standby release signal (B) Internal maskable interrupt Internal Bus Priority Control Vector Table Interrupt Circuit Address Generator...
  • Page 266 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1. Basic Configuration of Interrupt Function (2/2) (D) Software interrupt Internal Bus Interrupt Priority Control Vector Table request Circuit Address Generator Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 267: Interrupt Function Control Registers

    CHAPTER 17 INTERRUPT FUNCTIONS 17.3 Interrupt Function Control Registers The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) •...
  • Page 268 CHAPTER 17 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
  • Page 269 CHAPTER 17 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register, they are set with a 16-bit memory manipulation instruction.
  • Page 270 CHAPTER 17 INTERRUPT FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag registers are used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
  • Page 271 CHAPTER 17 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), External interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP3. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H.
  • Page 272 CHAPTER 17 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for an interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple processing are mapped.

  • Page 273: Interrupt Servicing Operations

    CHAPTER 17 INTERRUPT FUNCTIONS 17.4 Interrupt Servicing Operations 17.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag and ISP flag are reset (0), and the contents of the vector table are loaded into PC and branched.
  • Page 274 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-7. Non-Maskable Interrupt Request Generation to Acknowledge Flowchart Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending Interrupt...
  • Page 275 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-9. Non-Maskable Interrupt Request Acknowledge Operation (a) If a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main routine Execution of NMI request <1> NMI request <1> NMI request <2> held pending NMI request <2>...

  • Page 276: Maskable Interrupt Acknowledge Operation

    CHAPTER 17 INTERRUPT FUNCTIONS 17.4.2 Maskable interrupt acknowledge operation A maskable interrupt becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if in the interrupt enable state (when IE flag is set to 1).
  • Page 277 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Interrupt Request Acknowledge Processing Algorithm Start ××IF = 1? Yes (Interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?

  • Page 278: Software Interrupt Request Acknowledge Operation

    CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-11. Interrupt Request Acknowledge Timing (Minimum Time) 6 clocks PSW and PC Save, Interrupt servicing CPU processing Instruction Instruction Jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 17-12.

  • Page 279: Multiple Interrupt Servicing

    CHAPTER 17 INTERRUPT FUNCTIONS 17.4.4 Multiple interrupt servicing Multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except non-maskable interrupts).
  • Page 280 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-13. Multiple Interrupt Examples (1/2) Example 1. Multiple interrupts occur twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI RETI...
  • Page 281 CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-13. Multiple Interrupt Examples (2/2) Example 3. Multiple interrupt servicing does not occur because interrupt is not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 0 1 instruction execution RETI...

  • Page 282: Interrupt Request Hold

    CHAPTER 17 INTERRUPT FUNCTIONS 17.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.

  • Page 283: Chapter 18 External Device Expansion Function

    CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION 18.1 External Device Expansion Function The external device expansion function connects external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe, etc.
  • Page 284 CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION The memory maps when using the external device expansion function are as follows. Figure 18-1. Memory Map When Using External Device Function (a) Memory map of µ PD780065 and µ PD78F0066 when (b) Memory map of µ PD78F0066 internal ROM (flash memory) size is 40 Kbytes FFFFH FFFFH...

  • Page 285: External Device Expansion Function Control Register

    CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION 18.2 External Device Expansion Function Control Register The external device expansion function is controlled by the following two types of registers. • Memory expansion mode register (MEM) • Memory expansion wait setting register (MM) (1) Memory expansion mode register (MEM) MEM sets the external expansion area.
  • Page 286 CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION (2) Memory expansion wait setting register (MM) MM sets the number of waits. MM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 18-3. Format of Memory Expansion Wait Setting Register (MM) Address: FFF8H After reset: 10H R/W Symbol Wait control...

  • Page 287: External Device Expansion Function Timing

    CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION 18.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe output pin. The read strobe output pin is output in data accesses and instruction fetches from external memory.
  • Page 288 CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION Figure 18-4. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting ASTB Lower address Instruction code AD0 to AD7 A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB Lower address Instruction code...
  • Page 289 CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION Figure 18-5. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Lower address Read data AD0 to AD7 A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB AD0 to AD7 Lower address...
  • Page 290 CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION Figure 18-6. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z Lower address Write data AD0 to AD7 A8 to A15 Higher address (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Lower...
  • Page 291 CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION Figure 18-7. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z Lower AD0 to AD7 Read data Write data address Higher address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Lower...

  • Page 292: Example Of Connection With Memory

    CHAPTER 18 EXTERNAL DEVICE EXPANSION FUNCTION 18.4 Example of Connection with Memory This section provide an example of connecting the µ PD780065 with external memory (in this example, SRAM) in Figure 18-8. In addition, the external device expansion function is used in the full-address mode, and the addresses from 0000H to 9FFFH (40 Kbytes) are allocated for internal ROM, and the addresses after A000H from SRAM.

  • Page 293: Chapter 19 Standby Function

    CHAPTER 19 STANDBY FUNCTION 19.1 Standby Function and Configuration 19.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode Halt instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. The system clock oscillator continues oscillating.

  • Page 294: Standby Function Control Register

    CHAPTER 19 STANDBY FUNCTION 19.1.2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (OSTS). OSTS is set by an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.

  • Page 295: Standby Function Operations

    CHAPTER 19 STANDBY FUNCTION 19.2 Standby Function Operations 19.2.1 HALT mode (1) HALT mode setting and operating statuses The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating statuses in the HALT mode are described below.
  • Page 296 CHAPTER 19 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is cleared. If interrupt acknowledge is enabled, vectored interrupt service is carried out.
  • Page 297 CHAPTER 19 STANDBY FUNCTION (c) Clear upon RESET input When RESET signal is input, HALT mode is released. And, as in the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 19-3. HALT Mode Release by RESET Input Wait HALT instruction : 15.6 ms)

  • Page 298: Stop Mode

    CHAPTER 19 STANDBY FUNCTION 19.2.2 STOP mode (1) STOP mode setting and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull-up resistor to minimize the leakage current at the crystal oscillator.
  • Page 299 CHAPTER 19 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
  • Page 300 CHAPTER 19 STANDBY FUNCTION (b) Release by RESET input The STOP mode is cleared when RESET signal is input, and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 19-5. STOP Mode Release by RESET Input Wait STOP instruction : 15.6 ms)

  • Page 301: Chapter 20 Reset Function

    CHAPTER 20 RESET FUNCTION 20.1 Reset Function The following two operations are available to generate the reset function. (1) External reset input via RESET pin (2) Internal reset by watchdog timer runaway time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
  • Page 302 CHAPTER 20 RESET FUNCTION Figure 20-2. Timing of Reset by RESET Input Oscillation Normal operation Reset period Normal operation stabilization (Reset processing) (Oscillation stop) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 20-3. Timing of Reset due to Watchdog Timer Overflow Oscillation Normal operation Reset period...
  • Page 303 CHAPTER 20 RESET FUNCTION Table 20-1. Hardware Statuses after Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General register...
  • Page 304 CHAPTER 20 RESET FUNCTION Table 20-1. Hardware Statuses after Reset (2/2) Hardware Status After Reset Clock output controller Clock output selection register (CKS) A/D converter Conversion result registers (ADCR0) Mode register (ADM0) Analog input channel specification register (ADS0) Serial interface (UART0) Asynchronous serial interface mode register (ASIM0) Asynchronous serial interface status register (ASIS0) Baud rate generator control register (BRGC0)

  • Page 305: Chapter 21 Μ Pd78F0066

    CHAPTER 21 µ PD78F0066 The µ PD78F0066 is provided as the flash memory version of the µ PD780065 Subseries. The µ PD78F0066 replaces the internal mask ROM of the µ PD780065 with flash memory to which a program can be written, deleted and overwritten while mounted on the substrate. Table 21-1 lists the differences between the µ...

  • Page 306: Memory Size Switching Register

    CHAPTER 21 µ PD78F0066 21.1 Memory Size Switching Register The µ PD78F0066 allows users to select the internal memory capacity using the memory size switching register (IMS) so that the same memory map as that of the µ PD780065 with a different size of internal memory capacity can be achieved.

  • Page 307: Internal Expansion Ram Size Switching Register

    CHAPTER 21 µ PD78F0066 21.2 Internal Expansion RAM Size Switching Register The internal expansion RAM size switching register (IXS) is a register used to set internal expansion RAM capacity. IXS is set by using 8-bit memory manipulation instruction. RESET input sets IXS to 0CH. Caution Set IXS to 04H as the initial value of the program.

  • Page 308: Flash Memory Programming

    CHAPTER 21 µ PD78F0066 21.3 Flash Memory Programming On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done after connecting a dedicated flash programmer (Flashpro II (type FL-PR2), Flashpro III (type FL-PR3, PG-FP3)) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro II or Flashpro III.

  • Page 309: Flash Memory Programming Function

    CHAPTER 21 µ PD78F0066 21.3.2 Flash memory programming function Flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. The main functions are listed in Table 21-3. Table 21-3. Main Functions of Flash Memory Programming Function Description Reset...
  • Page 310 CHAPTER 21 µ PD78F0066 Figure 21-5. Connection of Flashpro II or Flashpro III Using UART Method µ Flashpro II or Flashpro III PD78F0066 RESET RESET RxD0 TxD0 Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 311: Chapter 22 Instruction Set

    CHAPTER 22 INSTRUCTION SET This chapter lists each instruction set of the µ PD780065 Subseries in table form. For details of its operation and operation code, refer to the separate document 78K/0 Series User’s Manual—Instructions (U12326E). Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 312: Symbols Used In Operation List

    CHAPTER 22 INSTRUCTION SET 22.1 Symbols Used in Operation List 22.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.

  • Page 313: Description Of "Operation" Column

    CHAPTER 22 INSTRUCTION SET 22.1.2 Description of “operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...

  • Page 314: Operation List

    CHAPTER 22 INSTRUCTION SET 22.2 Operation List Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 r ← byte 8-bit data r, #byte – transfer (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte –...
  • Page 315 CHAPTER 22 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 rp ← word 16-bit MOVW rp, #word – data (saddrp) ← word saddrp, #word transfer sfrp ← word sfrp, #word – AX ←...
  • Page 316 CHAPTER 22 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A, CY ← A – byte × × × 8-bit A, #byte – operation (saddr), CY ← (saddr) – byte × ×...
  • Page 317 CHAPTER 22 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 A ← A ∨ byte × 8-bit A, #byte – operation (saddr) ← (saddr) ∨ byte × saddr, #byte A ← A ∨ r ×...
  • Page 318 CHAPTER 22 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 AX, CY ← AX + word × × × 16-bit ADDW AX, #word – operation AX, CY ← AX – word ×...
  • Page 319 CHAPTER 22 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ (saddr.bit) × AND1 CY, saddr.bit manipulate CY ← CY ∧ sfr.bit × CY, sfr.bit – CY ← CY ∧ A.bit ×...
  • Page 320 CHAPTER 22 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) Call/return CALL !addr16 – PC ← addr16, SP ← SP – 2 (SP –...
  • Page 321 CHAPTER 22 INSTRUCTION SET Clock Flag Instruction Mnemonic Operands Byte Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 Conditional saddr.bit, $addr16 branch PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...

  • Page 322: Instructions Listed By Addressing Type

    CHAPTER 22 INSTRUCTION SET 22.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Preliminary User’s Manual U13420EJ2V0UM00...
  • Page 323 CHAPTER 22 INSTRUCTION SET Second Operand [HL + byte] Note #byte saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 None First Operand [HL + C] ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC SUBC SUBC ADDC SUBC B, C...
  • Page 324 CHAPTER 22 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand Note #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
  • Page 325 CHAPTER 22 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U13420EJ2V0UM00...
  • Page 326 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 327: Appendix A Development Tools

    APPENDIX A DEVELOPMENT TOOLS The following shows development tools necessary for the development of systems that employ the µ PD780065 Subseries. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT™ and compatibles can be used for the PC98- NX series.
  • Page 328 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) (1) When using the in-circuit emulator IE-78K0-NS Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tool • System simulator •...
  • Page 329 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using the in-circuit emulator IE-78001-R-A Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tool • System simulator •...

  • Page 330: Language Processing Software

    APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K/0 This assembler converts programs written in mnemonics into an object codes executable Assembler Package with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with an optical device file (DF780066).

  • Page 331: Flash Memory Writing Tools

    APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 µ S××××DF780066 µ S××××CC78K0-L ×××× Host Machine Supply Medium Note AA13 PC-9800 series Windows (Japanese version) 3.5-inch 2HD FD Note AB13 IBM PC/AT...

  • Page 332: Debugging Tools

    APPENDIX A DEVELOPMENT TOOLS A.3 Debugging Tools A.3.1 Hardware (1/2) (1) When using the in-circuit emulator IE-78K0-NS IE-78K0-NS The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K/0 Series product. It corresponds to integrated debugger (ID78K0-NS).
  • Page 333 APPENDIX A DEVELOPMENT TOOLS A.3.1 Hardware (2/2) (2) When using the in-circuit emulator IE-78001-R-A IE-78001-R-A The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K/0 Series product. It corresponds to integrated debugger (ID78K0).

  • Page 334: Software

    APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (1/2) SM78K0 This system simulator is used to perform debugging at C source level or assembler System Simulator level while simulating the operation of the target system on a host machine. This simulator runs on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency...
  • Page 335 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (2/2) ID78K0-NS This debugger is a control program to debug 78K/0 Series microcontrollers. Integrated Debugger It adopts a graphical user interface, which is equivalent visually and operationally to (supporting in-circuit emulator Windows or OSF/Motif™. It also has an enhanced debugging function for C language IE-78K0-NS) programs, and thus trace results can be displayed on screen in C-language level by using the windows integration function which links a trace result with its source program,...

  • Page 336: System Upgrade From Former In-Circuit Emulator For 78K/0 Series To Ie-78001-R-A

    Table A-1. System-up Method from Former In-circuit Emulator for 78K/0 Series to the IE-78001-R-A Note In-circuit Emulator Owned In-circuit Emulator Cabinet System-up Board to be Purchased IE-78000-R Required IE-78001-R-BK IE-78000-R-A Not required Note For system-up of a cabinet, send your in-circuit emulator to NEC. Preliminary User’s Manual U13420EJ2V0UM00...
  • Page 337 APPENDIX A DEVELOPMENT TOOLS Conversion Socket Drawing (EV-9200GC-80) and Footprints Figure A-2. EV-9200GC-80 Drawing (for reference only) Based on EV-9200GC-80 (1) Package drawing (in mm) EV-9200GC-80 No.1 pin index EV-9200GC-80-G1E ITEM MILLIMETERS INCHES 18.0 0.709 14.4 0.567 14.4 0.567 18.0 0.709 4-C 2.0 4-C 0.079...
  • Page 338 APPENDIX A DEVELOPMENT TOOLS Figure A-3. EV-9200GC-80 Footprints (for reference only) Based on EV-9200GC-80 (2) Pad drawing (in mm) EV-9200GC-80-P1E ITEM MILLIMETERS INCHES 19.7 0.776 15.0 0.591 0.65 ± 0.02 × 19=12.35 ± 0.05 × 0.748=0.486 +0.001 +0.003 0.026 –0.002 –0.002 0.65 ±...

  • Page 339: Appendix B Embedded Software

    APPENDIX B EMBEDDED SOFTWARE For efficient development and maintenance of the µ PD780065 Subseries, the following embedded products are available. Preliminary User’s Manual U13420EJ2V0UM00...
  • Page 340 APPENDIX B EMBEDDED SOFTWARE Real-Time OS (1/2) RX 78K/0 is a real-time OS conforming to the µ ITRON specifications. RX78K/0 Real-time OS Tool (configurator) for generating nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78/0) and device file (DF780066).
  • Page 341 APPENDIX B EMBEDDED SOFTWARE Real-Time OS (2/2) MX78K/0 is an OS for µ ITRON specification subsets. A nucleus for the MX78K/0 is MX78K0 OS also included as a companion product. This manages tasks, events, and time. In the task management, determining the task execution order and switching from task to the next task are performed.
  • Page 342 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...

  • Page 343: Appendix C Register Index

    APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register (ADCR0) … 174 A/D converter mode register (ADM0) … 176 Analog input channel specification register (ADS0) … 177 Asynchronous serial interface mode register (ASIM0) … 189, 194 Asynchronous serial interface status register (ASIS0) …...
  • Page 344 APPENDIX C REGISTER INDEX Port 0 (P0) … 73 Port 2 (P2) … 75 Port 3 (P3) … 76 Port 4 (P4) … 77 Port 5 (P5) … 78 Port 6 (P6) … 79 Port 7 (P7) … 80 Port 8 (P8) … 82 Port 9 (P9) …...
  • Page 345 APPENDIX C REGISTER INDEX 16-bit timer/counter 0 (TM0) … 106 16-bit timer mode control register 0 (TMC0) … 108 16-bit timer output control register 0 (TOC0) … 111 Timer clock select register 50 (TCL50) … 138 Timer clock select register 51 (TCL51) … 139 Transmit shift register (TXS0) …...

  • Page 346: Register Index (In Alphabetical Order With Respect To Register Symbol)

    APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR0: A/D conversion result register … 174 ADM0: A/D converter mode register … 176 ADS0: Analog input channel specification register … 177 ADTC0: Automatic data transmit/receive control register … 215, 226 ADTI0: Automatic data transmit/receive interval specification register …...
  • Page 347 APPENDIX C REGISTER INDEX Port 0 … 73 Port 2 … 75 Port 3 … 76 Port 4 … 77 Port 5 … 78 Port 6 … 79 Port 7 … 80 Port 8 … 82 Port 9 … 83 PCC: Processor clock control register …...
  • Page 348 APPENDIX C REGISTER INDEX TCL50: Timer clock select register 50 … 138 TCL51: Timer clock select register 51 … 139 TM0: 16-bit timer/counter 0 … 106 TM50: 8-bit counter 50 … 137 TM51: 8-bit counter 51 … 137 TMC0: 16-bit timer mode control register 0 … 108 TMC50: 8-bit timer mode control register 50 …...

  • Page 349: Appendix D Revision History

    APPENDIX D REVISION HISTORY The following shows major revisions up to now. Edition Major Revisions from Previous Edition Revised Chapters Modification of description of on-chip pull-up resistor specification CHAPTER 2 PIN FUNCTION Modification of description of TI00 pin Addition of input/output circuit type of each pin and pin input/output circuit figures Modification of caution on register initial setting for memory space CHAPTER 3 CPU ARCHITECTURE...
  • Page 350 [MEMO] Preliminary User’s Manual U13420EJ2V0UM00...
  • Page 351 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

This manual is also suitable for:

Mpd780065Mpd78f0066

Table of Contents