NEC mPD789426 Series User Manual

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User's Manual

µ µ µ µ PD789426, 789436, 789446

789456 Subseries

8-Bit Single-Chip Microcontrollers

µ µ µ µ PD789425

µ µ µ µ PD789426

µ µ µ µ PD789435

µ µ µ µ PD789436

µ µ µ µ PD78F9436

Document No. U15075EJ1V0UM00 (1st edition)

Date Published November 2000 N CP(K)

1999

2000

Printed in Japan

µ µ µ µ PD789445

µ µ µ µ PD789446

µ µ µ µ PD789455

µ µ µ µ PD789456

µ µ µ µ PD78F9456

Table of Contents

Summary of Contents for NEC mPD789426 Series

Page 1 User’s Manual µ µ µ µ PD789426, 789436, 789446 789456 Subseries 8-Bit Single-Chip Microcontrollers µ µ µ µ PD789425 µ µ µ µ PD789445 µ µ µ µ PD789426 µ µ µ µ PD789446 µ µ µ µ PD789435 µ µ µ µ PD789455 µ...
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Page 3 Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
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Page 7 INTRODUCTION Target Readers This manual is intended to give user engineers an understanding of the functions of the µ PD789426, 789436, 789446, and 789456 Subseries to design and develop its application systems and programs. Target products: • µ PD789426 Subseries: µ...
Page 8 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ...
Page 9 English SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
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Page 11: Table Of Contents
CONTENTS CHAPTER 1 GENERAL ...........................25 Features............................25 Applications ..........................25 Ordering Information .........................26 Pin Configuration (Top View) ....................27 Pin configuration of µ PD789426, 789436 Subseries (Top View) ..........27 1.4.1 Pin configuration of µ PD789446, 789456 Subseries (Top View) ..........28 1.4.2 78K/0S Series Lineup .........................30 Block Diagram ..........................32 Block diagram of µ...
Page 12 3.1.2 Internal data memory (internal high-speed RAM) space .............. 54 3.1.3 Special function register (SFR) area..................... 54 3.1.4 Data memory addressing......................55 Processor Registers........................61 3.2.1 Control registers ........................... 61 3.2.2 General-purpose registers ......................64 3.2.3 Special function registers (SFRs) ....................65 Instruction Address Addressing....................
Page 13 5.4.2 Subsystem clock oscillator ......................109 5.4.3 Divider circuit ..........................111 5.4.4 When no subsystem clock is used ..................... 111 Clock Generator Operation .....................112 Changing Setting of System Clock and CPU Clock..............113 5.6.1 Time required for switching between system clock and CPU clock ........... 113 5.6.2 Switching between system clock and CPU clock ...............
Page 14 Watchdog Timer Operation ....................181 9.4.1 Operation as watchdog timer...................... 181 9.4.2 Operation as interval timer......................182 CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES)......183 10.1 8-Bit A/D Converter Functions ....................183 10.2 8-Bit A/D Converter Configuration..................183 10.3 8-Bit A/D Converter Control Registers ..................
Page 15 CHAPTER 14 INTERRUPT FUNCTIONS.....................263 14.1 Interrupt Function Types ......................263 14.2 Interrupt Sources and Configuration ..................263 14.3 Registers Controlling Interrupt Function................266 14.4 Interrupt Servicing Operation ....................272 14.4.1 Non-maskable interrupt request acknowledgment operation ............. 272 14.4.2 Maskable interrupt request acknowledgment operation ............. 274 14.4.3 Multiple interrupt servicing......................
Page 16 APPENDIX B EMBEDDED SOFTWARE ..................... 315 APPENDIX C REGISTER INDEX......................317 Register Index (Alphabetic Order of Register Name) ............317 Register Index (Alphabetic Order of Register Symbol) ............319 User’s Manual U15075EJ1V0UM00...
Page 17 LIST OF FIGURES (1/5) Figure No. Title Page Pin Input/Output Circuits ..........................45 Memory Map ( µ PD789425, 789435) ......................47 Memory Map ( µ PD789426, 789436) ......................48 Memory Map ( µ PD78F9436)......................... 49 Memory Map ( µ PD789445, 789455) ......................50 Memory Map ( µ...
Page 18 LIST OF FIGURES (2/5) Figure No. Title Page 4-22 Format of Pull-Up Resistor Option Register B7................... 100 4-23 Format of Pull-Up Resistor Option Register B8................... 100 4-24 Format of Pull-Up Resistor Option Register B9................... 101 Block Diagram of Clock Generator ......................104 Format of Processor Clock Control Register ....................
Page 19 LIST OF FIGURES (3/5) Figure No. Title Page 7-16 Timing of Interval Timer Operation with 16-Bit Resolution ................155 7-17 Timing of External Event Counter Operation with 16-Bit Resolution............157 7-18 Timing of Square-Wave Output with 16-Bit Resolution ................159 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M >...
Page 20 LIST OF FIGURES (4/5) Figure No. Title Page 11-5 Relationship Between Analog Input Voltage and A/D Conversion Result ........... 204 11-6 Software-Started A/D Conversion ....................... 205 11-7 How to Reduce Current Consumption in Standby Mode................206 11-8 Conversion Result Read Timing (If Conversion Result Is Undefined)............207 11-9 Conversion Result Read Timing (If Conversion Result Is Normal)..............
Page 21 LIST OF FIGURES (5/5) Figure No. Title Page 14-7 Format of Key Return Mode Register 00..................... 271 14-8 Block Diagram of Falling Edge Detector ..................... 271 14-9 Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment......... 273 14-10 Timing of Non-Maskable Interrupt Request Acknowledgment ..............273 14-11 Non-Maskable Interrupt Request Acknowledgment ..................
Page 22 LIST OF TABLES (1/2) Table No. Title Page Types of Pin Input/Output Circuits......................... 44 Internal ROM Capacity ..........................53 Vector Table ..............................53 LCD Display RAM Capacity........................... 54 Special Function Register List........................66 Port Functions ............................... 79 Configuration of Port ............................. 80 Port Mode Register and Output Latch Settings When Using Alternate Functions ........
Page 23 LIST OF TABLES (2/2) Table No. Title Page 12-1 Configuration of Serial Interface 20......................211 12-2 Serial Interface 20 Operating Mode Settings ....................217 12-3 Example of Relationships Between System Clock and Baud Rate............. 220 12-4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H)..221 12-5 Example of Relationships Between System Clock and Baud Rate.............
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Page 25: Chapter 1 General
CHAPTER 1 GENERAL 1.1 Features • ROM and RAM capacities Item Program Memory Data Memory (ROM) Internal High-Speed LCD Display RAM Part Number µ PD789425, 789435 Mask ROM 8 KB 512 bytes 5 bytes µ PD789426, 789436 16 KB µ PD78F9436 Flash memory 16 KB µ...
Page 26: Ordering Information
CHAPTER 1 GENERAL 1.3 Ordering Information Part Number Package Internal ROM µ PD789425GK-×××-9ET 64-pin plastic TQFP (12 × 12 mm) Mask ROM µ PD789426GK-×××-9ET 64-pin plastic TQFP (12 × 12 mm) Mask ROM µ PD789435GK-×××-9ET 64-pin plastic TQFP (12 × 12 mm) Mask ROM µ...
Page 27: Pin Configuration (Top View)
CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) 1.4.1 Pin configuration of µ µ µ µ PD789426, 789436 Subseries (Top view) 64-pin plastic TQFP (fine pitch) (12 × 12) µ PD789425GK-×××-9ET µ PD789426GK-×××-9ET µ PD789435GK-×××-9ET µ PD789436GK-×××-9ET µ PD78F9436GK-9ET 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P62/ANI2 P63/ANI3 P64/ANI4...
Page 28 CHAPTER 1 GENERAL 1.4.2 Pin configuration of µ µ µ µ PD789446, 789456 Subseries (Top view) 64-pin plastic TQFP (fine pitch) (12 × 12) µ PD789445GK-×××-9ET µ PD789446GK-×××-9ET µ PD789455GK-×××-9ET µ PD789456GK-×××-9ET µ PD78F9456GK-9ET 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P62/ANI2 P63/ANI3 P64/ANI4...
Page 29 CHAPTER 1 GENERAL Note 1 ANI0 to ANI5: Analog input P90 to P97 Port 9 ASCK20: Asynchronous serial input RESET: Reset Analog power supply RxD20: Receive data Analog ground SS20: Serial chip select Note 2 BZO90: Buzzer output S0 to S4, S5 to S14 : Segment output CAPH, CAPL: LCD power supply capacitance control...
Page 30: 0S Series Lineup
CHAPTER 1 GENERAL 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications µ...
Page 31 CHAPTER 1 GENERAL The major functional differences among the subseries are listed below. Function 8-Bit 10-Bit Serial 8-Bit 16-Bit Watch I/O MIN. Remarks Capacity Interface Value Subseries Name µ PD789046 − − − Small-scale 16 K 1 ch 1 ch 1 ch 1 ch 1 ch (UART:...
Page 32: Block Diagram
CHAPTER 1 GENERAL 1.6 Block Diagram 1.6.1 Block diagram of µ µ µ µ PD789426, 789436 Subseries TO50/TMI60/ 8-bit Port 0 P00 to P03 Cascaded 16-bit timer 50 timer/ TO60/P32 8-bit event Port 1 P10, P11 TO61/P33 timer/event counter counter 60 TMI60/TO50/ Port 2 P20 to P26...
Page 33: Block Diagram Of Μ Pd789446, 789456 Subseries
CHAPTER 1 GENERAL 1.6.2 Block diagram of µ µ µ µ PD789446, 789456 Subseries TO50/TMI60/ 8-bit Port 0 P00 to P03 Cascaded 16-bit timer 50 timer/ TO60/P32 8-bit event Port 1 P10, P11 TO61/P33 timer/event counter counter 60 TMI60/TO50/ Port 2 P20 to P26 TO90/P26 CPT90/P30...
Page 34: Overview Of Functions
CHAPTER 1 GENERAL 1.7 Overview of Functions µ PD789425, µ PD789426, µ PD78F9436 µ PD789445, µ PD789446, µ PD78F9456 Item 789435 789436 789455 789456 Internal memory Mask ROM Flash Mask ROM Flash memory memory 12 KB 16 KB 12 KB 16 KB High-speed RAM 512 bytes...
Page 35 CHAPTER 1 GENERAL An outline of the timer is shown below. 16-Bit 8–Bit 8-Bit Watch Timer Watchdog Timer Timer 50 Timer 60 Timer Note 1 Note 2 Operation Interval timer – 1 channel 1 channel 1 channel 1 channel mode External event –...
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Page 37: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions Port pins (1/2) Pin Name Function After Reset Alternate Function P00 to P03 Port 0. Input KR0 to KR3 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00).
Page 38 CHAPTER 2 PIN FUNCTIONS Port pins (2/2) Pin Name Function After Reset Alternate Function − Note P80, P81 Port 8. Input 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B8 (PUB8).
Page 39 CHAPTER 2 PIN FUNCTIONS Non-port pins Pin Name Function After Reset Alternate Function INTP0 Input Input P30/CPT90 External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified INTP1 P31/TO50/TMI60 INTP2 P32/TO60 INTP3...
Page 40: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port. In addition, these pins enable key return signal detection. Port 0 can be specified in the following operation modes in 1-bit units. Port mode These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode register 0 (PM0).
Page 41: P30 To P33 (Port 3)
CHAPTER 2 PIN FUNCTIONS ASCK20 This is the serial clock input pin of the asynchronous serial interface. Caution When using P20 to P26 as serial interface pins, the I/O mode and output latch must be set according to the functions to be used. For the details of the setting, refer to Table 12-2 Settings of Serial Interface 20 Operating Mode.
Page 42: P70 To P72 (Port 7)
CHAPTER 2 PIN FUNCTIONS 2.2.7 P70 to P72 (Port 7) These pins constitute a 3-bit I/O port. Port 7 can be set in the input or output mode in 1-bit units by port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register B7 (PUB7) in port units.
Page 43: Vdd
CHAPTER 2 PIN FUNCTIONS 2.2.17 V This is the positive power supply pin. 2.2.18 V This is the ground pin. ( µ µ µ µ PD78F9436, 78F9456 only) 2.2.19 V A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified.
Page 44: Pin Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, see Figure 2-1. Table 2-1.
Page 45 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin Input/Output Circuits Type 2 Type 13-V IN/OUT Output data N-ch Output disable Input enable Schmitt-triggered input with hysteresis characteristics Middle-voltage input buffer Type 5-A Type 13-W Pull-up resistor Pull-up P-ch (mask option) enable IN/OUT Output data Data...
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Page 47: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µ PD789426, 789436, 789446, and 789456 Subseries can access 64 KB of memory space. Figures 3-1 through 3-6 show the memory maps. Figure 3-1. Memory Map ( µ µ µ µ PD789425, 789435) FFFFH Special function registers 256 ×...
Page 48 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ µ µ µ PD789426, 789436) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA05H FA04H LCD display RAM 5 ×...
Page 49 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( µ µ µ µ PD78F9436) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA05H FA04H LCD display RAM 5 × 4 bits Data FA00H memory space...
Page 50 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map ( µ µ µ µ PD789445, 789455) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 ×...
Page 51 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( µ µ µ µ PD789446, 789456) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 ×...
Page 52 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map ( µ µ µ µ PD78F9456) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 × 4 bits Data FA00H memory space...
Page 53: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The µ PD789426, 789436, 789446, and 789456 Subseries provide internal ROM (or flash memory) with the following capacity for each product.
Page 54: Internal Data Memory (Internal High-Speed Ram) Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory (internal high-speed RAM) space The µ PD789426, 789436, 789446, and 789456 Subseries products incorporate the following RAM. Internal high-speed RAM Internal high-speed RAM is incorporated in the area between FD00H and FEFFH. The internal high-speed RAM is also used as a stack.
Page 55: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing The µ PD789426, 789436, 789446, and 789456 Subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible. At the addresses corresponding to data memory area (FD00H to FFFFH) especially, specific addressing modes that correspond to the particular function an area, such as the special function registers are available.
Page 56 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing ( µ µ µ µ PD789426, 789436) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH...
Page 57 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing ( µ µ µ µ PD78F9436) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH...
Page 58 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing ( µ µ µ µ PD789445, 789455) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH...
Page 59 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data Memory Addressing ( µ µ µ µ PD789446, 789456) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH...
Page 60 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Data Memory Addressing ( µ µ µ µ PD78F9456) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH...
Page 61: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD789426, 789436, 789446, and 789456 Subseries provide the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers.
Page 62 CHAPTER 3 CPU ARCHITECTURE Interrupt enable flag (IE) This flag controls interrupt request acknowledgement operations of the CPU. When 0, IE is set to the interrupt disable status (DI), and interrupt requests other than non-maskable interrupt are all disabled. When 1, IE is set to the interrupt enable status (EI). Interrupt request acknowledgement enable is controlled with an interrupt mask flag for various interrupt sources.
Page 63 CHAPTER 3 CPU ARCHITECTURE Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-15. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10...
Page 64: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 65: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions.
Page 66 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Register List (1/2) Address Special Function Register (SFR) Name Symbol Bit Manipulation Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port 0 √ √ − FF01H Port 1 √...
Page 67 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Register List (2/2) Address Special Function Register (SFR) Name Symbol Bit Manipulation Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF27H Port mode register 7 √ √ − Note FF28H Port mode register 8...
Page 68: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 69: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...
Page 70: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Page 71: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 72: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 73: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 74: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 75: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code.
Page 76: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
Page 77: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD789426, 789436, 789446, and 789456 Subseries provide the ports shown in Figures 4-1 and 4-2, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Page 78 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Port Types ( µ µ µ µ PD789446, 789456 Subseries) Port 5 Port 0 Port 1 Port 6 Port 2 Port 7 Port 3 User’s Manual U15075EJ1V0UM00...
Page 79 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (1/2) Pin Name Function After Reset Alternate Function P00 to P03 Port 0. Input KR0 to KR3 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00).
Page 80: Port Configuration
CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (2/2) Pin Name Function After Reset Alternate Function − Note P80, P81 Port 8. Input 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B8 (PUB8).
Page 81: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 This is a 4-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using the port mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull-up resistor option register 0 (PU0).
Page 82: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (PU0).
Page 83: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is a 7-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2). When using the P20 to P26 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B2 (PUB2).
Page 84 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P21 and P26 PUB2 PUB21, PUB26 P-ch PORT Output latch P21/BZO90, (P21, P26) P26/TO90 PM21, PM26 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ1V0UM00...
Page 85 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P22 PUB2 PUB22 P-ch Alternate function PORT Output latch P22/SS20 (P22) PM22 PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ1V0UM00...
Page 86 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P23 PUB2 PUB23 P-ch Alternate function PORT Output latch P23/ASCK20/ (P23) SCK20 PM23 Alternate function PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ1V0UM00...
Page 87 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P24 PUB2 PUB24 P-ch PORT Output latch P24/SO20/TxD20 (P24) PM24 Alternate function SS20 output PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ1V0UM00...
Page 88 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P25 PUB2 PUB25 P-ch Alternate function PORT Output latch P25/SI20/ (P25) RxD20 PM25 PUB2: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15075EJ1V0UM00...
Page 89: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 This is a 4-bit I/O port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3 (PM3). When using the P30 to P33 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B3 (PUB3).
Page 90 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P31 to P33 PUB3 PUB31 to PUB33 P-ch Alternate function PORT Output latch P31/INTP1/TO50/ (P31 to P33) TMI60, P32/INTP2/TO60, P33/INTP3/TO61 PM31 to PM33 Alternate function PUB3: Pull-up resistor option register B3 Port mode register Port 3 read signal Port 3 write signal...
Page 91: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by a mask option.
Page 92: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 This is an 8-bit input-only port. This port is also used as the analog input of an A/D converter. Figure 4-14 shows a block diagram of Port 6. Figure 4-14. Block Diagram of Port 6 P60/ANI0 to P65/ANI5 A/D converter −...
Page 93: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 This is a 3-bit I/O port with an output latch. Port 7 can be specified in the input or output mode in 1-bit units by using port mode register 7 (PM7). When using the P70 to P72 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B7 (PUB7).
Page 94: Port 8 ( Μ Pd789426, 789436 Subseries Only)
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 8 ( µ µ µ µ PD789426, 789436 Subseries only) This is a 2-bit I/O port with an output latch. Port 8 can be specified in the input or output mode in 1-bit units by using port mode register 8 (PM8).
Page 95: Port 9 ( Μ Pd789426, 789436 Subseries Only)
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 9 ( µ µ µ µ PD789426, 789436 Subseries only) This is an 8-bit I/O port with an output latch. Port 9 can be specified in the input or output mode in 1-bit units by using port mode register 9 (PM9).
Page 96: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function The ports are controlled by the following two types of registers. • Port mode registers (PM0 to PM3, PM5, PM7 to PM9) • Pull-up resistor option registers (PU0, PUB2, PUB3, PUB7 to PUB9) Port mode registers (PM0 to PM3, PM5, PM7 to PM9) These registers are used to set port input/output in 1-bit units.
Page 97 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Format of Port Mode Register Symbol Address After reset PM01 PM00 FF20H PM03 PM02 PM13 PM12 PM11 PM10 FF21H PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM33 PM32 PM31 PM30 FF23H PM53 PM52 PM51 PM50 FF25H...
Page 98 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Alternate Function PMxx Pin Name Name P00 to P03 KR0 to KR3 Input TO90 Output INTP0 Input CPT90 Input INTP1 Input TO50 Output TMI60 Input INTP2...
Page 99 CHAPTER 4 PORT FUNCTIONS Pull-up resistor option register B2 (PUB2) Pull-up resistor option register B2 (PUB2) sets whether on-chip pull-up resistors on P20 to P26 are used or not. On the port specified to use an on-chip pull-up resistor by PUB2, the pull-up resistor can be internally used only for the bits set in the input mode.
Page 100 CHAPTER 4 PORT FUNCTIONS Pull-up resistor option register B7 (PUB7) Pull-up resistor option register B7 (PUB7) sets whether on-chip pull-up resistors on P70 to P72 are used or not. On the port specified to use an on-chip pull-up resistor by PUB7, the pull-up resistor can be internally used only for bits set in the input mode.
Page 101 CHAPTER 4 PORT FUNCTIONS Note Pull-up resistor option register B9 (PUB9) Pull-up resistor option register B9 (PUB9) sets whether on-chip pull-up resistors on P90 to P97 are used or not. On the port specified to use an on-chip pull-up resistor by PUB9, the pull-up resistor can be internally used only for bits set in the input mode.
Page 102: Port Function Operation
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
Page 103: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. • • • • Main system clock oscillator This circuit oscillates at 1.0 to 5.0 MHz.
Page 104 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus FRC SCC Suboscillation mode register (SCKM) 16-bit timer 90 Subsystem 8-bit timer 60 clock Watch timer oscillator LCD controller/driver Prescaler Clock to peripheral hardware Main system clock Prescaler oscillator Standby...
Page 105: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The clock generator is controlled by the following registers. • Processor clock control register (PCC) • Suboscillation mode register (SCKM) • Subclock control register (CSS) Processor clock control register (PCC) PCC sets CPU clock selection and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction.
Page 106 CHAPTER 5 CLOCK GENERATOR Suboscillation mode register (SCKM) SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SCKM to 00H. Figure 5-3.
Page 107 CHAPTER 5 CLOCK GENERATOR Subclock control register (CSS) CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the CPU clock operation status. CSS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSS to 00H.
Page 108: System Clock Oscillators
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin.
Page 109: Subsystem Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the inverted signal to the XT2 pin.
Page 110 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 3, 5) (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current High current...
Page 111: Divider Circuit
CHAPTER 5 CLOCK GENERATOR Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched (f) Parallel and near signal lines of main system clock and subsystem clock XT2 is wired parallel to X1. Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series.
Page 112: Clock Generator Operation
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The operation and function of the clock generator is determined by the processor clock control register (PCC), suboscillation mode register (SCKM), and subclock control register (CSS), as follows.
Page 113: Changing Setting Of System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS).
Page 114: Switching Between System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6.2 Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch. Figure 5-8. Switching Between System Clock and CPU Clock RESET Interrupt request signal System clock CPU clock Low-speed High-speed High-speed operation...
Page 115: Chapter 6 16-Bit Timer
CHAPTER 6 16-BIT TIMER 6.1 16-Bit Timer Functions The 16-bit timer has the following functions. • Timer interrupt • Timer output • Buzzer output • Count value capture Timer interrupt An interrupt is generated when a count value and compare value matches. Timer output Timer output can be controlled when a count value and compare value matches.
Page 116: 16-Bit Timer Configuration
CHAPTER 6 16-BIT TIMER 6.2 16-Bit Timer Configuration The 16-bit timer includes the following hardware. Table 6-1. 16-Bit Timer Configuration Item Configuration 16 bits × 1 (TM90) Timer counters 16 bits × 1 (CR90) Registers Compare register: 16 bits × 1 (TCP90) Capture register: Timer outputs 1 (TO90)
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Page 118 CHAPTER 6 16-BIT TIMER 16-bit compare register 90 (CR90) A value specified in CR90 is compared with the count in 16-bit timer register 90 (TM90). If they match, an interrupt request (INTTM90) is issued by CR90. CR90 is set with an 8-bit or 16-bit memory manipulation instruction. Any value from 0000H to FFFFH can be set.
Page 119: Registers Controlling 16-Bit Timer
CHAPTER 6 16-BIT TIMER 6.3 Registers Controlling 16-Bit Timer The 16-bit timer is controlled by the following three registers. • 16-bit timer mode control register 90 (TMC90) • Buzzer output control register 90 (BZC90) • Port mode register 2 (PM2) 16-bit timer mode control register 90 (TMC90) 16-bit timer mode control register 90 (TMC90) controls the setting of a count clock, capture edge, etc.
Page 120 CHAPTER 6 16-BIT TIMER Figure 6-2. Format of 16-Bit Timer Mode Control Register 90 Symbol <7> <6> <0> Address After reset Note TMC90 FF48H TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TOD90 Timer output data Timer output data is "0" Timer output data is "1"...
Page 121 CHAPTER 6 16-BIT TIMER Buzzer output control register 90 (BZC90) This register selects a buzzer frequency based on fcl selected with the count clock select bits (TCL901 and TCL900), and controls the output of the square wave. BZC90 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets BZC90 to 00H.
Page 122 CHAPTER 6 16-BIT TIMER Port mode register 2 (PM2) PM2 is used to set each bit of port 3 to input or output. When pin P26/ITO90 is used for timer output, reset the output latch of P26 and PM26 to 0; when pin P21/BZO90 is used for buzzer output, reset the output latch of P26 and PM26 to 0.
Page 123: 16-Bit Timer Operation
CHAPTER 6 16-BIT TIMER 6.4 16-Bit Timer Operation 6.4.1 Operation as timer interrupt In the timer interrupt function, interrupts are repeatedly generated at the count value preset in 16-bit compare register 90 (CR90) based on the intervals of the value set in TCL901 and TCL900. To operate the 16-bit timer as a timer interrupt, the following settings are required.
Page 124 CHAPTER 6 16-BIT TIMER Figure 6-6. Timing of Timer Interrupt Operation Count clock TM90 count value 0000H 0001H FFFFH 0000H 0001H FFFFH CR90 INTTM90 Interrupt Interrupt acknowledgement acknowledgement TO90 TOF90 Overflow flag set Remark N = 0000H to FFFFH User’s Manual U15075EJ1V0UM00...
Page 125: Operation As Timer Output
CHAPTER 6 16-BIT TIMER 6.4.2 Operation as timer output Timer outputs are repeatedly generated at the count value preset in 16-bit compare register 90 (CR90) based on the intervals of the value set in TCL901 and TCL900. To operate the 16-bit timer as a timer output, the following settings are required. •...
Page 126: Capture Operation
CHAPTER 6 16-BIT TIMER 6.4.3 Capture operation The capture operation consists of latching the count value of 16-bit timer register 90 (TM90) into a capture register in synchronization with a capture trigger, and retaining the count value. Set TMC90 as shown in Figure 6-9 to allow the 16-bit timer to start the capture operation. Figure 6-9.
Page 127: 16-Bit Timer Counter 90 Readout
CHAPTER 6 16-BIT TIMER 6.4.4 16-bit timer counter 90 readout The count value of 16-bit timer counter 90 (TM90) is read out using a 16-bit manipulation instruction. TM90 readout is performed through a counter read buffer. The counter read buffer latches the TM90 count value, and the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM90 lower byte rises, and the count value is retained.
Page 128: Buzzer Output Operation
CHAPTER 6 16-BIT TIMER 6.4.5 Buzzer output operation The buzzer frequency is set using buzzer output control register 90 (BZC90) based on the count clock selected with TCL901 and TCL900 of TMC90 (source clock). A square wave of the set buzzer frequency is output. Table 6-4 shows the buzzer frequency.
Page 129: Notes On Using 16-Bit Timer
CHAPTER 6 16-BIT TIMER 6.5 Notes on Using 16-Bit Timer Usable functions differ according to the settings of the count clock selection, CPU clock operation, system clock oscillation status, and BZOE90 (bit 0 of buzzer output control register 90 (BZC90)). Refer to the following table.
Page 130 CHAPTER 6 16-BIT TIMER Make the following settings when stopping the main system clock oscillation to support low current consumption and releasing the HALT mode. Count clock: Subsystem clock CPU clock: Subsystem clock Main system clock: Oscillation stopped BZOE90: 1 (Buzzer output enabled) At this time, when the setting of P21, the buzzer output alternate function pin, is “PM21 = 0, P21 = 0”, a square wave of the buzzer frequency is output from P21.
Page 131: Chapter 7 8-Bit Timer
CHAPTER 7 8-BIT TIMER 7.1 8-Bit Timer Functions An 8-bit timer (one channel, timer 50) and an 8-bit timer/event counter (one channel, timer 60) are incorporated in the µ PD789426, 789436, 799446, 789456 Subseries. The operation modes listed in the following table can be set via mode register settings.
Page 132: 8-Bit Timer Configuration
CHAPTER 7 8-BIT TIMER Timer 60: Pulse generator mode The timer output status inverts repeatedly due to the settings of TM60, CR60, and CRH60, and pulses of any duty ratio are output (either P32/INTP2/TO60 or P33/INTP3/TO61 can be selected as the timer output pin using software).
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Page 135 CHAPTER 7 8-BIT TIMER Figure 7-3. Block Diagram of Output Controller (Timer 60) TOE60 TOE61 PM32 PM33 Output latch Output latch TO60/P32/ INTP2 TO61/P33/ INTP3 Timer 60 output signal (1) 8-bit compare register 50 (CR50) This 8-bit register is used to continually compare the value set to CR50 with the count value in 8-bit timer counter 50 (TM50) and to generate an interrupt request (INTTM50) when a match occurs.
Page 136 CHAPTER 7 8-BIT TIMER (4) 8-bit timer counters 50 and 60 (TM50 and TM60) These are 8-bit registers that are used to count the count pulse. TM50 and TM60 are read with an 8-bit memory manipulation instruction. RESET input sets TM50 and TM60 to 00H. TM50 and TM60 are cleared to 00H under the following conditions.
Page 137 CHAPTER 7 8-BIT TIMER (d) PWM output mode (i) TM50 • After reset • When the TCE50 flag is cleared to 0 • When a match occurs between TM50 and CR50 • When the TM50 count value overflows (ii) TM60 •...
Page 138: Registers Controlling 8-Bit Timer
CHAPTER 7 8-BIT TIMER 7.3 Registers Controlling 8-Bit Timer The 8-bit timer is controlled by the following four registers. • 8-bit timer mode control register 50 (TMC50) • 8-bit timer mode control register 60 (TMC60) • Carrier generator output control register 60 (TCA60) •...
Page 139 CHAPTER 7 8-BIT TIMER Figure 7-4. Format of 8-Bit Timer Mode Control Register 50 Symbol <7> <6> <0> Address After reset TMC50 TCE50 TEG50 TCL502 TCL501 TCL500 TMD501 TMD500 TOE50 FF4DH Note 1 TCE50 Control of TM50 count operation Clears TM50 count value and stops operation Starts count operation TEG50 Valid edge selection for TM50 count clock...
Page 140 CHAPTER 7 8-BIT TIMER Cautions 1. In cascade connection mode, the output signal of timer 60 is forcibly selected as the count clock. 2. When operating TMC50, be sure to perform settings in the following order. <1> Stop TM50 count operation. <2>...
Page 141 CHAPTER 7 8-BIT TIMER Figure 7-5. Format of 8-Bit Timer Mode Control Register 60 Symbol <7> <6> <0> Address After reset TMC60 TCE60 TOE61 TCL602 TCL601 TCL600 TMD601 TMD600 TOE60 FF4EH Note 1 TCE60 Control of TM60 count operation Clears TM60 count value and stops operation (the count value is also cleared for TM50 in cascade connection mode) Starts count operation (the count operation is also started for TM50 in cascade connection mode) TCL602...
Page 142 CHAPTER 7 8-BIT TIMER (3) Carrier generator output control register 60 (TCA60) This register is used to set the timer output data in carrier generator mode. TCA60 is set with an 8-bit memory manipulation instruction. RESET input sets TCA60 to 00H. Figure 7-6.
Page 143: 8-Bit Timer Operation
CHAPTER 7 8-BIT TIMER 7.4 8-Bit Timer Operation 7.4.1 Operation as 8-bit timer counter Timer 50 and timer 60 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counter. • Interval timer with 8-bit resolution •...
Page 144 CHAPTER 7 8-BIT TIMER Table 7-3. Interval Time of Timer 50 TCL502 TCL501 TCL500 Minimum Interval Time Maximum Interval Time Resolution (0.2 µ s) (51.2 µ s) (0.2 µ s) (1.6 µ s) (409.6 µ s) (1.6 µ s) (25.6 µ s) (25.6 µ...
Page 145 CHAPTER 7 8-BIT TIMER Figure 7-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) Count clock TMn0 Clear Clear Clear CRn0 TCEn0 Count start Count stop INTTMn0 Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement TOnm Interval time Interval time Interval time Remarks 1.
Page 146 CHAPTER 7 8-BIT TIMER Figure 7-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) Count clock TMn0 Clear Clear Clear CRn0 TCEn0 Count start INTTMn0 TOnm Remark n = 5, 6 nm = 50, 60, 61 Figure 7-11.
Page 147 CHAPTER 7 8-BIT TIMER Figure 7-12. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > > > > M)) Count clock N − 1 TMn0 Clear Clear Clear CRn0 TCEn0 TMn0 overflows because M <...
Page 148 CHAPTER 7 8-BIT TIMER Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 60 Match Signal Is Selected for Timer 50 Count Clock) Timer 60 count clock TM60 Clear Clear Clear Clear CR60 TCE60 Count start INTTM60 Input clock to timer 50 (timer 60 match signal) Y −...
Page 149 CHAPTER 7 8-BIT TIMER Operation as external event counter with 8-bit resolution (timer 60 only) The external event counter counts the number of external clock pulses input to the TMI60/P31/INTP1/TO50 pin by using 8-bit timer counter 60 (TM60). To operate timer 60 as an external event counter, settings must be made in the following sequence. <1>...
Page 150 CHAPTER 7 8-BIT TIMER Figure 7-14. Timing of Operation of External Event Counter with 8-Bit Resolution TMI60 pin input N − 1 TM60 count value CR60 TCE60 INTTM60 Remark N = 00H to FFH User’s Manual U15075EJ1V0UM00...
Page 151 CHAPTER 7 8-BIT TIMER Operation as square-wave output with 8-bit resolution Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register n0 (CRn0). To operate timer n0 for square-wave output, settings must be made in the following sequence. <1>...
Page 152 CHAPTER 7 8-BIT TIMER Table 7-6. Square-Wave Output Range of Timer 60 (During f = 5.0 MHz Operation) TCL602 TCL601 TCL600 Minimum Pulse Width Maximum Pulse Width Resolution (51.2 µ s) (0.2 µ s) (0.2 µ s) (0.4 µ s) (0.4 µ...
Page 153: Operation As 16-Bit Timer Counter
CHAPTER 7 8-BIT TIMER 7.4.2 Operation as 16-bit timer counter Timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter 50 (TM50) is the higher 8 bits and 8-bit timer counter 60 (TM60) is the lower 8 bits. 8-bit timer 60 controls reset and clear.
Page 154 CHAPTER 7 8-BIT TIMER Table 7-7. Interval Time with 16-Bit Resolution (During f = 5.0 MHz Operation) TCL602 TCL601 TCL600 Minimum Interval Time Maximum Interval Time Resolution (0.2 µ s) (0.2 µ s) (13.1 ms) (0.4 µ s) (0.4 µ s) (26.2 ms) input cycle ×...
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Page 156 CHAPTER 7 8-BIT TIMER Operation as external event counter with 16-bit resolution The external event counter counts the number of external clock pulses input to the TMI60/P31/INTP1/TO50 pin by TM50 and TM60. To operate as an external event counter with 16-bit resolution, settings must be made in the following sequence.
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Page 158 CHAPTER 7 8-BIT TIMER Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR50 and CR60. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1>...
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Page 160: Operation As Carrier Generator
CHAPTER 7 8-BIT TIMER 7.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM60 can be output in the cycle set in TM50. To operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence. <1>...
Page 161 CHAPTER 7 8-BIT TIMER Figure 7-19. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > > > > N)) Count clock TM60 count value Clear Clear Clear Clear CR60 CRH60 TCE60 Count start INTTM60 Carrier clock Count pulse TM50 CR50...
Page 162 CHAPTER 7 8-BIT TIMER Figure 7-20. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < < < < N), Phases of Carrier Clock and NRZ60 Are Asynchronous) Count clock TM60 count value Clear Clear Clear Clear CR60 CRH60...
Page 163 CHAPTER 7 8-BIT TIMER Figure 7-21. Timing of Carrier Generator Operation (When CR60 = CRH60 = N) Count clock TM60 count value Clear Clear Clear Clear Clear CR60 CRH60 TCE60 Count start INTTM60 Carrier clock Count pulse TM50 CR50 TCE50 INTTM50 NRZB60 NRZ60...
Page 164: Pwm Free-Running Mode Operation (Timer 50)
CHAPTER 7 8-BIT TIMER 7.4.4. PWM free-running mode operation (timer 50) In the PWM free-running mode, TO50 becomes high level when TM50 overflows, and TO50 becomes low level when CR50 and TM50 match. It is thus possible to output a pulse with any duty ratio. To operate timer 50 in the PWM free-running mode, setting must be made in the following sequence.
Page 165 CHAPTER 7 8-BIT TIMER Figure 7-22. Operation Timing in PWM Free-Running Mode (When Rising Edge Is Selected) Count clock TM50 Overflow Overflow CR50 TCE50 Count start INTTM50 TO50 Caution When the rising edge is selected, do not set the CR50 to 00H. If the CR50 is set to 00H, PWM output may not be performed normally.
Page 166 CHAPTER 7 8-BIT TIMER Figure 7-23. Operation Timing When Overwriting CR50 (When Rising Edge Is Selected) (2/2) When setting CR50 < < < < TM50 after overflow Count clock TM50 Overflow Overflow Overflow CR50 TCE50 Count start INTTM50 TO50 Overflow occurs but CR50 overwrite no change takes place because TO50 is...
Page 167 CHAPTER 7 8-BIT TIMER Figure 7-24. Operation Timing in PWM Free-Running Mode (When Both Edges Are Selected) (2/2) When CR50 = Odd number Count clock 2N + 1 2N + 1 TM50 Overflow Overflow Overflow 2N + 1 CR50 TCE50 Count start INTTM50 TO50...
Page 168: Operation As Pwm Output (Timer 60)
CHAPTER 7 8-BIT TIMER 7.4.5 Operation as PWM output (timer 60) In the PWM pulse generator mode, a pulse of any duty ratio can be output by setting a low-level width using CR60 and a high-level width using CRH60. To operate timer 60 in PWM output mode, settings must be made in the following sequence. <1>...
Page 169 CHAPTER 7 8-BIT TIMER Figure 7-26. PWM Pulse Generator Mode Timing (Basic Operation) Count clock TM60 count value Clear Clear Clear Clear CR60 CRH60 TCE60 Count start INTTM60 TO60 or Note TO61 Note The initial value of TO60 is low level when output is enabled (TOE60 = 1). Figure 7-27.
Page 170: Notes On Using 8-Bit Timer
CHAPTER 7 8-BIT TIMER 7.5 Notes on Using 8-Bit Timer Error on starting timer An error of up to 1 clock is included in the time between the timer being started and a match signal being generated. This is because 8-bit timer counter n0 (TMn0) is started asynchronously to the count pulse. Figure 7-28.
Page 171: Chapter 8 Watch Timer
CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 8-1 is a block diagram of the watch timer. Figure 8-1.
Page 172: Watch Timer Configuration
CHAPTER 8 WATCH TIMER Watch timer The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to issue an interrupt request (INTWT) at 0.5-second intervals. Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5- second interval.
Page 173: Watch Timer Control Register
CHAPTER 8 WATCH TIMER 8.3 Watch Timer Control Register The watch timer is controlled by the watch timer mode control register (WTM). • Watch timer mode control register (WTM) WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer. It also specifies the prescaler interval and how the 5-bit counter is controlled.
Page 174: Watch Timer Operation
CHAPTER 8 WATCH TIMER 8.4 Watch Timer Operation 8.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate at 0.5-second intervals. The watch timer is used to generate an interrupt request at specified intervals. By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer starts counting.
Page 175 CHAPTER 8 WATCH TIMER Figure 8-3. Watch Timer/Interval Timer Operation Timing 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s) Interval timer interrupt INTWTI Interval timer (T) Caution When operation of the watch timer and 5-bit counter operation is enabled by setting bit 0 (WTM0) of the watch mode timer mode control register (WTM) to 1, the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the...
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Page 177: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). Watchdog timer The watchdog timer is used to detect a program runaway.
Page 178: Watchdog Timer Configuration
CHAPTER 9 WATCHDOG TIMER 9.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Figure 9-1. Block Diagram of Watchdog Timer Internal bus TMMK4 Prescaler...
Page 179: Watchdog Timer Control Registers
CHAPTER 9 WATCHDOG TIMER 9.3 Watchdog Timer Control Registers The watchdog timer is controlled by the following two registers. • Watchdog timer clock select register (WDCS) • Watchdog timer mode register (WDTM) Watchdog timer clock select register (WDCS) This register sets the watchdog timer count clock. WDCS is set with an 8-bit memory manipulation instruction.
Page 180 CHAPTER 9 WATCHDOG TIMER Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3.
Page 181: Watchdog Timer Operation
CHAPTER 9 WATCHDOG TIMER 9.4 Watchdog Timer Operation 9.4.1 Operation as watchdog timer The watchdog timer detects a program runaway when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (WDCS0 to WDCS2) of watchdog timer clock select register (WDCS).
Page 182: Operation As Interval Timer
CHAPTER 9 WATCHDOG TIMER 9.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value.
Page 183: Chapter 10 8-Bit A/D Converter ( Μ Μ Μ Μ Pd789426 And 789446 Subseries)
CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) 10.1 8-Bit A/D Converter Functions The 8-bit A/D converter is an 8-bit resolution converter used to convert analog inputs into digital signals. This converter can control six channels (ANI0 to ANI5) of analog inputs. A/D conversion can only be started by software.
Page 184 CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) Figure 10-1. Block Diagram of 8-Bit A/D Converter P-ch ANI0/P60 ANI1/P61 Sample & hold circuit ANI2/P62 ANI3/P63 Voltage comparator ANI4/P64 ANI5/P65 Successive approximation register (SAR) INTAD0 Controller A/D conversion result register 0 (ADCR0)
Page 185 CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string. Series resistor string The series resistor string is configured between AV and AV .
Page 186: 8-Bit A/D Converter Control Registers
CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) 10.3 8-Bit A/D Converter Control Registers The 8-bit A/D converter is controlled by the following two registers. • A/D converter mode register 0 (ADM0) • Analog input channel specification register 0 (ADS0) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs.
Page 187 CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) Analog input channel specification register 0 (ADS0) ADS0 specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADS0 to 00H.
Page 188: 8-Bit A/D Converter Operation
CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) 10.4 8-Bit A/D Converter Operation 10.4.1 Basic operation of 8-bit A/D converter <1> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0). <2>...
Page 189: Input Voltage And Conversion Result
CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) Figure 10-4. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled.
Page 190 CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Result A/D conversion result (ADCR0) Input voltage/AV User’s Manual U15075EJ1V0UM00...
Page 191: Operation Mode Of 8-Bit A/D Converter
CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) 10.4.3 Operation mode of 8-bit A/D converter The A/D converter is initially in select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI5 for A/D conversion.
Page 192: Cautions Related To 8-Bit A/D Converter
CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) 10.5 Cautions Related to 8-Bit A/D Converter Current consumption in standby mode In standby mode, the A/D converter stops operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption.
Page 193 CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and that to stop the A/D conversion operation conflict. Therefore, read the A/D conversion result while the A/D conversion operation is in progress.
Page 194 CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) Noise prevention To maintain a resolution of 8 bits, watch for noise to the AV and ANI0 to ANI5 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 10-10.
Page 195 CHAPTER 10 8-BIT A/D CONVERTER ( µ µ µ µ PD789426 AND 789446 SUBSERIES) Figure 10-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 Rewriting to ADM0 (to begin conversion ADIF0 has been set, but conversion (to begin conversion for ANIn) for ANIm has not been completed.
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Page 197: Chapter 11 10-Bit A/D Converter ( Μ Μ Μ Μ Pd789436 And 789456 Subseries)
CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) 11.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter used to convert analog inputs into digital signals. This converter can control six channels (ANI0 to ANI5) of analog inputs. A/D conversion can only be started by software.
Page 198 CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) Figure 11-1. Block Diagram of 10-Bit A/D Converter P-ch ANI0/P60 ANI1/P61 Sample & hold circuit ANI2/P62 ANI3/P63 Voltage comparator ANI4/P64 ANI5/P65 Successive approximation register (SAR) INTAD0 Controller A/D conversion result register 0 (ADCR0)
Page 199 CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string.
Page 200: 10-Bit A/D Converter Control Registers
CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) 11.3 10-Bit A/D Converter Control Registers The 10-bit A/D converter is controlled by the following two registers. • A/D converter mode register 0 (ADM0) • Analog input channel specification register 0 (ADS0) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs.
Page 201 CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) Analog input channel specification register 0 (ADS0) ADS0 specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H.
Page 202: 10-Bit A/D Converter Operation
CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) 11.4 10-Bit A/D Converter Operation 11.4.1 Basic operation of 10-bit A/D converter <1> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0). <2>...
Page 203: Input Voltage And Conversion Result
CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) Figure 11-4. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR0 result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled.
Page 204 CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) Figure 11-5. Relationship Between Analog Input Voltage and A/D Conversion Result 1023 1022 1021 A/D conversion result (ADCR0) 2043 1022 2045 1023 2047 2048 1024 2048 1024 2048 1024...
Page 205: Operation Mode Of 10-Bit A/D Converter
CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) 11.4.3 Operation mode of 10-bit A/D converter The A/D converter is initially in select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI5 for A/D conversion.
Page 206: Cautions Related To 10-Bit A/D Converter
CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) 11.5 Cautions Related to 10-Bit A/D Converter Current consumption in standby mode In standby mode, the A/D converter stops operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption.
Page 207 CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and that to stop the A/D conversion operation conflict. Therefore, read the A/D conversion result while the A/D conversion operation is in progress.
Page 208 CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) Noise prevention To maintain a resolution of 10 bits, watch for noise to the AV and ANI0 to ANI5 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 11-10.
Page 209 CHAPTER 11 10-BIT A/D CONVERTER ( µ µ µ µ PD789436 AND 789456 SUBSERIES) Figure 11-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 Rewriting to ADM0 (to begin conversion (to begin conversion ADIF0 has been set, but conversion for ANIm) for ANIn) for ANIm has not been completed.
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Page 211: Chapter 12 Serial Interface 20
CHAPTER 12 SERIAL INTERFACE 20 12.1 Serial Interface 20 Functions Serial interface 20 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. Asynchronous serial interface (UART) mode This mode is used to send and receive the one byte of data that follows a start bit.
Page 212 CHAPTER 12 SERIAL INTERFACE 20 User’s Manual U15075EJ1V0UM00...
Page 213 CHAPTER 12 SERIAL INTERFACE 20 User’s Manual U15075EJ1V0UM00...
Page 214 CHAPTER 12 SERIAL INTERFACE 20 Transmission shift register 20 (TXS20) TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20 bit-serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data to TXS20 triggers transmission.
Page 215: Serial Interface 20 Control Registers
CHAPTER 12 SERIAL INTERFACE 20 12.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following registers. • Serial operation mode register 20 (CSIM20) • Asynchronous serial interface mode register 20 (ASIM20) • Asynchronous serial interface status register 20 (ASIS20) •...
Page 216 CHAPTER 12 SERIAL INTERFACE 20 Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used to make the settings related to asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Figure 12-4.
Page 217 CHAPTER 12 SERIAL INTERFACE 20 Table 12-2. Serial Interface 20 Operating Mode Settings Operation stop mode ASIM20 CSIM20 PM25 PM24 PM23 First Shift P25/SI20/ P24/SO20/ P23/SCK20/ Clock RxD20 Pin TxD20 Pin ASCK20 Pin TXE20 RXE20 CSIE20 DIR20 CSCK20 Function Function Function ×...
Page 218 CHAPTER 12 SERIAL INTERFACE 20 Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode.
Page 219 CHAPTER 12 SERIAL INTERFACE 20 Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Figure 12-6. Format of Baud Rate Generator Control Register 20 Symbol Address After reset...
Page 220 CHAPTER 12 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the ASCK20 pin. (a) Generation of baud rate transmit/receive clock form system clock The transmit/receive clock is generated by scaling the system clock.
Page 221 CHAPTER 12 SERIAL INTERFACE 20 (b) Generation of baud rate transmit/receive clock from external clock input to ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression.
Page 222: Serial Interface 20 Operation
CHAPTER 12 SERIAL INTERFACE 20 12.4 Serial Interface 20 Operation Serial interface 20 provides the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 12.4.1 Operation stop mode In operation stop mode, serial transfer is not executed, thereby reducing the power consumption. P23/SCK20/ASCK20, P24/SO20/TxD20, and P25/SI20/RxD20 pins can be used as normal I/O ports.
Page 223 CHAPTER 12 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol <7> <6> Address After reset ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20...
Page 224: Asynchronous Serial Interface (Uart) Mode
CHAPTER 12 SERIAL INTERFACE 20 12.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received, enabling full-duplex communication. This device incorporates UART-dedicated baud rate generator that enables communications at the desired baud rate.
Page 225 CHAPTER 12 SERIAL INTERFACE 20 (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM20 to 00H. Set CSIM20 to 00H when UART mode is selected. Symbol <7> Address After reset CSIM20...
Page 226 CHAPTER 12 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol <7> <6> Address After reset ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20...
Page 227 CHAPTER 12 SERIAL INTERFACE 20 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS20 to 00H. Symbol <2> <1> <0> Address After reset ASIS20 PE20 FE20 OVE20 FF71H PE20...
Page 228 CHAPTER 12 SERIAL INTERFACE 20 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol Address After reset BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 3-bit counter source clock selection...
Page 229 CHAPTER 12 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the ASCK20 pin. (i) Generation of baud rate transmit/receive clock from system clock The transmit/receive clock is generated by scaling the system clock.
Page 230 CHAPTER 12 SERIAL INTERFACE 20 (ii) Generation of baud rate transmit/receive clock from external clock input to ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression.
Page 231 CHAPTER 12 SERIAL INTERFACE 20 Communication operation (a) Data format The transmit/receive data format is as shown in Figure 12-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out with asynchronous serial interface mode register 20 (ASIM20).
Page 232 CHAPTER 12 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
Page 233 CHAPTER 12 SERIAL INTERFACE 20 (c) Transmission A transmit operation is started by writing transmit data to transmission shift register 20 (TXS20). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated.
Page 234 CHAPTER 12 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by ASIM20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output.
Page 235 CHAPTER 12 SERIAL INTERFACE 20 (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, and overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20 (ASIS20).
Page 236 CHAPTER 12 SERIAL INTERFACE 20 Cautions related to UART mode (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmission shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission.
Page 237: 3-Wire Serial I/O Mode
CHAPTER 12 SERIAL INTERFACE 20 12.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series. Communication is performed using three lines: a serial clock (SCK20), serial output (SO20), and serial input (SI20).
Page 238 CHAPTER 12 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H. Symbol <7>...
Page 239 CHAPTER 12 SERIAL INTERFACE 20 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol Address After reset BRGC20 TPS203 TPS202 TPS201 TPS200 FF73H TPS203 TPS202 TPS201 TPS200 3-bit counter source clock selection...
Page 240 CHAPTER 12 SERIAL INTERFACE 20 Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Transmission shift register (TXS20/SIO20) and reception shift register (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20).
Page 241 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (2/7) (ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 write SCK20 SI20 SO20 Note INTCSI20 Note The value of the last bit previously output is output. (iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1) SS20 SIO20...
Page 242 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (3/7) (iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 write SCK20 SO20 SI20 INTCSI20 (v) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 write SCK20...
Page 243 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (4/7) (vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1) SS20 SIO20 write SCK20 Note 1 SIO20 write (master) SI20 Hi-Z Hi-Z Note 2 SO20 INTCSI20 Notes 1.
Page 244 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (5/7) (viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 write SCK20 Note SIO20 write (master) SI20 SO20 INTCSI20 Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20.
Page 245 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (6/7) (x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 write SCK20 SO20 Note SI20 INTCSI20 Note The value of the last bit previously output is output. (xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 write...
Page 246 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (7/7) (xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1) SS20 SIO20 write SCK20 SI20 Hi-Z Hi-Z Note 2 Note 1 SO20 INTCSI20 Notes 1. The value of the last bit previously output is output. 2.
Page 247: Chapter 13 Lcd Controller/Driver
CHAPTER 13 LCD CONTROLLER/DRIVER 13.1 LCD Controller/Driver Functions The functions of the LCD controller/driver of the µ PD789426, 789436, 789446, and 789456 Subseries are as follows. Automatic output of segment and common signals based on automatic display data memory read Two different display modes: •...
Page 248 CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15075EJ1V0UM00...
Page 249: Registers Controlling Lcd Controller/Driver
CHAPTER 13 LCD CONTROLLER/DRIVER 13.3 Registers Controlling LCD Controller/Driver • LCD display mode register 0 (LCDM0) • LCD clock control register 0 (LCDC0) • LCD voltage amplification control register 0 (LCDVA0) LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable display operation. It also specifies the operation mode, LCD drive power supply, and display mode.
Page 250 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-2. Format of LCD Display Mode Register 0 Symbol <7> <6> <4> Address After reset LCDM0 LCDON0 VAON0 LIPS0 LCDM00 FFB0H LCDON0 LCD display enable/disable Display off Display on Note VAON0 LCD controller/driver operation mode No internal voltage amplification (Normal operation) Internal voltage amplification enabled (Low-voltage operation) Note...
Page 251 CHAPTER 13 LCD CONTROLLER/DRIVER LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD clock and frame frequency. LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDC0 to 00H. Figure 13-3. Format of LCD Clock Control Register 0 Symbol Address After reset...
Page 252 CHAPTER 13 LCD CONTROLLER/DRIVER LCD voltage amplification control register 0 (LCDVA0) LCDVA0 controls the voltage amplification level during the voltage amplifier operation. Figure 13-4. Format of LCD Voltage Amplification Control Register 0 Symbol <0> Address After reset LCDVA0 GAIN FFB3H Note GAIN Reference voltage (V...
Page 253: Setting Lcd Controller/Driver
CHAPTER 13 LCD CONTROLLER/DRIVER 13.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <1> Set the frame frequency using LCD clock control register 0 (LCDC0). <2> Set the voltage amplification level using LCD voltage amplification control register 0 (LCDVA0). GAIN = 0: V = 4.5 V, V = 3 V, V...
Page 254: Common And Segment Signals
CHAPTER 13 LCD CONTROLLER/DRIVER 13.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, V ). It turns off when the potential difference becomes lower than V Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it.
Page 255 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-6 shows the common signal waveforms, and Figure 13-7 shows the voltages and phases of the common and segment signals. Figure 13-6. Common Signal Waveforms COMn (Three-time slot mode) = 3 × T COMn (Four-time slot mode) = 4 ×...
Page 256: Display Modes
CHAPTER 13 LCD CONTROLLER/DRIVER 13.7 Display Modes 13.7.1 Three-time slot display example Figure 13-9 shows how the 5-digit LCD panel having the display pattern shown in Figure 13-8 is connected to the segment signals (S0 to S14) and the common signals (COM0 to COM2) of the µ PD789446 or µ PD789456 Subseries chip.
Page 257 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-9. Example of Connecting Three-Time Slot LCD Panel Open COM 3 COM 2 COM 1 COM 0 FA00H S 10 S 11 S 12 S 13 S 14 x’: Can be used to store any data because there is no corresponding segment in the LCD panel. ×: Can always be used to store any data because of the three-time slot mode being used.
Page 258 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-10. Three-Time Slot LCD Drive Waveform Examples COM0 COM1 COM2 +1/3V COM0-S6 −1/3V −V +1/3V COM1-S6 −1/3V −V +1/3V COM2-S6 −1/3V −V User’s Manual U15075EJ1V0UM00...
Page 259: Four-Time Slot Display Example
CHAPTER 13 LCD CONTROLLER/DRIVER 13.7.2 Four-time slot display example Figure 13-12 shows how the 7-digit LCD panel having the display pattern shown in Figure 13-11 is connected to the segment signals (S0 to S14) and the common signals (COM0 to COM3) of the µ PD789446 or µ PD789456 Subseries chip.
Page 260 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-12. Example of Connecting Four-Time Slot LCD Panel COM 3 COM 2 COM 1 COM 0 FA00H User’s Manual U15075EJ1V0UM00...
Page 261 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-13. Four-Time Slot LCD Drive Waveform Examples COM0 COM1 COM2 COM3 +1/3V COM0-S2 −1/3V −V +1/3V COM1-S2 −1/3V −V User’s Manual U15075EJ1V0UM00...
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Page 263: Chapter 14 Interrupt Functions
CHAPTER 14 INTERRUPT FUNCTIONS 14.1 Interrupt Function Types The following two types of interrupt functions are used. Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 264 CHAPTER 14 INTERRUPT FUNCTIONS Table 14-1. Interrupt Source List Note 1 Interrupt Type Priority Interrupt Source Internal/ Basic Vector External Configuration Table Name Trigger Note 2 Type Address − Non-maskable INTWDT Watchdog timer overflow (with Internal 0004H watchdog timer mode 1 selected) Maskable INTWDT Watchdog timer overflow (with interval...
Page 265 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table Interrupt request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (C) External maskable interrupt Internal bus INTM0, INTM1, KRM00...
Page 266: Registers Controlling Interrupt Function
CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt functions. • Interrupt request flag registers 0, 1 (IF0 and IF1) • Interrupt mask flag registers 0, 1 (MK0 and MK1) •...
Page 267 CHAPTER 14 INTERRUPT FUNCTIONS Interrupt request flag registers 0, 1 (IF0 and IF1) The interrupt request flag is set (1) when the corresponding interrupt request is generated or an instruction is executed. It is cleared (0) when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input.
Page 268 CHAPTER 14 INTERRUPT FUNCTIONS Interrupt mask flag registers 0, 1 (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH. Figure 14-3.
Page 269 CHAPTER 14 INTERRUPT FUNCTIONS External interrupt mode register 0 (INTM0) This register is used to specify a valid edge for INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 to 00H. Figure 14-4. Format of External Interrupt Mode Register 0 Address After reset Symbol...
Page 270 CHAPTER 14 INTERRUPT FUNCTIONS External interrupt mode register 1 (INTM1) INTM1 is used to specify a valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 14-5. Format of External Interrupt Mode Register 1 Symbol Address After reset...
Page 271 CHAPTER 14 INTERRUPT FUNCTIONS Key return mode register 00 (KRM00) This register sets the pin that detects a key return signal (falling edge of port 0). KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM00 to 00H. Figure 14-7.
Page 272: Interrupt Servicing Operation
CHAPTER 14 INTERRUPT FUNCTIONS 14.4 Interrupt Servicing Operation 14.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Page 273 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-9. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) Interval timer overflows WDTM3 = 0 (non-maskable interrupt is selected) Reset processing Interrupt request is generated Interrupt servicing starts WDTM: Watchdog timer mode register WDT:...
Page 274: Maskable Interrupt Request Acknowledgment Operation
CHAPTER 14 INTERRUPT FUNCTIONS 14.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE flag is set to 1).
Page 275: Multiple Interrupt Servicing
CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-13. Interrupt Request Acknowledgment Timing (Example: MOV A, r) 8 clocks Clock Saving PSW and PC, and MOV A, r Interrupt servicing program jump to interrupt servicing Interrupt If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n −...
Page 276 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-15. Example of Multiple Interrupts Example 1. Acknowledging multiple interrupts INTxx servicing INTyy servicing Main servicing IE = 0 IE = 0 INTxx INTyy RETI RETI The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are performed.
Page 277: Putting Interrupt Requests On Hold
CHAPTER 14 INTERRUPT FUNCTIONS 14.4.4 Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions (interrupt request pending instructions) are as follows.
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Page 279: Chapter 15 Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function The standby function is to reduce the power consumption of the system and can be effected in the following two modes: HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU.
Page 280: Register Controlling Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 281: Standby Function Operation
CHAPTER 15 STANDBY FUNCTION 15.2 Standby Function Operation 15.2.1 HALT mode HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 15-1. HALT Mode Operating Status Item HALT Mode Operation Status While The Main HALT Mode Operation Status While The...
Page 282 CHAPTER 15 STANDBY FUNCTION Releasing HALT mode The HALT mode can be released by the following three types of sources: Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed.
Page 283 CHAPTER 15 STANDBY FUNCTION Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 15-3. Releasing HALT Mode by RESET Input Wait HALT : 6.55 ms)
Page 284: Stop Mode
CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset.
Page 285 CHAPTER 15 STANDBY FUNCTION Releasing STOP mode The STOP mode can be released by the following two types of sources: Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed, after the oscillation stabilization time has elapsed.
Page 286 CHAPTER 15 STANDBY FUNCTION Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 15-5. Releasing STOP Mode by RESET Input STOP Wait instruction RESET signal...
Page 287: Chapter 16 Reset Function
CHAPTER 16 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input by RESET pin (2) Internal reset by watchdog timer runaway time detection External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 288 CHAPTER 16 RESET FUNCTION Figure 16-2. Reset Timing by RESET Input Oscillation During normal Reset period Normal operation stabilization operation (oscillation stops) (reset processing) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 16-3. Reset Timing by Overflow in Watchdog Timer Oscillation Reset period During normal...
Page 289 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2...
Page 290 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (2/2) Hardware Status After Reset LCD controller/driver Display mode register (LCDM0) Clock control register (LCDC0) Voltage amplification control register (LCDVA0) Interrupt Request flag register (IF0, IF1) Mask flag register (MK0, MK1) External interrupt mode register (INTM0, INTM1) Key return mode register (KRM00) User’s Manual U15075EJ1V0UM00...
Page 291: Chapter 17 Μ Μ Μ Μ Pd78F9436, 78F9456
CHAPTER 17 µ µ µ µ PD78F9436, 78F9456 The µ PD78F9436 and 78F9456 are available as the flash memory versions of the µ PD789426, 789436, 789446, and 789456 Subseries. The µ PD78F9436 is a version with the internal ROM of the µ PD789426 and 789436 Subseries replaced with flash memory and the µ...
Page 292: Flash Memory Programming
CHAPTER 17 µ µ µ µ PD78F9436, 78F9456 17.1 Flash Memory Programming The on-chip program memory in the µ PD78F9436 and 78F9456 is a flash memory. The flash memory can be written with the µ PD78F9436 and 78F9456 mounted on the target system (on-board). Connect the dedicated flash writer (Flashpro III (part no.
Page 293: Function Of Flash Memory Programming
CHAPTER 17 µ µ µ µ PD78F9436, 78F9456 17.1.2 Function of flash memory programming By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 17-3 shows the major functions of flash memory programming. Table 17-3.
Page 294 CHAPTER 17 µ µ µ µ PD78F9436, 78F9456 Figure 17-3. Flashpro III Connection Example in UART Mode µ Flashpro III PD78F9436, 78F9456 Note , AV RESET RESET RxD20 TxD20 , AV Note n = 1, 2 User’s Manual U15075EJ1V0UM00...
Page 295: Example Of Settings For Flashpro Iii (Pg-Fp3)
CHAPTER 17 µ µ µ µ PD78F9436, 78F9456 17.1.4 Example of settings for Flashpro III (PG-FP3) Make the following settings when writing to flash memory using Flashpro III (PG-FP3). <1> Load the parameter file. <2> Select the serial mode and serial clock using the type command. <3>...
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Page 297: Chapter 18 Mask Options
CHAPTER 18 MASK OPTIONS Table 18-1. Selection of Mask Option for Pins Mask Option P50 to P53 Whether a pull-up resistor is to be incorporated can be specified in 1-bit units. For P50 to P53 (port 5), a mask option is used to specify whether a pull-up resistor is to be incorporated. The mask option is selectable in 1-bit units.
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Page 299: Chapter 19 Instruction Set
CHAPTER 19 INSTRUCTION SET This chapter lists the instruction set of the µ PD789426, 789436, 789446, and 789456 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 19.1 Operation 19.1.1 Operand identifiers and description methods Operands are described in “Operand”...
Page 300: Description Of "Operation" Column
CHAPTER 19 INSTRUCTION SET 19.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 301: Operation List
CHAPTER 19 INSTRUCTION SET 19.2 Operation List Mnemonic Operands Byte Clock Operation Flag Z AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
Page 302 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
Page 303 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY A, CY ← A − byte − CY SUBC A, #byte (saddr), CY ← (saddr) − byte − CY saddr, #byte A, CY ← A − r − CY A, r A, CY ←...
Page 304 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY A − byte A, #byte (saddr) − byte saddr, #byte A − r A, r A − (saddr) A, saddr A − (addr16) A, !addr16 A − (HL) A, [HL] A −...
Page 305 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) CALL !addr16 PC ← addr16, SP ← SP − 2 (SP − 1) ← (PC + 1) , (SP −...
Page 306: Instructions Listed By Addressing Type
CHAPTER 19 INSTRUCTION SET 19.3 Instructions Listed by Addressing Type 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr [DE] [HL] None !addr16 [HL+byte] $addr16 1st Operand Note ADDC...
Page 307 CHAPTER 19 INSTRUCTION SET 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL. Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand...
Page 308 CHAPTER 19 INSTRUCTION SET Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic Instructions CALL CALLT Compound Instructions DBNZ Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U15075EJ1V0UM00...
Page 309: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the µ PD789426, 789436, 789446, and 789456 Subseries. Figure A-1 shows development tools. • Support to PC98-NX Series Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in PC98-NX Series.
Page 310 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Language processing software · Embedded software Assembler package · C compiler package · · System simulator · Device file · C compiler source file · Integrated debugger Host machine (PC or EWS) Interface adapter Flash memory writing tools In-circuit emulator...
Page 311: Language Processing Software
APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K0S Program that converts program written in mnemonic into object codes that can be executed Assembler package by microcontroller. In addition, automatic functions to generate symbol table and optimize branch instructions are also provided. Used in combination with optional device file (DF789456).
Page 312: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS A.2 Flash Memory Writing Tools Flashpro III Dedicated flash programmer for microcomputers incorporating flash memory (Part No. FL-PR3, PG-FP3) Flash programmer FA-64GK Adapter for writing to flash memory and connected to Flashpro III. • FA-64GK: for 64-pin plastic TQFP (fine pitch) (GK-9ET type) Flash memory writing adapter Remark The FL-PR3 and FA-64GK are products made by Naito Densei Machida Mfg.
Page 313: Debugging Tools
APPENDIX A DEVELOPMENT TOOLS A.3 Debugging Tools A.3.1 Hardware IE-78K0S-NS In-circuit emulator for debugging hardware and software of application system using 78K/0S In-circuit emulator Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-70000-MC-PS-B Adapter for supplying power from AC 100 to 240 V outlet.
Page 314: Software
APPENDIX A DEVELOPMENT TOOLS A.3.2 Software ID78K0S-NS Control program for debugging 78K/0S Series. Integrated debugger This program provides a graphical use interface. It runs on Windows for personal computer (Supports in-circuit emulator users and on OSF/Motif for engineering work station users, and has visual designs and IE-78K0S-NS) operationability that comply with these operating systems.
Page 315: Appendix B Embedded Software
APPENDIX B EMBEDDED SOFTWARE The following embedded software is provided to perform the program development and maintenance of the µ PD789426, 789436, 789446, and 789456 Subseries effectively. Subset OS conformed to µ ITRON. Includes the nucleus of the MX78K0S. Task control, MX78K0S event control, and time control are performed.
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Page 317: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (Alphabetic Order of Register Name) Analog input channel specification register 0 (ADS0).................. 187, 201 A/D conversion result register 0 (ADCR0) ....................184, 198 A/D converter mode register 0 (ADM0)......................186, 200 Asynchronous serial interface mode register 20 (ASIM20)............216, 223, 226, 238 Asynchronous serial interface status register 20 (ASIS20)................
Page 318 APPENDIX C REGISTER INDEX Port 1 (P1)................................82 Port 2 (P2)................................83 Port 3 (P3)................................89 Port 5 (P5)................................91 Port 6 (P6)................................92 Port 7 (P7)................................93 Port 8 (P8)................................94 Port 9 (P9)................................95 Port mode register 0 (PM0)..........................96, 97 Port mode register 1 (PM1)..........................
Page 319: Register Index (Alphabetic Order Of Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (Alphabetic Order of Register Symbol) ADCR0: A/D conversion result register 0....................184, 198 ADM0: A/D converter mode register 0 ....................186, 200 ADS0: Analog input channel specification register 0................187, 201 ASIM20: Asynchronous serial interface mode register 20............216, 223, 226, 238 ASIS20: Asynchronous serial interface status register 20 ................
Page 320 APPENDIX C REGISTER INDEX Port 5..............................91 Port 6..............................92 Port 7..............................93 Port 8..............................94 Port 9..............................95 PCC: Processor clock control register ......................105 PM0: Port mode register 0........................96, 97 PM1: Port mode register 1........................96, 97 PM2: Port mode register 2........................
Page 321 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

This manual is also suitable for:

Mpd789436 series Mpd789446 series Mpd789456 series Mpd789425 Mpd789445Mpd789426 ... Show all

NEC mPD789426 Series User Manual

Chapter 1 General

Features

Applications

Ordering Information

Pin Configuration (Top View)

Block Diagram

Overview of Functions

Chapter 2 Pin Functions

List of Pin Functions

Description of Pin Functions

Pin Input/Output Circuits and Recommended Connection of Unused Pins

Chapter 3 Cpu Architecture

Memory Space

Processor Registers

Instruction Address Addressing

Operand Address Addressing

Chapter 4 Port Functions

Port Configuration

Registers Controlling Port Function

Port Function Operation

Chapter 5 Clock Generator

Clock Generator Functions

Clock Generator Configuration

Registers Controlling Clock Generator

System Clock Oscillators

Clock Generator Operation

Changing Setting of System Clock and CPU Clock

Chapter 6 16-Bit Timer

16-Bit Timer Functions

16-Bit Timer Configuration

Registers Controlling 16-Bit Timer

16-Bit Timer Operation

Notes on Using 16-Bit Timer

Chapter 7 8-Bit Timer

8-Bit Timer Functions

8-Bit Timer Configuration

Registers Controlling 8-Bit Timer

8-Bit Timer Operation

Notes on Using 8-Bit Timer

Chapter 8 Watch Timer

Watch Timer Functions

Watch Timer Configuration

Watch Timer Control Register

Watch Timer Operation

Chapter 9 Watchdog Timer

Watchdog Timer Functions

Watchdog Timer Configuration

Watchdog Timer Control Registers

Watchdog Timer Operation

CHAPTER 10 8-BIT A/D CONVERTER ( Μ Μ Μ Μ PD789426 and 789446 SUBSERIES)

8-Bit A/D Converter Functions

8-Bit A/D Converter Configuration

8-Bit A/D Converter Control Registers

8-Bit A/D Converter Operation

Cautions Related to 8-Bit A/D Converter

CHAPTER 11 10-BIT A/D CONVERTER ( Μ Μ Μ Μ PD789436 and 789456 SUBSERIES)

10-Bit A/D Converter Functions

10-Bit A/D Converter Configuration

10-Bit A/D Converter Control Registers

10-Bit A/D Converter Operation

Cautions Related to 10-Bit A/D Converter

Chapter 12 Serial Interface 20

Serial Interface 20 Functions

Serial Interface 20 Configuration

Serial Interface 20 Control Registers

Serial Interface 20 Operation

Chapter 13 Lcd Controller/Driver

LCD Controller/Driver Functions

LCD Controller/Driver Configuration

Registers Controlling LCD Controller/Driver

Setting LCD Controller/Driver

LCD Display Data Memory

Common and Segment Signals

Display Modes

Chapter 14 Interrupt Functions

Interrupt Function Types

Interrupt Sources and Configuration

Registers Controlling Interrupt Function

Interrupt Servicing Operation